View SCHS177A_1000882.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CD54/74HC297, CD74HCT297
Data sheet acquired from Harris Semiconductor SCHS177A
November 1997 - Revised May 2000
High-Speed CMOS Logic Digital Phase-Locked-Loop
Description
The 'HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL). These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop. The 'HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.
Features
* Digital Design Avoids Analog Compensation Errors
[ /Title (CD74 HC297 , CD74 HCT29 7) /Subject Highpeed MOS ogic igial haseocked
* Easily Cascadable for Higher Order Loops * Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) * Dynamically Variable Bandwidth * Very Narrow Bandwidth Attainable * Power-On Reset * Output Capability - Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT - Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/DOUT * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * 'HC297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V - High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V * CD74HCT297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V - Direct LSTTL Input Logic Compatibility VIL = 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility II 1A at VOL, VOH
Pinout
CD54HC297 (CERDIP) CD74HC297, CD74HCT29 (PDIP) TOP VIEW
B1 A2 ENCTR 3 KCP 4 I/DCP 5 D/U 6 I/DOUT 7 GND 8 16 VCC 15 C 14 D 13 A2 12 ECPDOUT 11 XORPDOUT 10 B 9 A1
Ordering Information
PART NUMBER CD54HC297F3A CD74HC297E CD74HCT297E NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2000, Texas Instruments Incorporated
1
CD54/74HC297, CD74HCT297
The phase detector generates an error signal waveform that, at zero phase error, is a 50% duty factor square wave. At the limits of linear operation, the phase detector output will be either HIGH or LOW all of the time depending on the direction of the phase error (IN - OUT). Within these limits the phase detector output varies linearly with the input phase error according to the gain Kd, which is expressed in terms of phase detector output per cycle or phase error. The phase detector output can be defined to vary between 1 according to the relation:
%HIGH - %LOW phase detector output = ------------------------------------------100
Functional Diagram
D 4 KCP D/U ENCTR I/DCP 5 9 11 10 13 J K Q 12 XORPDOUT ECPDOUT 6 3 C B 1 A 2 CARRY MODULO-K COUNTER BORROW I/D CKT 7 I/DOUT 14 15
A1 B A2
The output of the phase detector will be Kde, where the phase error e = IN - OUT. EXCLUSIVE-OR phase detectors (XORPD) and edge-controlled phase detectors (ECPD) are commonly used digital types. The ECPD is more complex than the XORPD logic function but can be described generally as a circuit that changes states on one of the transitions of its inputs. The gain (Kd) for an XORPD is 4 because its output remains HIGH (XORPDOUT = 1) for a phase error of one quarter cycle. Similarly, Kd for the ECPD is 2 since its output remains HIGH for a phase error of one half cycle. The type of phase detector will determine the zero-phase-error point, i.e., the phase separation of the phase detector inputs for a e defined to be zero. For the basic DPLL system of Figure 3, e = 0 when the phase detector output is a square wave. The XORPD inputs are one quarter cycle out-of-phase for zero phase error. For the ECPD, e = 0 when the inputs are one half cycle out of phase. The phase detector output controls the up/down input to the K-counter. The counter is clocked by input frequency Mfc which is a multiple M of the loop center frequency fc. When the K-counter recycles up, it generates a carry pulse. Recycling while counting down generates a borrow pulse. If the carry and the borrow outputs are conceptually combined into one output that is positive for a carry and negative for a borrow, and if the K-counter is considered as a frequency divider with the ratio Mfc/K, the output of the K-counter will equal the input frequency multiplied by the division ratio. Thus the output from the K-counter is (KdeMfc)/K. The carry and borrow pulses go to the increment/decrement (I/D) circuit which, in the absence of any carry or borrow pulses has an output that is one half of the input clock (I/DCP). The input clock is just a multiple, 2N, of the loop center frequency. In response to a carry of borrow pulse, the I/D circuit will either add or delete a pulse at I/DOUT. Thus the output of the I/D circuit will be Nfc + (KdeMfc)/2K. The output of the N-counter (or the output of the phaselocked-loop) is thus: fo = fc + (KdeMfc)/2KN. If this result is compared to the equation for a first-order analog phase-locked-loop, the digital equivalent of the gain of the VCO is just Mfc/2KN or fc/K for M = 2N. Thus, the simple first-order phase-locked-loop with an adjustable K-counter is the equivalent of an analog phase-lockedloop with a programmable VCO gain.
F/F
FUNCTION TABLE EXCLUSIVE-OR PHASE DETECTOR A1 L L H H B L H L H XORPD OUT L H H L
FUNCTION TABLE EDGE-CONTROLLED PHASE DETECTOR A2 H or L H or L B H or L H or L ECPD OUT H L No Change No Change
H = Steady-State High Level, L = Steady-State Low Level, = LOW to HIGH Transition, = HIGH to LOW Transition K-COUNTER FUNCTION TABLE (DIGITAL CONTROL) D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H MODULO (K) Inhibited 23 24 25 26 27 28 29 210 211 212 213 214 215 216 217
2
CD54/74HC297, CD74HCT297
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads VOH VIH or VIL -0.02 -0.02 -0.02 -6 (Note 4) -7.8 (Note 4) VOL VIH or VIL 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 (Note 4) 5.2 (Note 4) 2 4.5 6 4.5 6 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
Low Level Output Voltage CMOS Loads
3
CD54/74HC297, CD74HCT297
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 3) NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 5. XORPD, ECPD II ICC ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL II ICC VI (V) VCC or GND VCC or GND IO (mA) VCC (V) 0 6 6 MIN 25oC TYP MAX 0.1 8 -40oC TO 85oC MIN MAX 1 80 -55oC TO 125oC MIN MAX 1 160 UNITS A A
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
0.1 8 360
-
1 80 450
-
1 160 490
A A A
HCT Input Loading Table
INPUT ENCTR, D/U A, B, C, D, KCP, A2 I/DCP, A1, B UNIT LOADS 0.3 0.6 1.5
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360A max at 25oC.
4
CD54/74HC297, CD74HCT297
Prerequisite For Switching Function
25oC PARAMETER HC TYPES Maximum Clock Frequency KCP fMAX 2 4.5 6 Maximum Clock Frequency I/DCP fMAX 2 4.5 6 Clock Pulse Width KCP tw 2 4.5 6 Clock Pulse Width I/DCP tW 2 4.5 6 Set-up Time D/U, ENCTR to KCP tSU 2 4.5 6 Hold Time D/U, ENCTR to KCP tH 2 4.5 6 HCT TYPES Maximum Clock Frequency KCP Maximum Clock Frequency I/DCP Clock Pulse Width KCP Clock Pulse Width I/DCP Set-up Time D/U, ENCTR to KCP Hold Time D/U, ENCTR to KCP fMAX fMAX tw tw tSU tH 4.5 4.5 4.5 4.5 4.5 4.5 30 20 16 25 20 0 24 16 20 31 25 0 20 13 24 38 30 0 MHz MHz ns ns ns ns 6 30 35 4 20 24 80 16 14 125 25 21 100 20 17 0 0 0 5 24 28 3 16 19 100 20 17 155 31 26 125 25 21 0 0 0 4 20 24 2 13 15 120 24 20 190 38 32 150 30 26 0 0 0 MHz MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
Switching Specifications
Input tr, tf = 6ns TEST CONDITIONS 25oC VCC (V) TYP MAX -40oC TO 85oC -55oC TO 125oC MAX MAX UNITS
PARAMETER HC TYPES Propagation Delay, I/DCP to I/DOUT
SYMBOL
tPLH, tPHL
CL = 50pF
2 4.5 6
-
175 35 30
220 44 34
265 53 43
ns ns ns
5
CD54/74HC297, CD74HCT297
Switching Specifications
Input tr, tf = 6ns (Continued) TEST CONDITIONS CL = 50pF 25oC VCC (V) 2 4.5 6 Propagation Delay, B, A2 to ECPDOUT tPHL, tPHL CL = 50pF 2 4.5 6 Output Transition Time XORPDOUT ECPDOUT tTLH CL = 50pF 2 4.5 6 Output Transition Time I/DOUT tTLH CL = 50pF 2 4.5 6 Input Capacitance HCT TYPES Propagation Delay, I/DCP to I/DOUT Propagation Delay, A1, B to XORPDOUT Propagation Delay, B, A2 to ECPDOUT Output Transition Time XORPDOUT Output Transition Time ECPDOUT Input Capacitance tPLH, tPHL tPLH, tPHL tPHL, tPHL tTLH tTLH CI CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 4.5 4.5 4.5 4.5 4.5 35 30 40 15 12 10 44 38 50 19 15 10 53 45 60 22 18 10 ns ns ns ns ns pF CI TYP MAX 150 30 26 200 40 34 75 15 13 60 12 10 10 -40oC TO 85oC -55oC TO 125oC MAX 190 38 33 250 50 43 95 19 16 75 15 13 10 MAX 225 45 38 300 60 51 110 22 19 90 18 15 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns pF
PARAMETER Propagation Delay, A1, B to XORPDOUT
SYMBOL tPLH, tPHL
6
CD54/74HC297, CD74HCT297 Logic Diagram
A B C D 2 1 15 14 MODULO-K COUNTER 1 2 4 8
CONTROL CIRCUIT 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TO MODE CONTROLS 12-2 (11 STAGES NOT SHOWN) KCP D/U 4 6 D CP FF Q 3 ENCTR D CP FF Q POWER ON RESET 1=1 1 BORROW CARRY 5 I/DCP 7 I/DOUT D Q D Q D Q D CP FF Q Q CP FF J K D Q D Q D Q D CP FF Q Q INCREMENT/DECREMENT CIRCUIT T FF RQ
D
RD T FF Q T
RD FF Q
R DD T FF14 M Q
R D DQ T FF13 M
R D DQ T FF1 M
RD T
Q FF
M T FF RQ
D
M FF14
D
Q
T
DR Q
FF13 DR D
T
Q T FF1 M DR
D
T
Q FF RD
CP FF Q
CP FF Q
CP FF
CP FF Q
CP FF Q
CP FF
A1
9 EXCLUSIVE-OR PHASE DETECTOR 10 11 XORPDOUT
B
EDGE-CONTROLLED PHASE DETECTOR SD Q FF Q RD SD Q FF Q RD 12 ECPDOUT
A2
13
7
CD54/74HC297, CD74HCT297
MfC
KCP D/U ENCTR XORPDOUT DIVIDE-BY-K COUNTER
CARRY
BORROW
A1 OUT
ECPDOUT J J fOUT
B
I/D CIRCUIT
I/DCP
2NfC
IN
fIN
A2
ECPD K FF
I/DOUT
DIVIDE-BY-N COUNTER
FIGURE 1. DPLL USING BOTH PHASE DETECTORS IN A RIPPLE-CANCELLATION SCHEME
MfC
KCP DIVIDE-BY-K COUNTER
CARRY
D/U XORPDOUT fOUT
BORROW
IN
A1 B
I/D CIRCUIT
I/DCP
2NfC
I/DOUT
OUT
fOUT
DIVIDE-BY-N COUNTER
FIGURE 2. DPLL USING EXCLUSIVE-OR PHASE DETECTION
CARRY PULSE (INTERNAL SIGNAL) BORROW PULSE (INTERNAL SIGNAL) I/DCP INPUT I/DOUT OUTPUT
FIGURE 3. TIMING DIAGRAM: I/DOUT IN-LOCK CONDITION
8
CD54/74HC297, CD74HCT297
oB INPUT oA2 INPUT ECPDOUT OUTPUT
FIGURE 4. TIMING DIAGRAM: EDGE CONTROLLED PHASE COMPARATOR WAVEFORMS
oB INPUT
oA1 INPUT XORPDOUT OUTPUT
FIGURE 5. TIMING DIAGRAM: EXCLUSIVE OR PHASE DETECTOR WAVEFORMS
I/fMAX tW I/DCP tPLH I/DOUT tTLH VS tPHL VS tTHL
FIGURE 6. WAVEFORMS SHOWING THE CLOCK (I/DCP) TO OUTPUT (I/DOUT) PROPAGATION DELAYS, CLOCK PULSE WIDTH, OUTPUT TRANSITION TIMES AND MAXIMUM CLOCK PULSE FREQUENCY
VS oB INPUT
VS oA1 INPUT tTLH XORPDOUT OUTPUT tPLH tPLH VS tPLH tTHL tPHL
FIGURE 7. WAVEFORMS SHOWING THE PHASE INPUT (oB, oA1) TO OUTPUT (XORPDOUT) PROPAGATION DELAYS AND OUTPUT TRANSITION TIMES
9
CD54/74HC297, CD74HCT297
oB INPUT
VS
oA2 INPUT
VS
ECPDOUT OUTPUT tPHL
VS tPLH tTHL tTLH
FIGURE 8. WAVEFORMS SHOWING THE PHASE INPUT (oB, oA2) TO OUTPUT (ECPDOUT) PROPAGATION DELAYS AND OUTPUT TRANSITION TIMES
tH D/U, ENCTR INPUT tSU VS KCP INPUT tW 1/fMAX VS tSU
tH
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. FIGURE 9. WAVEFORMS SHOWING THE CLOCK (KCP) PULSE WIDTH AND MAXIMUM CLOCK PULSE FREQUENCY, AND THE INPUT (D/U, ENCTR) TO CLOCK (KCP) SETUP AND HOLD TIMES
10
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCHS177A

	To Download SCHS177A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .