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SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
* * * * * *
Combines F245 and F280B Functions in One Package High-Impedance N-P-N Inputs for Reduced Loading (70 A in Low and High States) High Output Drive and Light Bus Loading 3-State B Outputs Sink 64 mA and Source 15 mA Input Diodes for Termination Effects Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR NT PACKAGE (TOP VIEW)
description
The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.
T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY
The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port from the B port. When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R low), PARITY is an input. When transmitting (T/R high), the parity select (ODD/EVEN) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity. When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN is low (for even parity) and the number of highs on B port is: 1. Odd and the PARITY input is high, then ERR will be high signifying no error. 2. Even and the PARITY input is high, then ERR will be low indicating an error. The SN74F657 is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
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SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH INPUTS OE L L 0, 2 4 6 0 2, 4, 6, 8 L L L L L L 1357 1, 3, 5, L L L L Don't care H T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X INPUT/OUTPUT PARITY H L H L H L L H H L H L Z OUTPUTS ERR Z Z H L L H Z Z L H H L Z OUTPUT MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z
logic symbol
OE T/R ODD/EVEN A1 A2 A3 A4 A5 A6 A7 A8 24 1 11 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 2k 4, 2 5 4, 1 12 ERR G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 1 Z11 1 2 23 B1
22 21 20 17 16 15 14
B2 B3 B4 B5 B6 B7 B8
13
PARITY
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
logic diagram (positive logic)
T/R 1
OE A1
24 2 3
23 22
B1
A2
B2
A3
4
21
B3
A4
5
20
B4
A5
6
17
B5
A6
8
16
B6
A7
9
15
B7
A8
10
14
B8
ODD/EVEN
11
13 12
PARITY ERR
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-3
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (excluding I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Current into any output in the low state: A1- A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B1- B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.
recommended operating conditions
MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level High level output current Low-level Low level output current Operating free-air temperature A1 - A8 B1 - B8, PARITY, ERR A1 - A8 B1 - B8, PARITY, ERR 0 4.5 2 0.8 -3 - 12 24 64 70 NOM 5 MAX 5.5 UNIT V V V mA mA C
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK Any output VOH B1 - B8, PARITY, ERR Any output A1 - A8 VOL B1 - B8, PARITY, ERR T/R OE II ODD/EVEN A1 - A8 B1 - B8 A, B, PARITY IIH T/R, OE ODD/EVEN A, B, PARITY IIL T/R, OE ODD/EVEN A1 - A8 IOS IOZH IOZL ICCH B1 - B8 ERR ERR - 60 VCC = 5 5 V 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VO = 0 VI = 2.7 V VI = 0.5 V - 100 VCC = 5.5 V, VI = 0.5 V VCC = 5.5 V, VI = 2.7 V VCC = 4.5 V 45 VCC = 0, VCC = 0, VCC = 0, VCC = 5 5 V 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.75 V, TEST CONDITIONS II = - 18 mA IOH = - 3 mA IOH = - 15 mA IOH = - 1 mA to - 3 mA IOL = 24 mA IOL = 64 mA VI = 7 V, VI = 7 V, VI = 7 V VI = 7 V OE = 4.5 V T/R = 4.5 V MIN 2.4 2 2.7 0.35 0.42 0.5 0.55 0.1 0.1 0.1 2 1 70 40 20 - 70 - 40 - 20 - 150 - 225 50 - 50 125 150 145 mA A A mA mA mA A A mA V TYP 3.3 3.1 V MAX - 1.2 UNIT V
VCC = 5.5 V 90 ICCL VCC = 5.5 V 106 ICCZ VCC = 5.5 V 98 All typical values are at VCC = 5 V, TA = 25C. For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN74F657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SDFS027A - D3217, JANUARY 1989 - REVISED OCTOBER 1993
switching characteristics (see Note 2)
VCC = 5 V, CL = 50 pF, R1 = 500 , R2 = 500 , TA = 25C MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ A or B A B or A 2.5 3 6 6.8 4 4.5 8 8 6 7.5 3 4 2 2 TYP 4.2 4 8.4 8.5 6.4 6.9 12.7 13.4 8.1 8.8 5.3 5.4 4.2 3.7 MAX 7.5 7.5 14 15 11 11.5 20.5 20.5 15.5 15.5 8 9.5 7.5 6 VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 , R2 = 500 , TA = MIN to MAX MIN 2.5 3 6 6.8 4 4.5 7.5 7.5 6 7.5 3 4 2 2 MAX 8 8 16 16 12 12.5 22.5 22.5 16.5 17 9 11 8 6.5 ns ns ns ns ns ns ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
PARITY PARITY, PARITY ERR ERR ERR A, B, PARITY, A B PARITY or ERR A, B, PARITY, A B PARITY or ERR
ODD/EVEN B PARITY OE OE
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. These delay times reflect the 3-state recovery time only and not the signal through the buffers or parity check circuitry. To assure valid information at the ERR output pin, time must be allowed for the signal to propagate through the drivers (B to A), and to the ERR output. Valid data at the ERR output is greater than or equal to (B to A) + (A to PARITY). NOTE 2: Load circuits and waveforms are shown in Section 1.
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* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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