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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
D D D D D D D D D D D D D
Single 5-V Power Supply Sample Rates (Fs) up to 48 kHz 18-Bit Resolution Pulse-Width-Modulation (PWM) Output De-emphasis Filter for Sample Rates of 32, 37.8, 44.1, and 48 kHz Mute With Zero-Data-Detect Flags Digital Attenuation to - 60 dB Total Harmonic Distortion of 0.004% Maximum Total-Channel Dynamic Range of 96 dB Minimum Serial-Port Interface Differential Architecture CMOS Technology 2s-Complement Data Format
DWB PACKAGE (TOP VIEW)
INIT TEST ATT SHIFT LATCH 256FSO TEST DGND TEST BCK DATA LRCK MUTEL MUTER
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DVDD L1 AVDDL L2 AGNDL XGND XIN XOUT XVDD AGNDR R2 AVDDR R1 DVDD
description
The TMS57014A is a stereo oversampled-sigma-delta digital-to-analog converter (DAC) designed for use in systems such as compact disks, digital audio tapes, multimedia, and video cassette recorders. The device provides high-resolution signal conversion. This device consists of two identical synchronous conversion paths for left and right audio channels. Other overhead functions provide on-chip timing and control. Additional features include muting, attenuation, de-emphasis, and zero-data detection. Control words (16-bit) from a host controller or processor implement these functions. The TMS57014A is characterized for operation from 0C to 70C.
AVAILABLE OPTION PACKAGE TA SMALL OUTLINE (DWB)
0C to 70C TMS57014ADWBLE Available on tape and reel (LE) only.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
functional block diagram
INIT XIN XOUT 256FSO 1 22 21 6 ATT SHIFT LATCH 3 4 5 Serial Control Timing and Control Attenuation De-emphasis Filter DAC Modulator 27 25 L1 L2
13 14
MUTEL MUTER
Interpolation Filter Zero-Data Detect Zero-Data Detect Interpolation Filter
Left Channel
DATA 11 10 BCK LRCK 12
Serial Data Interface
Right Channel De-emphasis Filter DAC Modulator 16 18 R1 R2
2
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
Terminal Functions
TERMINAL NAME ATT AVDDL AVDDR AGNDL AGNDR BCK DATA DVDD DGND INIT LATCH LRCK MUTEL MUTER L1 L2 R1 R2 SHIFT TEST XIN XOUT XVDD XGND 256FSO NO. 3 26 17 24 19 10 11 15, 28 8 1 5 12 13 14 27 25 16 18 4 2, 7, 9 22 21 20 23 6 I/O I I I I I I I I I I I I O O O O O O I I I O I I O DESCRIPTION Serial control data. ATT is a 16-bit word configured as LSB first (see Tables 2, 3, and 4). Analog power supply (left channel) Analog power supply (right channel) Analog ground (left channel) Analog ground (right channel) Bit clock input. BCK clocks serial audio data into the device. Audio data input. DATA can be configured as 16 or 18 bits with MSB or LSB first. DATA is 2s complement. Digital supply Digital ground Reset. When INIT is brought low, the device is reset. The device is activated on the rising edge of INIT. The LRCK signal must be applied to the device for a reset to occur. Serial-control data latch. Control data loads into the internal registers when LATCH is brought low. Left /right clock. LRCK signifies whether the serial data is associated with the left-channel DAC (when high) or the right-channel DAC (when low). Left-channel mute flag active. When the left channel is mute or the data through the channel remains at zero for the system-register selected time, MUTEL is brought low. Right-channel mute flag active. When the right channel is mute or the data through the channel remains at zero for the system-register selected time, MUTER is brought low. Left PWM output 1 Left PWM output 2 Right PWM output 1 Right PWM output 2 Shift clock. SHIFT clocks the control data into the internal registers. All TEST inputs should be tied low. Master clock in. XIN derives all the key logic signals of the device. XIN runs at 512 Fs, where Fs is the sample rate. Master clock out Power supply for clock section Ground for clock section System clock out. 256FSO reflects the master clock input divided by 2. The rate is 256Fs, where Fs is the sample rate.
detailed description
The TMS57014A incorporates an interpolation impulse-response filter (FIR) and oversampled modulator. The pulse-width modulation (PWM) digital output feeds into an external low-pass filter to recover the analog audio signal. Two control registers configure the device, the attenuation register controls the attenuation range and the system register controls additional functions (see register set section). reset/ initialization When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling frequency (Fs) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive for a maximum of five LRCK periods after the rising edge of INIT. At this point, internal clocks are synchronous with LRCK and the PWM output is valid (see Figure 1). The LRCK signal must be applied for proper initialization.
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
reset/ initialization (continued)
INIT Internal Reset LRCK 120 Cycles of Fs 5 periods max
Figure 1. Reset Timing Relationships timing and control The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is shown in Table 1. The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate master-clock frequency. Some of the functions of the converter, such as the de-emphasis filter, operate only at the frequencies in Table 1. Table 1. Master Clock to Sample Rate Comparison
XIN (MHz) 24.5760 22.5792 19.3536 16.3840 256FSO (MHz) 12.2880 11.2896 9.6768 8.1920 LRCK (kHz) 48.0 44.1 37.8 32.0
digital-audio data interface The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB first as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16-bit data or 36 Fs for 18-bit data where Fs is the sample rate. Figure 2 illustrates the input timing.
BCK DATA (16-bit) DATA (18-bit) LRCK
15
14
1
0
15
14
1
17
16
15
14
1
0
17
16
15
14
1
Left Channel
Right Channel
Figure 2. Audio-Data Input Timing
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II II II II II
0 0
IIII IIII IIIIII IIIIII
IIIII IIIII IIIIIII IIIIIII
TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
serial-control interface This device uses the least-significant-bit-first format. Therefore, for a 16-bit word, D15 is the most significant bit and D0 is the least significant bit. Unless otherwise specified, all values are in 2s-complement format.
serial-control-data input
The 16-bit control-data input implements the device-control functions. The TMS57014A has two registers for this data: the system register and the attenuation register. The system register contains most of the system configuration information, and the attenuation register controls audio output level, de-emphasis, and mute. Figure 3 illustrates the input timing for ATT, SHIFT, and LATCH. The data loads internally on the falling edge of LATCH. The shift clock should be high for the LATCH setup time before LATCH goes low.
SHIFT ATT LATCH 0 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB
Figure 3. Control-Data-Input Timing
mute
When mute is activated, the output PWM becomes zero data (50% duty cycle). The two mute flags, MUTEL and MUTER, are independently set low based on the data in the respective channel being zero. This function becomes active under the following conditions: 1. When the zero-data detector detects that the input data has been zero for 2500 cycles of Fs or 12 500 cycles of Fs (as selected in the control registers), output is 50% duty cycle. 2. When the MUTE register value is set high by means of the serial-control data. 3. When INIT is active (low), output is 50% duty cycle.
zero-data detect
After the input data remains zero for 2500 or 12 500 cycles of Fs as set by the system register (D4, D5), the channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The zero-detect register value in the serial-control data selects the detection period. The mute flag returns high immediately when nonzero input data is received.
de-emphasis filter
Four sets of de-emphasis-filter coefficients support four sampling rates (Fs): 32, 37.8, 44.1, and 48 kHz. Internal register values select the filter coefficients. The internal register values enable or disable the filter. Figure 4 illustrates the de-emphasis characteristics. Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the de-emphasis characteristics shown in Figure 4. This device provides reconstruction of the original frequency response.
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
de-emphasis filter (continued)
10 Response - dB
0
- 10
De-emphasis
3.18 (50 s) Frequency - kHz
10.6 (15 s)
Figure 4. De-emphasis Characteristics
digital attenuation
A value selected in the internal attenuation register determines the attenuation of the digital-audio-data input. The attenuation value is 11 bits long with a valid range of hex values from 400h to 000h. A data value of 001h corresponds to an attenuation value of - 60 dB and a data value of 400h corresponds to 0 dB. The attenuation function is nonlinear (see equation 1). Figure 5 illustrates the attenuation function in dB. The default attenuation value is 400h. Attenuation
+ 20 log
0 - 10
attenuation data 1024
(1)
Attenuation - dB
- 20
- 30
- 40
- 50
- 60 1024 896
768
640
512
384
256
128
0
Attenuation Data (decimal values)
Figure 5. Digital Attenuation Characteristics
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
register set
Table 2 contains the register-set selection. Tables 3 and 4 list the bit functions. Table 2. Register-Set Selection
BITS 15 0 0 1 14 0 1 x DESCRIPTION Attenuation register System register Invalid condition
Bit 15 should always be set to 0 when writing data for proper operation.
Table 3. Attenuation-Register Bit Functions
BITS 13 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- 12 -- -- 0 1 -- -- -- -- -- -- -- -- -- -- -- 11 -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- 10 - 0 -- -- -- -- -- 0 1 2 3 ... 1FF 200 201 ... 3FF Digital attenuation, - 0.01 dB Digital attenuation, 0.00 dB Digital attenuation, - 6.04 dB Digital attenuation, - 6.02 dB Digital attenuation, - 6.00 dB FUNCTION De-emphasis off De-emphasis on Channel mute off Channel mute on Bit 11 must be low Digital attenuation, mute Digital attenuation, - 60.2 dB Digital attenuation, - 54.2 dB Digital attenuation, - 50.7 dB
-- -- -- 400 Default value = 0400h The attenuation values shown are typical values. Refer to the digital attenuation section for a description of the attenuation function.
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
Table 4. System-Register Bit Functions
BITS 13 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- 12 -- -- 0 1 -- -- -- -- -- -- -- -- -- -- -- 11 - 6 -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- -- 0 1 -- -- -- -- -- -- -- -- 4 -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- 3-2 -- -- -- -- -- -- -- -- 0 1 2 3 -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 1 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 FUNCTION MSB first, audio data LSB first, audio data 16-bit, audio data 18-bit, audio data Bits 11- 6 must be low Zero data detect period (2500 cycles of Fs) Zero data detect period (12500 cycles of Fs) Bit 4 must be low De-emphasis - 44.1 kHz De-emphasis - 48.0 kHz De-emphasis - 37.8 kHz De-emphasis - 32.0 kHz LRCK and PWM are not synchronized LRCK and PWM synchronized Bit 0 must be low
Default value = 0000h
interpolation filter The interpolation filter used prior to the DAC increases the digital-data rate from the LRCK speed to the oversampled rate by interpolating with a ratio of 1:32. The oversampling modulator receives the output of this filter with de-emphasis as an option. DAC modulator The DAC is a third-order modulator with 32 times oversampling. The DAC provides high-resolution, low-noise performance using a 15-value PWM output as shown in Figure 6.
APB(max) Noise Power - dB Quantization Noise Power With Noise Shaping Audio Signal Noise Excluded by Low-Pass Filter
Quantization Noise Power Without Noise Shaping 0 0 fB 0.1 0.2 0.3 0.4 0.5 Normalized Analog-Output Frequency (fO/Fs)
fO is the output frequency at the low-pass filter output (VO) shown in Figure 7. fB is the highest frequency of interest within the baseband. APB(max) is the passband maximum amplitude.
Figure 6. Oversampling Noise Power With and Without Noise Shaping
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
PWM output (L2 - L1 and R2 - R1) The L 2 - L1 and the R2 - R1 output pairs are PWM signals with the L 2 - L1 differential pulse duration determining the left-channel analog voltage and the R2 - R1 differential pulse duration determining the right-channel analog voltage. Each DAC left and right output consists of 15 levels of PWM and provides a differential signal as the input to two external differential amplifiers configured as a low-pass filter to produce the left and right audio outputs (see Figure 7).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Analog supply voltage range, left and right, AVDDL, AVDDR (see Note 1) . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Digital supply voltage range, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Clock supply voltage range, XVDD (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range, VO: L1, L 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to AVDDL + 0.3 V R1, R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to AVDDR + 0.3 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DVDD + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Case temperature for 10 seconds, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values for maximum ratings are with respect to AGNDL and AGNDR respectively. 2. Voltage values for maximum ratings are with respect to DGND. 3. Voltage values for maximum ratings are with respect to XGND.
recommended operating conditions (see Note 4)
MIN Analog supply voltage, left and right, AVDDL, AVDDR Digital supply voltage, DVDD Clock supply voltage, XVDD High-level High level input voltage, VIH voltage Low-level Low level input voltage VIL voltage, Load resistance at PWM, RL Master clock frequency at XIN Operating free-air temperature, TA NOTE 4: DVDD, AVDDL, XVDD and AVDDR tied together represents VDD. 16.3 0 XIN All other digital inputs XIN All other digital inputs 10 24.6 70 4.75 4.75 4.75 0.9 VDD 0.76 VDD 0.1 VDD 0.24 VDD NOM 5 5 5 MAX 5.25 5.25 5.25 UNIT V V V V V k MHz C
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
digital interface, AVDD = DVDD = 5 V 5% (see Note 4)
PARAMETER 256FSO VOH High-level High level output voltage L1, L 2, R1, R2 XOUT MUTEL, MUTER 256FSO VOL Low level output voltage Low-level L1, L 2, R1, R2 XOUT MUTEL, MUTER IIH IIL Ci High-level input current, any digital input Low-level input current, any digital input Input capacitance TEST CONDITIONS IO = - 0.4 mA IO = - 12 mA IO = - 1.2 mA IO = - 1 mA IO = 0.4 mA IO = 12 mA IO = 1.2 mA IO = 1 mA 1 1 5 5 MIN VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5 0.4 0.5 0.5 0.4 5 5 A A pF pF V TYP MAX UNIT
V
Co Output capacitance All typical values are at TA = 25C. NOTE 4: DVDD, AVDDL, XVDD and AVDDR tied together represents VDD.
supplies, AVDD = DVDD = 5 V 5%, no load
PARAMETER Analog power supply current Digital power supply current Total device supply current over operating temperature range Power dissipation All typical values are at TA = 25C. TEST CONDITIONS AVDDL and AVDDR are shorted together MIN TYP 15 15 60 350 MAX UNIT mA mA mA mW
DAC modulator, AVDD = DVDD = 5 V 5%, sample rate (Fs) = 44.1 kHz, full-scale input sine wave at 1 kHz, TA = 25C, bandwidth is 20 Hz to 20 kHz
PARAMETER Resolution Signal-to-noise ratio See Note 5 A-weighted, 20 Hz to 20 kHz, See Figure 10, Table 5, and Note 5 De-emphasis not selected TEST CONDITIONS MIN 18 96 100 0.003% 0.004% TYP MAX UNIT bits dB
Total harmonic distortion 20 Hz to 20 kHz, See Note 5 All typical values are at TA = 25C. NOTE 5: These specifications are measured at the output (VO) of the low-pass filter shown in Figure 7.
filter characteristics, AVDD = DVDD = 5 V 5%, de-emphasis disabled
PARAMETER Pass-band ripple Stop-band attenuation Pass band (- 3 dB) (DAC) Stop band See Note 5 Group delay All typical values are at TA = 25C. NOTE 5: These specifications are measured at the output (VO) of the low-pass filter shown in Figure 7. TEST CONDITIONS Sample rate (Fs) = 48 kHz kHz, See Note 5 MIN - 0.002 75 0 0.54 Fs 29 / Fs 0.46 Fs TYP MAX 0.002 UNIT dB dB kHz kHz s
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SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
timing requirements (see Figures 8 and 9 and Note 6)
MIN tw1 tsu1 th1 tsu2 th2 tw2 tsu3 th3 tw3 tsu4 Pulse duration, BCK Setup time, DATA before BCK Hold time, DATA after BCK Setup time, LRCK before BCK Hold time, LRCK after BCK Pulse duration, SHIFT Setup time, ATT before SHIFT Hold time, ATT after SHIFT Pulse duration, LATCH Setup time, LATCH before SHIFT 160 20 20 50 50 100 20 20 100 100 tw2 + 20 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
th4 Hold time, LATCH after SHIFT NOTE 6: All timing measurements were taken at the VDD/2 voltage level.
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TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
22 k 4700 pF 15 V 100 pF 10 k L2 (R2) 2 560 pF 3 560 pF AVSSL (AVSSR) L1 (R1) 10 k 5.6 k 100 pF 22 k AGNDL (AGNDR) - 15 V AGNDL (AGNDR) AGNDL (AGNDR) _8 + 4 NE5532 1200 pF 1 1.5 k 1.5 k 5.6 k 6_ 5 + 8 7 22 F 100 VO (BNC)
NE5532 4
220 k
Figure 7. Analog Low-Pass Filter Recommended for Measuring the Dynamic Specifications of the TMS57014A
tw1 tw1 BCK tsu1 th1 th2 tsu2
LRCK
Figure 8. Audio-Data Serial Timing
tsu3 SHIFT tw2 ATT 14 tw2 15 0 th3
LATCH th4 tw3 tsu4
Figure 9. Control-Data Serial Timing
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IIIIII
DATA
1
0
TMS57014A DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D - SEPTEMBER 1993 - REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Table 5. A-Weighted Data
FREQUENCY 25 31.5 40 50 63 80 100 125 160 200 250 315 400 500 630 A WEIGHTING (dB) - 44.6 2 - 39.2 2 - 34.5 2 - 30.2 2 - 26.1 2 - 22.3 2 - 19.1 1 - 16.1 1 - 13.2 1 - 10.8 1 - 8.6 1 - 6.5 1 - 4.8 1 - 3.2 1 - 1.9 1 FREQUENCY 800 1000 1250 1600 2000 2500 3150 4000 5000 6300 8000 10000 12500 16000 A WEIGHTING (dB) - 0.1 1 0 0 0.6 1 1.0 1 1.2 1 1.2 1 1.2 1 1.0 1 0.5 1 - 0.1 1 - 1.1 1 - 2.4 1 - 4.2 2 - 6.5 2
10
0
Attenuation - dB
- 10
- 20
- 30
- 40
- 50 20
100
1k
10 k 20 k
f - Signal Frequency - Hz
Figure 10. A-Weighted Function
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APPLICATION INFORMATION circuit and layout considerations
The designer should follow these guidelines for the best device performance.
D D D D D
Separate digital and analog ground planes should be used. All digital device functions should be over the digital ground plane, and all analog device functions should be over the analog ground plane. The ground planes should be connected at only one point to the direct power supply, and this is usually at the connector edge of the board. A single crystal-controlled clock should synchronously generate all digital signals All power supply lines should include a 0.1-F and a 1-F capacitor. When clock noise is excessive, a toroidal inductance of 10 H should be placed in series with XVDD before connecting to DVDD. The digital input control signals should be buffered when they are generated off the card. Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This minimizes any high-frequency coupling to the analog output.
PCB footprint
Figure 11 shows the printed-circuit-board (PCB) land pattern for the TMS57014A small-outline package.
W L1 P
L
L2 S L2
L
L1 P 1.27 S 9.53 W 0.76 L 1.55 L1 0.64 L2 0.91
NOTE A: All linear dimensions are in millimeters.
Figure 11. Land Pattern for PCB Layout
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MECHANICAL DATA
DWB (R-PDSO-G28) PLASTIC SMALL-OUTLINE PACKAGE
1,27 28
0,51 0,35 15
0,25 M
7,90 7,30
10,60 9,80 0,15 NOM
1 17,80 17,20
14 Gage Plane 0,25 0- 8 0,70 0,30
Seating Plane 2,80 MAX 0,05 MIN 0,15 4040259 / B 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusion.
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Copyright (c) 1998, Texas Instruments Incorporated

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