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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
D D D D D D D D D D D D D
12-Bit-Resolution A/D Converter 10-s Conversion Time Over Operating Temperature Range 11 Analog Input Channels 3 Built-In Self-Test Modes Inherent Sample and Hold Function Linearity Error . . . 1 LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Unipolar or Bipolar Output Operation (Signed Binary With Respect to Half of the Applied Referenced Voltage) Programmable MSB or LSB First Programmable Power Down Programmable Output Data Length CMOS Technology
DB, DW, OR N PACKAGE (TOP VIEW)
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF - AIN10 AIN9
description
The TLV2543C and TLV2543I are 12-bit, switched-capacitor, successive-approximation, analog-to-digital converters (ADCs). Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK), and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host. In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range. The TLV2543 is available in the DW, DB, and N packages. The TLV2543C is characterized for operation from 0C to 70C, and the TLV2543I is characterized for operation from - 40C to 85C.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SMALL OUTLINE DW TLV2543CDW TLV2543IDW DB TLV2543CDB TLV2543IDB PLASTIC DIP N TLV2543CN
TLV2543IN Available in tape and reel and ordered as the TLV2543CDWR, TLV2543CDBLE, TLV2543IDBR, or TLV2543IDWR.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
functional block diagram
REF + 14 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 Sample and Hold REF - 13
12-Bit Analog-to-Digital Converter (switched capacitors)
14-Channel Analog Multiplexer
12 Output Data Register 12 12-to-1 Data Selector and Driver
16
4
DATA OUT
Input Address Register
4 3 Self-Test Reference DATA INPUT I/O CLOCK CS 17 Control Logic and I/O Counters 19 EOC
18 15
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
Terminal Functions
TERMINAL NAME AIN0 - AIN10 NO. 1 - 9, 11, 12 15 I/O I DESCRIPTION Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a capacitance of 60 pF. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. Serial data output. This is the 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. Reference +. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF - terminal. Reference -. The lower reference voltage value (nominally ground) is applied to REF -. Positive supply voltage.
CS
I
DATA INPUT
17
I
DATA OUT
16
O
EOC GND I/O CLOCK
19 10 18
O
REF +
14
I
REF - VCC
13 20
I
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS, going low, begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7 - D4), a 2-bit data length select (D3 - D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
converter operation The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle, and 2) the actual conversion cycle. The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods depending on the selected output data length. 1. I/O cycle During the I/O cycle, two operations take place simultaneously. a. An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. b. The data output with a length of 8, 12, or 16 bits is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK. 2. Conversion cycle The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to the I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion. power up and initialization After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeros. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.
operational terminology
Previous (N - 1) conversion cycle Current (N) I/O cycle The conversion cycle prior to the current I/O cycle. The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks the digital result from the previous conversion cycle from DATA OUT. The last falling edge of the clock in the I/O CLOCK sequence signifies the end of the current I/O cycle. Immediately after the current I/O cycle, the current conversion cycle starts. When the current conversion cycle is complete, the current conversion result is loaded into the output register. The result of the current conversion cycle that is serially shifted out during the next I/O cycle. The I/O cycle after the current conversion cycle.
Current (N) conversion cycle Current (N) conversion result Next (N + 1) I/O cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this corrupts the output data from the previous conversion. The current conversion begins immediately after the twelfth falling edge of the current I/O cycle. data input The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data register format).
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
data input (continued) Table 1. Input-Register Format
INPUT DATA BYTE FUNCTION SELECT D7 (MSB) Select input channel AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 Select test voltage (Vref + - Vref -)/2 Vref - Vref + Software power down Output data length 8 bits 12 bits 16 bits Output data format MSB first LSB first Unipolar (binary) Bipolar (BIP, 2s complement) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 ADDRESS BITS D6 D5 D4 L1 D3 L0 D2 LSBF D1 BIP D0 (LSB)
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 X 1 1 0 1 0 1 0 1
data input address bits The four MSBs (D7 - D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ - Vref -. data output length The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, which is valid for the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested. With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial-data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle. With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial-data stream during the next I/O cycle with the four LSBs always set to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current I/O cycle.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
data output length (continued) With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial-data stream during the next I/O cycle. The current I/O cycle must be exactly 8 bits long to maintain synchronization, even when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result are truncated and discarded. The current conversion is immediately started after the eighth falling edge of the current I/O cycle. Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when the data format is selected to be least significant bit first, since at the time the data length change becomes effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when different data lengths are required within an application and the data length is changed between two conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB first format. sampling period During the sampling period, one of the analog inputs is internally connected to the capacitor array of the converter to store the analog input signal. The converter starts sampling the selected input immediately after the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty. After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence of external digital noise. data register, LSB first D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is set to 0, the conversion result shifts out MSB first. When set to 1, the data shifts out LSB first. Selection of MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to another, the current I/O cycle is never disrupted. data register, bipolar format D0 in the input data register controls the binary data format used to represent the conversion result. When D0 is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an input voltage equal to Vref - is a code of all zeros (000 . . . 0), the conversion result of an input voltage equal to Vref + is a code of all ones (111 . . . 1), and the conversion result of (Vref + + Vref - ) /2 is a code of a one followed by zeros (100 . . . 0). When D0 is set to 1, the conversion result is represented as bipolar data (signed binary). Nominally, conversion of an input voltage equal to Vref - is a code of a 1 followed by zeros (100 . . . 0), conversion of an input voltage equal to Vref + is a code of a 0 followed by all ones (011 . . . 1), and the conversion of (Vref + + Vref -) /2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other's complement. Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the current I/O cycle is not affected.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
EOC output The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting the conversion result. The EOC signal goes high again after the conversion completes and the conversion result is latched into the output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins. On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the falling edge of CS. data format and pad bits D3 and D2 of the input data register determine the number of significant bits in the digital output that represent the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines the arithmetic conversion. The numerical data is always justified toward the MSB in any output format. The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are zeros. When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the serial output is forced to a logic zero until EOC goes high again. When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in the serial conversion result until the required number of bits has been output. chip-select input (CS) The chip-select input (CS) enables and disables the device. During normal operation, CS should be low. Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data transfer of several devices sharing the same bus. When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its output data line to other devices that may share it. After an internally generated debounce time, the I/O CLOCK is inhibited, thus preventing any further change in the internal state. When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low) for a minimum time before a new I/O cycle can start. CS can be used to interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and then shifted out during the next I/O cycle.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
power-down features When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles, the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse. During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed, and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs are held above VCC - 0.3 V or below 0.3 V. The I/O logic remains active so the current I/O cycle must be completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The device remains in the power-down mode until a valid (other than 1110) input address clocks in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out during the next I/O cycle. analog input, test, and power-down mode The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling. Table 2. Analog-Channel-Select Address
ANALOG INPUT SELECTED AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 VALUE SHIFTED INTO DATA INPUT BINARY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 HEX 0 1 2 3 4 5 6 7 8 9 A
Table 3. Test-Mode-Select Address
INTERNAL SELF-TEST VOLTAGE SELECTED Vref + - Vref - 2 VALUE SHIFTED INTO DATA INPUT BINARY 1011 HEX B 200 UNIPOLAR OUTPUT RESULT (HEX)
Vref - 1100 C 000 Vref + 1101 D 3FF Vref + is the voltage applied to REF +, and Vref - is the voltage applied to REF -. The output results shown are the ideal values and may vary with the reference stability and with internal offsets.
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analog input, test, and power-down mode (continued) Table 4. Power-Down-Select Address
INPUT COMMAND Power down VALUE SHIFTED INTO DATA INPUT BINARY 1110 HEX E ICC 25 A RESULT
converter and analog input The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF -) voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. When the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC ), a bit 0 is placed in the output register and the 4096-weight capacitor is switched to REF -. When the voltage at the summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 4096-weight capacitor remains connected to REF + through the remainder of the successive-approximation process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are determined. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
SC
Threshold Detector
4096 Node 4096
2048 REF+
1024 REF+
16 REF+
8 REF+
4 REF+
2 REF+
1 REF+
1
To Output Latches
REF -
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST ST
VI
Figure 1. Simplified Model of the Successive-Approximation System
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
reference voltage inputs There are two reference voltage inputs on the device, REF+ and REF -. The voltage values on these terminals establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower than REF - terminal voltage.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V Negative reference voltage, Vref - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.1 V Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating free-air temperature range, TA: TLV2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminal with REF - and GND wired together (unless otherwise noted).
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
recommended operating conditions
MIN Supply voltage, VCC Positive reference voltage, Vref + (see Note 2) Negative reference voltage, Vref - (see Note 2) Differential reference voltage, Vref + - Vref - (see Note 2) Analog input voltage (see Note 2) High-level control input voltage, VIH Low-level control input voltage, VIL Clock frequency at I/O CLOCK Setup time, address bits at DATA INPUT before I/O CLOCK, tsu(A) (see Figure 5) Hold time, address bits at DATA INPUT after I/O CLOCK, th(A) (see Figure 5) Hold time, CS low after last I/O CLOCK, th(CS) (see Figure 6) Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 6) Pulse duration, I/O CLOCK high, twH(I/O) Pulse duration, I/O CLOCK low, twL(I/O) Transition time, I/O CLOCK, tt(I/O) (see Note 4 and Figure 7) Transition time, DATA INPUT and CS, tt(CS) Operating free-air temperature, TA free air temperature TLV2543C TLV2543I 0 - 40 VCC = 3 V to 3.6 V VCC = 3 V to 3.6 V 2.5 0 2.1 0.6 0 100 0 0 1.425 190 190 1 10 70 85 3 4.1 3 NOM 3.3 VCC 0 VCC VCC + 0.1 VCC MAX 3.6 UNIT V V V V V V V MHz ns ns ns s ns ns s s C
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the voltage applied to REF- convert as all zeros (000000000000). 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time elapses. 4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 s for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 3.6 V (unless otherwise noted)
PARAMETER VOH VOL IOZ IIH IIL ICC ICC(PD) Ilkg lk High-level High level output voltage Low level output voltage Low-level Off-state ( g (high-impedance-state) ) output current High-level input current Low-level input current Operating supply current Power-down current Selected channel leakage g current Maximum static analog reference current into REF + Ci Input capacitance Analog inputs Control inputs TEST CONDITIONS VCC = 3 V, VCC = 3 V to 3.6 V, VCC = 3 V, VCC = 3 V to 3.6 V, VO = VCC, VO = 0, VI = VCC VI = 0 CS at 0 V For all digital inputs, 0 VI 0.3 V or VI VCC - 0.3 V Selected channel at VCC, Unselected channel at 0 V Selected channel at 0 V, Unselected channel at VCC Vref + = VCC, Vref - = GND 1 30 5 IOH = - 0.2 mA IOH = - 20 A IOL = 0.8 mA IOL = 20 A CS at VCC CS at VCC MIN 2.4 VCC - 0.1 0.4 0.1 1 1 1 1 1 4 2.5 - 2.5 2.5 - 2.5 2.5 25 1 -1 2.5 60 15 TYP MAX UNIT V V A A A mA A A A pF
All typical values are at VCC = 5 V, TA = 25C.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 4.1 MHz, (unless otherwise noted)
PARAMETER EL ED EO EG ET Linearity error (see Note 6) Differential linearity error Offset error (see Note 7) Gain error (see Note 7) Total unadjusted error (see Note 8) DATA INPUT = 1011 Self-test output code (see Table 3 and Note 9) t(conv) tc Conversion time DATA INPUT = 1100 DATA INPUT = 1101 See Figures 10 - 15 See Figures 10 - 15 and Note 10 4075 2038 2048 0 4095 8 10 10 + total I/O CLOCK periods + td(I/O-EOC) 4 10 250 1.5 0.7 70 15 15 15 15 2.2 200 1.3 150 50 50 50 50 5 12 s s TEST CONDITIONS See Figure 2 See Figure 2 See Note 2 and Figure 2 See Note 2 and Figure 2 MIN TYP MAX 1 1 1.5 1 1.75 2058 10 UNIT LSB LSB LSB LSB LSB
Total cycle time (access, sample, and conversion)
tacq tv td(I/O-DATA) td(I/O-EOC) td(EOC-DATA) tPZH, tPZL tPHZ, tPLZ tr(EOC) tf(EOC) tr(bus) tf(bus) td(I/O-CS)
Channel acquisition time (sample) Valid time, DATA OUT remains valid after I/O CLOCK Delay time, I/O CLOCK to DATA OUT valid Delay time, last I/O CLOCK to EOC Delay time, EOC to DATA OUT (MSB / LSB) Enable time, CS to DATA OUT (MSB / LSB driven) Disable time, CS to DATA OUT (high impedance) Rise time, EOC Fall time, EOC Rise time, data bus Fall time, data bus Delay time, last I/O CLOCK to CS to abort conversion (see Note 11)
See Figures 10 - 15 and Note 10 See Figure 7 See Figure 7 See Figure 8 See Figure 9 See Figure 4 See Figure 4 See Figure 9 See Figure 8 See Figure 7 See Figure 7
I/O CLOCK periods ns ns s ns s ns ns ns ns ns s
All typical values are at TA = 25C. NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that applied to REF - convert as all zeros (000000000000). 6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 7. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. 8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 9. Both the input address and the output codes are expressed in positive logic. 10. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7). 11. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at 5 s of the tenth I/O CLOCK falling edge to ensure that a conversion is aborted. Between 5 s and 10 s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid.
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
15 V 50 C1 10 F C2 0.1 F C3 470 pF TLV2543 AIN0 - AIN10 C3 470 pF 50 - 15 V LOCATION U1 C1 C2 C3 DESCRIPTION OP27 10-F 35-V tantalum capacitor 0.1-F ceramic NPO SMD capacitor 470-pF porcelain high-Q SMD capacitor PART NUMBER -- -- AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent
VI C1 10 F C2 0.1 F
_ U1 +
10
Figure 2. Analog Input Buffer to Analog Inputs AIN0 - AIN10
Isource 0.8 mA See Note A Vcp = 2 V CL = 100 pF Isink - 0.2 mA NOTE A: Equivalent load circuit of the Teradyne A580 tester for timing parameter measurement.
Test Point Output Under Test
Figure 3. Timing Load Circuits
Data Valid 2V CS tPZH, tPZL 2.4 V DATA OUT 0.4 V 0.8 V tPHZ, tPLZ 90% 10% I/O CLOCK 0.8 V DATA INPUT 2V 0.8 V tsu(A) th(A)
Figure 4. DATA OUT to Hi-Z Voltage Waveforms
Figure 5. DATA INPUT and I/O CLOCK Voltage Waveforms
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
2V CS tsu(CS) I/O CLOCK 0.8 V Last Clock 0.8 V 0.8 V th(CS)
Figure 6. CS and I/O CLOCK Voltage Waveforms
To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. tt(I/O) I/O CLOCK 2V 0.8 V 2V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 0.4 V 2.4 V 0.4 V tr(bus), tf(bus) 0.8 V tt(I/O)
Figure 7. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last Clock td(I/O-EOC)
0.8 V
EOC
2.4 V 0.4 V tf(EOC)
Figure 8. I/O CLOCK and EOC Voltage Waveforms
tr(EOC) EOC 0.4 V td(EOC-DATA) DATA OUT 2.4 V 0.4 V Valid MSB 2.4 V
Figure 9. EOC and DATA OUT Voltage Waveforms
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15
TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 11 12
Access Cycle B DATA OUT
A11 A10 A9 A8 A7 A6
Sample Cycle B
A5 A4 A1 A0
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize t(conv) A/D Conversion Interval
Initialize
Figure 10. Timing for 12-Clock Transfer Using CS With MSB First
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 11 12 1
Access Cycle B DATA OUT
A11 A10 A9 A8 A7 A6
Sample Cycle B
A5 A4 A1 A0 B11
Low Level
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize t(conv) A/D Conversion Interval
Initialize
Figure 11. Timing for 12-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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IIII IIII
IIII IIII
IIIIII IIIIII
Hi-Z State
1
B11
IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII
C7
C7
TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8
Access Cycle B
A7 A6 A5 A4 A3
Sample Cycle B
A2 A1 A0
DATA OUT
MSB DATA INPUT
Previous Conversion Data
LSB
EOC
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 1
DATA OUT
DATA INPUT
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize
t(conv) A/D Conversion Interval
Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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IIIII IIIII
IIIII IIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIII
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize
A/D Conversion Interval
Figure 12. Timing for 8-Clock Transfer Using CS With MSB First
Access Cycle B
A7 A6 A5 A4 A3
Sample Cycle B
A2 A1 A0
MSB
Previous Conversion Data
LSB
IIIIII IIIIII
Hi-Z t(conv) Low Level
1
B7
C7
Initialize
B7
IIIII IIIIIIIIIII IIIII IIIIIIIIIII
C7
Initialize
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS (see Note A)
1 2 3 4 5 6 7 8 15 16
Access Cycle B
Sample Cycle B
DATA OUT
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize t(conv) A/D Conversion Interval
Initialize
Figure 14. Timing for 16-Clock Transfer Using CS With MSB First
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 15 16 1
Access Cycle B DATA OUT
A15 A14 A13 A12 A11 A10
Sample Cycle B
A9 A8 A1 A0
Low Level
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize
t(conv) A/D Conversion Interval
Figure 15. Timing for 16-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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IIIII IIIII
III II
IIIIII IIIIII
Hi-Z State
B15 C7
I/O CLOCK
1
B15
IIIIIIII I IIIIIIII IIIIIIII I IIIIIIII IIIIII IIIIIIIIIII IIIIII IIIIIIIIIII
C7
TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
APPLICATION INFORMATION
111111111111 See Notes A and B 111111111110 111111111101 VFS 4094 VFSnom 4093 4095
Digital Output Code
VFT = VFS - 1/2 LSB 100000000001 100000000000 011111111111 VZS 000000000010 000000000001 000000000000 0
2049 2048 Step 19
VZT = VZS + 1/2 LSB 2047
2 1 0 3.2768
0.0004
0.0008
0.0016
1.6376
1.6384
1.6392
3.2752
3.2756
3.2760
VI - Analog Input Voltage - V NOTES: A. This curve is based on the assumption that Vref+ and Vref - have been adjusted so that the voltage at the transition from digital 0 to 1 (VZT) is 0.0004 V and the transition to full scale (VFT) is 3.2756 V. 1 LSB = 0.8 mV. B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
TLV2543 1 2 3 4 5 Analog Inputs 6 7 8 9 11 12 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 GND 10 To Source Ground REF+ REF- 14 13 3-V DC Regulated DATA OUT EOC 16 19 CS I/O CLOCK DATA INPUT
15 18 17 Processor Control Circuit
Figure 17. Serial Interface
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
APPLICATIONS INFORMATION simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by V Where: Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS - (VS /8192) Equating equation 1 to equation 2 and solving for time tc gives V and tc (1/2 LSB) = Rt x Ci x ln(8192) Therefore, with the values given the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 k) x 60 pF x ln(8192) This time must be less than the converter sample time shown in the timing diagrams.
Driving Source Rs VS ri VC 1 k MAX Ci 50 pF MAX TLV2543
C
+ VS 1-e- tc RtCi
(1)
(2)
S
*
V
S
58192
+ VS 1-e- tc RtCi
(3) (4)
(5)
VI
VI = Input Voltage at AIN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Input Capacitance Driving source requirements: * Noise and distortion for the source must be equivalent to the resolution of the converter. * Rs must be real at the input frequency.
Figure 18. Equivalent Input Circuit Including the Driving Source
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
MECHANICAL DATA
DB (R-PDSO-G**)
28 PIN SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE PACKAGE
0,15 NOM 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 1,03 0,63
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 / B 10/94
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
MECHANICAL DATA
DW (R-PDSO-G**)
16 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) DIM 0.020 (0,51) 0.014 (0,35) 16 9 0.010 (0,25) M
PINS **
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78)
A MAX
A MIN
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 10/94 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
22
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TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C - MARCH 1995 - REVISED JUNE 2000
MECHANICAL DATA
N (R-PDIP-T**)
16 PIN SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
A 16 9 PINS ** DIM A MAX 0.260 (6,60) 0.240 (6,10) 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23.37) 0.850 (21.59) 20 0.975 (24,77) 0.940 (23,88)
A MIN
1
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
14 Pin Only 4040049 / C 7/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
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