View SLAS147A_1002329.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
D D D D D D D D D D D
8-Bit Resolution 2.7 V to 3.6 V VCC Easy Microprocessor Interface or Standalone Operation Operates Ratiometrically or With VCC Reference 4- or 8-Channel Multiplexer Options With Address Logic Input Range 0 V to VCC With VCC Reference Remote Operation With Serial Data Link Inputs and Outputs Are Compatible With TTL and MOS Conversion Time of 32 s at f(CLK) = 250 kHz Functionally Equivalent to the ADC0834 and ADC0838 at 3-V Supply Without the Internal Zener Regulator Network Total Unadjusted Error . . . 1 LSB
TLV0834 . . . D OR N PACKAGE (TOP VIEW)
NC CS CH0 CH1 CH2 CH3 DGTL GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC DI CLK SARS DO REF ANLG GND
TLV0838 . . . PW, DW, OR N PACKAGE (TOP VIEW)
description
These devices are 8-bit successive-approximation analog-to-digital converters, each with an input-configurable multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is readily available from the factory.
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGTL GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC CS DI CLK SARS DO SE REF ANLG GND
The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software configured for single-ended or differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution. The TLV0834C and TLV0838C are characterized for operation from 0C to 70C. The TLV0834I and TLV0838I are characterized for operation from - 40C to 85C.
AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) TLV0834CD TLV0834ID SMALL OUTLINE (DW) TLV0838CDW TLV0838IDW PLASTIC DIP (N) TLV0834CN TLV0834IN TLV0838CN TLV0838IN TSSOP (PW) TLV0838CPW TLV0838IPW
0C to 70C - 40C to 85C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
2
functional block diagram
CLK CS DI (see Note A) D CLK
SELECT0 SELECT1 ODD\ EVEN SGL\ DIF START
Start Flip-Flop CLK R 5-Bit Shift Register S R
CS
SARS
TLC0838 Only SE
POST OFFICE BOX 655303
To Internal Circuits
TLC0834
TLC0838
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
CLK
Analog MUX
Time Delay
S
R
EN
* DALLAS, TEXAS 75265
CS
Comparator EN REF Ladder and Decoder
CS R SAR Logic and Latch
CS CS R CLK Bits 0-7 Bit 1 MSB First LSB First 9-Bit Shift Register EOC CS R CLK DO D
Bits 0-7
One Shot
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
functional description
The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (-) polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. The common input on the TLV0838 can be used for a pseudo-differential input. In this mode, the voltage on the common input is considered to be the negative differential input for all channel inputs. This voltage can be any reference potential common to all channel inputs. Each channel input can then be selected as the positive differential input. This feature is useful when all analog circuits are biased to a potential other than ground. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is disabled for the duration of the conversion. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low. The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
sequence of operation
TLV0834 1 CLK 2 3 4 5 6 7 10 11 12 13 14 15 18 19 20 21
tc
CS tsu Start Bit DI DIF Hi-Z SARS MUX Settling Time MSB-First Data LSB-First Data Hi-Z MSB 7 6 2 1 LSB 0 1 2 6 MSB 7 EVEN 1 +Sign SELECT Bit Bit 1 SGL ODD Don't Care
DO
Hi-Z
TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS SGL/DIF ODD/EVEN SELECT BIT 1 CHANNEL NUMBER CH0 CH1 CH2 CH3
+ - L L L + - H L L - + L L H - + H L H + H L L + H L H + H H L + H H H H = high level, L = low level, - or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
sequence of operation
TLV0838
1 CLK 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
tsu
tc
CS MUX Addressing tsu + Sign SEL SEL Start Bit Bit Bit Bit SGL ODD 1 0 DI DIF EVEN 1 0 Don't Care
Hi-Z SARS
Hi-Z
SE LSB-First Data MSB-First Data Hi-Z DO Hi-Z MSB 7 6 2 1 LSB 0 1 2 3 4 5 6 MSB 7
SE Used to Control LSB-First Data SE MUX Settling Time MSB-First Data LSB Held LSB-First Data
DO
MSB 7 6 2 1
LSB 0 1 2 3 4 5 6
MSB 7
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS SGL/DIF L L L L L L L L H H H H H H H H ODD/EVEN L L L L H H H H L L L L H H H H SELECT 1 L L H H L L H H L L H H L L H H 0 L H L H L H L H L H L H L H L H + + + + + + + + - + - + - + - + - - - - - - - - CH0 + SELECTED CHANNEL NUMBER 0 CH1 - + - + - + - CH2 1 CH3 CH4 2 CH5 CH6 3 CH7 COM
H = high level, L = low level, - or + = polarity of external input
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC+ 0.3 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
recommended operating conditions
MIN Supply voltage, VCC (see clock frequency operating conditions) High-level input voltage, VIH Low-level input voltage, VIL Clock frequency, f(CLK) Clock frequency, f(CLK) Clock duty cycle (see Note 2) Pulse duration, CS high, twH(CS) Setup time, CS low, SE low, or data valid before CLK, tsu Hold time, data valid after CLK, th Operating free-air temperature, TA free air temperature C suffix I suffix VCC = 2.7 V VCC = 3.3 V 10 10 40% 220 350 90 0 - 40 70 85 2.7 2 0.8 250 600 60% ns ns ns C NOM 3.3 MAX 3.6 UNIT V V V kHz kHz
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the recommended duty-cycle range, the minimum pulse duration (high or low) is 1 s.
electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted)
digital section
PARAMETER VOH VOL IIH IIL IOH IOL IOZ Ci High level output voltage High-level Low-level output voltage High-level input current Low-level input current High-level output (source) current Low-level output (sink) current High-impedance-state output g current (DO or SARS) Input capacitance TEST CONDITIONS VCC = 3 V, VCC = 3 V, VCC = 3 V, VIH = 3.6 V IOH = - 360 A IOH = - 10 A IOL = 1.6 mA 0.005 - 0.005 - 6.5 8 - 15 16 0.01 - 0.01 3 -3 MIN 2.8 2.9 0.34 1 -1 - 6.5 8 0.005 - 0.005 - 15 16 0.01 - 0.01 5 3 -3 C SUFFIX TYP MAX MIN 2.4 2.8 0.4 1 -1 I SUFFIX TYP MAX UNIT V V A A mA mA A pF pF
VIL = 0 At VOH, DO = 0 V, TA = 25C A t VOL, DO = VCC, TA = 25C VO = 3.3 V, VO = 0, TA = 25C TA = 25C
Co Output capacitance 5 All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified). All typical values are at VCC = 3.3 V, TA = 25C.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted) (continued)
analog and converter section
PARAMETER VIC Common-mode input voltage g On channel II(stdby) I( tdb ) Standby input current (see Note 4) Off channel On channel Off channel ri(REF) Input resistance to REF TEST CONDITIONS See Note 3 VI = 3.3 V VI = 0 VI = 0 VI = 3.3 V 1.3 2.4 MIN - 0.05 to VCC + 0.05 1 -1 -1 1 5.9 k A TYP MAX UNIT V
total device
PARAMETER MIN TYP MAX UNIT ICC Supply current 0.2 0.75 mA All parameters are measured under open-loop conditions with zero common-mode input voltage. All typical values are at VCC = 3.3 V, TA = 25C. NOTES: 3. When channel IN - is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of 3.25 V for all variations of temperature and load. 4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is in a high or low steady-state condition.
operating characteristics, VCC = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25C (unless otherwise noted)
PARAMETER Supply-voltage variation error Total unadjusted error (see Note 5) Common-mode error tpd d tdis di tc Propagation delay time, output data after g y , CLK (see Note 6) Output disable time, DO or SARS after CS time Conversion time (multiplexer-addressing time not included) MSB-first data LSB-first data TEST CONDITIONS VCC = 3 V to 3.6 V Vref = 3.3 V, TA = MIN to MAX Differential mode CL = 100pF CL = 10 pF, CL = 100 pF, RL = 10 k RL = 2 k MIN TYP 1/16 1/16 MAX 1/4 1 1/4 500 200 80 250 8 UNIT LSB LSB LSB ns ns clock periods
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response time.
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
VCC CLK 50% 50% GND tsu CS 0.4 V th 2V 2V DI 0.4 V 0.4 V GND th VCC GND tsu VCC
Figure 1. Data-Input Timing
VCC CLK 50% tpd DO 50% tpd VCC 50% GND tsu VCC SE 50% GND 50% GND
Figure 2. Data-Output Timing
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
VCC Test Point From Output Under Test CL (see Note A) RL S1
S2
LOAD CIRCUIT tr VCC CS 50% 90% 10% tdis DO and SARS S1 open S2 closed 90% VCC DO and SARS GND S1 closed S2 open CS GND 50% tr 90% 10% tdis VCC 10% GND VCC GND
VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance.
VOLTAGE WAVEFORMS
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR vs REFERENCE VOLTAGE
16 EO(unadj) - Unadjusted Offset Error - LSB VI(+) = VI(-) = 0 V 14 1.25 E L - Linearity Error - LSB 12 10 8 6 4 2 0 0.01 0 1.5
LINEARITY ERROR vs REFERENCE VOLTAGE
VCC = 3.3 V f(CLK) = 250 kHz TA = 25C
1.0
0.75
0.5
0.25
0.1
1
10
0
1
2
3
4
Vref - Reference Voltage - V
Vref - Reference Voltage - V
Figure 4
LINEARITY ERROR vs FREE-AIR TEMPERATURE
0.5 Vref = 3.3 V f(CLK) = 250 kHz E L - Linearity Error - LSB 2.0 1.8 1.6 1.4 Vref = 3.3 V VCC = 3.3 V
Figure 5
LINEARITY ERROR vs CLOCK FREQUENCY
0.45 E L - Linearity Error - LSB
85C 1.2 1 0.8 0.6 0.4 - 40C 0.2 25C
0.4
0.35
0.3
0.25 - 50
- 25
0
25
50
75
100
0
0
100
200
300
400
500
600
700
800
TA - Free-Air Temperature - C
f(CLK) - Clock Frequency - kHz
Figure 6
Figure 7
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
TLV0831 TLV0831
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
0.3 f(CLK) = 250 kHz CS = High VCC = 3.6 V I CC - Supply Current - mA I CC - Supply Current - mA 0.4 0.5
SUPPLY CURRENT vs CLOCK FREQUENCY
VCC = 3.3 V TA = 25C
VCC = 3.3 V 0.2 VCC = 3 V
0.3
0.2
0.1
0.1 - 50
- 25
0
25
50
75
100
0
0
100
200
300
400
500
TA - Free-Air Temperature - C
f(CLK) - Clock Frequency - kHz
Figure 8
OUTPUT CURRENT vs FREE-AIR TEMPERATURE
16.5 VCC = 3.3 V 16 I O - Output Current - mA IOL (DO = 3.3 V) 15.5 - IOH (DO = 0 V) 15 - IOH (DO = 2.4 V) 14.5 IOL (DO = 0.4 V)
Figure 9
14 - 50
- 25
0
25
50
75
100
TA - Free-Air Temperature - C
Figure 10
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS147A - SEPTEMBER 1996 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
Differential Nonlinearity - LSB 1
0.5
0 Vref = 3.3 V TA = 25C f(CLK) = 250 kHz VDD = 3.3 V 0 32 64 96 128 Output Code 160 192 224 256
- 0.5
-1
Figure 11. Differential Nonlinearity With Output Code
1 Integral Nonlinearity - LSB Vref = 3.3 V TA = 25C f(CLK) = 250 kHz VDD = 3.3 V
0.5
0
- 0.5
-1 0 32 64 96 128 Output Code 160 192 224 256
Figure 12. Integral Nonlinearity With Output Code
1 Total Unadjusted Error - LSB Vref = 3.3 V TA = 25C f(CLK) = 250 kHz VDD = 3.3 V
0.5
0
- 0.5
-1 0 32 64 96 128 Output Code 160 192 224 256
Figure 13. Total Unadjusted Error With Output Code
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
13
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SLAS147A

	To Download SLAS147A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .