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TAS3001C
Stereo Audio Digital Equalizer
Data Manual
1999
Mixed Signal Linear Products
Printed in U.S.A. 09/99
SLAS226
TAS3001C Stereo Audio Digital Equalizer
SLAS226 September 1999
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1-1 1-2 1-2 1-3 1-3 1-4 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-6 2-7 2-7 2-7 2-7 2-7 2-8 2-8 2-8 2-8 2-8 2-9 2-9
iii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 I2S Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Left-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Right-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 System Clocks - Master Mode and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Filter Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10.1 Biquad Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10.2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 Volume Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.1 Soft Volume Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.2 Software Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.3 Mixer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.4 Treble Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.5 Bass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.6 Dynamic Range Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.12.2 Device Power On Plus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.12.3 Fast Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Static Digital Specifications, TA = 0C to 70C, all VDD = 3.3 V 0.3 V . . . . . . . . 3.4 Audio Serial Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 I2C Serial Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-1 3-2 3-2
4 5
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Appendix A Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
List of Illustrations
Figure Title Page
2-1 I2S Compatible Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 Left-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 Right-Justified Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-4 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-6 Typical I2C Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-7 Biquad Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-8 TAS3001C Digital Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-9 DRC Example With Threshold = -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-10 Main Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 4-1 I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
List of Tables
Table Title Page
2-1 I2C Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
iv
1 Introduction
The TAS3001C is a 32-bit processor that performs digital audio signal processing providing parametric equalization, bass, treble, and volume control, as well as dynamic range compression. This results in superior audio quality normally not available in a low-cost solution. Applications for this technology are speaker equalization, microphone equalization, and any audio application where tone, volume, and dynamic range management are important functions. The TAS3001C provides two digital stereo audio inputs, which are scaled and mixed prior to processing. The parametric EQ consists of multiple cascaded independent biquad filters per left/right channel. Each biquad is composed of five 24-bit coefficients. The user may dynamically adjust the volume, bass, and treble controls without causing the output signal to degrade. The audio control functions (mixer, volume, treble, and bass), dynamic range compression controls, and parametric EQ coefficients are downloaded via the I2C control port. The TAS3001C supports three serial audio formats: I2S, left justified, and right justified. Data word lengths of 16, 18, and 20 bits are supported. See section 2.5 Serial Audio Interface for more details. The typical sampling frequency (fs) is 44.1 kHz or 48 kHz. The digital audio processor and on-chip logic are sequenced via an internal system clock that is derived from an external MCLK (master clock). Also derived from MCLK are LRCLKOUT and SCLKOUT signals that provide clocks to the TAS3001C and other devices in the system. Two address-select pins are provided to allow multiple TAS3001Cs to be cascaded on the I2C bus. This allows speaker EQ to be provided to 3-channel systems consisting of left, right, and subwoofer speakers as well as 6-channel systems consisting of left, right, center, rear left, rear right, and subwoofer speakers.
1-1
1.1
Features
* * * * * * * * * * * * * * Programmable Serial Audio Port Two Input Data Channels (SDIN1 and SDIN2) Single Digital Output Data Channel (SDOUT) Programmable Digital Mixer Programmable Multiband Digital Parametric EQ Programmable Digital Bass and Treble Control (dynamically updateable) Programmable Digital Volume Control (dynamically updateable) Dynamic Range Compression (DRC) Serial I2C Slave Port Allows Downloading of Control Data to the Device Two I2C Address Pins Allow Cascading of Multiple Devices on the I2C Bus Supports 2 Speaker, 3 Speaker, and 6 (5.1) Speaker Systems Soft Mute via Software Control Single 3.3-V Power Supply Operation 28-Pin PW Package
Requires multiple TAS3001C devices
1.2
Functional Block Diagram
Scale SDIN1 SDIN1 Serial Audio Input Port SDIN2 LRCLK SCLK Scale SDIN2 Dynamic Range Compressor DRC Scale Factor
Parametric EQ (Multiple 2nd Order IIR Filters)
Treble/Bass
Volume
SDOUT
MCLK
Clock Generator
SCLKOUT LRCLKOUT
PLL CAP_PLL SDA SCL CS1 CS2 12C Slave
Internal Clocks
Internal Control
1-2
1.3
Terminal Assignments
PW PACKAGE (TOP VIEW)
CS2 DVSS DVDD SDA SCL SDIN1 SDIN2 SDOUT MCLK LRCLK SCLK AVSS_PLL AVDD_PLL CAP_PLL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CS1 RESERVED NC NC SCLKOUT LRCLKOUT NC NC NC RESET NC NC RESERVED RESERVED
NC - No internal connection
1.4
Ordering Information
PACKAGE TA 0C to 70C SMALL OUTLINE (PW) TAS3001CPW
1-3
1.5
Terminal Functions
TERMINAL NAME NO. 13 12 14 28 1 3 2 10 23 9 17, 18, 20-22, 25, 26 19 15, 16, 27 5 11 24 4 6 7 8 I/O I O I/O I I O I I/O I I I I I I I I O I DESCRIPTION Analog power supply for the PLL Analog ground for the PLL C1 = 1500 pF // R1 = 27 + C2 = 0.068 F (recommended) I2C address bit A0; low = 0, high = 1 I2C address bit A1; low = 0, high = 1 Digital power supply Digital ground I2S left/right clock sampling frequency (fs) LRCLK generated from input MCLK (usually 256 fs) - normally routed on PCB to pin 10 (LRCLK) as input fs sample clock. Master clock Reserved - No connection for normal operation Reset, high = normal operation, low = reinitialize the device Reserved - digital ground for normal operation Slave serial I2C clock Shift clock (bit clock) SCLK generated from input MCLK (usually 256 fs) - normally routed on PCB to pin 11 (SCLK) as input 64 fs bit clock. Slave serial I2C data Serial audio data input one Serial audio data input two Serial audio data output
AVDD_PLL AVSS_PLL CAP_PLL CS1 CS2 DVDD DVSS LRCLK LRCLKOUT MCLK NC RESET RESERVED SCL SCLK SCLKOUT SDA SDIN1 SDIN2 SDOUT
1-4
2 Description
2.1 Serial Audio Interface
* * * * * Programmable serial audio port - I2S, left justified, and right justified
Dual input data channels (SDIN1 and SDIN2) - 16-,18-, or 20-bit resolution (see Section 6.1, Audio Data)
Single output data channel (SDOUT) - 16-,18-, or 20-bit resolution (see Section 6.1, Audio Data)
Accepts 32 fs or 64 fs (SCLK) Two I2C programmable address pins (CS1 and CS2)
2.2
Serial Control Interface
* * * * * I2C slave port Downloads EQ coefficients Volume, bass, treble, and mixer control DRC control Write only
2.3
Audio Processing
* * * * * * Programmable multiband digital parametric EQ (dynamically updateable) Programmable volume control (dynamically updateable) Soft mute software controlled Digital mixing of SDIN1 and SDIN2 with independent gain control Programmable bass and treble tone control (dynamically updateable) Dynamic range compression (DRC)
2.4
Power Supply
* * Digital supply voltage - DVDD, DVSS of 3.3 V Analog supply voltage - AVDD_PLL, AVSS_PLL of 3.3 V
32 fs serial input mode is left justified 16 bit only
2-1
2.5
Serial Audio Interface 2.5.1 I2S Serial Format
SCLK
LRCLK = fs
SDIN
X
MSB
LSB
X
MSB
LSB
SDOUT
X
MSB
LSB
X
MSB
LSB
Left Channel
Right Channel
Figure 2-1. I2S Compatible Serial Format
2.5.2
1. 2. 3. 4. 5. 6.
Protocol
LRCLK = Sampling frequency (fs) Left channel is transmitted when LRCLK is low. SCLK = 64 x LRCLK. SCLK is sometimes referred to as the bit clock. Serial data is sampled with the rising edge of SCLK. Serial data is transmitted on the falling edge of SCLK. LRCLK must have a 50% duty cycle.
2.5.3
1.
Implementation
LRCLK and SCLK are both inputs.
2.5.4
Timing
See Figure 4-1 for I2S timing.
2-2
2.6
Left-Justified Serial Format
SCLK
LRCLK = fs
SDIN
MSB
LSB
MSB
LSB
SDOUT
MSB
LSB
MSB
LSB
Left Channel
Right Channel
Figure 2-2. Left-Justified Serial Format
2.6.1
1. 2. 3. 4. 5. 6. 7.
Protocol
LRCLK = Sampling frequency (fs) Left channel is transmitted when LRCLK is high. The SDIN1 data is justified to the leading edge of the LRCLK. Serial data is sampled on the rising edge of SCLK. Serial data is transmitted on the falling edge of SCLK. SCLK = 32 LRCLK (32 fs SCLK is only supported for 16 bit data) or 64 LRCLK In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.6.2
1.
Implementation
LRCLK and SCLK are both inputs.
2.6.3
Timing
See Figure 4-1 for I2S timing.
2-3
2.7
Right-Justified Serial Format
SCLK
LRCLK = fs
SDIN1
X
MSB
LSB
X
MSB
LSB
SDOUT
X
MSB
LSB
X
MSB
LSB
Left Channel
Right Channel
Figure 2-3. Right-Justified Serial Format
2.7.1
1. 2. 3. 4. 5. 6. 7.
Protocol
LRCLK = Sampling frequency (fs) Left channel is transmitted when LRCLK is high. The SDIN1 data is justified to the trailing edge of the LRCLK. Serial data is sampled on the rising edge of SCLK. Serial data is transmitted on the falling edge of SCLK. SCLK = 64 LRCLK In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.7.2
1.
Implementation
LRCLK and SCLK are both inputs.
2.7.3
Timing
See Figure 4-1 for I2S timing.
2-4
2.8
System Clocks - Master Mode and Slave Mode
The TAS3001 allows multiple system clocking schemes. In this document, master mode indicates that the TAS3001 provides system clocks (LRCLK and SCLK) to other parts of the system. Slave mode indicates that a system master other than theTAS3001 provides system clocks (LRCLK and SCLK) to the TAS3001. These are depicted in Figures 2-4 and 2-5.
MCLK TAS3001 LRCLKOUT SCLKOUT SCLK LRCLK 23 24 TLC320AD77 (Codec)
9 Crystal Oscillator 10 11
MCLK LRCLK SCLK
Figure 2-4. Master Mode
MCLK
9 SPDIF 10 11
MCLK LRCLK SCLK SCLK LRCLK TAS3001 TLC320AD77 (Codec)
Figure 2-5. Slave Mode
2.9
Serial Control Interface
Control parameters for the TAS3001C are loaded with an I2C master interface. Information is loaded into the registers defined in Appendix A, Software Interface. The I2C bus uses two pins, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. This device may be addressed by sending a unique 7-bit slave address plus R/W bit (1 byte). All I2C compatible devices share the same pins via a bidirectional bus using a wire-ANDed connection. A pullup resistor must be used to set the high level on the bus. The TAS3001C operates in standard I2C mode up to 100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF. Additionally, the TAS3001C operates only in slave mode; therefore, at least one device connected to the I2C bus with this device must operate in master mode.
2.9.1
I2C Protocol
The bus standard uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop condition. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 2-6. These start and stop conditions for the I2C bus are required by standard protocol to be generated by the master. The master must also generate the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The slave holds the SDA bit low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master begins transmitting. After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the number of bytes that may be transmitted between a start and stop condition. When the last word has been transferred, the master must generate a stop condition to release the bus. A generic data transfer sequence is shown in Figure 2-6.
2-5
SDA
7 Bit Slave Address
R/W A
8 Bit Register Address (N)
A
8 Bit Register Data For Address (N)
A
8 Bit Register Data For Address (N)
A
76
5
4
3
21
0
76
5
4
3
21
0
76
5
4
3
21
0
76
5
4
3
21
0
SCL Start Stop
Figure 2-6. Typical I2C Data Transfer Sequence The definitions used by the I2C protocol are listed below. Transmitter Receiver Master Slave Multi-master Arbitration Synchronization The device that sends data The device that receives data The device that initiates a transfer, generates clock signals, and terminates the transfer The device addressed by the master More than one master can attempt to control the bus at the same time without corrupting the message. Procedure to ensure the message is not corrupted when two masters attempt to control the bus Procedure to synchronize the clock signals of two or more devices
2.9.2
Operation
The 7-bit address for the TAS3001C is 01101XX, where X is a programmable address bit. Using the CS1 and CS2 pins on the device, the two LSB address bits may be programmed. These four addresses are licensed I2C addresses and will not conflict with other licensed I2C audio devices. To communicate with the TAS3001C, the I2C master must use 01101XX. In addition to the 7-bit device address, subaddresses are used to direct communication to the proper memory location within the device. A complete table of subaddresses and control registers is provided in the Appendix A, Software Interface. For example, to change the bass setting to 10-dB gain, Section 2.8.2.1, Write Cycle shows how the subaddress and data are written to the I2C port: Table 2-1. I2C Address Byte
I2C ADDRESS BYTE 0x68 0x6A 0x6C 0x6E A6-A2 01101 01101 01101 01101 CS2(A1) 0 0 1 1 CS1(A0) 0 1 0 1 R/W 0 0 0 0
The TAS3001C is a write only device.
2-6
2.9.2.1
Write Cycle
When writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle. For example, if the volume control register with subaddress 04 (hex) is written to, six bytes of data must follow, otherwise the cycle will be incomplete. The correct number of bytes corresponding to each subaddress is shown in Appendix A, Software Interface.
Start Slave Address R/W A Subaddress A Data A Stop
FUNCTION Start Slave address R/W A Subaddress Data Start condition as defined in I2C 0110100 (CS1 = CS2 = 0) 0 (write)
DESCRIPTION
Acknowledgement as defined in I2C (slave) 00000110 (see Appendix A, Software Interface)
00011100 (see Appendix A, Software Interface) Stop Stop condition as defined in I2C NOTE: This table applies to serial data (SDA). Serial clock (SCL) information is not shown since the same conditions apply as well.
2.10 Filter Processor 2.10.1 Biquad Block
The biquad block consists of multiple digital biquad filters per channel organized in a cascade structure as shown in Figure 2-7. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has independent coefficients. Note that the filters are implemented with 32-bit arithmetic and 56-bit accuracy for some internal calculations.
Biquad 1 Biquad 2 Biquad N
Figure 2-7. Biquad Cascade Configuration
2.10.2
Filter Coefficients
The filter coefficients for the TAS3001C are downloaded through the I2C port and loaded into the biquad memory space. Digital audio data coming into the device is processed by the biquad filters and then output from the device usually to an external DAC. Any biquad filter may be downloaded and processed by the TAS3001C. The biquad structure that is used for the parametric equalization filters is as follows:
H(z)
-1 -2 + b0 ) b1z-1 ) b2z-2 a )a z )a z
0 1 2
NOTE: a0 is fixed at value 1 and is not downloadable
The coefficients for these filters are quantized and represented in 4.20 format - 4 bits for the integer part and 20 bits for the fractional part. In order to transmit them over I2C, it is necessary to separate each coefficient into three bytes. The first nibble of byte 2 is the integer part, and the second nibble of byte 2 and bytes 1 and 0 are the fractional parts.
2.11 Volume Control Functions
2.11.1 Soft Volume Update
The TAS3001C implements a TI proprietary soft volume update. This update allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume (18 dB to mute). The volume is adjustable by downloading a 4.16 (see NOTE) gain coefficient through the I2C interface. Tables converting the 4.16 coefficient to dB in a range from -70 dB to 18 dB in 0.5 dB increments are found in Table A-6.
2-7
4.16 values other than those listed in Table A-6 are also allowed.
2.11.2
Software Soft Mute
Mute is implemented by loading all zeros in the volume control register. This will cause the volume to ramp down over a maximum of 2048 samples to a final output of zero (- infinity dB).
2.11.3
Mixer Control
The TAS3001C is capable of mixing and muxing two channels of serial audio data. This is accomplished by loading values into the MIXER1 and MIXER2 control registers. The values loaded into these registers are in 4.20 (see NOTE) format. Table A-9 contains 4.20 numbers converted into dB for the range -70 dB to 18 dB, although any positive 4.20 number may be used. NOTE: The 4.N number is a two's complement number with 1 sign bit, 3 integer bits, and N bits of fraction. Only positive numbers should be used for the volume and gain controls. The formula for converting a 4.N number to dB is: dB = 20 LOG(X), where X is a positive 4.N number. To mute either channel, zeros are loaded into either of the mixer control registers. The mixer controls are updated instantly and may cause audible artifacts when updated dynamically outside of fast load mode.
2.11.4
Treble Control
The treble gain level may be adjusted within the range of 18 dB to -18 dB with 0.5 dB step resolution. The level changes are accomplished by downloading treble codes shown in Appendix A, Software Interface Section.
2.11.5
Bass Control
The bass gain level may be adjusted within the range of 18 dB to -18 dB with 0.5 dB step resolution. The level changes are accomplished by downloading bass codes shown in Appendix A, Software Interface.
2.11.6
Dynamic Range Compression
The TAS3001C provides the user with the ability to manage the dynamic range of the audio system. The dynamic range compressor receives data after the bass control block, and affects scaling after the volume control block. Refer to Figure 2-8. The compressor does not employ a delay as used in many common compressors. This makes the compressor appropriate for this low-cost application without significantly degrading performance since the saturation logic, which is applied after the compressor scale factor, serves as a hard limiter that will not allow the signal to extend beyond the available range. Of course, the compressor can be adjusted such that the signal will not generally reach the hard limit value.
Up to 2 Stereo Inputs 2nd Order IIR Filters (Parametric EQ) 2 Channel Stereo Mixer Dynamic Range Compressor Treble/Bass Soft Volume DRC Scale Factor Saturation Logic
Figure 2-8. TAS3001C Digital Signal Processing Block Diagram The compression threshold is adjustable in increments of 1/2 dB between 0 dB and approximately -36 dB. The compression ratio is set to 3:1.
2-8
OUTPUT (dB) Vref = 0 dB
Final Output = -8 dB
T = -12 dB
3:1 Compression Ratio
INPUT (dB) T = -12 dB 0 dB
Figure 2-9. DRC Example With Threshold = -12 dB From the DRC example shown in Figure 2-7, the formula for calculating the output with a given threshold and the fixed compression ratio of 3:1 is: Final output (dB) = [T (dB) + [Vref (dB) - T (dB)] x (1/CR)] Where CR = compression ratio = 3 T = Threshold (dB) = -12 dB Vref = Reference voltage (normally 0 dB) As show in Figure 2-7, with the threshold set to -12 dB, if the input exceeds this value, then the output will be compressed at a 3:1 ratio until the max input of 0 dB yields an output of -8 dB.
2.12 Device Initialization
2.12.1 Reset
The reset pin allows the device to be reset. That is, the TAS3001C returns to its default state as defined in this section. The device does not reset automatically when power is applied to the device. A reset is required after the following condition occurs: * Power is applied to any of the power pins. Since the MCR sets the serial mode and fast load, it is recommended that it is written to only once, following reset. However, there are systems in which the user modifies the MCR without having to reset it first. Required conditions for a successful reset: * * MCLK is running RESET is low for a minimum of 1 s.
2.12.2
Device Power On Plus Reset
When power is applied to the TAS3001C, the device will power up in an unknown state. It must be reset before the device will be in a known state. Upon reset, the TAS3001C will initialize to its default state (fast load mode). The main control register will be configured to 1XXXXXXX, where X is not initialized, as shown in Figure 2-10 (see Appendix A for complete description of MCR). Only the fast load bit will be set to a 1
2-9
in the main control register. This puts the device into fast load mode (see Section 2.12.3, Fast Load). All random access memory (RAM) will be initialized (previous data will be overwritten).
Bit 7 1 X X X X X X X Bit 0
Figure 2-10. Main Control Register (MCR) The I2C address pins (CS1 and CS2) should be driven or biased to set the TAS3001C to a known I2C address. This also ensures the I2C port will be active immediately after the reset initialization phase. Furthermore, when implementing a three or six speaker system, the CS1 and CS2 pins must always be driven or set to unique addresses on all devices. The I2C port will be powered up but will not acknowledge any I2C bus activity until the entire device has been initialized. This initialization typically takes 5 ms.
2.12.3
* * * *
Fast Load
All of the parametric EQ will be initialized to 0 dB (all-pass). The tone (bass/treble) will be set to 0 dB. The mix function will set SDIN1 to 0 dB and SDIN2 to mute (no-pass). The volume will be set to mute.
Upon entering fast load mode, the following occurs as part of initialization:
While in fast load mode, it is possible to update the parametric EQ without any audio processing delay. The audio processor will be paused while the RAM is being updated in this mode. It is recommended that parametric EQ be downloaded in this mode. Bass and treble may not be downloaded in this mode. Mixer1 and Mixer2 registers may be downloaded in this mode or normal mode (FL bit = 0). It is not recommended to download the volume control register and mixer registers in this mode. Once the download is complete, the fast load bit needs to be cleared by writing a 0 into bit 7 of the main control register. This puts the TAS3001C into normal mode. NOTE: When writing to the FL bit in the MCR, the serial audio format is also written to at this time. However, the device will not recognize any serial audio until it has returned to normal mode. Entering fast load mode by resetting the TAS3001C is recommended. Once back in normal mode, treble, bass, and volume control may be downloaded to complete device setup.
2-10
3 Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
Supply voltage range, AVDD_PLL, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.2 V Digital Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3C Lead temperature from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.8C ESD tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Human Body Model per Method 3015.2 of MIL-STD-883B.
3.2
Recommended Operating Conditions
TEST CONDITIONS MIN 3 3 VDD = 3.3 V, No load SDA, SCL 0 NOM 3.3 3.3 20 400 25 70 MAX 3.6 3.6 UNIT V V mA pF C
PLL supply voltage, AVDD Digital IC supply voltage, DVDD PLL and digital IC supply current, IDD Capacitive load for each bus line CL(bus) Operating free-air temperature, TA
3.3
VIH VIL VOH VOL IIH IIL IOZH IOZL
Static Digital Specifications, TA = 0C to 70C, all VDD = 3.3 V 0.3 V
PARAMETER High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current SCL, SDA SCL, SDA IO = -1 mA IO = 4 mA TEST CONDITIONS MIN 2 -0.3 2.4 -10 -10 -10 -10 TYP MAX VDD +0.3 0.8 VDD 0.4 10 10 10 10 UNIT V V V V A A A A
3-1
3.4
Audio Serial Port Timing Requirements (see Note 1)
PARAMETER Frequency, SCLK Frequency, SCLKOUT Frequency, LRCLKOUT Rise time, SCLK (see Note 2) Fall time, SCLK (see Note 2) Delay time, SCLK rising to LRCLK edge (see Note 3) Delay time, SDOUT valid from SCLK falling Setup time, SDIN before SCLK rising edge 10 MIN 32 fs TYP MAX 64 fs UNIT MHz MHz MHz 25 25 ns ns ns 100 ns ns ns
f(SCLK) f(SCLKOUT) f(LRCLKOUT) tr(SCLK) tf(SCLK) td(SLR) td(SDOUT) tsu(SDIN)
MCLK 4 MCLK 256 5 16.3 5 50 16.3 T SCLK 2
th(SDIN) Hold time, SDIN from SCLK rising edge 100 Valid in 16-bit left justified mode only. NOTES: 1. Timing relative to 256 fs MCLK. 2. SCLK rising and falling are measured from 20% to 80%. 3. The rising edge of SCLK must not occur at the same time as either edge of LRCLK.
3.5
f(scl) tBUF
I2C Serial Port Timing Requirements
PARAMETER SCL clock frequency Bus free time between start and stop Pulse duration, SCL clock low (see Note 4) Pulse duration, SCL clock high (see Note 5) Hold time, repeated start Setup time, repeated start Hold time, data Setup time, data Rise time for SDA and SCL Fall time for SDA and SCL MIN 0 4.7 4.7 4 4 4.7 0 250 1000 300 20 MAX 100 UNIT kHz s s s s s s ns ns ns
tw(low) tw(high) th(STA) tsu(STA) th(DAT) tsu(DAT) tr tf
tsu(STO) Setup time for stop condition 4 s A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. NOTES: 4. tw(low) is measured from the end of tf to the beginning of tr. 5. tw(high) is measured from the end of tr to the beginning of tf.
3-2
4 Parameter Measurement Information
tc(SCLK) SCLK td(SLR) LRCLK td(SDOUT) SDOUT td(SLR) tf(SCLK) tr(SCLK)
SDIN
P
S
SDA tBUF
SCL Data Line Stable
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
tsu(SDIN) Valid th(STA) tr
th(SDIN)
Figure 4-1. I2S Timing
P
th(DAT) tf
th(STA) tsu(DAT) tsu(STA) tsu(STO)
Change of Data Allowed
Figure 4-2. I2C Timing
4-1
4-2
5 Application Information
Typical applications for the TAS3001C include: * * * * * * PC laptop audio Digital speakers Multimedia monitors with speakers USB audio devices MP3 players Portable stereo
5-1
5-2
Appendix A Software Interface
Table A-1. Register Map
REGISTER Reserved MCR DRC Reserved Volume Treble Bass Mixer 1 Mixer 2 Reserved Left Biquad 0 Left Biquad 1 Left Biquad 2 Left Biquad 3 Left Biquad 4 Left Biquad 5 Reserved Reserved ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 15 B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0) A2(23-16), A2(15-8), A2(7-0) 6 1 1 3 3 VL(23-16), VL(15-8), VL(7-0), VR(23-16), VR(15-8), VR(7-0) T(7-0) B(7-0) S(23-16), S(15-8), S(7-0) S(23-16), S(15-8), S(7-0) 1 2 C(7-0) See DRC section NO. of BYTES BYTE DESCRIPTION
0x0B
15
0x0C
15
0x0D
15
0x0E
15
0x0F
15
0x10 0x11
Reserved 0x12 The volume value is a 4.16 coefficient. In order to transmit it over I2C, it is necessary to separate the value into three bytes. Byte 2 is the integer part and bytes 1 and 0 are the fractional parts. The mixer gain values and biquad coefficients are 4.20 coefficients. In order to transmit them over I2C, it is necessary to separate the value into three bytes. The first nibble of byte 2 is the integer part and the second nibble of byte 2 and bytes 1 and 0 being the fractional parts. A-1
Table A-1. Register Map (Continued)
REGISTER Right Biquad 0 Right Biquad 1 Right Biquad 2 Right Biquad 3 Right Biquad 4 Right Biquad 5 Reserved ADDRESS 0x13 NO. of BYTES 15 BYTE DESCRIPTION B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0) B0(23-16), B0(15-8), B0(7-0), B1(23-16), B1(15-8), B1(7-0), B2(23-16), B2(15-8), B2(7-0), A1(23-16), A1(15-8), A1(7-0), A2(23-16), A2(15-8), A2(7-0)
0x14
15
0x15
15
0x16
15
0x17
15
0x18
15
0x19 to 0xFF
The volume value is a 4.16 coefficient. In order to transmit it over I2C, it is necessary to separate the value into three bytes. Byte 2 is the integer part and bytes 1 and 0 are the fractional parts. The mixer gain values and biquad coefficients are 4.20 coefficients. In order to transmit them over I2C, it is necessary to separate the value into three bytes. The first nibble of byte 2 is the integer part and the second nibble of byte 2 and bytes 1 and 0 being the fractional parts.
A-2
Main Control Register (MCR)
Configuration of the digital serial audio interface is set up through the main control register as shown below. Bits F0 and F1 allow selection between three different serial data formats (right justified = 00, right justified = 01, and I2S standard = 10). The output serial port mode set by E0 and E1 must be set to the same value as the input serial port mode set by F0 and F1. Bits W0 and W1 allow selection between three different word widths (16-bit word = 00, 18-bit word = 01, and 20-bit word = 10). The SC bit selects 32fs (0) or 64fs (1) bit clock. The FL bit is primarily for use during initialization and is defined in the device initialization section. See Section 2.8 Serial Control Interface for additional information on how to address the main control register. Table A-2. Main Control Register (MCR)
C7 FL 1 C6 SC x C5 E1 x C4 E0 x C3 F1 x C2 F0 x C1 W1 x C0 W0 x
Table A-3. Main Control Register (MCR) Description
BIT C(7) C(6) C(5,4) DESCRIPTOR FL SC E(1,0) FUNCTION Fast load SCLK frequency Output serial port mode VALUE 0 1 (default) 0 1 00 01 10 11 C(3,2) F(1,0) Input serial port mode 00 01 10 11 C(1,0) W(1,0) Serial port word length 00 01 10 11 FUNCTION Normal operating mode Fast load mode SCLK = 32 fs SCLK = 64 fs Left justified Right justified I2S Reserved Left justified Right justified I2S Reserved 16 bit 18 bit 20 bit Reserved
Table A-4. DRC Interface (Byte 1)
B7 CR1 BIT B0 B7, B6 B6 CR0 B5 X B4 X FUNCTION Enable DRC Compression ratio B3 X B2 X VALUE 0 1 CR1, CR0 00 01 10 11 B1 X B0 EN FUNCTION Disabled Enabled Invalid Invalid Invalid 3:1 A-3
DESCRIPTOR EN
Table A-5. DRC Interface (Byte 2) DRC Interface Byte 2 sets the threshold value. It is a 4.4 number and should always be greater than 9.0 (10010000). Legal values range from hex 91 to F0.
BYTE 2 (BITS) MIN 10010000 10010001 10100000 10110000 11000000 11010000 11100000 11110000 BYTE 2 (BITS) MAX 10010000 10011111 10101111 10111111 11001111 11011111 11101111 11110000 HEX MIN - MAX 90 91 - 9F A0 - AF B0 - BF C0 - CF D0 - DF E0 - EF F0 DECIMAL MIN - MAX 9.0 9.0625 - 9.9375 10.0 - 10.9375 11.0 - 11.9375 12.0 - 12.9375 13.0 - 13.9375 14.0 - 14.9375 15.0 DESCRIPTION ILLEGAL 91 ~ -36 dB A0 = -30 dB B0 = -24 dB C0 = -18 dB D0 = -12 dB E0 = -6 dB F0 = 0 dB
A-4
Table A-6. Volume Gain Values [The gain error is less than 0.12 dB (excluding mute)]
GAIN (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VOLUME V(23-16), V(15-8), V(7-0) 07, F1, 7B 07, 7F, BB 07, 14, 57 06, AE, F6 06, 4F, 40 05, F4, E5 05, 9F, 98 05, 4F, 10 05, 03, 0A 04, BB, 44 04, 77, 83 04, 37, 8B 03, FB, 28 03, C2, 25 03, 8C, 53 03, 59, 83 03, 29, 8B 02, FC, 42 02, D1, 82 02, A9, 25 02, 83, 0B 02, 5F, 12 02, 3D, 1D 02, 1D, 0E 01, FE, CA 01, E2, 37 01, C7, 3D 01, AD, C6 01, 95, BC 01, 7F, 09 01, 69, 9C 01, 55, 62 01, 42, 49 01, 30, 42 01, 1F, 3D 01, 0F, 2B GAIN (dB) 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 VOLUME V(23-16), V(15-8), V(7-0) 01, 00, 00 00, F1, AE 00, E4, 29 00, D7, 66 00, CB, 59 00, BF, F9 00, B5, 3C 00, AB, 19 00, A1, 86 00, 98, 7D 00, 8F, F6 00, 87, E8 00, 80, 4E 00, 79, 20 00, 72, 5A 00, 6B, F4 00, 65, EA 00, 60, 37 00, 5A, D5 00, 55, C0 00, 50, F4 00, 4C, 6D 00, 48, 27 00, 44, 1D 00, 40, 4E 00, 3C, B5 00, 39, 50 00, 36, 1B 00, 33, 14 00, 30, 39 00, 2D, 86 00, 2A, FA 00, 28, 93 00, 26, 4E 00, 24, 29 00, 22, 23 00, 20, 3A GAIN (dB) -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 VOLUME V(23-16), V(15-8), V(7-0) 00, 1E, 6D 00, 1C, B9 00, 1B, 1E 00, 19, 9A 00, 18, 2B 00, 16, D1 00, 15, 8A 00, 14, 56 00, 13, 33 00, 12, 20 00, 11, 1C 00, 10, 27 00, 0F, 40 00, 0E, 65 00, 0D, 97 00, 0C, D5 00, 0C, 1D 00, 0B, 6F 00, 0A, CC 00, 0A, 31 00, 09, 9F 00, 09, 15 00, 08, 93 00, 08, 18 00, 07, A5 00, 07, 37 00, 06, D0 00, 06, 6E 00, 06, 12 00, 05, BB 00, 05, 69 00, 05, 1C 00, 04, D2 00, 04, 8D 00, 04, 4C 00, 04, 0F 00, 03, D5 GAIN (dB) -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5 -54.0 -54.5 -55.0 VOLUME V(23-16), V(15-8), V(7-0) 00, 03, 9E 00, 03, 6A 00, 03, 39 00, 03, 0B 00, 02, DF 00, 02, B6 00, 02, 8F 00, 02, 6B 00, 02, 48 00, 02, 27 00, 02, 09 00, 01, EB 00, 01, D0 00, 01, B6 00, 01, 9E 00, 01, 86 00, 01, 71 00, 01, 5C 00, 01, 48 00, 01, 36 00, 01, 25 00, 01, 14 00, 01, 05 00, 00, F6 00, 00, E9 00, 00, DC 00, 00, CF 00, 00, C4 00, 00, B9 00, 00, AE 00, 00, A5 00, 00, 9B 00, 00, 93 00, 00, 8B 00, 00, 83 00, 00, 7B 00, 00, 75 A-5
Table A-6. Volume Gain Values [The gain error is less than 0.12 dB (excluding mute)] (Continued)
GAIN (dB) -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 6E 00, 00, 68 00, 00, 62 00, 00, 5D 00, 00, 57 00, 00, 53 00, 00, 4E 00, 00, 4A GAIN (dB) -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 45 00, 00, 42 00, 00, 3E 00, 00, 3A 00, 00, 37 00, 00, 34 00, 00, 31 00, 00, 2E GAIN (dB) -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 2C 00, 00, 29 00, 00, 27 00, 00, 25 00, 00, 23 00, 00, 21 00, 00, 1F 00, 00, 1D GAIN (dB) -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute VOLUME V(23-16), V(15-8), V(7-0) 00, 00, 1C 00, 00, 1A 00, 00, 19 00, 00, 17 00, 00, 16 00, 00, 15 00, 00, 00
Table A-7. Treble Control Register (Both left and right channel will be given the same treble gain setting)
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 T(7-0) (hex) 0x01 0x09 0x10 0x16 0x1C 0x22 0x28 0x2D 0x32 0x36 0x3A 0x3E 0x42 0x45 0x49 0x4C 0x4F 0x52 0x55 Gain (dB) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 T(7-0) (hex) 0x57 0x5A 0x5C 0x5E 0x60 0x62 0x63 0x65 0x66 0x68 0x69 0x6B 0x6C 0x6D 0x6E 0x70 0x71 0x72 Gain (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 T(7-0) (hex) 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 Gain (dB) -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 T(7-0) (hex) 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96
A-6
Table A-8. Bass Control Register (Both left and right channel will be given the same bass setting)
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 B(7-0) (hex) 0x01 0x03 0x06 0x08 0x0A 0x0B 0x0D 0x0F 0x10 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1C 0x1F 0x21 Gain (dB) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 B(7-0) (hex) 0x23 0x25 0x26 0x28 0x29 0x2B 0x2C 0x2E 0x30 0x31 0x33 0x35 0x36 0x38 0x39 0x3B 0x3C 0x3E Gain (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 B(7-0) (hex) 0x40 0x42 0x44 0x46 0x49 0x4B 0x4D 0x4F 0x51 0x53 0x54 0x55 0x56 0x58 0x59 0x5A 0x5C 0x5D Gain (dB) -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 B(7-0) (hex) 0x5F 0x61 0x64 0x66 0x69 0x6B 0x6D 0x6E 0x70 0x72 0x74 0x76 0x78 0x7A 0x7D 0x7F 0x82 0x86
Table A-9. Mixer1 and Mixer2 Gain Values [The gain error is less than 0.12 dB (excluding mute)]
Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 Gain S(23-16), S(15-8), S(7-0) 7F, 17, AF 77, FB, AA 71, 45, 75 6A, EF, 5D 64, F4, 03 5F, 4E, 52 59, F9, 80 54, F1, 06 50, 30, A1 4B, B4, 46 47, 78, 28 43, 78, B0 3F, B2, 78 3C, 22, 4C Gain (dB) 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 Gain S(23-16), S(15-8), S(7-0) 38, C5, 28 35, 98, 2F 32, 98, B0 2F, C4, 20 2D, 18, 18 2A, 92, 54 28, 30, AF 25, F1, 25 23, D1, CD 21, D0, D9 1F, EC, 98 1E, 23, 6D 1C, 73, D5 1A, DC, 61 Gain (dB) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 Gain S(23-16), S(15-8), S(7-0) 19, 5B, B8 17, F0, 94 16, 99, C0 15, 56, 1A 14, 24, 8E 13, 04, 1A 11, F3, C9 10, F2, B4 10, 00, 00 0F, 1A, DF 0E, 42, 90 0D, 76, 5A 0C, B5, 91 0B, FF, 91 Gain (dB) -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 Gain S(23-16), S(15-8), S(7-0) 0B, 53, BE 0A, B1, 89 0A, 18, 66 09, 87, D5 08, FF, 59 08, 7E, 80 08, 04, DC 07, 92, 07 07, 25, 9D 06, BF, 44 06, 5E, A5 06, 03, 6E 05, AD, 50 05, 5C, 04 A-7
Table A-9. Example Mixer1 and Mixer2 Gain Values [The gain error is less than 0.12 dB (excluding mute)] (Continued)
Gain (dB) -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 Gain S(23-16), S(15-8), S(7-0) 05, 0F, 44 04, C6, D0 04, 82, 68 04, 41, D5 04, 04, DE 03, CB, 50 03, 94, FA 03, 61, AF 03, 31, 42 03, 03, 8A 02, D8, 62 02, AF, A3 02, 89, 2C 02, 64, DB 02, 42, 93 02, 22, 35 02, 03, A7 01, E6, CF 01, CB, 94 01, B1, DE 01, 99, 99 01, 82, AF 01, 6D, 0E 01, 58, A2 01, 45, 5B 01, 33, 28 01, 21, F9 01, 11, C0 01, 02, 70 00, F3, FB Gain (dB) -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 Gain S(23-16), S(15-8), S(7-0) 00, E6, 55 00, D9, 73 00, CD, 49 00, C1, CD 00, B6, F6 00, AC, BA 00, A3, 10 00, 99, F1 00, 91, 54 00, 89, 33 00, 81, 86 00, 7A, 48 00, 73, 70 00, 6C, FB 00, 66, E3 00, 61, 21 00, 5B, B2 00, 56, 91 00, 51, B9 00, 4D, 27 00, 48, D6 00, 44, C3 00, 40, EA 00, 3D, 49 00, 39, DB 00, 36, 9E 00, 33, 90 00, 30, AE 00, 2D, F5 00, 2B, 63 Gain (dB) -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5 -54.0 -54.5 -55.0 Gain S(23-16), S(15-8), S(7-0) 00, 28, F5 00, 26, AB 00, 24, 81 00, 22, 76 00, 20, 89 00, 1E, B7 00, 1C, FF 00, 1B, 60 00, 19, D8 00, 18, 65 00, 17, 08 00, 15, BE 00, 14, 87 00, 13, 61 00, 12, 4B 00, 11, 45 00, 10, 4E 00, 0F, 64 00, 0E, 88 00, 0D, B8 00, 0C, F3 00, 0C, 3A 00, 0B, 8B 00, 0A, E5 00, 0A, 49 00, 09, B6 00, 09, 2B 00, 08, A8 00, 08, 2C 00, 07, B7 00, 07, 48 Gain (dB) -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute Gain S(23-16), S(15-8), S(7-0) 00, 06, E0 00, 06, 7D 00, 06, 20 00, 05, C9 00, 05, 76 00, 05, 28 00, 04, DE 00, 04, 98 00, 04, 56 00, 04, 18 00, 03, DD 00, 03, A6 00, 03, 72 00, 03, 40 00, 03, 12 00, 02, E6 00, 02, BC 00, 02, 95 00, 02, 70 00, 02, 4D 00, 02, 2C 00, 02, 0D 00, 01, F0 00, 01, D4 00, 01, BA 00, 01, A1 00, 01, 8A 00, 01, 74 00, 01, 5F 00, 01, 4B 00, 00, 00
A-8
Appendix B Mechanical Data
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 B-1
B-2
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