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TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230E - JULY 1999 - REVISED JUNE 2000
features
applications
D D D D D D
Dual 12-Bit Voltage Output DAC Programmable Settling Time - 2.5 s in Fast Mode - 12 s in Slow Mode Compatible With TMS320 and SPITM Serial Ports Differential Nonlinearity <0.5 LSB Typ Monotonic Over Temperature Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards
D D D D D
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
D OR JG PACKAGE (TOP VIEW)
DIN SCLK CS OUTA
1 2 3 4
8 7 6 5
VDD OUTB REF AGND
description
The TLV5618A is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is compatible with TMS320, SPITM, QSPITM, and MicrowireTM serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation.
NC
FK PACKAGE (TOP VIEW)
3
2
1
NC SCLK NC CS NC
VDD NC
20 19 18 NC 17 OUTB 16 NC 15 REF 14 NC
DIN OUTA
4 5 6 7 8 9 10 11 12 13
NC
NC
NC
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges. The TLV5618AC is characterized for operation from 0C to 70C. The TLV5618AI is characterized for operation from - 40C to 85C. The TLV5618AQ is characterized for operation from - 40C to 125C. The TLV5618AM is characterized for operation from - 55C to 125C.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C - 40C to 125C - 55C to 125C SOIC (D) TLV5618ACD TLV5618AID TLV5618AQD TLV5618AQDR -- CERAMIC DIP (JG) -- -- -- TLV5618AMJG 20 PAD LCCC (FK) -- -- -- TLV5618AMFK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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AGND
NC
1
TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230E - JULY 1999 - REVISED JUNE 2000
functional block diagram
REF AGND VDD
Power-On Reset
Power and Speed Control 2
x2 DIN 12 SCLK Serial Interface and Control 12-Bit DAC A Latch 12
OUTA
12 Buffer 12 12 x2
CS
12-Bit DAC B Latch
OUTB
Terminal Functions
TERMINAL NAME AGND CS DIN OUTA OUTB REF SCLK VDD NO. 5 3 1 4 7 6 2 8 I/O/P P I I O O I I P Ground Chip select. Digital input active low, used to enable/disable inputs. Digital serial data input DAC A analog voltage output DAC B analog voltage output Analog reference voltage input Digital serial clock input Positive power supply DESCRIPTION
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SLAS230E - JULY 1999 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5618AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5618AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C TLV5618AQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C TLV5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE D FK JG TA 25C POWER RATING 635 mW 1375 mW 1050 mW DERATING FACTOR ABOVE TA = 25C 5.08 mW/C 11.00 mW/C 8.40 mW/C TA = 70C POWER RATING 407 mW 880 mW 672 mW TA = 85C POWER RATING 330 mW 715 mW 546 mW TA = 125C POWER RATING 127 mW 275 mW 210 mW
This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). Thermal resistances are not production tested and are for informational purposes only.
recommended operating conditions
MIN Supply voltage VDD voltage, Power on reset, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal Load resistance, RL Load capacitance, CL Clock frequency, fCLK TLV5618AC Operating free-air temperature, TA free air temperature TLV5618AI TLV5618AQ TLV5618AM 0 - 40 - 40 - 55 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) VDD = 5 V VDD = 3 V 4.5 2.7 0.55 2 0.8 AGND AGND 2 100 20 70 85 125 125 C 2.048 1.024 VDD -1.5 VDD - 1.5 NOM 5 3 MAX 5.5 3.3 2 V V V V V k pF MHz UNIT V
NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD-0.4 V)/2 causes clipping of the transfer function.
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TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230E - JULY 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER IDD Power supply current y Power down supply current PSRR Power supply rejection ratio Zero scale, See Note 2 Full scale, See Note 3 TEST CONDITIONS No load, All inputs = AGND or VDD, DAC latch = 0x800 Fast Slow MIN TYP 1.8 0.8 1 -65 -65 MAX 2.3 mA 1 A dB UNIT
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin)/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin)/VDDmax]
static DAC specifications
PARAMETER Resolution INL DNL EZS EZS TC EG EG TC Integral nonlinearity Differential nonlinearity Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient Gain error Gain-error temperature coefficient See Note 4 See Note 5 See Note 6 See Note 7 See Note 8 See Note 9 1 3 0.6 TEST CONDITIONS MIN 12 2 0.5 4 1 12 TYP MAX UNIT bits LSB LSB mV ppm/C % full scale V ppm/C
NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero-code and full-scale errors. 5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/2Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k. 9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) - Eg (Tmin)]/2Vref x 106/(Tmax - Tmin).
output specifications
PARAMETER VO Output voltage range Output load regulation accuracy TEST CONDITIONS RL = 10 k VO = 4.096 V, 2.048 V RL = 2 k MIN TYP MAX VDD-0.4 0.29 UNIT V % FS
reference input
PARAMETER VI RI CI Input voltage range Input resistance Input capacitance Fast Reference input bandwidth Reference feedthrough REF = 0.2 Vpp + 1.024 V dc 02 1 024 REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow TEST CONDITIONS MIN 0 10 5 1.3 525 - 80 TYP MAX VDD-1.5 UNIT V M pF MHz kHz dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
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SLAS230E - JULY 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)
digital inputs
PARAMETER IIH IIL Ci High-level digital input current Low-level digital input current Input capacitance TEST CONDITIONS VI = VDD VI = 0 V MIN -1 8 TYP MAX 1 UNIT A A pF
analog output dynamic performance
PARAMETER ts(FS) (FS) ts(CC) (CC) SR Output settling time, full scale time Output settling time, code to code time Slew rate Glitch energy SNR SINAD THD SFDR Signal-to-noise ratio Signal-to-noise + distortion Total harmonic distortion Spurious free dynamic range fs = 102 kSPS, fout = 1 kHz, , , RL = 10 k, CL = 100 pF TEST CONDITIONS RL = 10 k, , See Note 11 RL = 10 k, , See Note 12 RL = 10 k, , See Note 13 DIN = 0 to 1, CS = VDD CL = 100 pF, , CL = 100 pF, , CL = 100 pF, , Fast Slow Fast Slow Fast Slow FCLK = 100 kHz, MIN TYP 1 3 1 2 3 0.5 5 76 68 -68 72 dB MAX 3 10 UNIT s s V/s nV-s
NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
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digital input timing requirements
MIN tsu(CS-CK) tsu(C16-CS) twH twL tsu(D) (D) th(D) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge before CS rising edge SCLK pulse width high SCLK pulse width low Setup time data ready before SCLK falling edge time, Hold time, data held valid after SCLK falling edge C and I suffixes Q and M suffixes 10 10 25 25 10 8 5 NOM MAX UNIT ns ns ns ns ns ns
timing requirements
twL twH
SCLK
X
1 tsu(D) th(D)
2
3
4
5 15
16
X
DIN
X
D15
D14
D13
D12
D1
D0
X tsu(C16-CS)
tsu(CS-CK)
CS
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs LOAD CURRENT
2.050 3 V Slow Mode, SOURCE 4.105 VDD=3 V VREF=1 V Full scale VO - Output Voltage - V
OUTPUT VOLTAGE vs LOAD CURRENT
5 V Slow Mode, SOURCE 4.100 4.095 VDD=5 V VREF=2 V Full scale
2.048 VO - Output Voltage - V 2.046 3 V Fast Mode, SOURCE
5 V Fast Mode, SOURCE
2.044 2.042 2.040 2.038 2.036
4.090 4.085 4.080 4.075 4.070 0.00 -0.02 -0.04-0.10 -0.20 -0.41 -1.02 -2.05 -4.10 Load Current - mA
0.00 -0.01 -0.02-0.05 -0.10 -0.20 -0.51 -1.02 -2.05 Load Current - mA
Figure 2
OUTPUT VOLTAGE vs LOAD CURRENT
0.20 0.18 0.16 VO - Output Voltage - V 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0.00 0.01 0.02 0.05 0.10 0.20 0.51 1.02 2.05 Load Current - mA 0.05 0.00 3 V Fast Mode, SINK VDD=3 V VREF=1 V Zero scale VO - Output Voltage - V 3 V Slow Mode, SINK 0.35 VDD=5 V VREF=2 V Zero scale
Figure 3
OUTPUT VOLTAGE vs LOAD CURRENT
0.30 0.25
5 V Slow Mode, SINK
0.20 0.15 5 V Fast Mode, SINK 0.10
0.00 0.02 0.04 0.10 0.20 0.41 1.02 2.05 4.09 Load Current - mA
Figure 4
Figure 5
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SLAS230E - JULY 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
1.8 1.6 I DD - Supply Current - mA 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 Slow Mode VDD=3 V VREF=1 V Full scale 1.8 1.6 Fast Mode I DD - Supply Current - mA 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 Slow Mode VDD=5 V VREF=2 V Full scale Fast Mode
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 6
TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB -10 -20 -30 -40 -50 3 V Fast Mode -60 -70 5 V Fast Mode -80 -90 1 10 f - Frequency - kHz 100 VREF = 1 V + 1 VP/P Sinewave, Output Full Scale 0 -10 THD - Total Harmonic Distortion - dB -20 -30 -40
Figure 7
TOTAL HARMONIC DISTORTION vs FREQUENCY
VREF = 1 V + 1 VP/P Sinewave, Output Full Scale
3 V Slow Mode -50 -60 -70 -80 -90 1 10 f - Frequency - kHz 100 5 V Slow Mode
Figure 8
Figure 9
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR vs DIGITAL CODE
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4 0 512 1024 1536 2048 Digital Code 2560 3072 3584 4096
INL - Integral Nonlinearity Error - LSB
Figure 10
DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL CODE
DNL - Differential Nonlinearity - LSB 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1 0 1024 2048 Digital Code 3072 4096
Figure 11
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APPLICATION INFORMATION general function
The TLV5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power-on reset initially puts the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPITM, and MicrowireTM.
TMS320 DSP FSX DX CLKX TLV5618A CS DIN SCLK SPI I/O MOSI SCK TLV5618A CS DIN SCLK Microwire I/O SO SK TLV5618A CS DIN SCLK
Figure 12. Three-Wire Interface Notes on SPITM and MicrowireTM: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPITM and MicrowireTM) two write operations must be performed to program the TLV5618A. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by: f sclkmax
+t
whmin
)t
1
wlmin
+ 20 MHz
wlmin
The maximum update rate is: f updatemax
+ 16
1 t whmin
)t
+ 1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5618A should also be considered.
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APPLICATION INFORMATION data format
The 16-bit data word for the TLV5618A consists of two parts:
D D
D15 R1
Program bits New data
D14 SPD D13 PWR D12 R0
(D15..D12) (D11..D0)
D11 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 12 Data bits
SPD: Speed control bit 1 fast mode 0 slow mode PWR: Power control bit 1 power down 0 normal operation On power up, SPD and PWD are reset to 0 (slow mode and normal operation) The following table lists all possible combination of register-select bits: register-select bits
R1 0 0 1 1 R0 0 1 0 1 REGISTER Write data to DAC B and BUFFER Write data to BUFFER Write data to DAC A and update DAC B with BUFFER content Reserved
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value:
examples of operation
D
D15 1
Set DAC A output, select fast mode: Write new DAC A value and update DAC A output:
D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC A output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
D
D15 0
Set DAC B output, select fast mode: Write new DAC B value to BUFFER and update DAC B output:
D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New BUFFER content and DAC B output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
D
D15 0
Set DAC A value, set DAC B value, update both simultaneously, select slow mode: 1. Write data for DAC B to BUFFER:
D14 0 D13 0 D12 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC B value
2. Write new DAC A value and update DAC A and B simultaneously:
D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC A value
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APPLICATION INFORMATION examples of operation (continued)
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
D
D15 X
Set power-down mode:
D14 X D13 1 D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
X = Don't care
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.
Output Voltage
0V Negative Offset DAC Code
Figure 13. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
definitions of specifications and terminology
integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
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definitions of specifications and terminology (continued)
zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
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MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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MECHANICAL DATA
FK (S-CQCC-N**)
28 TERMINALS SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.740 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
1
2
3
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / C 11/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold-plated. Falls within JEDEC MS-004
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
MECHANICAL DATA
SLAS230E - JULY 1999 - REVISED MAY 2000
MECHANICAL DATA
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
1
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
0-15
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
SLAS230E - JULY 1999 - REVISED MAY 2000
MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
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Copyright (c) 2000, Texas Instruments Incorporated

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