View SLAS236A_1002387.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
features
D D D D D D D D D D D
D PACKAGE (TOP VIEW)
Dual 8-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: 0.8 s in Fast Mode , 2.8 s in Slow Mode Compatible With TMS320 and SPITM Serial Ports Differential Nonlinearity <0.1 LSB Typ Monotonic Over Temperature
DIN SCLK CS OUTA
1 2 3 4
8 7 6 5
VDD OUTB REF AGND
applications
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
description
The TLV5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows glueless interface to TMS320 and SPITM, QSPITM, and MicrowireTM serial ports. It is programmed with a 16-bit serial string containing 2 control and 8 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5626 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SOIC (D) TLV5626CD TLV5626ID
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
functional block diagram
REF PGA With Output Enable Voltage Bandgap Power and Speed Control 2 2 2-Bit Control Latch DIN 8 SCLK Serial Interface and Control 8-Bit DAC A Latch 8 AGND VDD
Power-On Reset
x2
OUTA
8 Buffer 8 8 x2
CS
8-Bit DAC B Latch
OUTB
Terminal Functions
TERMINAL NAME AGND CS DIN OUTA OUTB REF SCLK VDD NO. 5 3 1 4 7 6 2 8 I/O/P P I I I O I/O I P Ground Chip select. Digital input active low, used to enable/disable inputs Digital serial data input DAC A analog voltage output DAC B analog voltage output Analog reference voltage input/output Digital serial clock input Positive power supply DESCRIPTION
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5626C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5626I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage VDD voltage, Power on threshold voltage, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal Load resistance, RL Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA free air temperature TLV5626C TLV5626I 0 -40 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) VDD = 5 V VDD = 3 V 4.5 2.7 0.55 2 0.8 AGND AGND 2 100 20 70 85 2.048 1.024 VDD -1.5 VDD - 1.5 NOM 5 3 MAX 5.5 3.3 2 UNIT V V V V V V V k pF MHz C
NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD - 0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS VDD = 5 V, Int. ref. No load, All inputs = AGND or VDD, DAC latch = 0x800 VDD = 3 V, Int. ref. VDD = 5 V, Ext. ref. VDD = 3 V, Ext. ref. Power-down supply current PSRR Power supply rejection ratio Zero scale, See Note 2 Full scale, See Note 3 Fast Slow Fast Slow Fast Slow Fast Slow MIN TYP 4.2 2 3.7 1.7 3.8 1.7 3.4 1.4 1 -65 -65 MAX 7 3.6 6.3 3.0 6.3 3.0 5.7 2.6 UNIT mA mA mA mA mA mA mA mA A dB
IDD
Power supply current
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax]
static DAC specifications
PARAMETER Resolution INL DNL EZS EZS TC EG Integral nonlinearity, end point adjusted Differential nonlinearity Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient Gain error See Note 4 See Note 5 See Note 6 See Note 7 See Note 8 10 0.6 TEST CONDITIONS MIN 8 0.4 0.1 1 0.5 24 TYP MAX UNIT bits LSB LSB mV ppm/C % full scale V
EG TC Gain error temperature coefficient See Note 9 10 ppm/C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin).
output specifications
PARAMETER VO Output voltage Output load regulation accuracy RL = 10 k VO = 4.096 V, 2.048 V, RL = 2 k vs 10 k(c) TEST CONDITIONS MIN 0 TYP MAX VDD-0.4 0.25 UNIT V % full scale V
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)
reference pin configured as output (REF)
PARAMETER Vref(OUTL) Vref(OUTH) Iref(source) Iref(sink) PSRR Low reference voltage High reference voltage Output source current Output sink current Load capacitance Power supply rejection ratio -65 -1 100 VDD > 4.75 V TEST CONDITIONS MIN 1.003 2.027 TYP 1.024 2.048 MAX 1.045 2.069 1 UNIT V V mA mA pF dB
reference pin configured as input (REF)
PARAMETER VI RI CI Input voltage Input resistance Input capacitance Fast Reference input bandwidth Reference feedthrough REF = 0 2 Vpp + 1.024 V dc 0.2 1 024 REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow TEST CONDITIONS MIN 0 10 5 1.3 525 - 80 TYP MAX VDD-1.5 UNIT V M pF MHz kHz dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER IIH IIL Ci High-level digital input current Low-level digital input current Input capacitance TEST CONDITIONS VI = VDD VI = 0 V MIN -1 8 TYP MAX 1 UNIT A A pF
analog output dynamic performance
PARAMETER ts(FS) (FS) ts(CC) (CC) SR Output settling time, full scale time Output settling time, code to code time Slew rate Glitch energy SNR S/(N+D) THD SFDR Signal-to-noise ratio Signal-to-noise + distortion Total harmonic distortion Spurious free dynamic range fs = 480 kSPS, fout = 1 kHz, , , RL = 10 k, CL = 100 pF TEST CONDITIONS RL = 10 k, , See Note 11 , RL = 10 k, See Note 12 RL = 10 k, , See Note 13 DIN = 0 to 1, CS = VDD CL = 100 pF, , , CL = 100 pF, CL = 100 pF, , Fast Slow Fast Slow Fast Slow fCLK = 100 kHz, 53 48 50 MIN TYP 0.8 2.8 0.4 0.8 12 1.8 5 57 47 -50 62 -48 dB MAX 2.4 5.5 1.2 1.6 UNIT s s V/s nV-S
NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
digital input timing requirements
MIN tsu(CS-CK) tsu(C16-CS) twH twL tsu(D) th(D) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge SCLK pulse width high SCLK pulse width low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge 10 10 25 25 10 5 NOM MAX UNIT ns ns ns ns ns ns
PARAMETER MEASUREMENT INFORMATION
twL twH
SCLK
X
1 tsu(D) th(D)
2
3
4
5 15
16
X
DIN
X
D15
D14
D13
D12
D1
D0
X tsu(C16-CS)
tsu(CS-CK)
CS
Figure 1. Timing Diagram
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
4.5 4 I DD - Supply Current - mA 3.5 3 2.5 2 Slow Mode 1.5 1 VDD = 5 V Vref = Int. 2 V Input Code = 1023 (Both DACs) I DD - Supply Current - mA Fast Mode 4.5 4 3.5 3 2.5 2 1.5 1 VDD = 3 V Vref = Int. 1 V Input Code = 1023 (Both DACs) Slow Mode
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
Fast Mode
0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TA - Free-Air Temperature - C
0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TA - Free-Air Temperature - C
Figure 2
POWER DOWN SUPPLY CURRENT vs TIME
2.6 I DD - Power Down Supply Current - mA 2.4 2.2 2 VO - Output Voltage - V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 50 30 40 t - Time - s 60 70 80 2.06 2.062 2.064
Figure 3
OUTPUT VOLTAGE vs LOAD CURRENT
VDD = 3 V Vref = Int. 1 V Input Code = 4095
Fast Mode
Slow Mode 2.058
2.056 2.054
2.052 2.05 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current - mA
Figure 4
Figure 5
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs LOAD CURRENT
4.128 Fast Mode 4.126 VO - Output Voltage - V VDD = 5 V Vref = Int. 2 V Input Code = 4095 VO - Output Voltage - V 3 VDD = 3 V Vref = Int. 1 V Input Code = 0 Fast Mode
OUTPUT VOLTAGE vs LOAD CURRENT
2.5
4.124 Slow Mode 4.122
2
1.5
4.12 4.118
1
0.5 4.116 Slow Mode 4.114 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current - mA 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current - mA
Figure 6
OUTPUT VOLTAGE vs LOAD CURRENT
VDD = 5 V Vref = Int. 2 V Input Code = 0 THD+N - Total Harmonic Distortion and Noise - dB 5 4.5 4 VO - Output Voltage - V 3.5 Fast Mode 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 Sink Current - mA 3 3.5 4 Slow Mode 0 -10 -20 -30 -40 -50 -60
Figure 7
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale
Slow Mode -70 -80 -90 -100 100 1000 10000 100000 Fast Mode
f - Frequency - Hz
Figure 8
Figure 9
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB -10 -20 -30 -40 -50 -60 -70 -80 Fast Mode -90 -100 100 1000 10000 100000 Slow Mode VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale
f - Frequency - Hz
Figure 10
DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE
DNL - Differential Nonlinearity - LSB 0.20 0.15 0.10 0.05 -0.00 -0.05 -0.10 -0.15 -0.2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code
Figure 11
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE
INL - Integral Nonlinearity - LSB 1.0 0.8 0.6 0.4 0.2 -0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 Digital Output Code
Figure 12
APPLICATION INFORMATION general function
The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to 0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPITM, and MicrowireTM.
TMS320 DSP FSX DX CLKX TLV5626 CS DIN SCLK SPI I/O MOSI SCK TLV5626 CS DIN SCLK Microwire I/O SO SK TLV5626 CS DIN SCLK
Figure 13. Three-Wire Interface
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
Notes on SPITM and MicrowireTM: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPITM and MicrowireTM), two write operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by: f sclkmax
+t
whmin
)t
1
wlmin
+ 20 MHz
wlmin
The maximum update rate is: f updatemax
+ 16
1 t whmin
)t
+ 1.25 MHz
The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626 has to be considered, too.
data format
The 16-bit data word for the TLV5626 consists of two parts:
D D
D15 R1
Program bits New data
D14 SPD D13 PWR D12 R0
(D15..D12) (D11..D0)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12 Data bits
SPD: Speed control bit PWR: Power control bit
1 fast mode 1 power down
0 slow mode 0 normal operation
The following table lists the possible combination of the register select bits: register select bits
R1 0 0 1 1 R0 0 1 0 1 REGISTER Write data to DAC B and BUFFER Write data to BUFFER Write data to DAC A and update DAC B with BUFFER content Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER
D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0
New DAC Value
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
data bits: CONTROL
D11 X X: don't care D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 REF1 D0 REF0
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits
REF1 0 0 1 1 REF0 0 1 0 1 REFERENCE External 1.024 V 2.048 V External
CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected.
examples of operation:
D
D15 1
Set DAC A output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register):
D14 1 D13 0 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
2. Write new DAC A value and update DAC A output:
D15 1 D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 New DAC A output value
The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again.
D
D15 1
Set DAC B output, select fast mode, select external reference: 3. Select external reference (CONTROL register):
D14 1 D13 0 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
4. Write new DAC B value to BUFFER and update DAC B output:
D15 0 D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 New BUFFER content and DAC B output value
X = Don't care
The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again.
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
APPLICATION INFORMATION examples of operation: (continued)
D
Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: 1. Set reference voltage to 1.024 V (CONTROL register):
D15 1
D14 0
D13 0
D12 1
D11 0
D10 0
D9 0
D8 0
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 1
2. Write data for DAC B to BUFFER:
D15 0 D14 0 D13 0 D12 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 New DAC B value
X = Don't care
3. Write new DAC A value and update DAC A and B simultaneously:
D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 New DAC A value
X = Don't care
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
D
D15 X
Set power-down mode:
D14 X D13 1 D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
X = Don't care
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
Output Voltage
0V Negative Offset DAC Code
Figure 14. Effect of Negative Offset (single supply)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
13
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
definitions of specifications and terminology
integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5626 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A -JUNE 1999 - REVISED JUNE 2000
MECHANICAL DATA
D (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SLAS236A

	To Download SLAS236A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .