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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
D D
D D D D D D D D
10-Bit Resolution 30 MSPS Analog-to-Digital Converter Configurable Input Functions: - Single-Ended - Single-Ended With Analog Clamp - Single-Ended With Programmable Digital Clamp - Differential Built-In Programmable Gain Amplifier (PGA) Differential Nonlinearity: 0.3 LSB Signal-to-Noise: 56 dB Spurious Free Dynamic Range: 60 dB Adjustable Internal Voltage Reference Straight Binary/2s Complement Output Out-of-Range Indicator Power-Down Mode
28-PIN TSSOP/SOIC PACKAGE (TOP VIEW)
AGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 OVR DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AVDD AIN VREF REFBS REFBF MODE REFTF REFTS CLAMPIN CLAMP REFSENSE WR OE CLK
description
The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 2.7 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp amplifier whose clamp input level can be driven from an external dc source or from an internal high-precision 10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small signals. The THS1031 provides a wide selection of voltage references to match the user's design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output indicates any out-of-range condition in THS1031's input signal. The format of digital output can be coded in either unsigned binary or 2s complement. The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box (STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function allows dc restoration of video signal and is suitable for video applications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both imaging and communications systems The THS1031C is characterized for operation from 0C to 70C, while the THS1031I is characterized for operation from -40C to 85C.
AVAILABLE OPTIONS TA 0C to 70C - 40C to 85C PACKAGED DEVICES 28-TSSOP (PW) THS1031CPW THS1031IPW 28-SOIC (DW) THS1031CDW THS1031IDW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
functional block diagram
Power Down 10-Bit Clamp 10 CLAMPIN CLAMP DAC Control Register WR
Clamp Amplifier
3 10 Core PGA DAC ADC Output Buffer I/O(0-9)
AIN REFTS REFBS A
Sample and Hold Internal Reference B Buffer
OVR OE
MODE REFTF REFBF Timing Circuit VBG
ORG
GND
REFSENSE
VREF
CLK
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
Terminal Functions
TERMINAL NAME AGND AIN AVDD CLAMP CLAMPIN CLK DGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 MODE OE OVR REFBS REFBF REFSENSE REFTF REFTS VREF WR NO. 1 27 28 19 20 15 14 2 3 4 5 6 7 8 9 10 11 12 23 16 13 25 24 18 22 21 26 17 I/O I I I I I I I I Analog ground Analog input Analog supply HI to enable CLAMP mode, LO to disable CLAMP mode Connect to an external analog clamp reference input. Clock input Digital ground Digital driver supply Digital I/O bit 0 (LSB) Digital I/O bit 1 Digital I/O bit 2 Digital I/O bit 3 Digital I/O bit 4 Digital I/O bit 5 Digital I/O bit 6 Digital I/O bit 7 Digital I/O bit 8 Digital I/O bit 9 (MSB) Mode input HI to the 3-state data bus, LO to enable the data bus Out-of-range indicator Reference bottom sense Reference bottom decoupling Reference sense Reference top decoupling Reference top sense Internal and external reference Write strobe DESCRIPTION
I/O
I I O I I I I I I/O I
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 6.5 to 6.5 V Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . - 0.3 to AVDD + 0.3 V Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference input VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference output VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN High-level High level input voltage VIH voltage, Low-level in ut voltage VIL input voltage, Clock input All other inputs Clock input All other inputs 0.8 x AVDD 0.8 x DVDD 0.2 x AVDD 0.2 x DVDD NOM MAX UNIT V
V
analog inputs
MIN Analog input voltage, VI(AIN) (PGA = 1x, top, bottom, or external reference mode) Reference input voltage, VI(VREF) Clamp input voltage, VI(CLAMPIN) REFBS 1 0.1 NOM MAX REFTS 2 AVDD-0.1 UNIT V V V
power supply
MIN Supply voltage Maximum sampling rate = 30 MSPS AVDD DVDD 3 3 NOM 3.3 3.3 MAX 5.5 5.5 UNIT V
REFTS, REFBS reference voltages (MODE = AVDD)
PARAMETER REFTS REFBS Reference input voltage (top) Reference input voltage (bottom) Differential input (REFTS - REFBS) Switched input capacitance on REFTS or REFBS MIN 1 0 1 0.6 TYP MAX AVDD AVDD-1 2 UNIT V V V pF
sampling rate and resolution
PARAMETER Fs Resolution MIN 5 10 NOM MAX 30 UNIT MHz Bits
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted)
analog inputs
PARAMETER VI(AIN) CI BW Ilkg Analog input voltage Switched sampling input capacitance Full power BW (- 3 dB) DC leakage current (input = FS) MIN REFBS 1.2 150 100 TYP MAX REFTS UNIT V pF MHz A
VREF reference voltages
PARAMETER Internal 1 V reference (REFSENSE = VREF) Internal 2 V reference (REFSENSE = AVSS) External reference (REFSENSE = AVDD) Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2) MIN 0.95 1.90 1 18 TYP 1 2 MAX 1.05 2.10 2 UNIT V V V k
REFTF, REFBF reference voltages
PARAMETER Differential input (REFTF - REFBF) Input common mode (REFTF + REFBF)/2 VREF = 1 V REFTF (MODE = AVDD) VREF = 2 V VREF = 1 V REFBF (MODE = AVDD) VREF = 2 V Input resistance between REFTF and REFBF AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V TEST CONDITIONS MIN 1 1.3 2 1.5 2.5 2 3 2.5 3.5 1 2 0.5 1.5 680 TYP MAX 2 1.7 3 UNIT V V V V V V
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
dc accuracy
PARAMETER INL DNL Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 2) Offset error (see Note 3) Gain error (see Note 4) Missing code MIN TYP 1 0.3 0.4 1.4 MAX 2 1 2 3.5 UNIT LSB LSB %FSR %FSR
No missing code assured
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level - first transition level) / (2 n - 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than -1 LSB ensures no missing codes. 3. Offset error is defined as the difference in analog input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). 4. Gain error is defined as the difference in analog input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).
dynamic performance (ADC and PGA)
PARAMETER TEST CONDITIONS f = 3.5 MHz ENOB Effective number of bits f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz SFDR Spurious free dynamic range f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz THD Total harmonic distortion f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz SNR Signal to noise Signal-to-noise f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz SINAD Signal-to-noise Signal to noise and distortion f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V 51.1 51.2 55 MIN 8.2 TYP 9 8.8 7.7 7.64 60 63 48 52.4 - 58.2 - 68.7 - 47 - 51.9 56 55 53 49.3 56 55 48.1 47.7 dB dB - 54.7 dB dB Bits MAX UNIT
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted) (continued)
PGA
PARAMETER Gain range (linear scale) Gain step size (linear scale) Gain error from nominal Number of control bits 3 MIN 0.5 0.5 3% Bits TYP MAX 4 UNIT V/V V/V
clamp amplifier and clamp DAC
PARAMETER Resolution DAC output range DAC DNL DAC INL Clamping analog output voltage range Clamping analog output voltage error 0.1 - 40 REFBF -1 1 AVDD- 0.1 40 MIN TYP 10 REFTF 1 MAX UNIT Bits V LSB LSB V mV
clock
PARAMETER tc tw(CKH) tw(CKL) td(o) td(AP) Clock period Pulse duration, clock high Pulse duration, clock high Clock to data valid Pipeline latency Aperture delay Aperture uncertainty (jitter) 3 4 2 MIN 33 15 15 16.5 16.5 25 TYP MAX UNIT ns ns ns ns Cycles ns ps
timing
PARAMETER td(DZ) td(DEN) td(OEW) td(WOE) tw(WP) tsu th Output disable to Hi-Z output Output enable to output valid Output disable to write enable Write disable to output enable Write pulse Input data setup time Input data hold time MIN 0 0 12 12 15 5 5 TYP MAX 20 20 UNIT ns ns ns ns ns ns ns
power supply
PARAMETER ICC PD PD(STBY) Operating supply current Power dissipation Standby power TEST CONDITIONS AVDD = 3 V, MODE = AGND AVDD = DVDD = 3 V AVDD = DVDD = 5 V AVDD = DVDD = 3 V, MODE = AGND MIN TYP 30.6 94 160 3 5 MAX 45 135 UNIT mA mW mW
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
OE See Note A
tw(WP) td(OEW) WE td(WOE)
td(DZ) tsu Hi-Z
th td(DEN) Hi-Z
I/O
Output
Input
Output
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
Sample 2 Sample 1 Analog Input tc tw(CKL)
Sample 3 Sample 4 Sample 5
t(CKH)
Input Clock
See Note A td(o) Pipeline Latency
Digital Output
Sample 1
Sample 2
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 2. Digital Output Timing Diagram
8
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
POWER DISSIPATION vs SAMPLING FREQUENCY
96 Power Dissipation - mW 94 92 90 88 86 84 82 5 10 15 20 25 30 fs - Sampling Frequency - MHz AVDD = DVDD = 3 V FI = 3.5 MHz TA = 25C
Figure 3
EFFECTIVE NUMBER OF BITS vs TEMPERATURE
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 -40 AVDD = DVDD = 3 V FI = 3.5 MHz Fs = 30 MSPS
-15
10
35
60
85
TA - Temperature - C
Figure 4
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 5 AVDD = DVDD = 3 V FI = 3.5 MHz TA = 25C 10 15 20 25 30
fs - Sampling Frequency - MSPS
Figure 5
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 5 10 15 20 25 30 fs - Sampling Frequency - MSPS AVDD = 5 V, DVDD = 3 V FI = 3.5 MHz TA = 25C
Figure 6
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.00 Effective Number of Bits 9.50 9.00 8.50 8.00 7.50 7.00 5 10 15 20 25 30 fs - Sampling Frequency - MSPS AVDD = DVDD= 5 V, FI = 3.5 MHz TA = 25C
Figure 7
DIFFERENTIAL NONLINEARITY vs INPUT CODE
DNL - Differential Nonlinearity - LSB 1.0 0.8 0.6 0.4 0.2 -0.0 -0.2 -0.4 -0.6 -0.8 -1 0 AVDD = 3 V, DVDD = 3 V Fs = 30 MSPS
128
256
384
512 Input Code
640
768
896
1024
Figure 8
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY vs INPUT CODE
INL - Integral Nonlinearity - LSB 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 128 256 384 512 Input Code 640 768 896 1024 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS
Figure 9
FFT vs FREQUENCY
0 -20 -40 FFT - dB -60 -80 -100 -120 -140 0 0 200 1.5 400 3 600 4.5 800 6 1000 7.5 1200 9 1400 10.5 1600 12 1800 13.5 2000 15 f - Frequency - MHz AVDD = 3 V DVDD = 3 V Fin = 3.5 MHz, -1 dBFS
Figure 10
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION
The analog input AIN is sampled in the sample-and-hold unit, the output of which goes to a programmable gain amplifier (PGA). The PGA feeds the ADC core, where the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF. Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations. The three settings open or close internal switches to select one of the three basic methods of ADC reference generation. Depending on the user's choice of operating configuration, the ADC reference voltages may come from the internal reference buffer (IRB) or may be fed from completely external sources. Where the reference buffer is employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user. The THS1031 offers a clamp function for dc restoration of ac coupled signals. The clamp voltage may be set digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input. The ADC core drives out through output buffers to the I/O pins I/O0 to I/O9. The output buffers can be disabled by the OE pin. Control input data on I/O0 to I/O9 can then be written, by pulses on WR, to the control registers. These registers control clamp operation, output format (unsigned binary or two's complement), the PGA gain setting and the device power down function. A single-ended, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on the rising edge of CLK, and corresponding data is output after the third following rising edge. The user-chosen operating configuration and reference voltages determine what input signal voltage range the THS1031 can handle. The following sections explain:
D D D D
The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages; The ways in which the ADC reference voltages can be buffered internally, or externally applied; How to set the onboard reference generator output, if required, and several examples of complete configurations. Subsequent sections explain the clamp function and digital controls, followed by more detailed application information.
signal processing chain (sample and hold, PGA, ADC)
REFTF VP+ AIN REFTS REFBS 1 -1/2 -1/2 Sample and Hold VP- VQ+ ADC Core
PGA
VQ- REFBF
Figure 11. Analog Input Signal Flow Figure 11 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION sample-and-hold
The analog input signal AIN is applied to the AIN pin, either dc coupled, ac coupled, or ac coupled with dc restoration using the THS1031 clamp circuit. The differential sample and hold processes AIN with respect to the voltages applied to the REFTS and REFBS pins, to give a differential output VP+ - VP- = VP given by: VP = AIN - VM Where: VM (1)
+ (REFTS ) REFBS) 2
(2)
For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if MODE = AVDD/2 then REFTS and REFBS can be connected together to operate with AIN as a complementary pair of differential inputs (see Figures 15 and 16).
programmable gain amplifier
VP is amplified by the PGA and fed into the ADC as a differential voltage VQ+ - VQ- = VQ VQ = Gain x VP = Gain x [AIN - VM] The default PGA gain at power-up is 1.0, but can be programmed from 0.5 to 4.0 via the control register.
analog-to-digital converter
In all operating configurations, VQ is digitized against ADC reference Voltages REFTF and REFBF, full scale values of VQ being given by
)+ ) (REFTF2* REFBF) * (REFTF * REFBF) VQFS *+
VQFS 2
(3)
VQ voltages outside the range VQFS- to VQFS+ lie outside the conversion range of the ADC. Attempts to convert out-of-range inputs are signalled to the application by driving the OVR output pin high. VQ voltages less than VQFS - give ADC output code 0. VQ voltages greater than VQFS+ give output code 1023. complete system Combining equations 1 to 3, the analog full-scale input voltages at AIN which give VQFS+ and VQFS- at the PGA output are: A and A IN IN
+ FS )+ VM ) (REFTF * REFBF) (2 Gain) + FS *+ VM * (REFTF * REFBF) (2 Gain)
(4)
(5)
The analog input span (voltage range) that lies within the ADC conversion range is: Input span
+ [(FS )) * (FS *)] + (REFTF * REFBF)
Gain
(6)
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION
complete system (continued) The REFTF and REFBF voltage difference and the gain sets the device input range. The next sections describe in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span and device performance.
ADC reference generation
The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to the MODE pin. Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the possibility of Kelvin connection of the reference inputs to the THS1031 to eliminate any voltage drops from remote references that may occur in the system. Only single-ended input is possible in this mode. Connecting the MODE pin to AVDD/2 gives differential mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins. A special case of differential mode is center span mode, in which user applies a single-ended signal to AIN and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins. Connecting the MODE pin to AVDD gives top/bottom mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS pins. Only single-ended input is possible in top/bottom mode.
full external reference mode (mode = AGND)
REFTF
AIN+ REFTS REFBS
1 -1/2 -1/2
Sample and Hold
PGA
ADC Core
Internal Reference Buffer
REFBF
Figure 12. ADC Reference Generation, MODE = AGND When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes are connected by the user to external sources to provide the ADC reference voltages. The mean of REFTF and REFBF must be equal to AVDD/2 (see Figure 13).
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION full external reference mode (mode = AGND) (continued)
AVDD AVDD 2 AVDD 2 AVDD 2 +FS -FS GAIN 2 GAIN 2 AIN REFSENSE
DC SOURCE = DC SOURCE =
+ [(FS+) - (FS-)] x - [(FS+) - (FS-)] x 0.1 F
REFTS
REFBS
REFTF 10 F 0.1 F REFBF MODE
0.1 F
Figure 13. Full External Reference Mode It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to overcome any voltage drops within the system (see Figure 14).
AVDD AVDD 2 +FS -FS AIN REFSENSE
REFTS REFBS _ AVDD REFT = 2 GAIN + [(FS+) - (FS-)] x 2 REFTF + 0.1 F 10 F _ REFB = AVDD 2 - [(FS+) - (FS-)] x GAIN 2 + 0.1 F REFBF MODE 0.1 F
Figure 14. Full External Reference With Kelvin Connections
16
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PRINCIPLES OF OPERATION differential mode (mode = AVDD/2)
REFTF = AVDD + VREF 2
AIN+ REFTS AIN- REFBS
1 -1/2 -1/2
Sample and Hold
PGA
ADC Core
VREF AGND
Internal Reference Buffer
REFBF =
AVDD - VREF 2
Figure 15. ADC Reference Generation, MODE = AVDD/2 When MODE = AVDD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF voltages are centered on AVDD/2 by the internal reference buffer and the voltage difference between REFTF and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are open in this mode, allowing REFTS and REFBS to form the AIN- to the sample and hold. Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to an internally generated voltage of 1 V, 2 V or an intermediate voltage (see the onboard reference generator configuration)
+FS AIN+ -FS +FS AIN- -FS AIN MODE AVDD 2
REFTS
REFBS REFSENSE 0.1 F
REFTF 10 F 0.1 F REFBF
VREF
0.1 F
Figure 16. Differential Input Mode, 1 V Reference Span
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION differential mode (mode = AVDD/2) (continued)
+FS VM -FS AIN MODE AVDD 2
DC SOURCE = VM VM 0.1 F
+ _
REFTS
REFBS
REFTF 10 F 0.1 F REFBF REFSENSE
0.1 F
Figure 17. Center Span Mode, 2 V Reference Span
top/bottom mode (MODE = AVDD)
REFTF = AVDD + (REFTS - REFBS) 2 1 -1/2 -1/2
AIN+ REFTS REFBS
Sample and Hold
PGA
ADC Core
Internal Reference Buffer
REFBF = AVDD - (REFTS - REFBS) 2
Figure 18. ADC Reference Generation Mode = AVDD Connecting MODE to AVDD enables the internal reference buffer. Its inputs are internally switched to the REFTS and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections (REFTS to REFTF) and (REFBS to REFBF) are broken. To match the signal span to the full ADC input span, the voltage difference between REFTS and REFBS should be REFTS - REFBS = [(FS+) - (FS-)] x Gain, with the average of the REFTS and REFBS voltages being the AIN midscale voltage, VM. Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 19), but the user can choose to use the ORG output to VREF as either REFTS or REFBS.
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PRINCIPLES OF OPERATION top/bottom mode (MODE = AVDD) (continued)
AVDD +FS -FS DC SOURCE = VM + [(FS+) - (FS-)] x DC SOURCE =VM - [(FS+) - (FS-)] x 0.1 F GAIN 2 GAIN 2 AIN MODE
REFTS REFSENSE
REFBS
REFTF 10 F 0.1 F REFBF
0.1 F
Figure 19. ADC Reference Generation Mode = AVDD
onboard reference generator configuration
The onboard reference generator (ORG) can supply a supply-voltage-independent and temperatureindependent voltage on pin VREF. External connections to REFSENSE control the ORG's output to the VREF pin as shown in Table 1. Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION VREF pin AGND External divider junction AVDD ORG OUTPUT TO VREF 1V 2V (1 + RA/RB) Open circuit REFER TO: Figure 20 Figure 21 Figure 22 Figure 23
REFSENSE = AVDD powers the ORG down, saving power when the ORG function is not required. If MODE = AVDD/2, the voltage on VREF determines the ADC reference voltages: REFTF
+ AV2DD ) VREF 2
(7)
+ AV2DD * VREF 2 REFTF * REFBF + VREF
REFBF
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SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION onboard reference generator configuration (continued)
Internal Reference Buffer Mode = AVDD 2 VREF = 1 V 0.1 F REFSENSE 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 20. 1-V VREF Using ORG
Internal Reference Buffer Mode = AVDD 2 VREF = 2 V 10 k REFSENSE 10 k 0.1 F 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 21. 2-V VREF Using ORG
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PRINCIPLES OF OPERATION onboard reference generator configuration (continued)
Internal Reference Buffer Mode = AVDD 2 VREF = 1 + (Ra/Rb) Ra REFSENSE Rb 0.1 F 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 22. External Divider Mode
Internal Reference Buffer Mode = AVDD 2
VBG
+ _
+ _
VREF = External
REFSENSE AVDD AGND
Figure 23. Drive VREF Mode
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THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION operating configuration examples
This section provides examples of operating configurations. Figure 24 shows the operating configuration in top/bottom mode for a 2 V span single-ended input, using VREF to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AVDD puts the THS1031 in top/bottom mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the input signal.
AVDD 2V 1V 0V AIN MODE
VREF = 2 V
REFTS 0.1 F
REFTF REFSENSE 10 F 0.1 F REFBF REFBS
0.1 F
Figure 24. Operation Configuration in Top/Bottom Mode In Figure 25, the input signal is differential, so Mode = AVDD/2 (differential mode) is set to allow the inverse signal to be applied to REFTS and REFBS. The differential input goes from - 0.8 V to 0.8 V, giving a total input signal span of 1.6 V. Using a PGA gain of 1, REFTF - REFBF should therefore, equal 1.6 V. REFSENSE is connected to resistors RA and RB (external divider mode) to make VREF = 1.6 V, that is RA/RB = 0.6 (see Figure 22).
1.4 V 1V 0.6 V AVDD 2 AIN MODE
AIN+
1.4 V AIN- 1 V 0.6 V
REFTS VREF = 1.6 V REFBS RA REFSENSE REFTF 10 F 0.1 F REFBF RB
0.1 F
0.1 F
Figure 25. Differential Operation
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PRINCIPLES OF OPERATION operating configuration examples
Figure 26 shows a center span configuration for an input waveform swinging between 0.2 and 1.9 V. Pins REFTS and REFBS are connected to a voltage source of 1.05 V, equal to the mid-scale of the input waveform. With the PGA gain set to its default value of 1.0, REFTF - REFBF should be set equal to the span of the input waveform, 1.7 V, so VREF is connected to an external source of 1.7V. REFSENSE must be connected to AVDD to disable the ORG output to VREF (see Figure 23) to allow this external source to be applied.
1.9 V 1.05 V 0.2 V AIN MODE REFSENSE AVDD 2 AVDD
REFTS DC SOURCE = 1.05 V REFBS 0.1 F
REFTF 10 F 0.1 F REFBF
VREF
DC SOURCE = 1.7 V
0.1 F
Figure 26. Center Span Operation Figure 27 shows an example of top/bottom mode operation on an input span of 800 mV with mid-scale value 1.5 V. Pin REFTS is set to 2.5 V and pin REFBS to 0.5 V, making their average value equal to the mid-scale value of AIN and giving the maximum specified difference of 2 V between REFTS and REFBS to maximize the full-scale range of the ADC core for best resolution. The PGA gain then has to be set to 2.5, to amplify the 800 mVPP input signal to 2 VPP at the ADC core input.
AVDD 1.9 V 1.5 V 1.1 V DC SOURCE = 2.5 V AIN MODE REFSENSE
REFTS
DC SOURCE = 0.5 V 0.1 F
REFBS
REFTF 10 F 0.1 F REFBF
0.1 F
Figure 27. Top/Bottom Mode, PGA Gain 2.5
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PRINCIPLES OF OPERATION clamp operation
CLAMPIN CLAMP + _ RIN SW1 AIN S/H 10-Bit DAC Control Register (Bit CLINT) V(Clamp)
CIN VIN
Figure 28. Schematic of Clamp Circuitry The THS1031 provides a clamp function for restoring a dc reference level to the signal at AIN which has been lost through ac coupling from the signal source to this pin. Figure 29 shows an example of using the clamp to restore the black level of a composite video input ac coupled to AIN. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN to equal the clamp reference voltage, setting the dc voltage at AIN for the video black level. After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be taken from the internal CLAMP DAC by suitably programming the THS1031 clamp and control registers. Clamp acquisition and clamp droop design calculations are discussed later.
Line Sync Black Level Video at AIN
CLAMP
Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level clamp DAC output voltage range and limits When using the internal clamp DAC in top/bottom or center span mode, the user must ensure that the desired dc clamp level at AIN lies within the voltage range VREFBF to VREFTF. This is because the clamp DAC voltage is constrained to lie within this range VREFBF to VREFTF. Specifically: VDAC
+ VREFBF ) (VREFTF * VREFBF)
(0.006
) 0.988
(DAC code) 1024)
(8)
DAC codes can range from 0 to 1023. Figure 30 graphically shows the clamp DAC output voltage versus the DAC code.
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PRINCIPLES OF OPERATION
clamp DAC output voltage range and limits (continued)
VDAC VREFTF VREFBF + 0.006(VREFTF-VREFBF)
VREFBF + 0.987(VREFTF-VREFBF) VREFBF 0 1023 DAC Code
Figure 30. Clamp DAC Output Voltage Versus DAC Register Code Value If the desired dc level at AIN does not lie within the voltage range VREFTF to VREFBF, then either the CLAMPIN pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both top/bottom and center span modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range is to be moved.
power management
In power-sensitive applications (such as battery-powered systems) where the THS1031 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the THS1031 into power down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power down mode, the device typically consumes less than 1 mW of power in either top/bottom or center-span modes. Power down mode is exited by resetting control register bit 3 to 0. On power up, the THS1031 typically requires 5 ms of wake up time before valid conversion results are available. In systems where the ADC must run continuously, but where the clamp is not required, setting control register bit 6 (CLDIS to 1), which disables only the clamp circuits, can save power. Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by 1 mA analog IDD. This is achieved by connecting the REFSENSE pin to AVDD.
output format and digital I/O
While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input over-range indicator is output at pin OVR. OVR is also disabled when OE is held high. The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be switched to 2s complement (output codes -512 to 511) by setting control register bit 5 (TWOC) to 1.
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PRINCIPLES OF OPERATION
writing to the internal registers through the digital I/O bus Pulling pin OE high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance state. This allows control register data to be loaded into the THS1031 by presenting it on the I/O0 to I/O9 pins and pulsing the WR pin high to latch the data into the chosen control or DAC register. Figure 31 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to clamp registers 1 and 2 (see the register map in Table 2). Pins I/O0 to I/O7 are driven to the clamp DAC code lower byte (0F hex) and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination. The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp register 2. Interface timing parameters are given in Figures 1 and 2.
OE
WR
I/O (0-9)
Output
Input 00F Load 0F Into REGISTER 0
Input 101 Load 01 Into REGISTER 1
Output
Figure 31. Example Register Write Cycle to Clamp DAC Register
digital control registers
The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation. Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01 clamp register 2 and 10 the control register. Table 2. Register Map
ADDRESS I/O[9:8] 00 01 10 11 DESCRIPTION Clamp Reg. 1 Clamp Reg. 2 Control Reg. Reserved DEF (HEX) 00 00 01 RW RW RW RW CLDIS TWOC CLINT PDWN PGA[2] BIT B7 DAC[7] B6 DAC[6] B5 DAC[5] B4 DAC[4] B3 DAC[3] B2 DAC[2] B1 DAC[1] DAC[9] PGA[1] B0 DAC[0] DAC[8] PGA[0]
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PRINCIPLES OF OPERATION
Table 3. Register Contents
REGISTER BIT NO BIT NAME(S) DEFAULT PGA gain: 000 = 0.5 001 = 1.0 (default value) 010 = 1.5 011 = 2.0 100 = 2.5 101 = 3.0 110 = 3.5 111 = 4.0 Power down 0 = THS1031 powered up 1 = THS1031 powered down Clamp voltage internal/external 0 = external analog clamp voltage from CLAMPIN pin 1 = from onboard DAC (see clamp register) Output format 0 = unsigned binary 1 = two's complement Clamp amplifier disable (for power saving) 0 = Enable 1 = Disable Unused Clamp DAC voltage (DAC[0] = LSB.) DAC[9:0] = 00h: Clamp voltage = REFBF DAC[9:0] = 3Fh: Clamp voltage = REFTF Unused DAC[9:8] 0 Clamp DAC voltage (DAC[9] = MSB) DESCRIPTION
2:0
PGA[2:0]
0
Control Register I/O[9:8] = 10
3
PDWN
0
4
CLINT
0
5
TWOC
0
6 7 Clamp Register 1 I/O[9:8] = 00
CLDIS
0
7:0
DAC[7:0]
0
Clamp Register 2 I/O[9:8] = 01
7:2 1:0
driving the THS1301 analog inputs
driving AIN Figure 32 shows an equivalent circuit for the THS1031 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, CSAMPLE, and various stray capacitances, CP1 and CP2.
AVDD CLK 1.2 pF AIN C1 8 pF AGND + _ CLK VLAST CSAMPLE C2 1.2 pF
Figure 32. Equivalent Circuit of Analog Input AIN
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PRINCIPLES OF OPERATION
driving AIN (continued) In any single-ended input mode, VLAST = the average of the previously sampled voltage at AIN and the average of the voltages on pins REFTS and REFBS. In any differential mode, VLAST = the common mode input voltage. The external source driving AIN must be able to charge and settle into CSAMPLE and the CP1 and CP2 strays to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution. AIN input current and input load modeling When CLK goes low, the source driving AIN must charge the total switched capacitance CS = CSAMPLE + CP2. The total charge transferred depends on the voltage at AIN and is given by Q CHARGING
+ (AIN * VLAST )
C. S
(9)
For a fixed voltage at AIN, so that AIN and VLAST do not change between samples, the maximum amount of charge transfer occurs at AIN = FS- (charging current flows out of THS1030) and AIN = FS+ (current flows into THS1030). If AIN is held at the voltage FS+, VLAST = [(FS+) + VM]/2, giving a maximum transferred charge: Q(FS)
+ (FS )) * [(FS )) ) VM] CS + [(FS )) *2VM] 2 + ( 1 4 of the input voltage span ) CS +3
Q(FS)
C
S (10)
If the input voltage changes between samples, then the maximum possible charge transfer is Q(max) (11)
which occurs for a full-scale input change (FS+ to FS- or FS- to FS+) between samples. The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive at high frequencies. Inserting a small series resistor of 20 or less in the input path can damp source ringing. See 3. This resistor can be made larger than 20 if reduced input bandwidth or distortion performance is acceptable.
R< 20 AIN VS
Figure 33. Damping Source Ringing Using a Small Resistor equivalent input resistance at AIN and ac coupling to AIN Some applications may require ac coupling of the input signal to the AIN pin. Such applications can use an ac coupling network such as shown in Figure 34.
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PRINCIPLES OF OPERATION
equivalent input resistance at AIN and ac coupling to AIN (continued)
AVDD
R(Bias1) Cin AIN R(Bias2)
Figure 34. AC Coupling the Input Signal to the AIN Pin Note that if the bias voltage is derived from the supplies, as shown in Figure 34, then additional filtering should be used to ensure that noise from the supplies does not reach AIN. Working with the input current pulse equations given in the previous section is awkward when designing ac coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent resistance, RAIN, from the AIN pin to a voltage source VM where VM = (REFTS + REFBS)/2 and RAIN = 1 / (Cs x Fclk) where Fclk is the CLK frequency. The high-pass -3 dB cut-off frequency for the circuit shown in Figure 34 is: f (*3 dB)
+
1 2
p
R
tot IN
(12)
where RINtot is the parallel combination of Rbias1, Rbias2 and RAIN. This approximation is good provided that the clock frequency, Fclk, is much higher than f(-3 dB). Note also that the effect of the equivalent RAIN and VM at the AIN pin must be allowed for when designing the bias network dc level. details The above value for RAIN is derived by noting that the average AIN voltage must equal the bias voltage supplied by the ac coupling network. The average value of VLAST in equation 13 is thus a constant voltage VLAST = V(AIN bias) - VM For an input voltage Vin at the AIN pin, Qin = (Vin - VLAST) x Cs (14) (13)
Provided that f (-3 dB) is much lower than Fclk, a constant current flowing over the clock period can approximate the input charging pulse Iin = Qin/Tclk = Qin x Fclk = (Vin - VLAST) x Cs x Fclk
(15)
The ac input resistance RAIN is then RAIN = dIin/dVin = 1 / (dVin / dIin) = 1 / (Cs x Fclk)
(16)
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PRINCIPLES OF OPERATION
driving the VREF pin (differential mode) Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin (MODE = AVDD/2 and REFSENSE = AVDD).
AVDD
RIN VREF 14 k
REFSENSE = AVDD, Mode = AVDD 2
AGND + _ AVDD + VREF/4 4 4
Figure 35. Equivalent Circuit of VREF The current flowing into IIN is given by I IN
+ (3
VREF (4 R
* AVDD )
)
IN
(17)
Note that the actual IIN may differ from this value by up to +50% due to device-to-device processing variations and allowing for operating temperature variations. The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground and capable of driving IIN. driving the internal reference buffer (top/bottom mode) Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.
AVDD
REFTS REFBS
RIN 14 k Mode = AGND AVDD 2
AVDD + REFTS + REFBS 4
+ _
Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer
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PRINCIPLES OF OPERATION
driving the internal reference buffer (top/bottom mode) (continued) Equations for the currents flowing into REFTS and REFBS are: I TS IN
+ (3 + (3
REFTS
* AVDD * REFBS )
R
(4 REFBS
I
BS IN
* AVDD * REFTS )
R IN )
IN
)
(18)
(4
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold. Tolerance on these currents are 50%. driving REFTS and REFBS
AVDD CLK 0.6 pF REFTS REFBS C1 7 pF AGND Mode = AVDD + _ Internal Reference Buffer CLK VLAST CSAMPLE C2 0.6 pF
Figure 37. Equivalent Circuit of REFTS and REFBS Inputs This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also driving a switched capacitor load like AIN, but with the sampling capacitor and CP2 on each pin now being 0.6 pF and about 0.6 pF respectively. driving REFTF and REFBF (full external reference mode)
AVDD
REFTF
To REFBS (For Kelvin Connection) AGND AVDD 680
REFBF
To REFTS (For Kelvin Connection) AGND
Figure 38. Equivalent Circuit of REFTF and REFBF Inputs Note the need for off-chip decoupling.
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PRINCIPLES OF OPERATION clamp operation
The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by programming the on-chip clamp DAC. clamp acquisition time Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.
10-Bit DAC Control Register VCLAMP S/H
CLAMPIN CLAMP + _ RIN SW1 AIN
CIN VIN
Figure 39. Schematic of Clamp Circuitry After powerup, the clamp circuit requires SW1 to be closed to charge the coupling capacitor, CIN, to the voltage required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called the clamp acquisition time, TACQ: T ACQ
+ CIN
R
IN
In Vc Ve
(19)
Vc is the difference between the dc bias voltage level of the input signal, VIN, and the target clamp output voltage, V(clamp). Ve is the difference between the ideal Vc and the actual Vc obtained during the acquisition time. The maximum tolerable error depends on the application requirements. For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of 1.3 V at the THS1031 input. The voltage Vc required across the input coupling capacitor is thus 1.3 - 0.3 = 1 V. If a 10 mV or less clamp voltage error Ve will give acceptable system operation, if the source resistance Rin is 20 and the coupling capacitor Cin is 1 F, then the total clamp pulse duration required to reach this error is: T ACQ
+ CIN
R
IN
In Vc Ve
+ 1 mF
20
W
In
1 = 92 s (approximately) 0.01
(20)
Note that SW1 does not have to be closed continuously until the desired clamp voltage is achieved. The clamp level can be acquired over a longer interval by using a series of shorter clamp pulses with total pulse duration at least equal to the acquisition time calculated using equation 19.
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SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION clamp operation (continued)
droop The charge pulses entering or leaving AIN caused by the sample and hold switched capacitor input can charge or discharge CIN, causing the voltage at AIN to drift toward VM (the average of REFTS and REFBS) during the time between clamp pulses. This effect is called clamp droop and can be seen as a slow change in the ADC output code when the input signal is a constant dc level. Through careful clamp circuit design, this droop can be kept below 1 LSB, giving no change in the ADC output between clamp pulses. The clamp voltage droop is a function of the input current to the THS1031 and the time between clamp pulses, td V DROOP Where: I IN I + CIN td (approximately) (21)
IN
+ (VAIN - VM) + (VAIN - VM) + (VAIN - VM)
2 Cs
R AIN Fclk 2
RAIN is the input resistance given by equation 20. Cs is approximately 2.5 pF. Substituting Iin into the droop voltage equation gives V DROOP Cs td (2 C IN) (22)
Note that IIN has maximum value when Vain is either +FS or -FS, and so the droop rate is worst then the clamp level is near either full-scale input voltage. There is no droop when the clamp level equals VM because IIN is zero. Note that the actual voltage droop may be up to 50% more than given by equation 22 when allowing for temperature variations and device to device processing variations. For example, with CIN = 1 F at Fclk = 30 MSPS conversion rate in top/bottom mode with REFTS = 2.5 V and REFBS = 0.5 V, the clamp droop over td = 63.5 ms when VAIN = +FS is V DROOP
+ (VAIN - VM) Cs Fclk td (2 + (2.5 V - 1.5 V) 2.5 pF 30 MMz + 0.0024 mV + 1.25 LSB (assuming PGA gain + 1)
C IN) 2
(23)
Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no over-range), then the ADC output code will slowly drop to code 1022, or possibly code 1021, over the period td. If the calculated droop is greater than can be tolerated in the application then increase CIN to slow the droop and hence reduce the voltage change between clamp pulses. If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly larger than calculated above due to the capacitor's rapid rate of self-discharge. Avoid using electrolytic and tantalum coupling capacitors as these usually exhibit much higher leakage then nonpolarized capacitor types. Electrolytic and tantalum capacitors also tend to have higher parasitics inductance, which can cause further problems at high input frequencies.
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33
THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION
steady-state clamp voltage error Under steady-state conditions, the change in the clamp voltage caused during clamping must equal the change caused by clamp droop, otherwise the effect causing the largest voltage change would pull the clamp voltage away until these charging and droop effects equalize. Figure 40 shows the approximate voltage waveform at AIN resulting from clamp droop during td and clamp voltage reacquisition during the clamp pulse time, tc.
V(Clamp) V COS VDROOP = VAIN VAIN
tc VM
td
Figure 40. Approximate Waveforms at AIN During Droop and Clamping The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming that almost all of VCOS appears across RIN, giving a charging current VCOS/Rin (this is a reasonable approximation when VCOS is large enough to be a problem). The voltage change at AIN during clamp acquisition is then
DVAIN +
V
COS R IN
tc (24)
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the droop voltage to the clamp acquisition voltage change gives V
+ RIN COS
IN tc
I
td (25)
Where IIN is the input current given by equation, thus for low offset voltage, keep RIN low and ensure that the ratio td/tc is not unreasonably large.
driving the clock input
Obtaining good performance from the THS1031 requires care when driving the clock input. Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the THS1031 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. The CLK input threshold is nominally around AVDD/2 - ensure that any clock buffers have an appropriate supply voltage to drive above and below this level.
34
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION digital output loading and circuit board layout
The THS1031 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V digital supply. Minimizing the load on the outputs will improve THS1031 signal-to-noise performance by reducing the switching noise coupling from the THS1031 output buffers to the internal analog circuits. The output load capacitance can be minimized by buffering the THS1031 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the THS1031 and this buffer. Noise levels at the output buffers, and hence coupling to the analog circuits within THS1031, becomes worse as the THS1031 digital supply voltage is increased. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the THS1031 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analog circuits. The THS1031 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1031
D D D D D D D D
Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails. ORG modes offer the simplest configurations for ADC reference generation. Choose differential input mode for best distortion performance. Choose a 2 V ADC input span for best noise performance. Choose a 1 V ADC input span for best distortion performance. If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the system. Care should be taken to ensure noise is not injected into the THS1031. Use external voltage sources for ADC reference generation where there are stringent requirements on accuracy and drift. Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
35
THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
MECHANICAL DATA
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
36
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
THS1031 2.7 V TO 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242B - NOVEMBER 1999 - REVISED AUGUST 2000
MECHANICAL DATA
DW (R-PDSO-G**)
16 PINS SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000 / C 07/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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* DALLAS, TEXAS 75265
37
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Copyright (c) 2000, Texas Instruments Incorporated

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