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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
features
D D D D D D D D D D D D D D D D
Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Integrated 16 Word FIFO Signal-to-Noise and Distortion Ratio: 66 dB at fI = 2 MHz Differential Nonlinearity Error: 1 LSB Integral Nonlinearity Error: 1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 216 mW Max 5-V Analog Single Supply Operation Internal Voltage References . . . 50 PPM/C and 5% Accuracy Parallel C/DSP Interface
DA PACKAGE (TOP VIEW)
D0 D1 D2 D3 D4 D5 BVDD BGND D6 D7 D8 D9 RA0/D10 RA1/D11 CONV_CLK (CONVST) DATA_AV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
applications
Radar Applications Communications Control Applications High-Speed DSP Front-End Automotive Applications
OV_FL RESET AINP AINM REFIN REFOUT REFP REFM AGND AVDD CS0 CS1 WR (R/W) RD DVDD DGND
description
The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In the single conversion mode, a single and simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal clock oscillator is switched off in the continuous conversion mode. The THS12082C is characterized for operation from 0C to 70C, and the THS12082I is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
AVAILABLE OPTIONS PACKAGED DEVICE TA 0C to 70C -40C to 85C TSSOP (DA) THS12082CDA THS12082IDA
functional block diagram
AVDD DVDD
3.5 V REFP 1.5 V 1.225 V REF
2.5 V REFOUT
REFM REFP REFIN Single-Ended and/or Differential MUX REFM
DATA_AV OV_FL BVDD 12
+ -
AINP AINM S/H
S/H
12-Bit Pipeline ADC
12
FIFO 16 x 12
Buffers
CONV_CLK (CONVST) CS0 CS1 RD WR (R/W) RESET Logic and Control Control Register
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1 BGND
AGND
DGND
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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
Terminal Functions
TERMINAL NAME AINP AINM AVDD AGND BVDD BGND CONV_CLK (CONVST) NO. 30 29 23 24 7 8 15 I/O I I I I I I I DESCRIPTION Analog input, single-ended or positive input of differential channel A Analog input, single-ended or negative input of differential channel A Analog supply voltage Analog ground Digital supply voltage for buffer Digital ground for buffer Digital input. This input is used to apply an external conversion clock in the continuous conversion mode. In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. Chip select input (active low) Chip select input (active high) Data available signal, which can be used to generate an interrupt for processors and as a level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 7. Digital ground. Ground reference for digital circuitry. Digital supply voltage Digital input, output; D0 = LSB Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO. Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 6. Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 6. Hardware reset of the THS12082. Sets the control register to default values. Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 A. The reference output requires a capacitor of 10 F to AGND for filtering and stability. The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input (WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section.
CS0 CS1 DATA_AV
22 21 16
I I O
DGND DVDD D0 - D9 RA0/D10 RA1/D11 OV_FL REFIN REFP
17 18 1-6, 9-12 13 14 32 28 26
I I I/O/Z I/O/Z I/O/Z O I I
REFM
25
I
RESET REFOUT RD WR (R/W)
31 27 19 20
I O I I
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
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SLAS271A - MAY 2000 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3 V to AVDD + 1.5 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 + AGND to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to BVDD/DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating free-air temperature range: THS12082C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C THS12082I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN Supply voltage AVDD DVDD BVDD 4.75 3 3 NOM 5 3.3 3.3 MAX 5.25 5.25 5.25 V UNIT
analog and reference inputs
MIN Analog input voltage in single-ended configuration Common-mode input voltage VCM in differential configuration External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) Input voltage difference, REFP - REFM 1.4 VREFM 1 NOM 2.5 3.5 1.5 2 MAX VREFP 4 AVDD-1.2 UNIT V V V V V
digital inputs
MIN High-level High level input voltage VIH voltage, Low-level Low level input voltage VIL voltage, Input CONV_CLK frequency CONV_CLK pulse duration, clock high, tw(CONV_CLKH) CONV_CLK pulse duration, clock low, tw(CONV_CLKL) Operating free-air temperature, TA free air temperature BVDD = 3 V BVDD = 5.25 V BVDD = 3 V BVDD = 5.25 V DVDD = 3 V to 5.25 V DVDD = 3 V to 5.25 V DVDD = 3 V to 5.25 V THS12082CDA THS12082IDA 0.1 62 62 0 -40 83 83 2 2.6 0.6 0.6 8 5000 5000 70 85 NOM MAX UNIT V V V V MHz ns ns C
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SLAS271A - MAY 2000 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions, VREFP = 3.5 V, VREFM = 1.5 V (unless otherwise noted)
digital specifications
PARAMETER Digital inputs IIH IIL Ci VOH VOL IOZ CO CL High-level input current Low-level input current Input capacitance High-level output voltage Low-level output voltage High-impedance-state output current Output capacitance Load capacitance at databus D0 - D11 IOH = -50 A, IOL = 50 A, CS1 = DGND, BVDD = 3.3 V, 5 V BVDD = 3.3 V, 5 V CS0 = DVDD BVDD-0.5 0.4 -10 5 30 10 DVDD = digital inputs Digital input = 0 V -50 -50 5 50 50 A A pF V V A pF pF TEST CONDITIONS MIN TYP MAX UNIT
Digital outputs
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SLAS271A - MAY 2000 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions, AVDD = 5 V, DVDD = BVDD = 3.3-V, fs = 8 MSPS, VREF = internal (unless otherwise noted)
dc specifications
PARAMETER Resolution Accuracy Integral nonlinearity, INL Differential nonlinearity, DNL Offset error Gain error Analog input Input capacitance Input leakage current Internal voltage reference Accuracy, VREFP Accuracy, VREFM Temperature coefficient Reference noise Accuracy, REFOUT Power supply IDDA IDDD IDDB IDD_AP Analog supply current Digital supply voltage Buffer supply voltage Analog supply current in power-down mode Power dissipation Power dissipation in power down AVDD =5 V, AVDD = 5 V AVDD = 5 V, AVDD = 5 V, AVDD = 5 V, AVDD = 5 V, BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V DVDD = BVDD = 3.3 V DVDD = BVDD = 3.3 V 186 30 36 0.5 1.5 40 1 4 8 216 mA mA mA mA mW mW 2.475 3.3 1.4 3.5 1.5 50 100 2.5 2.525 3.7 1.6 V V PPM/C V V VAIN = VREFM to VREFP 15 10 pF A After calibration in single-ended mode After calibration in differential mode -20 -20 20 20 20 1.5 1 LSB LSB LSB LSB LSB TEST CONDITIONS MIN 12 TYP MAX UNIT Bits
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SLAS271A - MAY 2000 - REVISED JUNE 2000
electrical characteristics over recommended operating conditions, VREF = internal, fs = 8 MSPS, fI = 2 MHz at -1dBFS (unless otherwise noted)
ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER SINAD SNR THD ENOB (SNR) SFDR Signal-to-noise Signal to noise ratio + distortion Signal-to-noise Signal to noise ratio Total harmonic distortion Effective number of bits Spurious free dynamic range TEST CONDITIONS Differential mode Single-ended mode (see Note 1) Differential mode Single-ended mode (see Note 1) Differential mode Single-ended mode Differential mode Single-ended mode (see Note 1) Differential mode Single-ended mode 67 10.17 64 MIN 63 TYP 65 64 69 68 -70 -68 10.5 10.34 71 69 -67 MAX UNIT dB dB dB dB dB dB Bits Bits dB dB
Analog Input Full-power bandwidth with a source impedance of 150 in differential configuration. Full-power bandwidth with a source impedance of 150 in single-ended configuration. Small-signal bandwidth with a source impedance of 150 in differential configuration. Small-signal bandwidth with a source impedance of 150 in single-ended configuration. Full scale sinewave, -3 dB Full scale sinewave, -3 dB 100 mVpp sinewave, -3 dB 100 mVpp sinewave, -3 dB 96 54 96 54 MHz MHz MHz MHz
NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock.
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timing specifications (AVDD = BVDD = DVDD = 5 V, VREFP = 3.5 V, VREFM = 1.5 V, CL < 30 pF
PARAMETER td(DATA_AV) td(o) td(pipe) Delay time Delay time Latency TEST CONDITIONS MIN TYP 5 5 5 MAX UNIT ns ns CONV CLK
timing specification of the single conversion mode
PARAMETER tc t1 tdA t2 Clock cycle of the internal clock oscillator Pulse duration, CONVST duration Aperture time Time between consecutive start of single conversion 1 analog input 2 analog inputs 1 analog input, TL = 1 2 analog inputs, TL = 2 1 analog input, TL = 4 td(DATA_AV) d(DATA AV) Delay time, DATA_AV becomes active for the trigger y , _ gg level condition: TRIG0 = 1, TRIG1 = 1 2 analog inputs, TL = 4 1 analog input, TL = 8 2 analog inputs, TL = 8 1 analog input, TL = 14 2 analog inputs, TL = 12 2xtc 3xtc 6xtc 7xtc 3xt2 +6xtc t2 +7xtc 7xt2 +6xtc 3xt2 +7xtc 13xt2 +6xtc 5xt2 +7xtc 1 analog input 2 analog inputs TEST CONDITIONS MIN 117 1.5xtc 2.5xtc 1 TYP 125 MAX 133 UNIT ns ns ns ns ns ns ns ns
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detailed description
reference voltage The THS12082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. analog inputs The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed. analog-to-digital converter The THS12082 uses a 12-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit stages, which achieves a high sample rate with low power consumption. The THS12082 distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. conversion modes The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations. Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION 1 single-ended channel 2 single-ended channels 1 differential channel NUMBER OF CHANNELS 1 2 1 MAXIMUM CONVERSION RATE PER CHANNEL 8 MSPS 4 MSPS 8 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by: fc MSPS + #8channels
Table 2 shows the maximum conversion rate in the single conversion mode.
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sampling rate (continued) Table 2. Maximum Conversion Rate in Single Conversion Mode
CHANNEL CONFIGURATION 1 single-ended channel 2 single-ended channels 1 differential channel NUMBER OF CHANNELS 1 2 1 MAXIMUM CONVERSION RATE PER CHANNEL 4 MSPS 2.67 MSPS 4 MSPS
In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1. A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13. Figure 1 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be selected to be sampled simultaneously (see Table 2).
t2 CONVST t1 td(A) AIN Sample N tDATA_AV t1
DATA_AV, Trigger Level = 1
Figure 1. Timing of Single Conversion Mode The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n x tc. This equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer to the timing specifications of single conversion mode.
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continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO. Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 8 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set to 1 or 4.
Sample N Channel 1 Sample N+1 Channel 1 Sample N+2 Channel 1 Sample N+3 Channel 1 Sample N+4 Channel 1 Sample N+5 Channel 1 Sample N+6 Channel 1 Sample N+7 Channel 1 Sample N+8 Channel 1
AIN
td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) 50% tc 50% td(O)
Data N-4 Channel 1 Data N-3 Channel 1 Data N-2 Channel 1 Data N-1 Channel 1 Data N Channel 1 Data N+1 Channel 1 Data N+2 Channel 1 Data N+3 Channel 1
CONV_CLK
Data Into FIFO DATA_AV, Trigger Level = 1
Data N-5 Channel 1
td(DATA_AV)
td(DATA_AV)
DATA_AV, Trigger Level = 4
Figure 2. Timing of Continuous Conversion Mode (1-channel operation) Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4.
Sample N Channel 1,2 Sample N+1 Channel 1,2 Sample N+2 Channel 1,2 Sample N+3 Channel 1,2 Sample N+4 Channel 1,2
AIN
td(A) tw(CONV_CLKH) td(Pipe) tw(CONV_CLKL) 50% td(O)
Data N-2 Channel 1 Data N-2 Channel 2 Data N-1 Channel 1 Data N-1 Channel 2 Data N Channel 1 Data N Channel 2 Data N+1 Channel 1 Data N+1 Channel 2
CONV_CLK
50% tc
Data Into FIFO DATA_AV, Trigger Level = 2
Data N-3 Channel 2
td(DATA_AV)
td(DATA_AV)
DATA_AV, Trigger Level = 4
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
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digital output data format
The digital output data format of the THS12082 can be in either binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE AIN = VREFP AIN = (VREFP + VREFM)/2 AIN = VREFM DIGITAL OUTPUT CODE FFFh 800h 000h
Table 4. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT ANALOG INPUT VOLTAGE AIN = VREFP AIN = (VREFP + VREFM)/2 AIN = VREFM DIGITAL OUTPUT CODE 7FFh 000h 800h
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE Vin = AINP - AINM VREF = VREFP - VREFM Vin = VREF Vin = 0 Vin = -VREF FFFh 800h 000h DIGITAL OUTPUT CODE
Table 6. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE Vin = AINP - AINM VREF = VREFP - VREFM Vin = VREF Vin = 0 Vin = -VREF 7FFh 000h 800h DIGITAL OUTPUT CODE
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FIFO description
In order to facilitate an efficient connection to today's processors, the THS12082 is supplied with a FIFO. This integrated FIFO enables a problem-free processing of data. The FIFO is provided as a flexible circular buffer. The circular buffer integrated in the THS12082 can store up to 16 conversion values. Therefore, the number of interrupts to be served by a processor can be reduced significantly.
16 15 14 13 12 Trigger Pointer 11 10 9 8 Write Pointer 7 6 Data in FIFO Free Read Pointer 1 2 3 4 5
Figure 4. Circular Buffer The converted data of the THS12082 is automatically written into the FIFO. To control the writing and reading process, a write pointer, a read pointer, and a trigger pointer are used. The read pointer always shows the location which will be read next. The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is continually maintained. The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger level from Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values as selected for the trigger level where written into the FIFO. The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel according to the autoscan mode, which is shown in Table 10. The channel information is therefore always maintained.
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reading data from the FIFO
The THS12082 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion values is ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle of reading the data. In Figure 5, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK DATA_AV READ
Figure 5. Trigger Level 1 Selected In Figure 6, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK DATA_AV READ
Figure 6. Trigger Level 4 Selected In Figure 7, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK DATA_AV READ
Figure 7. Trigger Level 8 Selected In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK DATA_AV READ
Figure 8. Trigger Level 14 Selected READ is always the logical combination of CS0, CS1 and RD.
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ADC control register
The THS12082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7. Table 7. Bit Definitions of Control Register CR0 and CR1
BIT CR0 CR1 BIT 9 TEST1 RBACK BIT 8 TEST0 OFFSET BIT 7 SCAN BIN/2's BIT 6 DIFF1 R/W BIT 5 DIFF0 DATA_P BIT 4 CHSEL1 DATA_T BIT 3 CHSEL0 TRIG1 BIT 2 PD TRIG0 BIT 1 MODE OVFL/FRST BIT 0 VREF RESET
writing to control register 0 and control register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control register. Table 8. Control Register Addressing
D0 - D9 Desired register value Desired register value Desired register value Desired register value D10/RA0 0 1 0 1 D11/RA1 0 0 1 1 Addressed Control Register Control register 0 Control register 1 Reserved for future Reserved for future
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initialization of the THS12082
The initialization of the THS12082 should be done according to the configuration flow shown in Figure 9.
Start
Use Default Values? Yes Write 0x401 to THS12082 (Set Reset Bit in CR1)
No
Write 0x401 to THS12082 (Set Reset Bit in CR1)
Clear RESET By Writing 0x400 to CR1
Clear RESET By Writing 0x400 to CR1
Write the User Configuration to CR0
Write the User Configuration to CR1 (Can Include FIFO Reset, Must Exclude RESET)
Continue
Figure 9. THS12082 Configuration Flow
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ADC control registers
control register 0 (see Table 8)
- - - - BIT 9 TEST1 BIT 8 TEST0 BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 CHSEL1 BIT 3 CHSEL0 BIT 2 PD BIT 1 MODE BIT 0 VREF
Table 9. Control Register 0 Bit Functions
BITS 0 RESET VALUE 0 NAME VREF FUNCTION Vref select: Bit 0 = 0 The internal reference is selected. Bit 0 = 1 The external reference voltage is selected. Continuous conversion mode/single conversion mode Bit 1 = 0 Continuous conversion mode is selected. An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 Single conversion mode is selected. In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the THS12082 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is satisfied. 2 0 PD Power down. Bit 2 = 0 The ADC is active. Bit 2 = 1 Power down The reading and writing to and from the digital outputs is possible during power down. It is also possible to read out the FIFO. 3, 4 5,6 7 8,9 0,0 1,0 0 0,0 CHSEL0, CHSEL1 DIFF0, DIFF1 SCAN TEST0, TEST1 Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10. Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10. Autoscan enable Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10. Test input enable Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation. Refer to Table 11 for selection of the three different test voltages.
1
0
MODE
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analog input channel selection
The analog input channels of the THS12082 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections. Table 10. Analog Input Channel Configurations
BIT 7 AS 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 BIT 6 DF1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 BIT 5 DF0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 BIT 4 CHS1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 BIT 3 CHS0 0 1 0 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 1 DESCRIPTION OF THE SELECTED INPUTS Analog input AINP (single ended) Analog input AINM (single ended) Reserved Reserved Differential channel (AINP-AINM) Reserved Autoscan two single ended channels: AINP, AINM, AINP, ... Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11. Table 11. Test Mode
BIT 9 TEST1 0 0 1 1 BIT 8 TEST0 0 1 0 1 OUTPUT RESULT Normal mode VREFP ((VREFM)+(VREFP))/2 VREFM
Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor.
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analog input channel selection (continued)
control register 1 (see Table 8)
- - - - BIT 9 RBACK BIT 8 OFFSET BIT 7 BIN/2s BIT 6 R/W BIT 5 DATA_P BIT 4 DATA_T BIT 3 TRIG1 BIT 2 TRIG0 BIT 1 OVFL/FRST BIT 0 RESET
Table 12. Control Register 1 Bit Functions
BITS 0 RESET VALUE 0 NAME RESET Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first value is converted and written into the FIFO. 1 0 OVFL (read only) Overflow flag (read only) Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 no overflow occurred. Bit 1 = 1 an overflow occurred. This bit is reset to 0, after this control register is read from the processor. FRST: FIFO reset (write only) By writing a 1 into this bit, the FIFO is reset. FIFO trigger level Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This indicates to the processor that the ADC values can be read. Refer to Table 13. DATA_AV type Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a pulse. Refer to Table 14. 5 1 DATA_P DATA_AV polarity Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0, DATA_AV is active low. Refer to Table 14. 6 0 R/W R/W, RD/WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. 7 0 BIN/2s Complement select If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6. 8 0 OFFSET Offset cancellation mode Bit 8 = 0 normal conversion mode Bit 8 = 1 offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error. 9 0 RBACK Debug mode Bit 9 = 0 normal conversion mode Bit 9 = 1 enable debug mode When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. FUNCTION
FRST (write only) 2, 3 0,0 TRIG0, TRIG1
4
1
DATA_T
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FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read. Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be selected, is dependent on the number of input channels. Either a differential or a single-ended input is considered as one channel. The processor, therefore, always reads the data from the FIFO in the same order and is able to distinguish between the channels. Table 13. FIFO Trigger Level
BIT 3 TRIG1 0 0 1 1 BIT 2 TRIG0 0 1 0 1 TRIGGER LEVEL FOR 1 CHANNEL (ADC values) 01 04 08 14 TRIGGER LEVEL FOR 2 CHANNELS (ADC values) 02 04 8 12
timing and signal description of the THS12082
The reading from the THS12082 and writing to the THS12082 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS12082 takes place by an internal RDint signal, which is generated from the logical combination of the external signals CS0, CS1 and RD (see Figure 10). This signal is then used to strobe the words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RDint active while the write input (WR) is inactive. The first of those external signals going to its inactive state will then deactivate RDint again. Writing to the THS12082 takes place by an internal WRint signal, which is generated from the logical combination of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WRint active while the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate WRint again.
CS0 CS1 RD Write Enable WR Read Enable
Control/Data Registers Data Bits
Figure 10. Logical Combination of CS0, CS1, RD, and WR
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DATA_AV type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in Table 14. Table 14. DATA_AV Type
BIT 5 DATA_P 0 0 1 1 BIT 4 DATA_T 0 1 0 1 DATA_AV TYPE Active low level Active low pulse Active high level Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive independent of the DATA_T selection (pulse or level). If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of READ). The trigger condition is checked again after TL reads. If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode. When the TL values previously written into the FIFO were read out by the processor, the next DATA_AV pulse (when the trigger condition is satisfied) is sent out first.
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timing and signal description of the THS12082
read timing (using R/W, CS0-controlled) Figure 11 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
tw(CS) 90% CS0 10% 10%
CS1 tsu(R/W) 90% th(R/W)
R/W
90%
RD
ta 90%
th
D(0-11) td(CSDAV) DATA_AV 90%
Figure 11. Read Timing Diagram Using R/W (CS0-controlled) read timing parameter (CS0-controlled)
PARAMETER tsu(R/W) ta td(CSDAV) th th(R/W) tw(CS) CS = CSO Setup time, R/W high to last CS valid Access time, last CS valid to data valid Delay time, last CS valid to DATA_AV inactive Hold time, first CS invalid to data invalid Hold time, first external CS invalid to R/W change Pulse duration, CS active 0 5 10 MIN 0 0 12 5 10 TYP MAX UNIT ns ns ns ns ns ns
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timing and signal description of the THS12082 (continued)
write timing (using R/W, CS0-controlled) Figure 12 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
tw(CS) CS0 90% 10% 10%
CS1 tsu(R/W) WR
th(R/W)
RD
tsu
D(0-11)
90%
DATA_AV
write timing parameter (CSO-controlled)
tsu(R/W) tsu th th(R/W) tw(CS) CS = CSO Setup time, R/W stable to last CS valid Setup time, data valid to first CS invalid Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change Pulse duration, CS active
IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII
Figure 12. Write Timing Diagram Using R/W (CS0-controlled)
PARAMETER MIN 0 5 2 5 10 TYP MAX UNIT ns ns ns ns ns
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timing and signal description of the THS12082 (continued)
interfacing the THS12082 to the TMS320C30/31/33 DSP The following application circuit shows an interface of the THS12082 to the TMS320C30/31/33 DSPs. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS12082 DVDD CS0 CS1 RD R/W DATA_AV CONV_CLK DATA STRB A23 R/W INTX TOUT DATA TMS320C30/31/33
interfacing the THS12082 to the TMS320C54x using I/O strobe The following application circuit shows an interface of the THS12082 to the TMS320C54x. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS12082 DVDD CS0 CS1 RD R/W DATA_AV CONV_CLK DATA I/O STRB A15 R/W INTX BCLK DATA TMS320C54x
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timing and signal description of the THS12082 (continued)
read timing (using RD, RD-controlled) Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD that becomes valid.
CS0
CS1 tsu(CS) WR th(CS)
tw(RD) 10% ta 90% 10% th
RD
D(0-11) td(CSDAV) DATA_AV 90%
Figure 13. Read Timing Diagram Using RD (RD-controlled) read timing parameter (RD-controlled)
PARAMETER tsu(CS) ta td(CSDAV) th th(CS) tw(RD) Setup time, RD low to last CS valid Access time, last CS valid to data valid Delay time, last CS valid to DATA_AV inactive Hold time, first CS invalid to data invalid Hold time, RD change to first CS invalid Pulse duration, RD active 0 5 10 MIN 0 0 12 5 10 TYP MAX UNIT ns ns ns ns ns ns
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timing and signal description of the THS12082 (continued)
write timing (using WR, WR-controlled) Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR that becomes valid.
CS0
CS1 tsu(CS) tw(WR) WR 10% 10% th(CS)
RD
tsu 90%
D(0-11)
DATA_AV
write timing parameter using WR (WR-controlled)
PARAMETER tsu(CS) tsu th th(CS) tw(WR) Setup time, CS stable to last WR valid Setup time, data valid to first WR invalid Hold time, WR invalid to data invalid Hold time, WR invalid to CS change Pulse duration, WR active MIN 0 5 2 5 10 TYP MAX UNIT ns ns ns ns ns
26
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
Figure 14. Write Timing Diagram Using WR (WR-controlled)
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interfacing the THS12082 to the TMS320C6201 DSP
The following application circuit shows an interface of the THS12082 to the TMS320C6201. The read (using RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.
THS12082-1 CS0 CS1 RD WR DATA_AV DATA CONV_CLK TMS320C6201 CE1 EA20 ARE AWE EXT_INT6 DATA TOUT1 TOUT2 EA21 EXT_INT7
THS12082-2 CS0 CS1 RD WR DATA_AV DATA CONV_CLK
analog input configuration and reference voltage
The THS12082 features two analog input channels. These can be configured for either single-ended or differential operation. Best performance is achieved in differential mode. Figure 15 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference voltage). The analog input voltage range goes from VREFM to VREFP. This means that VREFM defines the minimum voltage, which can be applied to the ADC. VREFP defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V. The resulting analog input voltage swing of 2 V can be expressed by: V REFM
v AINP v VREFP
(1)
VREFP
AINP
12-Bit ADC VREFM
Figure 15. Single-Ended Input Stage
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analog input configuration and reference voltage (continued)
A differential operation is desired for many applications. Figure 16 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which are discussed in the following paragraphs.
VREFP AINP +
- AINM
VADC
12-Bit ADC VREFM
Figure 16. Differential Input Stage In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the input of the ADC, is the difference between the input AINP and AINM. This means that VREFM defines the minimum voltage (VADC), which can be applied to the ADC. VREFP defines the maximum voltage (VADC), which can be applied to the ADC. The voltage VADC can be calculated as follows: V ADC
+ ABS(AINP-AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage V CM
+ AINM ) AINP 2
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true: AGND
v AINM, AINP v AVDD 1 VvV v4 V CM
(4) (5)
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection, which is common to both analog inputs. See also Figure 18.
single-ended mode of operation
The THS12082 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the THS12082 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS12082 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc- and ac-coupling. An application example is shown for dc-coupled level shifting in the following section, dc-coupling.
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dc coupling
An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS12082. The analog input voltage range of the THS12082 goes from 1.5 V to 3.5 V. An operational amplifier specified for 5-V single supply can be used as shown in Figure 17. Figure 17 shows an application example where the analog input signal in the range from -1 V up to 1 V is shifted by an operational amplifier to the analog input range of the THS12082 (1.5 V to 3.5 V). The operational amplifier is configured as an inverting amplifier with a gain of -1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS12082 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
R 5V 1V 0V -1 V R 1.25 V _ + REFIN REFOUT R 3.5 V 2.5 V 1.5 V RS THS12082 AINP
R
Figure 17. Level-Shift for DC-Coupled Input
differential mode of operation
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode.
Mini Circuits T4-1 49.9 R 200 R AINM C REFOUT C THS12082 AINP
Figure 18. Transformer Coupled Input
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED)
80 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS SINAD - Signal-to-Noise and Distortion - dB 70
SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED)
THD - Total Harmonic Distortion - dB
65
60
55
50
45
AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS
40 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz
Figure 19
Figure 20
SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (SINGLE-ENDED)
90 SFDR - Spurious Free Dynamic Range - dB 85 65 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS 40 0 SNR - Signal-to-Noise - dB 80 70
SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (SINGLE-ENDED)
60
55
50
45
AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS
1
2
3
4
5
6
7
8
9
fs - Sampling Frequency - MHz
Figure 21
Figure 22
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL)
85 80 THD - Total Harmonic Distortion - dB 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS SINAD - Signal-to-Noise and Distortion - dB 80 75 70 65 60 55 50 45 40 0
SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS 1 2 3 4 5 6 7 8 9
fs - Sampling Frequency - MHz
Figure 23
Figure 24
SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (DIFFERENTIAL)
100 SFDR - Spurious Free Dynamic Range - dB 95 90 SNR - Signal-to-Noise - dB 85 80 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz 40 0 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS 70 65 60 55 50 45 80 75
SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -1 dBFS
1
2
3
4
5
6
7
8
9
fs - Sampling Frequency - MHz
Figure 25
Figure 26
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TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED)
80 THD - Total Harmonic Distortion - dB 75 70 65 60 55 50 45 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS SINAD - Signal-to-Noise and Distortion - dB 80 75 70 65 60 55 50 45 40 0
SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fi - Input Frequency - MHz
Figure 27
Figure 28
SIGNAL-TO-NOISE vs INPUT FREQUENCY (SINGLE-ENDED)
80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS
SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (SINGLE-ENDED)
100 SFDR - Spurious Free Dynamic Range - dB 95 90 SNR - Signal-to-Noise - dB 85 80 75 70 65 60 55 50 45 40 0 0.5 1.0 1.5 2.0 2.5 3.0 fi - Input Frequency - MHz 3.5 4.0 40 0 70 65 60 55 50 45 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS
75
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fi - Input Frequency - MHz
Figure 29
Figure 30
32
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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL)
80.00 75.00 70.00 65.00 60.00 55.00 50.00 45.00 40.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 80.00 75.00 70.00 65.00 60.00 55.00 50.00 45.00 40.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS
SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL)
Figure 31
SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (DIFFERENTIAL)
100.00 SFDR - Spurious Free Dynamic Range - dB 95.00 90.00 85.00 80.00 75.00 70.00 65.00 60.00 55.00 50.00 45.00 40.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz 45.00 40.00 0 0.5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS SNR - Signal-to-Noise - dB 80.00 75.00 70.00 65.00 60.00 55.00 50.00
Figure 32
SIGNAL-TO-NOISE vs INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS
1.0
1.5
2.0
2.5
3.0
3.5
4.0
fi - Input Frequency - MHz
Figure 33
Figure 34
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* DALLAS, TEXAS 75265
33
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED)
12 ENOB - Effective Number of Bits - Bits ENOB - Effective Number of Bits - Bits AVDD = 5 V, DVDD = BVDD = 3 V, fin = 500 kHz, AIN = -1 dBFS 11 12
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (DIFFERENTIAL)
11
10
10
9
9
8
8
7
7
AVDD = 5 V, DVDD = BVDD = 3 V, fin = 500 kHz, AIN = -1 dBFS
6 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz
6 0 1 2 3 4 5 6 7 8 9 fs - Sampling Frequency - MHz
Figure 35
EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (SINGLE-ENDED)
12 ENOB - Effective Number of Bits - Bits ENOB - Effective Number of Bits - Bits AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS 11 12
Figure 36
EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS 11
10
10
9
9
8
8
7
7
6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz
6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fi - Input Frequency - MHz
Figure 37
Figure 38
34
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY vs ADC CODE
1.00 0.80 0.60 0.40 0.20 -0.00 -0.20 -0.40 -0.60 -0.80 -1 0 500 1000 1500 2000 ADC Code 2500 3000 3500 4000 AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS
DNL - Differential Nonlinearity - LSB
Figure 39
INTEGRAL NONLINEARITY vs ADC CODE
INL - Integral Nonlinearity - LSB 1.00 0.80 0.60 0.40 0.20 -0.00 -0.20 -0.40 -0.60 -0.80 -1 0 AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS 500 1000 1500 2000 ADC Code 2500 3000 3500 4000
Figure 40
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35
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY
0 -20 Magnitude - dB -40 -60 -80 -100 -120 -140 0 1000000 2000000 f - Frequency - Hz 3000000 4000000 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS fin = 1.25 MHz
Figure 41
FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY
0 -20 Magnitude - dB -40 -60 -80 -100 -120 -140 0 1000000 2000000 f - Frequency - Hz 3000000 4000000 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = -1 dBFS fin = 1.25 MHz
Figure 42
36
POST OFFICE BOX 655303
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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
definitions of specifications and terminology
integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than 1 LSB ensures no missing codes. zero offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. gain error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N
+ (SINAD * 1.76) 6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
POST OFFICE BOX 655303
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THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271A - MAY 2000 - REVISED JUNE 2000
MECHANICAL DATA
DA (R-PDSO-G**)
38 PINS SHOWN 0,30 0,19 20
PLASTIC SMALL-OUTLINE PACKAGE
0,65 38
0,13 M
6,20 NOM
8,40 7,80 0,15 NOM
Gage Plane 1 A 19 0- 8 0,75 0,50 0,25
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
28
30
32
38
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40 4040066 / D 11/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153
38
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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