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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
features
applications
D D D D D D D D D D D D
40 MSPS Maximum Sample Rate 12-Bit Resolution No Missing Codes On-Chip Sample and Hold 73 dB Spurious Free Dynamic Range at fIN = 15.5 MHz 5 V Analog and Digital Supply 3 V and 5 V CMOS Compatible Digital Output 10.6 Bit ENOB at fIN = 31 MHz 66 dB SNR at fIN = 15.5 MHz 82 MHz Bandwidth Internal or External Reference Buffered 900- Differential Analog Input
D D D D D
Wireless Local Loop Wireless Internet Access Cable Modem Receivers Medical Ultrasound Magnetic Resonant Imaging
48 PHP PACKAGE (TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
AVSS AVDD AVSS AVDD AVSS AVSS DRVSS DRVSS DRVDD DRVDD
VCM AVDD
description
5 6
32
31 The THS1240 is a high speed low noise 12-bit 30 7 CMOS pipelined analog-to-digital converter. A 29 8 differential sample and hold minimizes even order 28 9 harmonics and allows for a high degree of 27 10 common mode rejection at the analog input. A 26 11 buffered analog input enables operation with a 25 12 constant analog input impedance, and prevents transient voltage spikes from feeding backward to 13 14 15 16 17 18 19 20 21 22 23 24 the analog input source. Full temperature DNL performance allows for industrial application with the assurance of no missing codes. The typical integral nonlinearity (INL) for the THS1240 is less than one LSB. The superior INL curve of the THS1240 results in SFDR performance that is exceptional for a 12-bit analog-to-digital converter. The THS1240 can operate with either internal or external references. Internal reference usage selection is accomplished simply by externally connecting reference output terminals to reference input terminals. AVAILABLE OPTIONS PACKAGE TA - 40C to 85C 0C to 70C 48-TQFP (PHP) THS1240I THS1240C
VREFOUT- VREFIN- VREFIN+ VREFOUT+ VBG AVSS AVDD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
AVSS AVDD VIN+ VIN- AVDD
1 2 3 4
36 35 34 33
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
DVSS CLK+ CLK- DVDD DVSS DVSS DVDD DVSS DVDD DRVSS DRVDD
AV SS
THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
functional block diagram
AVDD DVDD DRVDD VIN+ Buffer 900 VIN-
A/D D/A
Stage 1 S/H
Stages 2 - 10
Stage 11
Stage 12
A/D D/A
1 Digital Error Correction
A/D
VREFIN+ VREFOUT+ VREFOUT- VREFIN- VCM CLK+
1
3.0 V Reference AVDD/2 2.0 V
1
Timing CLK-
PRODUCT PREVIEW
AVSS
DVSS DRVSS
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Terminal Functions
TERMINAL NAME AVDD AVSS CLK+ CLK- D11-D0 DRVDD DRVSS DVDD DVSS VBG VCM VIN+ VIN- VREFIN - VREFIN+ VREFOUT+ VREFOUT - NO. 2, 5, 12 43, 45, 47 1, 11, 13, 41, 42, 44, 46 15 16 25-36 24, 37, 38 23, 39, 40 17, 20, 22 18, 19, 21 10 48 3 4 7 8 9 6 I/O I I I I O I I I I O O I I I I O O Analog power supply Analog ground return for internal analog circuitry Clock input Complementary clock input Digital data output bits; LSB= D0, MSB = D9 (2s complement output format) Digital output driver supply Digital output driver ground return Positive digital supply Digital ground return Band gap reference. Bypass to ground with a 1 F and a 0.01 F chip capacitor. Common mode voltage output. Bypass to ground with a 0.1 F and a 0.01 F chip device capacitor. Analog signal input Complementary analog signal input External reference input low External reference input high Internal reference output. Compensate with a 1 F and a 0.01 F chip capacitor. Internal reference output. Compensate with a 1 F and a 0.01 F chip capacitor. DESCRIPTION
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
detailed description
The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible bandwidth. The differential analog inputs are terminated with a 900- resistor. The inputs are then fed to a unity gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram. The digital output of the 12 stages are sent to a digital correction logic block which then outputs the final 12 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V DRVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage between AVSS and DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 0.5 V Voltage between DRVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5 V Voltage between AVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5 V Digital data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DVDD + 0.3 V CLK peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA Operating free-air temperature range, TA: THS1240C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C THS1240I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER Sample rate Analog supply voltage, AVDD Digital supply voltage, DVDD Digital output driver supply voltage, DRVDD CLK + high level input voltage, VIH CLK + low-level input voltage, VIL CLK - high-level input voltage, VIH CLK - low-level input voltage, VIL CLK pulse-width high, tp(H) CLK pulse-width low, tp(L) Operating free-air temperature range, TA Operating free-air temperature range, TA THS1240C THS1240I 11.25 11.25 0 - 40 4 MIN 1 4.75 4.75 3 4 5 5 3.3 5 0 5 0 12.5 12.5 70 85 NOM MAX 40 5.25 5.25 5.25 5.5 1 5.5 1 UNIT MSPS V V V V V V V ns ns C C
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 40 MHz (unless otherwise noted)
dc accuracy
PARAMETER DNL INL Differential nonlinearity No missing codes Integral nonlinearity EO Offset error EG Gain error All typical values are at TA = 25C. TEST CONDITIONS MIN TYP 0.6 Assured 2 14 -7 2.5 29 - 10 LSB mV %FSR MAX 0.9 UNIT LSB
power supply
PARAMETER I(AVDD) I(DVDD) Analog supply current Digital supply current TEST CONDITIONS V(VIN) = V(VCM) V(VIN) = V(VCM) V(VIN) = V(VCM) V(VIN) = V(VCM) MIN TYP 100 2 2 0.5 MAX 145 5 6 UNIT mA mA mA W
PRODUCT PREVIEW
I(DRVDD) Output driver supply current PD Power dissipation All typical values are at TA = 25C.
reference
PARAMETER VREFOUT - VREFOUT+ VREFIN - VREFIN+ V(VCM) Negative reference output voltage Positive reference output voltage External reference supplied External reference supplied Common mode output voltage TEST CONDITIONS MIN 1.95 2.95 TYP 2 3 2 3 AVDD/2 10 MAX 2.05 3.05 UNIT V V V V V A
I(VCM) Common mode output current All typical values are at TA = 25C.
analog input
PARAMETER RI CI VI VID Differential input resistance Differential input capacitance Analog input common mode range Differential input voltage range -3 dB TEST CONDITIONS MIN TYP 900 4 VCM 0.05 2 82 MAX UNIT pF V V p-p MHz
BW Analog input bandwidth (large signal) All typical values are at TA = 25C.
digital outputs
PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS IOH = - 50 A IOL = 50 A MIN 0.8DRVDD 0.2DRVDD 15 TYP MAX UNIT V VDD pF
CL Output load capacitance All typical values are at TA = 25C.
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
ac specifications over recommended operating free-air temperature range, AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 40 MHz, analog input at -2 dBFS (unless otherwise noted)
PARAMETER SNR Signal-to-noise ratio TEST CONDITIONS fIN = 2.2 MHz fIN =15.5 MHz fIN =31 MHz fIN = 2.2 MHz SINAD ENOB THD SFDR d 2nd Harmonic Signal-to-noise and distortion Effective number of bits Total harmonic distortion Spurious-free dynamic range Distortion fIN =15.5 MHz fIN =31 MHz fIN =15.5 MHz fIN =15.5 MHz fIN =15.5 MHz fIN = 2.2 MHz fIN =15.5 MHz fIN = 31 MHz fIN = 2.2 MHz d 3rd Harmonic Distortion fIN =15.5 MHz fIN = 31 MHz F1 = 14.9 MHz, F2 = 15.6 MHz, Analog inputs at - 8 dBFS each MIN 64 TYP TBD 66 TBD TBD 66 TBD 10.4 72 10.6 -72 76 TBD -84 -80 -75 -80 72 dBc dBc -68 dBc bits dBc dBFS dBFS MAX UNIT
Two tone SFDR All typical values are at TA = 25C.
operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V, DRVDD = 3.3 V
switching specifications
PARAMETER Aperture delay, td(A) Aperture jitter Output delay td(O) Pipeline delay td(PIPE) All typical values are at TA = 25C. After falling edge of CLK+ 6.5 TEST CONDITIONS MIN TYP 120 1 13 MAX UNIT ps ps RMS ns CLK Cycle
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
definitions of specifications
analog bandwidth The analog input frequency at which the spectral power of the fundamental frequency of a large input signal is reduced by 3 dB. aperture delay The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainity (jitter) The sample-to-sample variation in aperture delay differential nonlinearity The average deviation of any output code from the ideal width of 1 LSB. clock pulse width/duty cycle Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock rate, these specs define acceptable clock duty cycles.
PRODUCT PREVIEW
offset error The difference between the analog input voltage at which the analog-to-digital converter output changes from negative full scale, to one LSB above negative full scale, and the ideal voltage at which this transition should occur. gain error The maximum error in LSBs between a digitized ideal full scale low frequency offset corrected triangle wave analog input, from the ideal digitized full scale triangle wave, divided by the full scale range, in this case 1024. harmonic distortion The ratio of the power of the fundamental to a given harmonic component reported in dBc. integral nonlinearity The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB. Also the integral of the DNL curve. output delay The delay between the 50% point of the falling edge of the clock and signal and the time when all output data bits are within valid logic levels (not including pipeline delay). signal-to-noise-and distortion (SINAD) When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral components, excluding dc, referenced to full scale. signal-to-noise ratio (SNR) When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral components, excluding dc and the first 9 harmonics, referenced to full scale. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula, ENOB
+ (SINAD * 1.76) 6.02
spurious-free dynamic range (SFDR) The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
Sample N
V(VIN)
td(A) tp(H) tP(L) td(Pipe)
CLK+
tc td(O)
Data N-6 Data N-5 Data N-4 Data N-3 Data N-2 Data N-1 Data N Data N+1 Data N+2
Digital Output (D0 - D9)
Data N-7
Figure 1. Timing Diagram
equivalent circuits
R2 BAND GAP R1 VREFOUT+ VREFOUT- R1 R2 AVDD 600 VCM 590 AVSS VIN+ 900 VIN- 1 1 VCM 2 1 2 VCM
Figure 3. Analog Input Stage
Figure 2. References
DVDD VDD CLK+ 10 Timing D0-D11
DVSS DVDD
CLK-
VSS
DVSS
Figure 5. Digital Outputs
Figure 4. Clock Inputs
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PRODUCT PREVIEW
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
APPLICATION INFORMATION using the THS1240 references
The option of internal or external reference is provided by allowing for an external connection of the internal reference to the reference inputs. This type of reference selection offers the lowest noise possible by not relying on any active switch to make the selection. Compensating each reference output with a 1-F and 0.01-F chip capacitor is required as shown in Figure 6. The differential analog input range is equal to 2 (VREFOUT+ - VREFOUT-). When using external references, it is best to decouple the reference inputs with a 0.1-F and 0.01-F chip capacitor as shown in Figure 7.
VREFIN+ VREFOUT+ 0.01 F 1 F VREFIN- VREFOUT- External Reference - 0.01 F 0.1 F VREFIN- External Reference + 0.01 F 0.1 F VREFIN+
PRODUCT PREVIEW
0.01 F
1 F
Figure 6. Internal Reference Usage
Figure 7. External Reference Usage
using the THS1240 clock input
The THS1240 is a high performance A/D converter. In order to obtain the best possible performance, care should be taken to ensure that the device is clocked appropriately. The optimal clock to the device is a low jitter square wave with sharp rise times (< 2ns) at 50% duty cycle. The two clock inputs (CLK+ and CLK-), should be driven with complementary signals that have minimal skew, and nominally swing between 0 V and 5 V. The device will still operate with a peak-to-peak swing of 3 V on each clock channel (around the 2.5 V midpoint). Use of a transformer coupled clock input ensures minimal skew between the CLK+ and CLK- signals. If the available clock signal swing is not adequate, a step-up transformer can be used in order to deliver the required levels to the converter's inputs, see Figure 8. For example if a 3.3 V standard CMOS logic is used for clock generation, a minicircuits T4 -1H transformer can be used for 2x voltage step-up. This provides greater than 6-V differential swing at the secondary of the transformer, which provides greater than 3-V swings to both CLK+ and CLK- terminals of THS1240. The center tap of the transformer secondary is connected to the VCM terminal of the THS1240 for proper dc biasing. Both the transformer and the clock source should be placed close to THS1240 to avoid transmission line effects. 3.3 V TTL logic is not recommended with T4 -1H transformer due to TTLs tendency to have lower output swings. If the input to the transformer is a square wave (such as one generated by a digital driver), care must be taken to ensure that the transformer's bandwidth does not limit the signal's rise time and effectively alter its shape and duty cycle characteristics. For a 40 MSPS rate, the transformer's bandwidth should be at least 300 MHz. A low phase noise sinewave can also be used to effectively drive the THS1240. In this case, the bandwidth of the transformer becomes less critical, as long as it can accommodate the frequency of interest (for example, 50 MHz). The turns ratio should be chosen to ensure appropriate levels at the device's input. If the clock signal is fed through a transmission line of characteristic impedance Zo, then the secondary of the transformer should be terminated with a resistor of nZo, where n is the transformer's impedance ratio (1:n) as shown in Figure 8. Alternatively a series termination resistor having impedance equal to the characteristic impedance of the transmission line can be used at the clock source.
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
APPLICATION INFORMATION
3 V p-p to 5 V p-p Zo R = Zo T4-1H ac Signal Source R = 4 Zo THS1240 CLK- VCM Impedance Ratio = 1:4 CLK+
0.1 F
0.01 F
0.1 F
Figure 8. Driving the Clock From an Impedance Matched Source The clock signals, CLK+ and CLK-, should be well-matched and must both be driven.
The clock input can also be driven differentially with a 5 V TTL signal by using an RF transformer to convert the TTL signal to a differential signal. The TTL signal is ac-coupled to the positive primary terminal with a high pass circuit. The negative terminal of the transformer is connected to ground (see Figure 9). The transformer secondary is connected to the CLK inputs.
Impedance Ratio = 1:4 0.1 F 5 V TTL CLK T4 - 1H CLK+ THS1240 CLK- VCM
0.01 F
0.1 F
Figure 9. TTL Clock Input
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PRODUCT PREVIEW
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up to 500 ps between CLK+ and CLK- can be tolerated with some performance degradation.
THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
APPLICATION INFORMATION using the analog input
The THS1240 obtains optimum performance when the analog signal inputs are driven differentially. The circuit below shows the optimum configuration, see Figure 10. The signal is fed to the primary of an RF transformer. Since the input signal must be biased around the common mode voltage of the internal circuitry, the common mode (VCM) reference from the THS1240 is connected to the center-tap of the secondary. To ensure a steady low noise VCM reference, the best performance is obtained when the VCM output is connected to ground with a 0.1-F and 0.01-F low inductance capacitor.
R0 Z0 = 50
1:1
50
ac Signal Source T1-1T R 50
VIN+ THS1240 VIN- VCM
PRODUCT PREVIEW
0.01 F
0.1 F
Figure 10. Driving the THS1240 Analog Input With Impedance Matched Transmission Line When it is necessary to buffer or apply a gain to the incoming analog signal, it is also possible to combine a single-ended amplifier with an RF transformer as shown in Figure 11. For this application, a wide-band current mode feedback amplifier such as the THS3001 is best. The noninverting input to the operational amplifier is terminated with a resistor having an impedance equal to the characteristic impedance of the wave-guide or trace that sources the IF input signal. The single ended output allows the use of standard passive filters between the amplifier output and the primary. In this case, the SFDR of the operational amplifier is not as critical as that of the A/D converter. While harmonics generated from within the A/D converter fold back into the first Nyquist zone, harmonics generated externally in the operational amplifier can be filtered out with passive filters.
1 k 1 k Impedance Ratio = 1:n _ IF Input RT + THS3001 10 BPF VIN+ THS1240 VIN- VCM
0.1 F
0.01 F
Figure 11. IF Input Buffered With THS3001 Operational Amplifier
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SLAS279 - JUNE 2000
APPLICATION INFORMATION digital outputs
The digital outputs are in 2s complement format and can drive either TTL, 3-V CMOS, or 5-V CMOS logic. The digital output high voltage level is equal to DRVDD. Table 1 shows the value of the digital output bits for full scale analog input voltage, midrange analog input voltage, and negative full scale input voltage. To reduce capacitive loading, each digital output of the THS1240 should drive only one digital input. The CMOS output drivers are capable of handling up to a 15 pF load. For better SNR performance, use 3.3 V for DRVDD. Resistors of 200 in series with the digital output can be used for optimizing SNR performance. Table 1. Digital Outputs
ANALOG INPUT (VIN+) OR - (VIN-) Vref+ VCM Vref- D11 0 0 1 D10 1 0 0 D9 1 0 0 D8 1 0 0 D7 1 0 0 D6 1 0 0 D5 1 0 0 D4 1 0 0 D3 1 0 0 D2 1 0 0 D1 1 0 0 D0 1 0 0
power supplies
Best performance is obtained when AVDD is kept separate from DVDD. Regulated or linear supplies, as opposed to switched power supplies, must be used to minimize supply noise. It is also recommended to partition the analog and digital components on the board in such a way that the analog supply plane does not overlap with the digital supply plane in order to limit dielectric coupling between the different supplies. package The THS1240 is packaged in a small 48-pin quad flat-pack PowerPADTM package. The die of the THS1240 is bonded directly to copper alloy plate which is exposed on the bottom of the package. Although, the PowerPADTM provides superior heat dissipation when soldered to ground land, it is not necessary to solder the bottom of the PowerPADTM to anything in order to achieve minimum performance levels indicated in this specification over the full recommended operating temperature range. If the device is to be used at ambient temperatures above the recommended operating temperatures, use of the PowerPADTM is suggested. The copper alloy plate or PowerPADTM is exposed on the bottom of the device package for a direct solder attachment to a PCB land or conductive pad. The land dimensions should have minimum dimensions equal to the package dimensions minus 2 mm, see Figure 12. For a multilayer circuit board, a second land having dimensions equal to or greater than the land to which the device is soldered should be placed on the back of the circuit board (see Figure 13). A total of 9 thermal vias or plated through-holes should be used to connect the two lands to a ground plane (buried or otherwise) having a minimum total area of 3 inches square in 1 oz. copper. For the THS1240 package, the thermal via centers should be spaced at a minimum of 1 mm. The ground plane need not be directly under or centered around the device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel the heat from the vias to the larger portion of the ground plane. The THS1240 package has a standoff of 0.19 mm or 7.5 mils. In order to apply the proper amount of solder paste to the land, a solder paste stencil with a 6 mils thickness is recommended for this device. Too thin a stencil may lead to an inadequate connection to the land. Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts. For more information, refer to Texas Instruments literature number SLMA002 PowerPADTM Thermally Enhanced Package.
PowerPAD is a trademark of Texas Instruments.
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
APPLICATION INFORMATION package (continued)
1.25 mm 2 x 1.25 mm 1.25 mm
5 mm 2 x 1.25 mm
PRODUCT PREVIEW
0.33 mm Diameter Plated Through Hole 5 mm
Figure 12. Thermal Land (top view)
PHP (S-PQFP-G48)
Plated Through Hole
Thermal Land
Figure 13. Top and Bottom Thermal Lands With Plated Through Holes (side view)
12
IIIIIII II IIII I IIIIIIIIIIIII IIIIIIII IIII IIIIIIIIIIIII II IIIIIII I IIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIII IIIIIIIIIIIII I II I II
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THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER
SLAS279 - JUNE 2000
MECHANICAL DATA
PHP (S-PQFP-G48)
0,50 36 25 0,27 0,17
PowerPADTM PLASTIC QUAD FLATPACK
0,08 M
37
24 Thermal Pad (see Note D)
48
13
1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,05 0,95
12 Gage Plane 0,25 0,15 0,05 0- 7
0,75 0,45 Seating Plane
1,20 MAX
0,08
4146927/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
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PRODUCT PREVIEW
0,13 NOM
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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