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TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
features
application
D D D D D D D D D D D
Single-Chip CCD Analog Front-End 10-Bit, 28-MSPS, Single 3-V Supply Operation A/D Converter Very Low Power: 150-mW Typical, 2-mW Power-Down Mode Differential Nonlinearity Error: < 0.5 LSB Typical Integral Nonlinearity Error: < 0.75 LSB Typical Programmable Gain Amplifier (PGA) With 0-dB to 36-dB Gain Range (0.045 dB/Step) Automatic or Programmable Optical Black Level and Offset Calibration With Digital Filter and Bad Pixel Limits Additional DACs for External Analog Setting Serial Interface for Register Configuration Internal-Reference Voltages 48-Pin TQFP Package
D D
Digital Still Camera Video Camcorder
PFB PACKAGE (TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
STBY RESET CS SDIN SCLK ADCCLK
BLKG CP CP AVDD4 AGND4 OBCLP
AGND5 RBD RMD RPD AVDD5 VSS AVDD1 AGND1 SR SV CLCCD CLREF
37 38 39 40 41 42 43 44 45 46 47 48 1 234 567 8 9 10 11 12 TLV990-28PFB
24 23 22 21 20 19 18 17 16 15 14 13
OE SCKP DACO2 DACO1 AGND3 AVDD3 DIGND DIVDD D9 D8 D7 D6
description
The TLV990-28 is a complete CCD signal processor/digitizer designed for digital still camera and PC camera applications. The TLV990-28 performs all the analog-processing functions necessary to maximize the dynamic range, corrects various errors associated with the CCD sensor, and then digitizes the results with an on-chip high-speed analog-to-digital converter (ADC). The key components of the TLV990-28 include: an input clamp circuit for CCD signal, a correlated double sampler (CDS), a programmable-gain amplifier (PGA) with 0 to 36-dB gain range, two internal digital-to-analog converters (DAC) for automatic or programmable optical black level and offset calibration, a 10-bit, 28-MSPS pipeline ADC, a parallel data port for easy microprocessor interface, a serial port for configuring internal control registers, two additional DACs for external system control, and internal reference voltages. Designed in advanced CMOS process, the TLV990-28 operates from a single 3-V power supply with a normal power consumption of 150 mW at 28 MSPS and 2 mW in power-down mode. Its very high throughput rate, single 3-V operation, very low-power consumption, and fully-integrated analog-processing circuitry make the TLV990-28 an ideal CCD signal-processing solution for digital still cameras and electronic video camcorder applications. This device is available in a 48-pin TQFP package and is specified over a -20C to 75C operating-temperature range.
CCDIN NC AVDD2 AGND2 DGND DVDD D0 D1 D2 D3 D4 D5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
AVAILABLE OPTIONS PACKAGE DEVICE TA - 20C to 75C TQFP (PFB) TLV990-28PFB
functional block diagram
AVDD1-5 CLCCD CLREF RPD RBD RMD DVDD DIVDD OE Three State Latch D0
INT. REF. Clamp 1.2 V REF CDS/ MUX
CCDIN
8-Bit CDAC
PGA 10 PGA Regulator
8-Bit FDAC
10-Bit ADC
D9
Optical Black Pixel Limits
Offset Register
Offset Register
Digital Averager/ Filter
Timing and Control Logic
RESET CLK SV SR BLKG OBCLP STBY
DACO1
8-Bit DAC
DAC REG SCKP CS SCLK SDIN
DACO2
8-Bit DAC
DAC REG
Serial Port
VSS AGND1-5
DGND
DIGND
2
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TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
Terminal Functions
TERMINAL NAME ADCCLK AGND1 AGND2 AGND3 AGND4 AGND5 AVDD1 AVDD2 AVDD3 AVDD4 AVDD5 BLKG CLCCD CCDIN CLREF CP CS D0 - D9 DACO1 DACO2 DGND DIGND DIVDD DVDD NC OBCLP OE RBD RESET RMD RPD SDIN SCKP SCLK SR STBY SV VSS NO. 25 44 4 20 32 37 43 3 19 33 41 36 47 1 48 34, 35 28 7-16 21 22 5 18 17 6 2 31 24 38 29 39 40 27 23 26 45 30 46 42 I I I O I O O I I I I I I I I I O I I O O O I ADC clock input Analog ground for internal CDS circuits Analog ground for internal PGA circuits Analog ground for internal DAC circuits Analog ground for internal ADC circuits Analog ground for internal REF circuits Analog supply voltage for internal CDS circuits, 3 V Analog supply voltage for internal PGA circuits, 3 V Analog supply voltage for internal DAC circuits, 3 V Analog supply voltage for internal ADC circuits, 3 V Analog supply voltage for internal ADC circuits, 3 V Control input. The CDS operation is disabled when BLKG is pulled low. CCD signal clamp control input CCD input Clamp-reference-voltage output Connect these pins to AVDD Chip select. A logic low on this input enables the serial port. 10-bit 3-state ADC output data or offset DACs test data Digital-to-analog converter output1 Digital-to-analog converter output2 Digital ground Digital-interface-circuit ground Digital-interface-circuit supply voltage, 1.8 V- 4.4 V Digital-supply voltage, 3 V No connect Optical black-level and offset-calibration control input, active low Output-data enable, active low Internal bandgap reference for external decoupling Hardware-reset input, active low. This signal forces a reset of all internal registers. Ref- output for external decoupling Ref+ output for external decoupling Serial-data input to configure the internal registers This pin selects the polarity of SCLK. 0 - active low (high when SCLK is not running), 1 - active high (low when SCLK is not running). Serial-clock input. This clock synchronizes the serial data transfer. CCD reference-level-sample clock input Hardware power-down control input, active low CCD signal-level sample clock input Silicon substrate, normally connected to analog ground I/O DESCRIPTION
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, AVDD, DVDD, DIVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD+0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD+0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to 75C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN Analog supply voltage Digital supply voltage Digital interface supply voltage AVDD DVDD DIVDD 2.7 2.7 1.8 NOM 3 3 MAX 3.3 3.3 4.4 UNIT V V V
digital inputs, DIVDD = 3 V
MIN High-level input voltage, VIH Low-level input voltage, VIL Input ADCCLK frequency ADCCLK pulse duration, clock high, tw(MCLKH) ADCCLK pulse duration, clock low, tw(MCLKL) Input SCLK frequency SCLK pulse duration, clock high, tw(SCLKH) SCLK pulse duration, clock low, tw(SCLKL) 12.5 12.5 17.8 17.8 40 0.8DIVDD 0.2DIVDD 28 NOM MAX UNIT V V MHz ns ns MHz ns ns
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TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
electrical characteristics over recommended operating free-air temperature range, TA = 25C, AVDD = DVDD = 3 V, ADCCLK = 28 MHz (unless otherwise noted)
total device
PARAMETER AVDD operating current DVDD operating current Device power consumption Power consumption in power-down mode INL DNL Full CCD channel integral nonlinearity Full CCD channel differential nonlinearity No missing code Full channel output latency AVDD=DVDD= 2.7 V - 3.3 V, Using best fit method AVDD=DVDD= 2.7 V - 3.3 V TEST CONDITIONS MIN TYP 34 4 150 2 0.75 0.5 Assured 6 CLK cycles 2 0.99 MAX UNIT mA mA mW mW LSB LSB
analog-to-digital converter (ADC)
PARAMETER ADC resolution in CCD mode Full-scale input span Conversion rate TEST CONDITIONS MIN TYP 10 2 28 MAX UNIT Bits VP-P MHz
correlated double sample (CDS) and programmable gain amplifier (PGA)
PARAMETER CDS and PGA sample rate CDS full-scale input span Input capacitance of CDS Minimum PGA gain Maximum PGA gain PGA gain resolution PGA programming code resolution 35 Single-ended input 4 0 36 0.045 10 1 37 TEST CONDITIONS MIN TYP MAX 28 1 UNIT MHz V pF dB dB dB Bits
internal digital-to-analog converters (DAC) for offset correction
PARAMETER DAC resolution INL DNL Integral nonlinearity Differential nonlinearity Output settling time To 1% accuracy TEST CONDITIONS MIN TYP 8 0.5 0.5 80 MAX UNIT Bits LSB LSB ns
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electrical characteristics over recommended operating free-air temperature range, TA = 25C, AVDD = DVDD = 3 V, ADCCLK = 28 MHz (unless otherwise noted) (continued)
user digital-to-analog converters (DAC)
PARAMETER DAC resolution INL DNL Integral nonlinearity Differential nonlinearity Output voltage range Output settling time 10 pF external load, settle to 1 mV 0 4 TEST CONDITIONS MIN TYP 8 0.75 0.5 VDD MAX UNIT Bits LSB LSB V s
reference voltages
PARAMETER Internal bandgap voltage reference Temperature coefficient ADC Ref+ ADC Ref- Externally decoupled TEST CONDITIONS MIN 1.43 TYP 1.50 100 2 1 MAX 1.58 UNIT V ppm/C V V
digital specifications
PARAMETER Logic inputs IIH IIL Ci VOH VOL IOZ Co High-level input current Low-level input current Input capacitance High-level output voltage Low-level output voltage High-impedance-state output current Output capacitance IOH = 50 A, DIVDD = 3 V IOL = 50 A, DIVDD = 3 V DIVDD = 3 V -10 -10 5 DIVDD-0.4 0.4 10 5 10 10 A pF V V A pF TEST CONDITIONS MIN TYP MAX UNIT
Logic outputs
key timing requirements
PARAMETER tSRW tSVW tOD tCSF tCSR SR pulse width SV pulse width ADCCLK rising edge to output data delay CS falling edge to SCLK rising edge SCLK falling edge to CS rising edge 0 5 TEST CONDITIONS Measured at 50% of pulse height MIN 10 10 6 TYP MAX UNIT ns ns ns ns ns
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10 BIT-PGA GAIN CURVE
40 35 30 25 20 15 10 5 0 0 200 400 600 800 PGA Codes 1000 1200
Gain - dB
Figure 1
TYPICAL CHARACTERISTICS
Optical Black Interval CCD Output n n+1 Dummy Black (Blanking) Interval Signal Interval
SR tSRW SV tSvW BLKG CLCCD OBCLP
ADCCLK tOD ADC OUT Latency: 6 ADC Cycles n
Figure 2. System Operation Timing Diagram
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TYPICAL CHARACTERISTICS
tCSF CS 1 SCLK 2 3 4 5 6 7 16 tCSR
SDIN
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI0
SCKP Pin is Pulled Low
tCSF CS 1 SCLK 2 3 4 5 6 7
tCSR
16
SDIN
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI0
SCKP Pin is Pulled High
Figure 3. Serial Interface Timing Diagram
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TYPICAL CHARACTERISTICS
tSRD
CCD IN
tSVD SR
SV
tADC_SV ADCCLK
Figure 4. Detailed Internal Timing Diagram
TIMING PARAMETER tSRD Delay between sample reset (SR) rising edge and actual sampling instant (ns) Delay between sample video (SV) rising edge and actual instant of video signal sampling (ns) Time between ADCCLK and SV falling edges MIN 6 TYP MAX EXPLANATION This is the fixed internal delay in the chip. The reset value of the CCD waveform should be stable until the end of this period. This is the fixed internal delay in the chip. The video signal value of the CCD waveform should be stable until the end of this period. The timing margin required to ensure the ADCCLK positive half cycle is in between two SV pulses.
tSVD
6
tADC_SV
3
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SLAS300 - AUGUST 2000
APPLICATION INFORMATION
AVDD 0.1 F AVDD 0.1 F 0.1 F 0.1 F Inputs 1 F 1 F 1 F 1 F
CLREF
CLCCD
SR AGND1
RBD AGND5
AVDD1 V SS AVDD5
RPD RMD
SV
Area CCD
0.1 F
1 F
48 47 46 45 44 43 42 41 40 39 38 37 AVDD 0.1 F BLKG CP CP 36 35 34 33 Inputs
1 2 AVDD 0.1 F DVDD 0.1 F 3 4 5 6 7 8 9 10 11 12
CCDIN NC AVDD2 AGND2 DGND DVDD D0 D1 D2 D3 D4 D5 D9 DIVDD D6 D7 D8 TLV990-28PFB
AGND3 DACO1 DACO2
DIGND AVDD3
AVDD4 32 AGND4 31 OBCLP 30 STBY 29 RESET 28 CS 27 SDIN 26 SCLK 25 SDCCLK SCKP OE
Inputs
13 14 15 16 17 18 19 20 21 22 23 24
Inputs
D (0-9) AVDD - 3 V DVDD - 3 V DIVDD - 1.8 V to 4.4 V
DIVDD 0.1 F
AVDD 0.1 F Analog GND Digital GND
NOTE: All analog outputs should be buffered if the load is resistive, or if the load is capacitive and greater than 2-pF.
Figure 5. Typical Application Connection
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REGISTER DEFINITION serial input data format
DI15 X DI14 X DI13 A3 DI12 A2 DI11 A1 DI10 A0 DI9 D9 DI8 D8 DI7 D7 DI6 D6 DI5 D5 DI4 D4 DI3 D3 DI2 D2 DI1 D1 DI0 D0
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Control register1 PGA gain register User DAC1 register User DAC2 register Coarse offset DAC Fine offset DAC
D9-D0 10-bit data be to written into the selected register
Digital Vb register (sets reference-code level at the ADC output during the optical black interval) Optical black setup register (sets the number of black pixels per line for digital averaging) Hot/cold pixel limit register (sets the limit for maximum positive deviation of optical black pixel from Vb value) Reserved Control register2 (sets the weight for digital filtering) Blanking data register (The data in this register appears at digital output during blanking (BLKG is low)) ADCCLK internal programmable delay register SR and SV internal programmable delay register
control register1 format
D9 STBY D8 PDD1 D7 PDD2 D6 ACD D5 AFD D4 OBM D3 X D2 SRSV D1 RTOB D0 RTSY
control register1 description
BIT D9 D8 D7 D6 NAME STBY PDD1 PDD2 ACD DESCRIPTION Device power-down control: 1 = standby, 0 = active (default) Power-down user DAC1: 1 = standby, 0 = active (default) Power-down user DAC2: 1 = standby, 0 = active (default) Coarse-offset DAC mode control: 0 = autocalibration (default), 1 = bypass autocalibration. Note: When D6 is set to 0, D5 must also be set to 0 (automode). Otherwise, the automode will be disabled on both offset DACs. Fine offset DAC mode control: 0 = autocalibration (default), 1 = bypass autocalibration. Note: D5 can be set to 0 with or without D6 being set to 0. This bit initiates the offset DAC's starting sequence. 0 = coarse-offset DAC starts first (default) 1 = fine-offset DAC starts first Reserved This bit specifies the polarity of SR and SV input pulses. 0 - SR/SV active low (default) 1 - SR/SV active high Writing 1 to this bit will reset calculated black-level results in the digital averager. Writing 1 to this bit will reset entire system to the default settings (edge sensitive).
D5
AFD
D4
OBM
D3 D2
X SRSV
D1 D0
RTOB RTSY
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REGISTER DEFINITION PGA register format
D9 Bit 9 D8 Bit 8 D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
Default PGA gain = 0000000000 or 0 dB
user DAC1 and DAC2 registers format
D9 X D8 X D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
Default user DAC register value = XX00000000
coarse offset DAC register format
D9 X D8 SIGN D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
coarse offset DAC register description
BIT D9 D8 D7-D0 NAME X SIGN Reserved Coarse DAC sign bit, 0 = + sign (default), 1 = - sign Coarse DAC control data when the D6 in the control register is set at 1. DESCRIPTION
Default coarse DAC register value = X000000000
fine offset DAC register format
D9 X D8 SIGN D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
fine offset DAC register description
BIT D9 D8 D7-D0 NAME X SIGN Reserved Fine DAC sign bit, 0 = + sign (default), 1 = - sign Fine DAC control data when the D5 in the control register is set at 1. DESCRIPTION
Default fine DAC register value = X000000000
digital Vb (optical black level) register format
D9 Bit 9 D8 Bit 8 D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
Default Vb register value = 00 Hex
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REGISTER DEFINITION optical black setup register format
D9 OMUX1 D8 OMUX0 D7 HYS D6 X D5 SOFW1 D4 SOFW0 D3 MP D2 PN2 D1 PN1 D0 PN0
optical black setup register description
BIT D8, D9 NAME OMUX1, OMUX0 DESCRIPTION These two bits multiplex digital output (data presented at D[9:0] pins): OMUX1 OMUX0 0 0 D[9:0] = ADC output (default) 0 1 D[9:0] = ADC output 1 0 D[9] = fine/coarse (1/0) autocorrection flag D[8] = coarse DAC sign D[7:0] = coarse DAC value 1 1 D[9] = fine/coarse (1/0) autocorrection flag D[8] = fine DAC sign D[7:0] = fine DAC value Sets the hysteresis 0 = Apply hysteresis to FDAC (default) 1 = No hysteresis Reserved These two bits set the digital filter weight when SOF is activated (the SOF bit in control register 2 is set to 1). SOFW1 SOFW0 Weight 0 0 0 (default) 0 1 1 1 0 2 1 1 3 When this bit is 1, the number of optical black pixels to be averaged per line (2N) is multiplied by 3. By setting the MP and PN2-PN0 bits together, the number of optical black pixels can be programmed to have the following numbers: 1, 2, 3 (1X3), 4, 6 (2x3), 8, 12 (4x3), 16, 24 (8x3), 32, 48 (16x3), 64, 96 (32x3), and 192 (64x3). Default: MP = 0, no multiplication D2-D0 PN2-PN0 Number of optical black pixels per line to average = 2N N can be 0, 1, 2, 3, 4, 5, and 6. Or number of pixels per line can be 1, 2, 4, 8 (default), 16, 32, or 64. The maximum number of pixels per line is 64, even if N>6.
D7
HYS
D6 D5, D4
X SOFW1, SOFW0
D3
MP
Default optical black calibration register value = 0000000011
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REGISTER DEFINITION hot/cold pixel limit register format
D9 Bit 9 D8 Bit 8 D7 Bit 7 D6 Bit 6 D5 Bit 5 D4 Bit 4 D3 Bit 3 D2 Bit 2 D1 Bit 1 D0 Bit 0
Default hot pixel limit register value = 1111111111
control register2 format
D9 SOF D8 NOS D7 ASOF D6 X D5 X D4 X D3 WT3 D2 WT2 D1 WT1 D0 WT0
control register 2 description
BIT D9 NAME SOF DESCRIPTION 0 - Normal mode (default) 1 - Start of frame (only used when exposure time is changed) When this bit is set to 1, next positive ADCCLK edge indicates that next pixel line is the beginning of a new frame. The optical black correction will be performed with one line averaging only (digital filtering weight = 1) and without hot/cold pixel limits. Internal test bit, add 255 to optical black pixels when bit set to 1 Default = 0 Enable auto SOF 0 = No auto SOF (default) 1 = Automatically enable SOF at major gain changes Reserved. Set bits to 0. These three bits set the weight for digital filtering. WT3 WT2 WT1 WT0 Weight (effect of the averaged result of each optical black pixel line on 0 overall optical black averaging 0 0 0 0 1 0 0 0 1 1/2 0 0 1 0 1/4 0 0 1 1 1/8 0 1 0 0 1/16 0 1 0 1 1/32 0 1 1 0 1/64 0 1 1 1 1/128 (default) 1 0 0 0 1/256
D8 D7
NOS ASOF
D6-D4 D3-D0
X WT2-WT0
Default control register2 value = X000000111
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REGISTER DEFINITION blanking data register format
D9 0 D8 0 D7 0 D6 0 D5 BDTA D4 0 D3 0 D2 0 D1 0 D0 0
blanking data register description
BIT D5 NAME BDTA DESCRIPTION This register value appears at the digital output when BLKG is low. When this bit is set to 1, digital output during blanking will be V6.
Default = 0000000000
ADCCLK internal delay register format
D9 X D8 X D7 X D6 X D5 X D4 X D3 ADL3 D2 ADL2 D1 ADL1 D0 ADL0
ADCCLK internal delay register description
BIT D9-D4 D3-D0 NAME X ADL3-ADL0 Reserved These four bits set the internal ADCCLK delay. ADL3 ADL2 ADL1 ADL0 Typical internal delay 0 0 0 0 0 ns (default) : : 1 1 1 1 10 ns DESCRIPTION
Default register value = XXXXXX0000
SR and SV internal delay register format
D9 X D8 X D7 SVL3 D6 SVL2 D5 SVL1 D4 SVL0 D3 SRL3 D2 SRL2 D1 SRL1 D0 SRL0
SR and SV internal delay register description
BIT D9-D8 D7-D4 NAME X SVL3-SVL0 Reserved These four bits set the internal SV delay. SVL3 SVL2 SVL1 SVL0 Typical internal delay 0 0 0 0 0 ns (default) : : 1 1 1 1 10 ns These four bits set the internal SV delay. SRL3 SRL2 SRL1 SRL0 Typical internal delay 0 0 0 0 0 ns (default) : : 1 1 1 1 10 ns DESCRIPTION
D3-D0
SRL3-SRL0
Default register value = XX00000000
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PRINCIPLES OF OPERATION CDS and PGA
The output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. The CCD signal is sampled and held during the reset-reference interval and the video-signal interval. By subtracting two resulting voltage levels, the CDS removes low-frequency noise from the output of the CCD sensor and obtains the voltage difference between the CCD reference level and the video level of each pixel. Two sample/hold control pulses (SR and SV) are required to perform the CDS function. The CCD output is capacitively coupled to the TLV990-28. The ac-coupling capacitor is clamped to establish proper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990-28 is set to 1.2 V. Normally, CLCCD is applied at the sensor's line rate. A capacitor, with a value ten times larger than that of the input ac-coupling capacitor, should be connected between the CLREF pin and AGND. When operating the TLV990-28 at its maximum speed, the CCD internal source resistance should be smaller than 50 . Otherwise CCD output buffering is required. The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB by programming the internal-gain register via the serial port. The PGA is digitally controlled with 10-bit resolution on a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation, Gain = PGA code x 0.045 dB Where PGA code has a range of 0 to 767.
ADC
The ADC employs a pipelined architecture to achieve high throughput and low-power consumption. Fullydifferential implementation and digital-error correction ensure 10-bit resolution. The latency of the ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) high puts the ADC output in high impedance.
user DACs
The TLV990-28 includes two user DACs that can be used for external analog settings. The output voltage of each DAC can be independently set and has a range of 0 V up to the supply voltage, with an 8-bit resolution. When the user DACs are not used in a camera system, they can be put in the standby mode by programming control bits in the control register.
internal timing
The SR and SV signals are required to operate the CDS, as previously explained. The user needs to synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by the ADCCLK signal, which is also used internally to control both ADC and PGA operations. The positive-half cycle of the ADCCLK signal is required to always fall in between two adjacent SV pulses as shown in Figure 1. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance. The CLCCD signal is used to activate the input clamping and the OBCLP signal is used to activate auto-optical black and offset correction.
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PRINCIPLES OF OPERATION input blanking function
Large input transients may occur at the TLV990-28's input during some period of operation which can saturate the input circuits and cause long recovery time. To prevent circuit saturation, the TLV990-28 includes an input blanking function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulled low. The TLV990-28 digital output will be set by the blanking data register after BLKG is pulled low.
NOTE: If the BLKG pulse is located before the OBCLP pulse, there must be at least 4 pixels between the rising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse is located after the OBCLP, the minimum number of pixels between the falling edge of the OBCLP and the falling edge of the BLKG pulse should be equal to the number of optical black pixels per line + 4.
3-wire serial interface
A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of the TLV990-28. The serial clock SCLK can be run at a maximum frequency of 40 MHz. Serial data SDIN is 16 bits long. The two leading null bits are followed by four address bits for which the internal register is to be updated, and then ten bits of data to be written to the register. The CS pin must be held low to enable the serial port. The data transfer is initiated by the incoming SCLK after CS falls. The SCLK polarity is selectable by pulling the SCKP pin either high or low.
device reset
When pin RESET (pin 29) is pulled low, all internal registers are set to their default values. The device also resets itself when it is first powered on. In addition, the TLV990-28 has a software-reset function that resets the device when writing a control bit to the control register. See the register definition section for the register default values.
voltage references
An internal precision-voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate the ADC Ref- voltage of 1 V and Ref+ of 2 V. It is also used to set the clamp voltage. All internally-generated voltages are fixed values and cannot be adjusted.
power-down mode (standby)
The TLV990-28 implements both hardware and software power-down modes. Pulling pin STBY (pin 30) low puts the device in the low-power standby mode. Total supply current drops to about 0.6 mA. Setting a power-down control bit in the control register can also activate the power-down mode. The user can still program all internal registers during the power-down mode.
power supply
The TLV990-28 has several power-supply pins. Each major internal analog block has a dedicated AVDD supply pin. All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3-V nominal. The DIVDD and DIGND pins supply power to the output digital driver (D9-D0). The DIVDD is independent of the DVDD and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiring different supply voltages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
PRINCIPLES OF OPERATION ground and decoupling
All ground pins of the TLV990-28 are not internally connected and must be connected externally to PCB ground. General practices should apply to the PCB design to limit high-frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. In the case of power supply decoupling, 0.1-F ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Recommended external decoupling for the three voltage-reference pins is shown in Figure 4. Since their effectiveness depends largely on the proximity to the individual supply pin, all decoupling capacitors should be placed as close as possible to the supply pins. To reduce high-frequency and noise coupling, it is highly recommended that digital and analog grounds be shorted immediately outside the package. This can be accomplished by running a low-impedance line between DGND and AGND under the package.
automatic optical black and offset correction
In the TLV990-28, the optical black and system channel-offset corrections are performed by an autodigital feedback loop. Two DACs are used to compensate for both channel offset and optical black offset. A coarse correction DAC (CDAC) is located before the PGA gain stage, and a fine correction DAC (FDAC) is located after the gain stage. The digital-calibration system is capable of correcting the optical black and channel offset down to one ADC LSB accuracy. The TLV990-28 automatically starts autocalibration whenever the OBCLP input is pulled low. The OBCLP pulse should be wide enough to cover one positive half cycle of the ADCCLK, as shown in Figure 1. For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the ADC. A digital circuit averages the data during the optical black pixels. The averaged result is compared digitally with the desired output code stored in the Vb register (default is 40H), then control logic adjusts the FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (255 ADC LSBs), the error is corrected by both CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB, depending on whether the offset is negative of positive, until the output is within the range of the FDAC. The remaining residue is corrected by the FDAC. The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows: 1 FDAC LSB = 1 ADC LSB, 1 CDAC LSB = PGA linear gain x n ADC LSB. Where n is: 4 for 0 =< gain code <128 3 for 128 =< gain code <192 2 for 192 =< gain code <256 1 for 256 =< gain code For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 2 x 3 ADC LSBs = 6 ADC LSBs. After autocalibration is complete, the ADC's digital output during CCD signal interval can be expressed by the following equation: ADC output [D9-D0] = CCD_input x PGA gain + Vb, Where Vb is the desired black level selected by the user. The total offset, including optical black offset, is calibrated to be equal to Vb by adjusting the offset correction DACs during autocalibration.
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV990-28 3-V, 10-BIT, 28-MSPS AREA CCD ANALOG FRONT END
SLAS300 - AUGUST 2000
PRINCIPLES OF OPERATION automatic optical black and offset correction (continued)
A weighted rolling average of the optical black pixels is taken during averaging. The weighting factor can be programmed in control register2. The weighting factor determines the speed of convergence of the digital filtering implemented within the CCD signal processor. Weighting factors closer to 1 result in faster convergence. As the weighting factor decreases towards its minimum value of 1/256, the speed of convergence of the digital filtering decreases. The algorithm also takes hot pixels and cold pixels into consideration. A hot optical black pixel is a defective pixel that generates too much charge, while a cold pixel is the one that generates very little or no charge. A digital comparator compares the digitized optical black pixels with user-selected hot and cold pixel limits. If the optical black pixel value is out of range, then that hot or cold pixel is replaced with the value of the previous pixel. Due to different exposure times, there might be a sudden optical black level shift at the start of each frame. Thus, a quick optical black level correction is desirable. The user can set an internal control bit (the SOF bit in control register2) to automatically disable the hot/cold pixel limits and to set the digital filtering weighting factor to 1 (equivalent to one-line averaging). In this way the optical black correction could be performed very quickly for the first line of each frame. The number of black pixels in each line is programmable. The number of black pixels per line that can be averaged is 2N, where N can be any integer from 0 to 6. The autocalibration feature can be bypassed if the user prefers to directly program the offset DAC registers. Switching the autocalibration mode to the direct-programming mode requires two register writes. First, the control bits for the offset DACs in the control register must be changed; then the desired offset value for the register is loaded to the offset DAC registers for proper error correction. If the total offset, including optical black level, is less than 255 ADC LSBs, only the FDAC needs to be programmed. When switching from directprogramming mode to autocalibration mode, the previous DAC register values, rather than default DAC register values, are used as starting offsets.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
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