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| TLV1504/1508/1544/2544/2548, TLC1514/1518/2554/2558 10 Bit and 12 Bit ADC EVM User's Guide May 1999 - Revised May 2000 Mixed-Signal Products SLAU029A IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated Information About Cautions and Warnings Preface Read This First About This Manual This user's guide describes the characteristics, operation, and use of the TLV1504/1508/1544/2544/2548/TLC1514/1518/2554/2558 EVM for the TLV1504, TLV1508, TLC1514, TLC1518, TLC2554, TLC2558, TLV1544, TLV2544, and TLV2548 10-bit/12-bit analog-to-digital converter (ADC). The TLV1504/1508/1544/2544/2548/TLC1514/1518/2554/2558 EVM will be referred to as the ADC EVM throughout this manual. How to Use This Manual This document contains the following chapters: - Chapter 1 Overview Chapter 2 Physical Description Chapter 3 Circuit Description Chapter 4 Operation Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. Read This First iii Related Documentation From Texas Instruments The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering, please identify the book by its title and literature number if possible. Data Sheets: FCC Warning Literature Number SLAS252 SLAS220A SLAS251 SLAS139C SLAS198A SLAS156E SCLS226H SLVS092F SLOS183A SLOS209D SCLS314G SCLS231J/ SCLS078B SCLS115B SCLS094B/ SCLS255G SLAS078C SCLS236E/ SCLS081B SCLS317H SCLS141C/ SCLS240G TLC1514/18 TLC2554/58 TLV1504/08 TLV1544CPW TLV2544/8CPW TLC5618ACD SN74AHC244IDW TPS7101QD TLE2142AID TLV2772ACD SN74AHC1G08DBVR SN74AHC04D/ SN74HC04D SN74HC164D SN74HC74D/ SN74AHC74D TL7726CD SN74AHC08D/ SN74HC08D SN74AHCIG32 SN74HC374DW/ SN74AHC374DW Application Reports: Interfacing the TLVX544/TLVX548 Analog-to-Digital Converter to the TMS320C50 and TMS320C203 DSPs, literature number SLAA025 and SLAA028A. This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules. This device has been tested and found to comply with the limits for a CISPRII Group 1 and the following directives: EMC Directive 89/336/ECC amending directive 92/31/ECC and 93/68/ECC as per ENV50204:1995, EN55011: 1995 Class A, EN61000-4-4: 1995, and EN61000-4-3:1993. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks SPI and QSPI are trademarks of Motorola, Inc. iv Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 I/O CLK or SCLK Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 I/O Interface Connector Provisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 ADC EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Functional Testing Without a DSP or Microcontroller EVM . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-3 1-3 1-4 1-5 1-6 2 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 A0 - External Input via Input Scaling and Voltage Follower Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 A1 - External Input via Dual Supply Operational Amplifiers Used for Input Scaling and Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Voltage Reference Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Test and Interfacing Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Jumper Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 Breadboard Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 TLC5618A, 12-Bit Serial DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.10 LOOPBACK Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 TLV1544/2544/2548 Hardware Interfacing to the TMS320 DSP . . . . . . . . . . . . . . . . . . . 4.3 Data Sheet Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-5 3-5 3-5 3-5 3-6 3-6 3-7 3-8 3-8 3-8 3-8 4-1 4-2 4-2 4-2 4-3 4-4 3 4 A Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Printed Circuit Board Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Chapter Title--Attribute Reference v Running Title--Attribute Reference Figures 2-1 2-2 2-3 2-4 2-5 3-1 3-2 4-1 4-2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-5 2-6 3-3 3-4 4-3 4-4 Tables 1-1 2-1 3-1 Maximum I/O CLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Test Connector J7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 vi Chapter 1 Overview This chapter gives a general overview of the ADC EVM and describes some of the factors that must be considered in using the module. Topic 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Page Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 I/O CLK Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 I/O Interface Connector Provisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 ADC EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Functional Testing Without a DSP or Microcontroller EVM . . . . . . . . 1-6 Overview 1-1 Purpose 1.1 Purpose The ADC EVM provides a platform for evaluating the TLV1504, TLV1508, TLV1544, TLC1514, and TLC1518 10-bit analog-to-digital converter (ADC), TLC2554, TLC2558, TLV2544 and TLV2548, 12-Bit ADCs under various signal, reference, and supply conditions. 1.2 EVM Basic Function The TLV1504/1544/2544 and TLC1514/2554 has four analog inputs, while the TLV1508/2548 and TLC1518/2558 has eight analog inputs. All inputs are available for external signal inputs through SMA connectors. To perform testing without having to apply an external signal via the SMA inputs, an onboard DC signal, REF_CH3/7 is available via jumper W3 to channel A3/A7. The internal dc input signal consists of a voltage reference with a potentiometer for adjusting the dc input voltage. The reference voltage is either 5 V or 3.3 V and is selected by operating switch, SW1. If the ADC EVM board is built to evaluate the TLC series of ADC devices, then SW1 is not installed on the EVM board. Instead, switch1 (SW1), is replaced with a jumper wire connected directly to the output 5 V since the TLC devices only operate in a single 5-V supply. Signal conditioning operational amplifiers are used to interface the input signal to channel A0 and A1. For use in the evaluation of the ADC, the EVM incorporates a 12-bit TLC5618A digital-to-analog converter (DAC), an SN74HC74, and a 74HC374, used during loopback testing, to format the serial word to the DAC. An SN74AHC244 buffers the digital I/O signals to the output header and test connector. The SN74HC164 is used to convert the serial data stream from the ADC to parallel data for displaying on a logic analyser. 1-2 Overview Power Requirements 1.3 Power Requirements The EVM dc supply voltage range is 7 V to 10 V. The power supply and externally-applied reference voltage should be supplied to the EVM through shielded twisted-pair wire for best performance. This type of power cabling minimizes any stray or transient pickup from the higher frequency digital circuitry. Voltage Limits Exceeding the 10-volt maximum can damage EVM components. Under voltage may cause improper operation of the bipolar op amp channel A1, depending on the application. The positive supply can be lowered to 6 volts and the EVM will maintain the 5-V supply. 1.4 I/O CLK or SCLK Requirements The TLV1544 has a maximum I/O CLK of 10 MHz at VCC = 5 V and is limited to 2.8 MHz for a supply voltage of 2.7 V. The TLV2544/48 has a maximum SCLK of 20 MHz at VCC = 5 V and 15 MHz at 2.7 V. Table 1-1 lists the maximum I/O CLK/SCLK frequencies for different supply ranges. This also depends on input source impedance. For example, I/O CLK speed faster than 2.39 MHz is achievable if the input source impedance is less than 1 k. Table 1-1. Maximum I/O CLK Frequency VCC TLV1544 27V 2.7 4.5 45V TLV2544 TLV2548 TLV1504 TLV1508 TLC1514 TLC1518 TLC2554 TLC2558 2.7 V 4.5 V 2.7 V 5.5 V 5.5 V 5.5 V Maximum Input Resistance (Max) 5K 1K 600 500 600 500 500 500 Source Impedance 1 k 100 1 k 100 1 k 1 k 1 k 1 k 1 k 1 k I/O CLK/SCLK 2.39 MHz 2.81 MHz 7.18 MHz 10 MHz 15 MHz 20 MHz 15 MHz 20 MHz 20 MHz 20 MHz Overview 1-3 I/O Interface Connector Provisions 1.5 I/O Interface Connector Provisions The connector interface is versatile, allowing different connection arrangements depending on the user selected interface. A 20-position dual inline header connector, J11, is used to interface the TMS320C5x DSP and microcontroller devices to the EVM. It is hard-wired to the input/output signals of the ADC through the SN74AHC244. J12 is a dual row, 24-position header, used to interface both TMS320C2xx/TMS320C54x DSPs to the EVM. The headers are readily available 100-mil center connectors. A ribbon cable with the corresponding female plug, mates to the header the appropriate DSP or microcontroller EVM. Figure 3-1 shows the signal arrangement for J11 and J12. Ideally, J12 should be arranged so that the clock lines have a ground line on either side in the ribbon cable to minimize crosstalk. If possible, every other conductor in the ribbon cable should be grounded. However, keep in mind that, many DSP/microcontroller EVM boards restrict the interface connector size, and signals going to the output connector are not routed for minimum crosstalk. An isometric drawing showing the ADC EVM connected to the TMS320C54x DSKplus EVM can be found in literature number SLAU030 (TMS320C54x DSKplus Adapter Kit). 1-4 Overview ADC EVM Operational Procedure 1.6 ADC EVM Operational Procedure Some signal setup or software is required for the ADC EVM. The ADC data sheet (refer to section 4.3 for specific ADC data sheet information) provides the timing requirements and the application report (literature number SLAA025A and SLAA028A) supplies an example of software using the TMS320C50 DSP and TMS320C203 DSP. Once the input requirements are completed, the operating procedures for the ADC EVM are as follows. - Connect 7 to 10 V and ground to the 10 V, -10 V, and GND terminals of J10. These terminals are marked on the top side of the EVM silkscreen. TP3-TP8 is shorted to establish zero volts as the operating point. When TP1 and TP2 are shorted, the output at both the TLV2772 and TLE2142 operational amplifiers, reads 2.5 V for an AVDD of 5 V. SW1 can select 5-V VCC or 3.3-V VCC, making it convenient to evaluate both 3.3-V and 5-V systems. Note that when evaluating the TLC version the switch, SW1, is not installed as discussed in section 1.2. For most DSP operation, JP1 is open, and for most microprocessor operation, JP1 is shorted. The device INV CLK/ PWDN input is controlled by this jumper. The state of the inverted signal is used to control the I/O CLK edge used for sampling the input data. Applying a logic low signal to the PWDN causes both analog and digital circuits to go into the power-down mode. The analog input that is connected to the ADC is determined by software, and any input can be selected for testing. The TLV1544/2544 and TLC1514/2554 four channels are configured as follows: Analog Input A0 Interface to a buffer driven by a single supply input scaling operational amplifier Unbuffered external input is via W2 positions 1-2 A1 Interface to a buffer driven by a dual supply, 10 V used for input scaling Unbuffered external input is provided via W1 positions 1-2 A2 Uses unbuffered external input A3 Uses unbuffered external input or dc REF_CH3/7 A4-A7 Uses unbuffered external input Normally, through the software, or loopback testing via the TLC5618A, the ADC full-scale, mid-scale, and zero-scale values are first checked. Channel A3/A7 can be selected and checked with the dc signal REF_CH3/7 using jumper W3. An external reference voltage, derived from a MAX6250 precision voltage regulator, is used to provide the REF+ and REF- reference voltage for the ADC as well as the 2.5 V reference for the TLC5618A - when operating the ADC with Vref = 5 V. Designation Reference Voltage Onboard absolute reference = 5 V, at Vin = 7 V to 10 V When SW1 is changed the onboard absolute reference is automatically changed to the proper value for the DVdd/AVdd selected. - - - Overview 1-5 Functional Testing Without a DSP or Microcontroller EVM REF+, REF- and 2.5REF are automatically changed when SW1 is changed. However, some slight adjustment of individual potentiometer may be necessary. - The I/O signals can be monitored at J7, J11 and J12. The additional analog inputs can be used for application of external signals that might be used to digitize signals for further processing. In short, select the desired analog input channel: implement the data loopback tests by shunting positions 2-3 of W5 and W7 positions 3-4 with a jumper connection. With the TMS320C5x DSP, positions 1-2 of W9 are shorted with a jumper connector or shunt. Positions 2-3 of W9 are shorted when using either the TMS320C203 or TMS320C54x DSP. 1.7 Functional Testing Without a DSP or Microcontroller EVM With the aid of an arbitrary waveform generator, generating FS, CS, and SCLK for the device is straight-forward. Configure the device by applying a DATA IN input waveform of A000h at the falling edge of FS while CS is LOW (refer to the device datasheet for more information). Then select channel A0 by grounding the DATA IN input, and activate both CS and FS high-to-low. Apply the ac analog or dc input to SMA connector J3 and set W2 appropriately. Simply shunt W5 positions 2-3 and W7 positions 3-4 to connect the ADC output to the TLC5618A DAC channel B (J14). Observe a replica of the input signal connected to A0. 1-6 Overview Chapter 2 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module. Topic 2.1 2.2 Page PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Physical Description 2-1 PCB Layout 2.1 PCB Layout The EVM is constructed on a 4-layer, 12 cm (4.7-inch) x 10 cm (3.9-inch), 0.157 cm (0.062-inch) thick PCB using FR-4 material. Figures 2-1 through 2-5 show the individual layers. Figure 2-1. PCB Layout 2-2 Physical Description PCB Layout Figure 2-2. PCB Layout Physical Description 2-3 PCB Layout Figure 2-3. PCB Layout 2-4 Physical Description PCB Layout Figure 2-4. PCB Layout Physical Description 2-5 PCB Layout Figure 2-5. PCB Layout 2-6 Physical Description Parts List 2.2 Parts List Table 2-1 lists the parts used in constructing the EVM. Table 2-1. Parts List Qty 4-Ain 1 3 25 Qty 8-Ain 1 3 25 NA C39 C44 C50 C10 C17 C20 C23 C26 C27 C28 C30 C31 C33 C34 C36 C37 C41 C43 C46 C49 C53 C54 C55 C56 C60 C61 C62 C9 C47 C48 C24 C22 C29 C11 C12 C4 C6 8 8 2 1 1 1 4 2 1 1 8 2 1 1 1 4 2 1 1 10 6 1 1 4 1 1 4 C11 C12 C4 C6 C8 C14 C16 C19 C32 C35 C38 C40 C42 C45 C51 C52 C57 C21 D1 D2 D3 FB1 FB2 FB3 FB4 JP1 W6 W7 J12 J1 J2 J3 J4 J5 J6 J8 J9 J13 J14 J1 J2 J3 J4 J13 J14 J10 J11 R54 R57 R59 R66 REV A PCB fabrication Ceramic, X7R, 50 V, 10% Ceramic, X7R, 50 V, 10% Texas Instruments Kemet Kemet TLVX544/X548 C1206C103K5RAC C1206C104K5RAC Reference Description Description Manufacturer Part Number 2 1 2 4 2 1 2 Ceramic, X7R, 50 V, 10% Ceramic, X7R, 16 V, 10% 2.2 F, 16 V tantalum. capacitor Ceramic, X7R, 50 V, 10% Ceramic, X7R, 50 V, 10% 4.7 F, 16 V, tantalum capacitor Ceramic, Y5V, 10 V, 20% Green 1206 size chip LED 40 V, 400 mW Schottky Hi-speed switching diode Surface-mount ferrite bead Single row 2-pin header 6-Pin dual row header 26-Pin dual row header PCB mount SMA jack PCB mount SMA jack 3-terminal screw connector 20-pin dual row header 1206 chip resistor., 5% Kemet Kemet Kemet Kemet Kemet Kemet AVX Chicago Miniature Diodes Inc. Edmar Electronics Fair Rite Samtec Samtec Samtec Johnson Components Johnson Components Lumberg Samtec Bourns C1206C101K5GAC C1206C105K4RAC T491A225K016AS C1206C682K5RAC C1206C682K5RAC T491A475K016AS 1206ZG106ZAT2A CMD15-21VGC LLSD101C DL4148 2744044447 TWS-102-07-L-S TWS-103-07-L-D TWS-113-07-L-D 142-0701-206 142-0701-206 KRMZ3 TWS-110-07-L-D CR1206-FX-000 Physical Description 2-7 Parts List Table 2-1. Component List (Continued) Qty 4 8 15 15 Qty Reference Description R10 R16 R17 R4 R10 R16 R17 R4 R18 R20 R23 R29 R14 R24 R27 R38 R40 R41 R53 R6 R64 R65 R37 R56 R58 R63 R70 R36 R43 R44 R46 R48 R7 R5 R52 R45 R12 R47 R25 R70 R11 R8 R31 R33 R49 R60 R61 R62 R69 R21 W4 W10, See Note 2 R26 R30 R32 R34 R39 R42 R50 R51 R13 R67 R55 SW1 TP10 TP11 TP12 TP18 TP14 TP15 TP16 TP17 TP9 TP13 U11 U16 U10 U9 U15 U17 U18 U14 Description 1206 chip resistor., 5% 1206 chip resistor., 5% 1206 chip resistor., 1% Manufacturer Bourns Bourns Bourns Part Number CR1206-FX-22R0 CR1206-FX-22R0 CR1206-FX-1002 4 1 1 1 1 1 2 1 1 2 10 4 1 1 1 1 1 2 1 1 2 10 4mm, 5T, SM potentiometer 9.09 k 1206 chip resistor., 1% 1206 chip resistor., 1% 1206 chip resistor., 1% 1206 chip resistor., 5% 1206 chip resistor., 1% 1206 chip resistor., 5% 1206 chip resistor., 1% 1206 chip resistor., 1% 1206 chip resistor., 5% Bourns Bourns Bourns Bourns Bourns Bourns Bourns Bourns Bourns Bourns Bourns 3214J-1-103-W CR1206-FX-9092 CR1206-FX-1213 CR1206-FX-1502 CR1206-FX-1693 CR1206-FX-1001 CR1206-FX-2002 CR1206-FX-2001 CR1206-FX-2261 CR1206-FX-3012 CR1206-FX-33R0 7 1 1 1 1 1 8 2 1 1 1 2 1 1 1 7 1 1 1 1 1 8 2 1 1 1 2 1 1 1 1206 chip resistor., 5% 1206 chip resistor., 1% 1206 chip resistor., 1% 1206 chip resistor., 1% 1206 chip resistor., 1% PCB mount DPDT slide switch Test point - single .025" pin Turret type test pin Micro AND gate Micro OR gate Maxim precision voltage regulator Hex inverter Octal D type FF Dual D-type FF Quad AND gate Bourns Bourns Bourns Bourns Bourns C&K Samtec Cambion Texas Instruments Texas Instruments Maxim Texas Instruments Texas Instruments Texas Instruments Texas Instruments CR1206-FX-3300 CR1206-FX-5903 CR1206-FX-4022 CR1206-FX-4751 CR1206-FX-6043 1201M2S3CQE2 TWS-101-07-L-S 180-7337-02-05 SN74AHC1G08DBVR SN74AHC1G32DBVR MAX6250BCSA/ MAX6250BESA SN74AHCT04D SN74HC374DW SN74HC74D SN74AHCT08D Not installed on ADC EVM board built to evaluate TLC series ADCs. 2-8 Physical Description Parts List Table 2-1. Component List (Continued) Qty 1 2 1 1 Qty Reference Description U6 U5 U6 U12 Description Clamp circuit Clamp circuit Programmable dual 12-bit DAC Dual op amp in 8-pin SOP package Manufacturer Texas Instruments Texas Instruments Texas Instruments Part Number TL7726CD/TL7726ID/ TL7726QD TL7726CD/TL7726ID/ TL7726QD TLC5618ACD/ TLC5618AID TLE2142CD/ TLE2142ACD/ TLE2142ID/ TLE2142AID TLV2772AID/ TLV2772AMD TLC1514CPW TLC1518CPW TLC2554CPW TLC2558CPW TLV1504CPW TLV1508CPW TLV1544CPW TLV2544CPW TLV2548CPW TPS7101QD SN74AHCT244DW TWS-103-07-L-S 1 1 U1 Texas Instruments 1 1 1 U2 U7 Dual op amp in 8-pin SOP package Serial ADC Serial ADC Serial ADC Serial ADC Serial ADC Serial ADC Serial ADC Serial ADC Serial ADC Low dropout voltage regulator Octal buffer and line driver 0.025" square, 3-pin header, 0.1" centers Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments Samtec 1 1 1 1 1 1 1 1 1 1 6 1 1 6 U7 U7 U7 U7 U7 U7 U7 U7 U13 U8 W1 W2 W3 W5 W8 W9 Customer Installed Options 4 8 2 1 1 1 1 5 9 2 1 1 1 1 C1 C2 C3 C5 C1 C2 C3 C5 C7 C13 C15 C18 C58 C59 W11 J7 J5 R35 R1 R2 R3 R9 R68 R1 R2 R3 R9 R15 R19 R22 R28 R68 TP1 TP2 TP3 TP4 Ceramic, X7R, 50 V, 10% Ceramic, X7R, 50 V, 10% Ceramic, X7R, 50 V, 10% Single row 2-pin header 24-pin dual row header PCB mount SMA jack 1206 chip resistor., 5% 1206 chip resistor., 1% 1206 chip resistor., 1% Samtec Samtec Johnson Components Bourns Bourns Bourns TWS-102-07-L-S TWS-112-07-L-D 142-0701-206 CR1206-FX-000 CR1206-FX-49R9 CR1206-FX-49R9 Kemet Kemet C1206C101K5GAC C1206C101K5GAC 4 Test point - dual .025" pin Samtec TWS-102-07-L-S Physical Description 2-9 Parts List Table 2-1. Component List (Continued) Qty Qty 8 2 2 Reference Description TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 U3 U4 Description Test point - dual .025" pin 8-Bit parallel out shift register Manufacturer Samtec Texas Instruments Part Number TWS-102-07-L-S SN74HC164D Note: MFG/PN for reference only. Substitutions permissable on all parts except integrated circuits. 2-10 Physical Description Chapter 3 Circuit Description This chapter contains the EVM schematic diagram and discusses the various functions on the EVM. Topic 3.1 3.2 Page Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Circuit Description 3-1 Schematic Diagram 3.1 Schematic Diagram Figure 3-1 shows the schematic diagram for the EVM. The following paragraphs describe the EVM circuits. 3-2 Circuit Description Figure 3-1. EVM Schematic Diagram DVdd U5C 4 J5 TP5 G CLKS TL7726 AVdd C20 0.1uF 5 FS CS DATA IN U5E 6 J8 22 TL7726 8 A2 33 A3/A7 DATA OUT U8B DVdd G 13 15 9 3 Y1 Y4 R25 2K R24 10K A2 A3 A1 A4 Y2 Y3 7 5 11 17 R40 10K R39 R42 SDO 330 330 19 R61 R33 33 DR 33 DVdd 12 1 SN74AHCT04 W9 3 10 I/O3 TLVX544/X548 7 15 REF+ CSTART REF- INV CLK / PWDN 11 DVdd C54 C12 6800pF 0.1uF C57 10uF 7 6 TLV2772 JP1 I/O FSX W10 DVdd REF- TP12 C11 6800pF U6E 6 TP10 U1B 5 7 6 TLE2142 U4 1 2 9 8 A B CLR CLK TL7726 SN74HC164 REF+ 1 2 9 8 A B CLR CLK 33 14 R17 W2 22 3 R8 1 R7 121K R5 3 8 R6 10K AVdd AVdd 15K 5 U2B 1 TLV2772 R27 10K 30.1K U2A 4 2 TL7726 1 -INT3 EOC / INT- 9 U6F 4 5 6 R31 C5X (uP) J11 R22 49.9 C15 100pF C16 6800pF A1 C19 6800pF TL7726 TP7 7 U9C R41 10K R23 5 A0 I/O CLK 6 3 U5D 2 DVdd 13 16 SN74HCT244 330 DX CLKX FSR Y1 Y2 Y3 Y4 A1 A2 A3 A4 FSX XF DX CLKX (BDX) (BCLKX) (BFSR) 18 16 14 12 2 4 6 8 R26 R34 R32 R30 PINOUT SHOWN IS BASED ON THE TLVX544 PART. PLEASE CHECK DATASHEET FOR THE TLVX548 PINOUT U7 NA/A3 NA/A4 NA/A5 NA/A6 R15 49.9 C7 100pF 22 C8 6800pF 1 McBSP TL7726 R18 3 U8A -INT3 FS ~CS R63 10K (~INT3) U5B PARTS WITHIN DOTTED LINE FOR TLVX548 DEVICES ONLY C203 (C54X) R20 J6 TP6 (N/A) (XF) I/O3 XF (TOUT) (BFSX) (BDR) (BCLKR) J12 R19 49.9 C13 100pF 22 C14 6800pF 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 TOUT FSX DR CLKR R29 J9 TP8 22 R28 C18 49.9 100pF CLKR DR FSR -INT3 CSTART CLKX TOUT DX FSX I/O XF 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 J3 TP2 SN74HCT244 R53 10K W6 CSTART CLKX W4 33 R2 49.9 C2 100pF AVdd TOUT CLKR FSR U3 Optional Components J7 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 XF FSX -INT3 QA QB QC QD QE QF QG QH 3 4 5 6 10 11 12 13 C50 0.01uF TP11 R16 W1 22 R14 1 3 R13 40.2K R11 30.1K C49 0.1uF QA QB QC QD QE QF QG QH 3 4 5 6 10 11 12 13 J2 TP1 C1 R1 49.9 100pF AVdd 10K -VIN U1A 4 (-10) 2 1 3 TLE2142 (+10) 8 R12 +VIN 20K D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 J1 TP3 22 C3 R3 49.9 100pF C4 6800pF R4 U6D 5 TL7726 4 U6C SN74HC164 R21 33 CLK TL7726 1 3 REF_CH3/7 R69 J15 W11 W3 33 CLKS TP9 J4 TP4 R9 C5 49.9 100pF 22 R10 Circuit Description C6 6800pF TP13 R68 49.9 Schematic Diagram Optional Components 3-3 3-4 U9D DVdd W7 1 FSX 2 FS U14B 33 1 2 TP17 33 DVdd U14C 9 11 10 6 SN74HC08 5 +5V 4 2 C59 TBD 3 SN74AHC1G08 SDO FB3 1 W8 3 R46 0.1uF AVdd 10 GND SN74HC374 4 DVdd DVdd U18A Q Q SN74HC74 8 FB4 + C45 4.7uF C46 0.1uF C42 4.7uF C43 0.1uF C44 0.01uF + D2 AVdd 8 (+5V) R52 169K + C38 4.7uF C36 0.1uF C39 0.01uF +5V OUT + C29 2.2uF R70 2.26K 2.5REF R64 10K R44 REF+ R45 1K C27 0.1uF C21 10uF C26 0.1uF R43 REF- R67 4.75K R36 REF_CH3/7 +VIN + C37 0.1uF C31 0.1uF C10 0.1uF C9 0.1uF 6 SW1A DVdd C28 0.1uF C41 0.1uF C17 0.1uF C53 0.1uF C61 0.1uF C62 0.1uF C23 0.1uF FB2 AVdd TP14 SW1B 2 U5A TL7726 1 U6A TL7726 1 AVdd 8 2 U15A 2 1 2 U9A 1 SN74AHCT04 U5F 7 TL7726 TL7726 U15F 12 13 SN74AHCT04 0 ohm R35 0 ohm R66 0 ohm R54 U6B 3 10 U15E 11 DVdd TP16 SN74AHCT04 8 5 6 4 2 3 SN74AHC1G32 C58 1 5 U16 U15B 3 CLKX DVdd U18B 10 11 12 13 PRE CLK D CLR Q Q SN74HC74 PRE CLK D CLR 9 8 DVdd 4 3 2 1 4.7uF C33 0.1uF R48 9.09K TP15 C35 + C34 D+1 D+2 D+3 2 5 6 9 12 15 16 19 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 D1 D2 D3 D4 D5 D6 D7 D8 5 CLK SN74HC08 C55 0.1uF 11 4 3 33 CLKX 1 /OE DVdd U11 13 CLKX VCC 20 1 U9B R60 U17 12 VDD REFIN GND TLC5618A 8 8 U14D R49 330 3 SN74AHCT08 W5 XF TP18 R50 1 5 FSX+XF 6 DX 4 SN74AHCT04 8 9 10 11 12 13 1 3 5 2 4 6 FS-DLY 3 U14A U9E U9F U12 4 OUTA /CS DIN 7 OUTB SCLK 3 R38 10K R62 3 4 D+1 7 D+2 8 D+3 13 14 17 18 ~CS FS U13 3 IN 4 IN PG 6 5 R55 604K (+3V) R51 590K 2 /EN OUT OUT 7 R47 20K 1 GND SENSE TPS7101 U15D 9 6 U15C 5 R65 10K D3 1N4148 C56 0.1uF C60 0.1uF TRIM 5 C51 4.7uF + C52 4.7uF -VIN Figure 3-2. EVM Schematic Diagram J13 R56 10K J14 Schematic Diagram C47 100pF R57 0 ohm R58 10K Circuit Description C48 100pF R59 0 ohm 2.5REF Power In J10 1 +VIN (+10V) 2 C30 0.1uF D1 + 3 C32 4.7uF R37 10K + C40 4.7uF (-10V) -VIN +VIN U10 FB1 2 VIN C22 2.2uF + 3 C24 1uF 4 GND MAX6250 Circuit Function 3.2 Circuit Function The following paragraphs describe the function of individual circuits. 3.2.1 Inputs The TLV1504/1544/2544/TLC1514/2554 has four analog inputs; A0, A1, A2, and A3. While the TLV1508/2548/TLC1518/2558 has eight input channels; A0-A7. The applied input signal connects to these inputs as follows: - A0. One operational amplifier of a single-supply TLV2772 is used to scale the input analog signal and the dynamic range of the output is compressed to 0 V-5 V over a wide range of input levels (0 V - 10 V and zero dc input offset). The second TLV2772 op amp is used to buffer the A0 input signal. A1. A TLE2142 dual-supply operational amplifier is used to scale the wide ranging(0 V- 10 V) signal connected to the A1 input. The operational amplifier receives external input through J2. A2-A7. These inputs are available for user-defined inputs. The external inputs to these channels are applied through J1, J4 through J7, respectively. It is important to note that each input channel has a low-pass filter. The filter RC components can be adjusted to suit the application. 3.2.2 A0 - External Input via Input Scaling and Voltage Follower Operational Amplifiers It should be noted that for AVDD = 5 V there is a 2.5 V dc offset voltage, produced by the node voltage of the voltage divider (R5/R6) multiplied by the amplifier gain, at the input of channel A0. The offset is used to convert the bipolar input to a single-ended input needed by the ADC. It is assumed that the analog input signal is free of dc offset. If the incoming analog signal has a dc offset, then the ADC REF- voltage is typically adjusted to the same value as the input signal dc offset voltage and REF+ is raised by the same amount. Since REF+ max is 5 V, a sinusoid input signal of 8Vpp and 0.5 V dc offset produces full-scale from the ADC. By ac-coupling the input to J3, the dynamic range of the input increases. 3.2.3 A1 - External Input via Dual Supply Operational Amplifiers Used for Input Scaling and Buffering The inverting input of one TLE2142 operational amplifier is connected to J2 via a 40.2K resistor, and signal from this amplifier (gain = 0.25) is buffered by a second TLE2142 op amp used to drive input A1. This arrangement minimizes the interaction between A1 and the output of the first operational amplifier. With an input power supply of 7 V or greater, this amplifier configuration produces a linear signal from 0 V to 5 V. This signal does not approach the amplified nonlinearity limits when operating close to the supply rail voltages. Input A1 is protected from voltages below and above the ADC supply by two diodes. Also input A1 is low-pass filtered and the filter 3 dB cutoff frequency should be set to pass the desired input signal. The amplifier noninverting input signal has a quiescent value of AVDD/2 for proper midpoint biasing for the ADC. When using the amplifier with direct Circuit Description 3-5 coupling and an input with dc offset, full-scale ADC output code is achieved with less input amplitude. In this instance, reduce the dynamic range of the input and adjust REF+ and REF- as necessary. When capacitor coupling is used between the source and J2, an input range of 10 V to -10 V produces 0 V to 5 V at input channel A1. The SMA connectors, J1, J4-J9, provide unbuffered inputs to the ADC. These inputs are protected by diodes to prevent damage to the ADC from voltages in excess of the supply rail voltages. Each channel has RC components used for band limiting the input signal. The dc signal REF_CH3/7, via W3 pins 2-3, is made available at channel A3 (TLV1504/1514/2544/TLC1514/2554) and channel A7 (TLV1508/2548/TLC1518/2558). In this configuration the ADC operation can be checked without having to apply an external input to the EVM. When using the unbuffered inputs, the driving source impedance must be less than 1 k for proper slew rate of the input signal. The source must provide enough current into 50 pF to arrive at a final voltage value within the device-specified sampling time. Also, if the source noise is not below the 10-bit or 12-bit level, this noise could cause jitter in the output least significant bit (LSB). 3.2.4 Power A balanced voltage input of 10 V maximum (7 V minimum) and ground should be supplied to the EVM through connector J10 with the positive supply voltage applied to J10-1, the negative supply to J10-3, and ground to J10-2. The operational amplifier, U1, uses the bipolar power supplies. The remainder of the EVM uses regulated 5 V from the positive supply through the TPS7101 low dropout regulator. Switch SW1 can switch the output voltage of the regulator from nominally 5-V to 3.3-V operation. The regulator output voltage is divided into the digital supply (DVdd) and analog supply (AVdd) through ferrite beads and individual filter capacitors. The 5-V or 3.3-V output powers the following devices: U2, U3, U4, U5, U6, U7, U8, U9, U11, U12, U14, U15, U16, U17, and U18. The 7 V to 10 V is applied to the TLE2142 while only the positive supply voltage is applied to the TPS7101 low-dropout regulator. The TPS7101 regulates for a 5-V or 3.3-V VCC such that ADC evaluation can be done at either VCC through switch SW1. SW1 changes the ADC/TLC5618A DAC voltage reference to accommodate the change in VCC; SW1 also changes VCC to the SN74AHC244. The microinverter can be used to accommodate inversion for software interrupt processing. 3.2.5 Voltage Reference Generation A nominal 5 V reference is supplied by the MAX6250 precision reference. When switch SW1 is in the 5 V supply position the REF+ can be adjusted from 1.62 V - 5 V and REF- from 0 V - 2.50 V, and with 3.30 V VCC supply selected REF+ ranges from 0.97 V - 3 V and REF- ranges from 0 V - 1.50 V. The voltage differential between REF+ and REF- should always be equal to, or greater than, 2.5 V for proper operation within the TLV1544, TLV2544, TLV2548, TLV1504, TLV1508, TLC1514, TLC2554, TLC1518, and TLC2558 specified limits. Ratiometric measurements are the signals that vary with the supply voltage. If an input signal voltage is used that varies proportionately with the supply 3-6 Circuit Description voltage, such as the potentiometer input to A3/A7 (REF_CH3/7), the signal is a ratio of the absolute value of the supply. Also it should be remarked that the input conversion result is independent of supply voltage variations. The reference voltage for the TLC5618A, 12-bit DAC is generated from the same source as the ADC, therefore, both devices will track together once the voltages are set. 3.2.6 Test and Interfacing Connectors Test connector J7 provides a convenient point for measuring the ADC device signal with a logic analyser. The device test points as listed in Table 3-1. Table 3-1. Test Connector J7 J7 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 U3 and U4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Function DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA GND XF GND FSX GND INT3 GND CLKX(I/OCLK) U3 and U4 are not part of the ADC EVM and must be added. J12 is a 26-way, 100-mil spacing, male 2-row header that interfaces the TMS320C203 DSP EVM board from Wyle Electronics or the TMS320C54X DSKplus EVM. In order to minimize crosstalk introduced in the ribbon cable by the CLKOUT signal, the pin carrying the CLKOUT should be disconnected at Wyle's TMS320C203 DSP EVM board. J11 is used to interface the TMS320C50 DSP EVM from Texas Instruments. Circuit Description 3-7 3.2.7 Jumper Arrangement The EVM evaluation can begin with the following shorting plug arrangement. Device TLV1544 TLV1504 TLC1514 TLC1518 TLV1508 Jumper Configuration W1 pins 2-3 shorted W2 pins 2-3 shorted W3 pins 1-2 shorted W5 pins 1-2 shorted (during loopback testing W5 pins 2-3 shorted) W6 shorted (when using the DSP timer) W7 pins 3-4 shorted (W7 pins 5-6 shorted for real-time DSP captured data to the DAC) W8 pins 1-2 shorted W9 pins 1-2 shorted W11 open JP1 open W1 pins 2-3 shorted W2 pins 2-3 shorted W3 pins 1-2 shorted W5 pins 1-2 shorted (during loopback testing W5 pins 2-3 shorted) W6 shorted (when using the DSP timer) W7 pins 3-4 shorted (W7 pins 5-6 shorted for real-time DSP captured data to the DAC) W8 pins 1-2 shorted W9 pins 2-3 shorted W11 open JP1 open TLV2544 TLV2548 TLC2554 TLC2558 3.2.8 Breadboard Area The breadboard area on the EVM board is an arrangement which is most convenient for a discrete component filter stage/adding functions to the EVM. The voltages AVDD and DVDD, and GND are conveniently provided at the periphery of the breadboard area. 3.2.9 TLC5618A, 12-Bit Serial DAC A 12-bit serial DAC is provided on the EVM for evaluating the output from the ADC. The serial digital input value applied to the converter, is converted into an analog value. The reference voltage for the DAC is set to (REF since the DAC output has a X2 op amp. Monitoring the out2 put from the DAC at J13 gives a very sensitive measure of the analog input applied to the ADC. ))-(REF-) 3.2.10 LOOPBACK Testing LOOPBACK testing is a convenient way for checking how well the ADC is performing, without having to store the ADC output in memory. Additional circuitry is provided on the EVM for doing just that. The ADC output data is formatted, using D-type flip flops, to directly drive the TLC5618A, 12-bit serial DAC. With jumper W5 pins 2-3 shorted, the ADC output applied to the DAC is converted to an analog replica of the ADC input. The DAC output is monitored at OUTB (J14). Setting up the ADC for conversion is simple - see Section 1.7. 3-8 Circuit Description Chapter 4 Operation This chapter describes the basic operation of the EVM with a host DSP or processor. Topic 4.1 4.2 4.3 Page ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 TLV1544/2544/2548 Hardware Interfacing to the TMS320 DSP . . . . . 4-3 Data Sheet Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Operation 4-1 ADC Overview 4.1 ADC Overview The following paragraphs describe the TLV1504, TLV1508, TLV1544, TLV2544, TLV2548, TLC1514, TLC2554, and TLC2558 ADCs in general. 4.1.1 General Description As discussed earlier in Chapter 1, this evaluation module (EVM) provides a platform for evaluating the following 10-bit ADCs: TLV1504, TLV1508, TLV1544, TLC1514, and TLC1518, and the following 12-bit ADCs: TLV2544, TLV2548, TLC2554, and TLC2558. These are CMOS devices where the TLV version operates from a wide range of voltage ranging from 2.7 V to 5.5 V supply voltage while the TLC version is fixed 5-V supply. The converter uses an n-bit (n = 10-bit or 12-bit resolution), switched-capacitor successive approximation (SAR) ADC and a 2-bit resistor string. The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binaryweighted capacitors (see Figure 1 of SLAS139C). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the following phase of the conversion process switches are manipulated allowing the threshold detector to begin identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-) voltage. This process is repeated until all n-bits are counted. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB. 4.1.2 Timing Diagrams Refer to each specific data sheet for the system signal timing diagrams which are listed below as follows: - Figures 16 through 19 of the device datasheet (SLAS139C) for TLV1544 Figures 2 through 14 of the device datasheet (SLAS198A) for TLV2544/2548) Figures 2 through 14 of the device datasheet (SLAS251) for TLV1504/1508. Figures 2 through 14 of the device datasheet (SLAS252) for TLC1514/1518) Figures 2 through 14 of the device datasheet (SLAS220A) for TLC2554/2558 The timing diagrams show the four basic I/O signal sets required for microprocessor and DSP timing. 4-2 Operation TLV1544/2544/2548 Hardware Interfacing to the TMS320 DSP 4.2 TLV1544/2544/2548 Hardware Interfacing to the TMS320 DSP Figures 4-1 and 4-2 are the schematic diagram showing the hardware connections between the TLV1544 to the TMS320C50 and the TLV25448 and the TMS320C203/54X DSP respectively. Refer to Figure 4-1 to interface TLC1514/8 and TLV1504/8 to the TMS320C DSP and Figure 4-2 to interface TLC2554/8 to the TMS320C DSP. Figure 4-1. Schematic Diagram VCC = 5 V 4.7 F 0.01 F A0 Analog Inputs A1 A2 A3 TLV1544 9 A2 A3 10 CSTART A1 11 GND A0 12 INV CLK VCC 13 FS EOC 14 REF- I/O CLK 15 REF+ DATA IN 16 CS DATA OUT TMS320C50 DSP VCC 40 INT3 8 7 6 5 4 3 2 1 0.01 F See Note 0.01 F CLKR 124 CLKX 106 DX 43 DR 109 104 45 XF FSX FSR 46 NOTE: Software programs using interrupt processing may need the inverter and the connection shown in dotted lines. In programs using wait states, EOC is not required. Operation 4-3 Data Sheet Information Figure 4-2. Schematic Diagram VCC = 5 V 4.7 F 0.01 F A0 Analog Inputs A1 A2 A3 TLV1544/2548 A2 A3 10 CSTART A1 11 GND A0 12 PWDN VCC 13 FS EOC/INT 14 REFM SCLK 15 REFP SDI 16 CS SDO 9 8 7 6 5 4 3 2 1 I/O CLK DATA IN DATA OUT See Note 84 (41) CLKR (BCLKR) 87 (48) CLKX (BCLKX) 90 (59) DX (BDX) 86 (45) DR (BDR) 98 (27) 89 (53) 85 (43) XF (XF) FSX (BFSX) FSR (BFSR) 0.01 F VCC 20 (67) INT3 (INT3) TMS320C203 (TMS320C54X) 0.01 F NOTE: Software programs using interrupt processing may need the inverter and the connection shown in dotted lines. In programs using wait states, EOC is not required. 4.3 Data Sheet Information Further information for a specific device can be obtained through their datasheet by accessing the TI website at htt://www.ti.com/. A list of the device datasheet and their respective literature number are as follows: - TLV1504/8CPW TLV1544CPW TLV2544/8CPW TLC1514/8CPW TLC2554/8CPW Literature Number SLAS251 Literature Number SLAS139C Literature Number SLAS198A Literature Number SLAS252 Literature Number SLAS220A The literature number can change anytime due to revisions and may cause a miss when searching the TI website. In this case the device part number can be used to narrow down the search. To order a copy of the above literature, or any literature for each of the devices mentioned in this manual, refer to the Preface section of this manual. All related data sheets and their corresponding literature numbers are listed under the Related Documentation from Texas Instruments section. 4-4 Operation Appendix A Grounding Considerations This appendix contains general information on grounding techniques for a printed-circuit board using the TLV1544/2544/2548 devices. Topic A.1 Page Printed Circuit Board Grounding Considerations . . . . . . . . . . . . . . . A-2 Grounding Considerations A-1 Printed Circuit Board Grounding Considerations A.1 Printed Circuit Board Grounding Considerations When designing analog circuits that share a ground with digital and high current power supplies, the voltage drop along the high current paths must be considered. This voltage drop is a result of the current flowing through the greater than zero resistance of the current path, or high frequency current transients flowing through a greater than zero inductance of a current path. If the signal ground is connected to the power supply ground at an improper location, an excessive voltage drop may occur in the signal ground and appears as part of the signal, causing an error. The solution for low frequency analog signals is to establish a single ground point on the PC board and connect all low frequency grounds to that point. By using this method, currents flowing along any one path to ground do not produce error voltages in any other ground path. Analyzing the current flow paths within the analog section gives an indication of which components can be lumped together to a common ground path and which should be separate. One half LSB error with a reference of 4.1 volts would be approximately 0.5 mV, so the ground trace resistance would have to be no greater than 0.5 ohms with 1 mA of ground current. When input source signals are low current, a common ground trace may be appropriate. Higher input current sources, however, should always have a separate ground trace to the most robust ground point location, usually at the ground entrance to the PCB. Even though the TLV1544/2544/2548 operating current is low, some high speed current transients are present, usually caused by output digital switching requiring a ground plane or wide ground return trace to the central board entry ground for these signals. All signal paths and their respective ground returns must be examined to minimize signal loop area. The power inputs and VCC lines must also be analyzed in the same manner and detail that the ground returns are. A-2 Grounding Considerations |
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