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THS1206, THS12082, THS10064, THS10082
Evaluation Module
User's Guide
May 2000
AAP Data Conversion
SLAU042A
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
About This Manual
This user's guide serves as a reference book for the THS1206/THS12082/ THS10064/THS10082 evaluation module. It describes the operation and usage of the 12-bit THS1206/THS12082 and 10-bit THS10064/THS10082 analog-to-digital converter (ADC) evaluation modules.
How to Use This Manual
This document contains the following chapters:
-
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6
EVM Description Physical Description Schematic Diagram Common-Connector Interface PC Board and Bill of Materials Schematics
Information About Cautions and Warnings
This book contains cautions.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
The information in a caution is provided for your protection. Please read each caution carefully.
Read This First
iii
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
Data Sheets: THS1206 data sheet (literature number SLAS217B) contains electrical specifications, available temperature options, general overview of the device, and application information. THS12082 data sheet (literature number SLAS216) contains electrical specifications, available temperature options, general overview of the device, and application information. THS10064 data sheet (literature number SLAS255) contains electrical specifications, available temperature options, general overview of the device, and application information. THS10082 data sheet (literature number SLAS254) contains electrical specifications, available temperature options, general overview of the device, and application information.
iv
Running Title--Attribute Reference
Contents
1 EVM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 EVM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-2 1-3
2
Common-Connector Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Daughtercard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
3
4
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
3-1 3-2 3-3 3-4 3-5 3-6 Silkscreen (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silkscreen (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 3-3 3-3 3-4 3-4
Tables
2-1 2-2 3-1 Jumper J6, Expansion Peripheral Interface Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Jumper J7, Expansion Peripheral Interface Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
vi
Chapter 1
EVM Description
This chapter gives a general description and overview of the THS1206/ THS12082/THS10064/THS10082 evaluation module (EVM), and describes the requirements for using this module.
Topic
1.1 1.2 1.3 1.4
Page
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
EVM Description
1-1
Purpose
1.1 Purpose
The evaluation module provides a platform for lab prototype evaluation of the Texas Instruments 12-bit THS1206/THS12082 and the 10-bit THS10064/ THS10082 high-speed analog-to-digital converters. In addition, it provides the interface to Texas Instruments digital signal processor kits or evaluation modules, which provide the common-connector interface (C6201, C6701, C6211, C5402).
1.2 Power Supply Requirements
-
The EVM is designed to be powered by a lab dc power supply (red and black inputs VDD and AGND). The required supply voltage range is from 6 V to 10 V. It can also be powered by a DSP starter kit or evaluation module, which features the common-connector interface. The selection is done with jumpers J1 and J2.
Voltage Limits Exceeding the 10-V maximum supply voltage range can damage EVM components.
1.3 EVM Basic Function
The EVM allows evaluation of the THS1206, THS12082, THS10064, and THS10082 analog-to-digital converters. Typically, a processor is used for evaluating these devices. The EVM is specifically designed for interfacing to the DSP starter kits or evaluation modules, which feature the commonconnector interface (C6201, C6701, C6211, C5402). The different operation modes for the analog input configuration of the THS1206, THS12082, THS10064, and THS10082 are available on the evaluation module. Any channel selection can be done according to the data sheet of each device.
-
Single-ended analog input The THS1206/THS10064 (THS12082/THS10082) provide up to four (two) single-ended analog input channels. These four (two) single-ended inputs are provided on the EVM via the four BNC connectors, which are labeled AINP, AINM, BINP, and BINM. BNC connectors AINP and AINM do not have any function with the THS12082 and THS10082, which only feature two single-ended analog input channels. The analog input voltage range is from -1 V to 1 V. The analog input is level-shifted into the analog input range of the analog-to-digital converter (1.5 V to 3.5 V) by using an operational amplifier in an inverting configuration. The voltage used for the level shift is generated by the REFOUT (2.5 V) of the analog-to-digital converter. A resistor divider provides the 1.25 V from the 2.5-V output voltage. The analog input signal is dc-coupled.
1-2
EVM Setup
-
Differential analog input The THS1206/THS10064 (THS12082/THS10082) provide up to two (one) differential analog input channels to the analog-to-digital converter. These two (one) differential inputs are provided on the EVM via the two BNC connectors, which are labeled ADIFF and BDIFF. The BNC connector ADIFF does not have any function with the THS12082 and THS10082, which only feature one differential analog input channel. The analog input voltage range is from -2 V to 2 V. To use the differential mode, a single ended signal is applied to ADIFF or BDIFF. This signal is converted into a differential signal by a transformer, and is therefore ac coupled. The center tap of the transformer is connected to the common mode output voltage REFOUT of the analog-to-digital converter. As a result of this, the input signal is shifted to the common-mode voltage REFOUT. Clock circuit An external clock with frequency up to 6 MHz (8 MHz for the THS10082 and THS12082) is required for operation of the analog-to-digital converter in the continuous-conversion mode. The external clock source is required to drive the 50- BNC input EXT-CLK. The clock signal can also be generated from the connected processor. J7 should be set to the appropriate position. Digital output The digital output of the analog-to-digital converter is applied to connector block J9 and is also connected to the data bus of the common connector interface. No latch is used between the analog-to-digital converter and J9. The analog-to-digital converter is able to drive up to 30 pF at the data bus D0-D11 (D0-D9 for the THS10064 and THS10082).
-
-
1.4 EVM Setup
The EVM provides a platform for lab-prototype evaluation. Typically, it is operated by using a Texas Instruments DSP kit or evaluation module.
-
J1: selection of the analog supply voltage: J1 inserted between 1 and 2: the supply voltage (5 V) is taken from the DSP starter kit or evaluation module with the common-connector interface. No external analog supply voltage is required in this configuration. J1 inserted between 2 and 3: for use of an external dc power supply (6 V to 10 V). The supply voltage, ranging from 6 V to 10 V, is regulated to 5 V by using the Texas Instruments low-dropout regulator TPS7250.
-
J2: selection of the digital supply voltage: J2 inserted between 1 and 2: the supply voltage (3.3 V) is taken from the DSP starter kit or evaluation module with the common-connector interface. No external digital supply voltage is required in this configuration. J2 inserted between 2 and 3: for use of an external dc power supply (6 V to 10 V). The supply voltage, ranging from 6 V to 10 V, is regulated to 3.3 V by using the Texas Instruments low-dropout regulator TPS7233.
EVM Description
1-3
EVM Setup
-
J3: selection of the analog input configuration: J3 inserted between 1 and 4: selection of the differential input ADIFF (in combination with J4 set between 1 and 4) J3 inserted between 2 and 5: selection of the single ended input AINP J3 inserted between 3 and 6: required for the THS12082 and THS10082, where the input AINM of the THS1206 functions as RESET input. Point 3 of J3 is connected to the RESET signal of the common-connector interface.
-
J4: selection of the analog input configuration: J4 inserted between 1 and 4: selection of the differential input ADIFF (in combination with J3 set between 1 and 4) J4 inserted between 2 and 5: selection of the single ended input AINM J4 inserted between 3 and 6: required for the THS12082 and THS10082, where pin 31 (input AINP of the THS1206) functions as an internal FIFO overflow indicator. This pin can be monitored during data converter software debugging.
-
J5: selection of the analog input configuration; J5 inserted between 1 and 2: selection of the single ended input BINP J5 inserted between 2 and 3: selection of the differential input BDIFF (in combination with J6 set between 2 and 3) J6: selection of the analog input configuration: J6 inserted between 1 and 2: selection of the single ended input BINM J6 inserted between 2 and 3: selection of the differential input BDIFF (in combination with J5 set between 2 and 3) J7: selection of the clock source: J7 inserted between 1 and 2: the clock input of the data converter is connected to the common connector interface. In this case, the DSP should generate the clock signal. J7 inserted between 2 and 3: the clock signal should be applied to the BNC connector EXT_CLK in this configuration.
-
J8: J8 is a connector block where the following digital signals can be monitored:
Pin Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Description GND CONV_CLK GND DATA_AV GND Pin Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Description WR/ GND OV_FL GND RESET
1-4
EVM Setup
-
J9: J9 is a connector block where the following digital signals can be monitored:
Pin Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Description NC GND CS0 GND NC GND DATA_AV GND CONV_CLK GND CS1 GND RD GND D0 GND D1 GND D2 GND Pin Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 Pin 27 Pin 28 Pin 29 Pin 30 Pin 31 Pin 32 Pin 33 Pin 34 Pin 35 Pin 36 Pin 37 Pin 38 Pin 39 Pin 40 Description D3 GND D4 GND D5 GND D6 GND D7 GND D8 GND D9 GND D10/RA0 GND D11/RA1 GND NC GND
-
Pin 20
J10: generation of chip select with C5000 DSP For an interface of the THS1206EVM to the C5000 DSP starter kit or EVM, J10 should be inserted while J11 is left open. J11: generation of CS1 with C6000 DSP For an interface of the THS1206EVM to the C6000 DSP starter kit or EVM, J11 should be inserted while J10 is left open. J12: generation of the write signal J12 inserted between 1 and 2: to interface the THS1206EVM to the C5000 DSP starter kit or EVM, J12 should be inserted between 1 and 2. J12 inserted between 2 and 3: to interface the THS1206EVM to the C6000 DSP starter kit or EVM, J12 should be inserted between 2 and 3. J13: generation of CS0 J13 inserted between 1 and 2: to interface the THS1206EVM to the C6000 DSP starter kit or EVM, J12 should be inserted between 1 and 2. J13 inserted between 2 and 3: to interface of the THS1206EVM to the C5000 DSP starter kit or EVM, J12should be inserted between 2 and 3.
-
The EVM provides several test points for the analog and digital grounds. These are labeled TPA and TPD respectively. Two test points for AVDD and DVDD are also provided.
EVM Description
1-5
1-6
Chapter 2
Common-Connector Interface
This chapter presents the common-connector interface.
Topic
2.1
Page
Daughtercard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Common-Connector Interface
2-1
Daughtercard Interface
2.1 Daughtercard Interface
A standard is under definition for daughtercards made to function with TMS320C6000 and TMS320C5000 systems. This interface standard is necessary to allow daughtercards to be used on systems from different vendors, and even across devices and DSP platforms. The `C6000 daughtercard standard is applicable to all of the `C6000 interfaces, and a subset applies to the `C5000 platform. Parallel interfaces that can communicate with the daughtercards are the 32-bit external-memory interface (EMIF), the 32-bit expansion bus, and the 16-bit host-port interface (HPI). The `C5000 family has a 16-bit EMIF, and 8- and 16-bit HPIs. The specific pinout of the `C5000 daughtercards is a subset of the `C6000. The pinouts of the J6 connector are described in Table 2-1, and the J7 connector pinouts are described in Table 2-2. Also see Chapter 4 - Schematics.
2-2
Daughtercard Interface
Table 2-1. Jumper J6, Expansion Peripheral Interface Pinout
J1 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND X_A15 X_A19 X_A18 Name +5V Signal Name C5000 Power Supply NC Address pin Address pin NC NC Address pin NC NC NC Ground NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND X_A17 X_A21 X_A20 Name +5V Signal Name C6000 (EMIF) Power Supply NC Address pin Address pin NC NC Address pin NC NC NC Ground NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC J1 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 X_DS X_RE X_WE X_OE X_D7 X_D6 X_D5 X_D4 X_D3 X_D2 X_D1 X_D0 X_D11 X_D10 X_D9 X_D8 Name 3.3V Signal Name C5000 Power supply NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Data pin Data pin Data pin Data pin NC NC Data pin Data pin Data pin Data pin Data pin Data pin Data pin Data pin NC NC Asynchronous read enable Asynchronous write enable Asynchronous output enable NC NC Data space select NC NC CE0 ARE AWE AOE X_D7 X_D6 X_D5 X_D4 X_D3 X_D2 X_D1 X_D0 X_D11 X_D10 X_D9 X_D8 Name 3.3V Signal Name C6000 (EMIF) Power Supply NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Data pin Data pin Data pin Data pin NC NC Data pin Data pin Data pin Data pin Data pin Data pin Data pin Data pin NC NC Asynchronous read enable Asynchronous read enable Asynchronous output enable NC NC Chip enable 0 NC NC
Common-Connector Interface
2-3
Daughtercard Interface
Table 2-2. Jumper J7, Expansion Peripheral Interface Pinout
J1 Pin Name Signal Name C5000 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Name Signal Name C6000 (EMIF) NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC J1 Pin Name Signal Name C5000 Name Signal Name C6000 (EMIF)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND GND DB_DET X_RESET X_IOSTRB X_INT0 X_TOUT
NC NC NC NC Timer output NC NC NC NC NC NC NC External interrupt 0 NC NC I/O access strobe NC NC System reset signal NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Daughterboard detect NC Ground NC Ground NC GND GND GND RESET INUM2 EXT_INT0 TOUT0
NC NC NC NC Timer 0 output NC NC NC NC NC NC NC External interrupt 0 NC NC Active interrupt number NC NC System reset signal NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ground NC Ground NC Ground NC
2-4
Chapter 3
Physical Description
This chapter provides information about the PCB layout, and contains a list of the components used.
Topic
3.1 3.2
Page
Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Physical Description
3-1
3.1 Printed-Circuit Board
The following figures show the silkscreen and the four layers of the evaluation module's printed-circuit board.
Figure 3-1. Silkscreen (Top)
Figure 3-2. Silkscreen (Bottom)
3-2
Figure 3-3. Printed-Circuit Board Layer 1
Figure 3-4. Printed-Circuit Board Layer 2
Physical Description
3-3
Figure 3-5. Printed-Circuit Board Layer 3
Figure 3-6. Printed-Circuit Board Layer 4
3-4
Bill of Materials
3.2 Bill of Materials
Table 3-1 lists the components used in constructing the EVM.
Table 3-1. Bill of Materials
Quantity Reference 8 13 7 1 15 2 11 1 1 1 1 1 1 7 1 14 1 1 2 7 2 2 12 2 1 1 C1-C3, C5-C7, C20-C21 C4, C8-C19 L1-L4, L6-L8 L5 R1, R3, R5, R8-R11, R13, R15, R18-R20, R25, R27, R28 R23, R24 R2, R4, R6, R7, R12, R14, R16, R17, R21, R22, R26 IC1 IC2 IC3 IC4 IC5 IC6 ADIFF, AINM, AINP, BDIFF, BINM, BINP, EXT-CLK D1 AVDD, DGND, DVDD, SUPPLY, TPA1-TPA5, TPD1-TPD5 AGND VDD T1, T2 J1, J2, J5-J7, J12, J13 J10, J11 J6, J7 (HD-DSP) 1, 3, J14, J20-J24, J100, J101, J103, TEST J3, J4 J8 J9 Description 1 nF, SMD, size 0805 10 F Tantalum, C-Case 10 H, size 1206 470 H, size 49.9 , size 0805 0 , size 0805 10 k, size 0805 THS1206CDA AD8044AR TPS7250QD TPS7233QD SN74AHC1G04DBVR SN74AHC1G02DBVR BNC 1N4004 Test point PB4 black PB4 red Transformer: T1-6T-KK81 Jumper 3 pole Jumper 2 pole SMD-Connector Jumper 2 x 18 pole Jumper 2 x 3 pole Jumper 2 x 5 pole Jumper 2 x 18 pole MIRA-Electronic: 8132/10 k Bereitstellung von TI Sporle Bereitstellung von TI Bereitstellung von TI Bereitstellung von TI Bereitstellung von TI Burklin: 78F2475 Burklin: 26 S 7950 Burklin: 07 F 810 Burklin: 35 F 234 Burklin: 35 F 236 Municom Riebensahm : 0100125112003 Riebensahm : 0100125112002 Samtec: TFM-140-32-S-D-LC Where to buy MIRA-Electronic:8231/102 Burklin: 25 D 1046 Burklin: 76 D 470 Burklin: 74 D 4742 MIRA-Electronic: 8132/49.9
Physical Description
3-5
3-6
Chapter 4
Schematics
This chapter contains the evaluation module schematics.
Schematics
4-1
4-2
AVDD VREF 1 2 R13 3 49R9 C5 1nF 10k J3 3 R3 2 5 4 BDIFF 4 AGND R4 BNC AGND C20 1nF AGND AGND R10 4 49R9 R9 UMID BINM R16 C3 BNC 10k R15 49R9 12 13 49R9 R27 49R9 AGND 1nF 5 6 TRAF0 1 2 T1 3 AGND VREF AGND 3 2 BINM AGND 10k 1nF 5 6 TRAF0 T2 3 2 1 R28 49R9 R19 49R9 R20 49R9 C21 1nF AGND UMID AINP 1 49R9 C1 2 11 AD8044 4 AGND IC2A OV_FL 6 3 AGND AGND AGND IC2C 8 AD8044 R14 10 R12 9 10k C4 10 J5 L1 10 BINP
+ _
BINP
Schematics
+
BNC 49R9 R11 VREF AGND
AINP
C7 1nF
R2
+ _
10k
BNC
R1
49R9
AGND
AGND AGND
ADIFF
BNC
+ _
IC2D 14 AD8044 R17
R18 49R9 C6 1nF 10k
1 J6
AGND
AGND
VREF AGND 1 4 5 6 J4 1nF 10k RESET AGND AINM IC2B 7 R8 2 3 49R9 C2 AD8044 R7 5 6
AGND
AGND AGND
AGND
AINM
R6
+ _
10k
BNC
R5
49R9
AGND
AGND AGND
03-03-200009:12:28 f=1.073 D:\hpeagle\ths1206\THS1206EVM\THS1206EVM.sch
(Sheet:1/5)
J7 1 CONV_CLK 2 3 DVDD
L2 CLK 10 10 EXT_CLK C8
L3
+
10 10 R25 49R9 BNC_B
C9
+
RESET 10 OV_FL 8 WR/ 6 DATA_AV 4 CONV_CLK 2 J8
9 7 5 3 1
DGND THS1206 DGND DGND DATA_AV CS0/
DGND 1 J9 2
DGND
RD/ WR/ CS/ CS0/ BINP BINM AINP AINM C12 10 IC1 AVDD DB[0..11] AGND 10 L4 10 AGND R21 10k C13 AGND C10 10
DATA_AV CONV_CLK CS1 RD/
+ C11 +
DGND BGND DVDD BVDD /RD DATA_AV /WR CONV_CLK RA1/D11 CS1 RA0/D10 /CS0 D9 BINP D8 BINM D7 AINP D6 AINM D5 VREFP D4 VREFM D3 REFOUT D2 AVDD D1 AGND D0 SIG_CM
+
10
+
39
40 DGND DGND
VREF R22 10k
Schematics
AGND AGND
4-3
03-03-200009:12:28 f=1.073 D:\hpeagle\ths1206\THS1206EVM\THS1206EVM.sch
(Sheet:2/5)
4-4
1 HD-DSP J6 1 5 IC6 A GND Y CS1 VCC B 1G02 3 DGND J11 DVDD J10 2 2 CONV_CLK DATA_AV RESET 3 2 1 J13 CS0/ 3 CS0/ 2 WR/ 1 J12 DGND DVDD J7 VCC12 1 2 VCC12# GND@25 GND@13 VCC5@5 VCC5@7 GND@14 GND@26 VCC5@6 VCC5@8 NC2 NC8 NC3 NC9 NC4 NC10 NC5 NC11 VCC3@3 VCC3@4 XCLKX0 XCLKS0 XFSX0 XDX0 GND@15 GND@27 XCLKR0 NC12 XFSR0 XDR0 GND@16 GND@28 XCLKX1 XCLKS1 XFSX1 XDX1 SND@17 GND@29 XCLKR1 TMS320C6xxx DSP NC13 XFSR1 XDR1 (shown) GND@19 GND@30 TOUT0 TINP0 NC6 NC14 TOUT1 TINP1 GND@20 GND@31 XEX_INT7 IACK INUM3 IOSTRB/ INUM2 INUM1 INUM0 XRESET# DSP_PD GND@21 GND@32 XCNTL1 XCNTL0 XSTAT1 XSTAT0 NC7 NC15 XCE2# XCE3# DMAC3 DMAC2 DMAC1 DMAC0 GND@22 GND@33 GND@23 XCLKOUT2 GND@24 GND@34 79 80 IC5 5 2 4 3 DGND
Schematics
(Sheet:3/5)
DSP5V VCC5@1 1 2 VCC5@3 XA21 XA20 XA19 AX18 XA17 XA16 XA15 XA14 GND@1 GND@7 XA13 XA12 XA11 XA10 XA9 XA8 DGND XA7 XA6 VCC5@2 VCC5@4 XA5 XA4 XA3 XA2 XBE3# XBE2# XBE1# XBE0# GND@2 GND@8 XD31 XD30 XD29 XD28 XD27 XD26 XD25 TMS320C6xxx DSP XD24 DSP3V3 VCC3@1 (shown) VCC3@2 XD23 XD22 XD21 XD20 XD19 XD18 XD17 XD16 GND@3 GND@9 XD15 XD14 XD13 XD12 XD11 XD10 DVDD XD9 XD8 GND@4 GND@10 XD7 XD6 XD5 XD4 XD3 R26 XD2 XD1 10k XD0 GND@5 GND@11 XRE# XWE# RD/ XOE# XRDY NC1 XCE1# GND@6 79 80 GND@12
03-03-200009:12:28 f=1.073 D:\hpeagle\ths1206\THS1206EVM\THS1206EVM.sch
DSP5U DSP3U3 3 C15 DSPAVDD 10 J1 AGND C14 AGND TPA1 TPA2 TPA3 TPA4 TPA5 10 10 C18 1 DSPAVDD L6 L7 C19 AVDD 2 10 10 AVDD
IC3
+ +
1
SENSE/F8
OUT2
8
DSPRVDD
2
P6
OUT
7
+
10
3
GND
IN2
6
4
/EN
IN
5
TPS7250
+
AGND 0 R23 0 R24
AGND
AGND TPD1
AGND
AGND TPD2
AGND TPD3
AGND TPD4 TPD5
DGND
DGND
DGND
DGND
DGND
DGND
DGND
SUPPLY 470
L5
VDD ZDIODE D1
AGND 3 C17 DSPAVDD 10 J2 AGND C16 10 AGND 1 AVDD 2 AVDD AGND AGND
IC4
+
1
SENSE/F8
OUT2
8
2
P6
OUT
7
3
GND
IN2
6
4
Schematics
+
(Sheet:4/5)
/EN
IN
5
TPS7233
AGND
4-5
03-03-200009:12:28 f=1.073 D:\hpeagle\ths1206\THS1206EVM\THS1206EVM.sch
4-6
AVDD 3 AGND
Schematics
(Sheet:5/5)
03-03-200009:12:28 f=1.073 D:\hpeagle\ths1206\THS1206EVM\THS1206EVM.sch

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