View SLLS264A_1002781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TUSB2140 Data Manual
4-Port Hub With an Embedded Function for the Universal Serial Bus
SLLS264A November 1997
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1997, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1-1 1-1 1-1 1-1 1-2 1-2 1-4 1-5 1-5 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-3 3-1 3-2 3-4 3-4 3-5 3-5 3-6 3-6 3-7 3-8 3-9 3-9 3-9
iii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Embedded Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Device-Numbering Convention and Ordering Information . . . . . . . . . . . . . . . . . . . 1.5 Related Documents Referenced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Serial Interface Engine (SIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 SIE Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Hub Command Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Frame Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Suspend/Resume Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Hub Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Port Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 Embedded Function Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13 Embedded Function Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14 Embedded Function FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15 Embedded Function I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Register Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Function Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Endpoint 0 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Endpoint 0 Transmit Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 Endpoint 0 Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 Endpoint 0 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 Endpoint 0 Transmit FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 Endpoint 0 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.10 Endpoint 0 Receive Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
3.2.11 Endpoint 0 Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.12 Endpoint 0 Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.13 Endpoint 0 Receive FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.14 Endpoint 1 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.15 Endpoint 1 Transmit Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.16 Endpoint 1 Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.17 Endpoint 1 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.18 Endpoint 1 Transmit FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Embedded Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Interrupt Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Suspend and Remote Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Over-current Detection and Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Clock Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings Over Operating Free-air Temperature Range . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Ranges of Operating Free-air Temperature and Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Timing Characteristics for USB Transceivers . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Timing Characteristics for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Timing Characteristics for Remote Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . USB Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Bus-powered Hub, Ganged Port Power Management . . . . . . . . . . . . . . . . . . . . . . . 6.3 Self-powered Hub, Ganged Port Power Management . . . . . . . . . . . . . . . . . . . . . . . 6.4 Self-powered Hub, Individual Port Power Management . . . . . . . . . . . . . . . . . . . . .
3-10 3-11 3-12 3-12 3-12 3-13 3-14 3-15 4-1 4-1 4-1 4-1 4-1 4-1 4-2 4-2 4-2 4-3 4-3 4-5 4-5 4-5 5-1 5-1 5-1 5-2 5-3 5-3 5-5 5-7 6-1 6-2 6-3 6-4 6-5
5
6
Appendix A Firmware Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
iv
List of Illustrations
Figure
5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 6-3 6-4 6-5 6-6 A-1 A-2 A-3 A-4
Title
Page
5-3 5-3 5-4 5-4 5-5 5-5 E-6 E-6 E-6 E-7 E-7 E-7 6-1 6-2 6-2 6-3 6-4 6-5 A-2 A-3 A-5 A-6
Differential Driver Switching Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Driver Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Receiver Input Sensitivity Vs. Common Mode Input Range . . . . . . . . . Single-Ended Receiver Input Signal Parameter Definitions . . . . . . . . . . . . . . . . . . . SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Tiered Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical I2C Interface Connection to a Micro-Controller . . . . . . . . . . . . . . . . . . . . . . . Typical Crystal Tuning Circuit for the TUSB2140 USB Device . . . . . . . . . . . . . . . . . TUSB2140 Bus-Powered Hub, Ganged Port Power Management Application . . . TUSB2140 Self-Powered Hub, Ganged Port Power Management Application . . . TUSB2140 Self-Powered Hub, Individual-Port Power Management Application . Flow Chart for TUSB2140 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 0 Receive Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint 1 Transmit Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
1 Introduction
The TUSB2140 is a compound USB device that provides a 4-port hub and an embedded function. The TUSB2140 is fully compatible with the USB, version 1.0, specification and the embedded function is fully compatible with the USB display-device class specification. The embedded function is virtually connected to a fifth full-speed downstream hub port. In addition, the embedded function includes a control endpoint and an interrupt endpoint to support USB data transfers. The FIFOs and control registers associated with the endpoints are fully integrated within the device. An Inter IC(I2C), 2-wire serial interface is provided for a local micro-controller unit (MCU) to access the FIFOs and control registers. The TUSB2140 hub supports power switching to the downstream ports for either individual or ganged power management modes. External devices are required to switch power and to detect overcurrent conditions. Please see the application notes in Section 6. The TUSB2140 provides the required outputs to control power switching and the inputs to monitor any overcurrent conditions. In the ganged mode, all PWRON signals switch simultaneously.In addition, in the ganged mode the OVRCUR inputs should be tied together and driven by the same signal. The TUSB2140 requires a 48-MHz clock signal to sample data from the upstream port and to generate a synchronized 12-MHz USB clock signal. The hub supports the flexibility to use either a 48-MHz oscillator or a crystal tuned to 48-MHz. When an oscillator is used, the oscillator output must be connected to the XTAL1 terminal and the XTAL2 terminal should remain open. An oscillator with a TTL level output may be used if the output does not exceed 3.6-V maximum. For a crystal implementation, the XTAL1 terminal should be used as the input and the XTAL2 terminal should be used as the feedback path to the crystal. Because the crystal is required to resonate at 48-MHz, a tuning circuit may be required such as shown in Figure 6-3. USB-compatible transceivers are provided for all upstream and downstream ports. All external downstream ports support both full- and low-speed connection by automatically setting the slew rate according to the speed of the device attached to the port.
1.1
1.1.1
Features
Hub
* * * * * Universal Serial Bus (USB) Version 1.0 Compatible Includes Serial Interface Engine (SIE) All Four External Downstream Ports Support Full-Speed and Low-Speed Operations Integrated USB Transceivers Power Switching and Overcurrent Conditions are Reported for Per Port or Ganged Modes
The main features of the TUSB2140 hub and embedded function are listed in the following sections.
1.1.2
* * * * *
Embedded Function
USB Display Class Compatible Supports both Control and Interrupt Data Transfers Integrated FIFOs and Control/Status Registers Supports Interrupt Driven Operation to Minimize Local Micro-Controller Polling Supports USB Remote Wake-Up
1-1
1.1.3
* * * * *
General Characteristics
Low-Power CMOS Technology Generates a Clock Output With a Frequency of 12 MHz, 8 MHz, 6 MHz, or 4 MHz Available in a 40-Pin Dip Package or a 64-Pin TQFP Package Requires a 48-MHz Crystal or Oscillator Input Uses a 3.3 V and 5 V Power Supply
1.2
Terminal Assignments
N PACKAGE (TOP VIEW)
WAKEUP CLKOUT GND CLKSEL0 CLKSEL1 OVRCUR5 OVRCUR2 PWRON1 OVRCUR1 DP0 DM0 GND DP1 DM1 BUSPWR GANGED DP2 DM2 VCC3V DP3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC5V SCL SDA IRQ PWRON5 FUNCSUSP PWRON2 VCC3V OVRCUR3 PWRON3 GND XTAL1 XTAL2 OSCOFF PWRON4 OVRCUR4 RESET DM4 DP4 DM3
NC - No internal connection
1-2
PAG PACKAGE (TOP VIEW) CLKSEL1 CLKSEL0 GND NC CLKOUT NC NC WAKEUP NC VCC 5V SCL SDA NC NC IRQ PWRON5 OVRCUR5 NC OVRCUR2 PWRON1 NC OVRCUR1 NC DP0 DM0 NC GND NC DP1 DM1 NC BUSPWR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FUNCSUSP NC PWRON2 NC VCC3V OVRCUR3 NC PWRON3 GND NC NC XTAL1 XTAL2 NC OSCOFF PWRON4
NC - No internal connection
GANGED NC DP2 DM2 VCC 3V NC NC DP3 DM3 NC NC DP4 DM4 NC RESET OVRCUR4
1-3
1.3
Terminal Functions
TERMINAL NAME PAG NO. 16 N NO. 15 I/O I DESCRIPTION Port power indicator. BUSPWR is an active low input that indicates whether the ports and the hub source power from the bus or are self-powered by the local power supply. This standard TTL input must not change dynamically during operation. Clock output. Depending on the configuation of CLKSEL0 and CLKSEL1, CLKOUT is a selected clock output of 12 MHz, 8 MHz, 6 MHz, or 4 MHz. Data minus USB differential data pairs. DM1 - DM4 support up to four negative-signal downstream USB ports. Data plus USB differential data pairs. DP1 - DP4 support up to four positive-signal downstream USB ports. Data minus USB differential data. DM0 is used for the upstream USB port cable pair and negative signal. Data plus USB differential data. DP0 is used for the upstream USB port cable pair and positive signal. Function port suspend. FUNCSUSP is an active high output that indicates if the port that connects to the embedded function has been selectively suspended. Power switch/overcurrent detection. GANGED selects between gang or per port switching for overcurrent detection of the downstream ports. The setting is dependent upon an external power control device. This standard TTL input must not change dynamically during operation. Ground. All terminals must be tied to ground for proper operation O I I Interrupt. IRQ is an active low output that indicates that an interrupt condition has occured. Oscillator off. OSCOFF disables the internal oscillator for quiescent current draw (ICCQ) testing. OSCOFF must be tied low for operation. Overcurrent indicators. OVRCUR1 - OVRCUR5 are active low, standard TTL inputs. One overcurrent indicator is available for each of the four downstream ports. These inputs are internally gated when port power switching is ganged. The unused terminals must be tied high. Power on/off control switches. PWRON1 - PWRON5 are active low, open-drain outputs. One power on/off control switch is used for each of the four downstream ports. All outputs are switched together when the port power switching is ganged. Reset. RESET is a TTL input with hysteresis and must be asserted at power up for conformance to USB. When RESET is an active low, it initializes all logic. Serial clock. SCL is the clock signal for the I2C serial interface and is 5-V tolerant. Serial data. SDA is the bidirectional data signal for the I2C serial interface and is 5-V tolerant. SDA uses an open-drain output driver. 3.3-V supply voltage 5-V supply voltage
BUSPWR
CLKOUT
60
2
O
DM1 - DM4 DP1 - DP4 DM0 DP0 FUNCSUSP
14, 20, 25, 29 13, 19, 24, 28 9 8 48
14, 18, 21, 23 13, 17, 20, 22 11 10 35
I/O I/O I/O I/O O
GANGED
17
16
I
GND IRQ OSCOFF OVRCUR1 - OVRCUR5
11, 40, 62 50 34 6, 3, 43, 32, 1
3, 12, 30 37 27 9, 7, 32, 25, 6
PWRON1 - PWRON5
4, 46, 41, 33, 49 31
8, 34, 31, 26, 36 24
O
RESET
I
SCL SDA VCC3V VCC5V 1-4
54 53 21, 44 55
39 38 19, 33 40
I I/O
1.3
Terminal Functions (Continued)
TERMINAL NAME PAG NO. 57 N NO. 1 I/O I DESCRIPTION Function port remote wake-up. WAKEUP is an active high input used by the micro-controller to initiate a remote wake-up from a suspended mode. WAKEUP is 5-V tolerant. Crystal 1. XTAL1 is a 48-MHz crystal or oscillator input. Operation at 48-MHz is four times the USB full-speed bit rate of 12 Mbps. Crystal 2. XTAL2 is a 48-MHz crystal output. Operation at 48-MHz is four times the USB full-speed bit rate of 12 Mbps Clock select inputs. CLKSEL0 and CLKSEL1 determine the CLKOUT frequency (See Table 4-2).
WAKEUP
XTAL1 XTAL2 CLKSEL0, CLKSEL1
37 36 63, 64
29 28 4, 5
I O I
1.4
Device-Numbering Convention and Ordering Information
T USB 2 1 40 N Texas Instruments
Universal Serial Bus
Hub Device
Hub Generation Type 1 = Embedded Function with I 2C 0 = Pure Hub Number of Downstream Ports 40 = 4 Downstream USB Ports Package Type PDIP 40 pins TQFP 64 pins
N PAG
1.5
Related Documents Referenced
* * Universal Serial Bus Specification version 1.0 dated January 19, 1996. Inter IC (I2C) Specification
1-5
2 Functional Description
The functional block diagram for the TUSB2140 is shown in Section 2.1. The description for the function blocks follow Section 2.1. For additional information, including USB signaling specifications, packet protocol, and hub functionality, please refer to the Universal Serial Bus Specification version 1.0 dated January 19, 1996.
2.1
Functional Block Diagram
DP0 10 DM0 11
USB Transceiver 27 29, 28 Clock Generator SIE 4, 5 2 24
OSCOFF XTAL1, XTAL2 CLKSEL1, CLKSEL0 CLKOUT RESET 1 35 WAKEUP FUNCSUSP 38 39 37 SDA SCL IRQ
Hub Repeater State Machine and Signal Router
Suspend / Resume Logic and Frame Timer
SIE Interface Logic Port 1 Logic Port 4 Logic Hub / Device Command Decoder
FIFOs
I2C Slave
Function Control Logic
Control Status Registers
Embedded Function
USB Transceiver 22 23 DP4 DM4
USB Transceiver 13 14 DP1 DM1
16 Power Control Logic 15 9, 7, 32, 25, 6 8, 34, 31, 26, 36
GANGED BUSPWR OVRCUR1 - OVRCUR5 PWRON1 - PWRON5
NOTE A: Terminal numbers shown are for the N package
2.2
USB Transceiver
The TUSB2140 provides integrated transceivers for all the USB ports. The transceivers include a differential output driver, a differential input receiver and two single ended inputs. The transceiver for each port connects to the appropriate DP and DM differential signal pair.
2.3
Clock Generator
Utilizing the 48-MHz input signal, the clock generator logic generates the CLKOUT output signal in addition to the various internal clock signals. The TUSB2140 internal clocks consist of the 48-MHz clock, a 12-MHz clock and a USB clock. The USB clock also has a frequency of 12-MHz. The USB clock is the same as the 12-MHz clock when the TUSB2140 is transmitting data and is derived from the data when the TUSB2140 is receiving data.
2-1
2.4
Serial Interface Engine (SIE)
The serial interface engine logic manages the USB packet protocol requirements for the packets being received and transmitted by the TUSB2140. For packets being received, the SIE decodes the packet identifier field (PID) to determine the type of packet being received and ensures the PID is valid. For token packets and data packets being received, the SIE calculates the packet CRC and compares the value to the CRC contained in the packet to verify that the packet was not corrupted during transmission. For token packets and data packets being transmitted, the SIE generates the CRC that is transmitted with the packet. For packets being transmitted, the SIE also generates the synchronization field (SYNC) which is the eight bit field at the beginning of each packet. In addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial conversion of the data packets being transmitted.
2.5
SIE Interface Logic
The SIE interface logic provides the control logic that interfaces the SIE to the hub control logic and the embedded function control logic. One of the major functions of the SIE interface logic is to decode the function address from the SIE to determine if either the hub or embedded function is being addressed. In addition, the endpoint address field is decoded to determine which particular endpoint of the hub or embedded function is being addressed. The SIE interface logic also managers the multiplexing of the byte-wide transmit data signals and other control signals, from the hub control logic and embedded function control logic.
2.6
Hub Command Decoder
The hub command decoder logic manages the overall control of the hub including the decode and execution of host initiated control commands, as well as the status change endpoint. During USB interrupt transfers, the USB host uses the status change endpoint to aquire hub status and port status change information.
2.7
Frame Timer
The frame timer logic generates the End of Frame (EOF) signal which is used mainly to ensure that all downstream traffic is completed during each frame period. In addition, since the frame timer counts 1.0 ms periods, the EOF signal is used by other logic that needs to time events based on multiples of 1.0 ms periods. The hub frame timer logic is locked to the host frame timer logic by the host generated Start of Frame (SOF) packets.
2.8
Suspend/Resume Logic
The suspend/resume logic is used to detect the suspend/resume states and to generate the signals used to control the overall device during the suspend/resume states.
2.9
Hub Repeater
The hub repeater logic manages the connectivity of the root port and the downstream ports on a per-packet basis. The data flow of the USB packets through the TUSB2140 from the root port to the downstream ports and vice-a-versa is totally asynchronous.
2.10 Port Logic
The port logic manages the overall state of a particular downstream port. Each of the downstream ports has unique port logic which controls the connect/disconnect, enable/disable, suspend/resume and reset states of the port.
2.11 Power Control Logic
The power control logic generates the PWRON1 thru PWRON5 output signals based on the GANGED, BUSPWR, and OVRCUR input signals.
2-2
2.12 Embedded Function Control Logic
The Function Control Logic (FCL) manages communication between the local Micro-Controller Unit (MCU) and the Serial Interface Engine (SIE). The local MCU directs the operation of the FCL through the control and status registers. One of the major functions performed by the FCL is to move data to and from the internal FIFOs during the control and interrupt endpoint transfer operations.
2.13 Embedded Function Control/Status Registers
The control and status registers allow the local MCU to control and monitor transfer operations done by the TUSB2140. A separate set of registers is used to control the transmit and receive operations for the control endpoint which is endpoint 0. In addition, a seperate set of registers are provided for the interrupt endpoint transmit operations, which is endpoint 1. Also, an interrupt and interrupt mask register is provided to control the conditions that generate the IRQ output signal.
2.14 Embedded Function FIFOs
The TUSB2140 internal FIFOs provide a buffer between the SIE and the local MCU. There are three 8-byte by 8-bit FIFOs provided. There is a separate transmit and receive FIFO provided for the control endpoint, which is endpoint 0. In addition, there is a transmit FIFO provided for the interrupt endpoint, which is endpoint 1.
2.15 Embedded Function I2C Interface
The I2C Interface logic provides a two-wire serial interface that is used by a local MCU or device needing serial access to the TUSB2140 control/status registers and FIFOs. The interface allows single byte read and writes to the registers and multiple byte read and writes to the FIFOs. Note that the transmit FIFOs are write only and the receive FIFOs are read only from the local MCU side.
2-3
3 Internal Registers
The TUSB2140 provides a set of control and status registers to be used by the local micro-controller unit to control the overall operation of the embedded function. The control and status registers allow the local MCU to control and monitor USB transfers to both the control endpoint and the interrupt endpoint of the embedded function. There is a separate set of registers provided for the control endpoint transmit and receive operations. In addition, there is a separate set of registers provided for the transmit operations of the interrupt endpoint. Also, an interrupt and interrupt mask register is provided to control the conditions that generate the IRQ output signal.
3-1
3.1
Address Map
MSB 7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h TXCLR TXSEQ TXSOW D7 D6 D5 D4 D3 BCNT3 TXSTL STALL EMPT NACK FULL D2 BCNT2 D1 BCNT1 TXFEN ERROR UNDR D0 BCNT0 TXEN ACK OVRR EP1 TX FIFO EP1 TX Byte Count Register EP1 TX Control Register EP1 TX Status Register EP1 TX FIFO Flags Register RXCLR RXSEQ SETUP RXFSW STSGE D7 D6 D5 D4 TXCLR TXSEQ STSGE D7 D6 D5 D4 D3 BCNT3 TXSTL STALL EMPT D3 BCNT3 RXSTL STALL EMPT NACK FULL NACK FULL D2 BCNT2 D2 BCNT2 D1 BCNT1 TXFEN ERROR UNDR D1 BCNT1 RXFEN ERROR UNDR D0 BCNT0 TXEN ACK OVRR D0 BCNT0 RXEN ACK OVRR EP0 TX FIFO EP0 TX Byte Count Register EP0 TX Control Register EP0 TX Status Register EP0 TX FIFO Flags Register EP0 RX FIFO EP0 RX Byte Count Register EP0 RX Control Register EP0 RX Status Register EP0 RX FIFO Flags Register FEN FA6 FA5 6 5 4 FSUSP FSUSP FA4 3 FRST FRST FA3 2 EP1TX EP1TX FA2 1 EP0RX EP0RX FA1 LSB 0 EP0TX EP0TX FA0 Interrupt Register Interrupt Mask Register Function Address Register NAME
3-2
ADDRESS
3.1
Address Map (continued)
MSB 7 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 6 5 4 3 2 1 LSB 0 NAME
ADDRESS
3-3
3.2
Register Functional Description
The following sections contain the functional descriptions for each register and the individual register bits. Note that firmware should write a "0" to reserved bits and ignore any value read from reserved bits.
3.2.1
Interrupt Register
The interrupt register bits are used to indicate when an interrupt condition is pending. If one or more of the interrupt bits are set, the TUSB2140 interrupt output signal (IRQ) will be asserted until the interrupt condition(s) is cleared. One or more of the interrupt bits can be masked by setting the corresponding bit in the interrupt mask register. If the interrupt mask bit is set, the corresponding interrupt bit will still be set when an interrupt condition occurs. However, the IRQ output signal will not be asserted. This feature is provided for systems that detect pending interrupt conditions with a polling scheme rather than by monitoring the IRQ output signal.
7 - - - FSUSP FRST EP1TX EP0RX 0 EP0TX
BIT 7:5 4
MNEMONIC - FSUSP
NAME Reserved Function suspend Reserved for future use.
DESCRIPTION The function suspend interrupt bit is set in response to the hub suspend logic detecting a global suspend condition or a selective suspend condition for the embedded function. To enable the TUSB2140 to enter a low-power suspend state which includes disabling the clocks, this bit must be cleared by the local MCU. This bit is cleared by writing a "1" to this register. This bit is read/write and is cleared by power-on reset. The function reset interrupt bit is set in response to the host initiating a port reset on the function port. When a function reset occurs, all of the Function Interface logic within the TUSB2140 will be reset except the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN), the function reset interrupt bit (FRST) and all of the interrupt mask bits. This bit is cleared by writing a "1" to this register. This bit is read/write and is cleared by power-on reset. The endpoint 1 transmit interrupt bit is set in response to the endpoint 1 transmit acknowledge status bit (ACK), the endpoint 1 transmit FIFO over-run flag bit (OVRR), or the endpoint 1 transmit FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset. The endpoint 0 receive interrupt bit is set in response to the endpoint 0 receive acknowledge status bit (ACK), the endpoint 0 receive FIFO over-run flag bit (OVRR), or the endpoint 0 receive FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset. The endpoint 0 transmit interrupt bit is set in response to the endpoint 0 transmit acknowledge status bit (ACK), the endpoint 0 transmit FIFO over-run flag bit (OVRR), or the endpoint 0 transmit FIFO under-run flag bit (UNDR) being set. This bit is cleared by clearing the corresponding status or FIFO flag bit that caused the interrupt. This bit is read-only and is cleared by power-on reset.
3
FRST
Function reset
2
EP1TX
Endpoint 1 transmit interrupt
1
EP0RX
Endpoint 0 receive interrupt
0
EP0TX
Endpoint 0 transmit interrupt
3-4
3.2.2
7 -
Interrupt Mask Register
0 - - FSUSP FRST EP1TX EP0RX EP0TX
The interrupt mask register bits are used to mask the corresponding interrupt bits.
BIT 7:4 4
MNEMONIC - FSUSP Reserved
NAME Function suspend interrupt mask
DESCRIPTION Reserved for future use. The function suspend interrupt mask bit is set to enable the function suspend interrupt bit. This bit is read/write and is cleared by power-on reset. The function reset interrupt mask bit is set to enable the function reset interrupt bit. This bit is read/write and is cleared by power-on reset. The endpoint 1 transmit interrupt mask bit is set to enable the endpoint 1 transmit interrupt bit. This bit is read/write and is cleared by power-on reset. The endpoint 0 receive interrupt mask bit is set to enable the endpoint 0 receive interrupt bit. This bit is read/write and is cleared by power-on reset. The endpoint 0 transmit interrupt mask bit is set to enable the endpoint 0 transmit interrupt bit. This bit is read/write and is cleared by power-on reset.
3
FRST
Function reset interrupt mask
2
EP1TX
Endpoint 1 transmit interrupt mask
1
EP0RX
Endpoint 0 receive interrupt mask
0
EP0TX
Endpoint 0 transmit interrupt mask
3.2.3
Function Address Register
The function address register contains the current setting of the USB device address assigned to the function. During enumeration of the function, the function address is loaded into this register automatically by the TUSB2140 Function Control Logic when a Set Address request is received from the USB host. This register is read only and is used only for diagnostic purposes.
7 FEN FA6 FA5 FA4 FA3 FA2 FA1 0 FA0
BIT 7
MNEMONIC FEN
NAME Function enabled
DESCRIPTION The function enabled bit is set when the embedded function port has been enabled by the host with a set port feature request. This bit is read-only and is cleared by power-on reset. The function register value is set to the current device address assigned to the function. These bits are read-only and are cleared by power-on reset.
6:0
FA(6:0)
Function address
3-5
3.2.4
7
Endpoint 0 Transmit FIFO
0 D7 D6 D5 D4 D3 D2 D1 D0
BIT 7:0
MNEMONIC D(7:0)
NAME Transmit FIFO data
DESCRIPTION Endpoint 0 transmit FIFO data is written to the transmit FIFO on a byte-to-byte basis. These bits are write-only.
3.2.5
7 -
Endpoint 0 Transmit Byte Count Register
0 - - - BCNT3 BCNT2 BCNT1 BCNT0
BIT 7:4 3:0
MNEMONIC - BCNT(3:0)
NAME Reserved Transmit byte count Reserved for future use.
DESCRIPTION The transmit byte count register should be loaded with the number of bytes to be transmitted. The byte count should be the number of bytes in the data packet that was loaded into the transmit FIFO. When the local MCU writes to the byte count register, the EP0 transmit FIFO enable bit (TXFEN) will automatically be set. Also, the byte count register does not decrement as data is transmitted. These bits are read/write and are cleared by power-on reset.
3-6
3.2.6
Endpoint 0 Transmit Control Register
The transmit control register is used to store bits which control various functions and operating modes of the Function Interface Logic within the TUSB2140.
7 TXCLR - - - TXSTL - TXFEN 0 TXEN
BIT 7
MNEMONIC TXCLR
NAME Transmit clear
DESCRIPTION The transmit clear bit is set to reset the transmit FIFO pointers and flags. This bit should be set in response to a transmit FIFO over-run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. Reserved for future use. Reserved for future use. Reserved for future use. The transmit stall bit is set to enable a STALL handshake to be returned in response to the next valid In Transaction. This bit is automatically cleared if a new Setup Stage Transaction is successfully received. This bit is read/write and is cleared by power-on reset. Reserved for future use. The transmit FIFO enable bit is set to enable the transmission of data in the transmit FIFO when the next valid In Transaction occurs. This bit is automatically set when the local MCU writes to the EP0 transmit byte count register and is automatically cleared when the EP0 transmit acknowledge status bit (ACK) is set. This bit is also automatically cleared if a new Setup Stage Transaction is successfully received or the EP0 transmit clear bit (TXCLR) is set. If the transmit enable bit is not set, the device returns a NACK handshake. If the transmit stall control bit (TXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit is read/write and is cleared by power-on reset. The transmit enable bit is set to enable the transmit endpoint. For endpoint 0, the Control Endpoint, both a receive and transmit endpoint are required. Therefore, the transmit enable and receive enable bits must both be set before the device will be enumerated. If either of these bits are not set, the function port will remain in the disconnected state. This bit is read/write and is cleared by power-on reset.
6 5 4 3
- - - TXSTL
Reserved Reserved Reserved Transmit stall
2 1
- TXFEN
Reserved Transmit FIFO enable
0
TXEN
Transmit enable
3-7
3.2.7
Endpoint 0 Transmit Status Register
The transmit status register is used to store bits which report status information about the operating conditions of the Function Control Logic within the TUSB2140.
7 TXSEQ - - STSGE STALL NACK ERROR 0 ACK
BIT 7
MNEMONIC TXSEQ
NAME Transmit sequence
DESCRIPTION The transmit sequence bit value determines the data packet PID to be used for the next data packet to be transmitted for the next In Data Stage Transaction. This bit is automatically set at the end of a successful Setup Stage Transaction and is automatically toggled at the end of each successful In Data Stage Transaction. If this bit is a '0', a DATA0 PID is sent in the data packet. If this bit is a'1', a DATA1 PID is sent in the data packet. This bit is read only and is cleared by power-on reset. Reserved for future use. Reserved for future use. The in status stage bit is set when the Function Control Logic detects the Status Stage Transaction of a Control Transfer. This bit will be automatically cleared at the beginning of the next Setup Stage Transaction. This bit is read-only and is cleared by power-on reset. The stall status bit is set at the end of an In Transaction if a STALL handshake packet is returned to the host instead of a data packet. The Function Control Logic will automatically return a STALL handshake to the host if a valid In Transaction is received and the transmit stall control bit is set. This stall status bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The no acknowledge status bit is set at the end of an In Transaction if a NACK handshake packet is returned to the host instead of a data packet. The Function Control Logic will automatically return a NACK handshake to the host if a valid In Transaction is received and there is not a data packet in the transmit FIFO ready to be transmitted. This bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The error status bit is set at the end of an In Transaction if a timeout, bit-stuff, CRC, force transmit or other errors occur. This bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The acknowledge status bit is set at the end of an In Transaction if the data packet in the transmit FIFO was sent successfully and an acknowledge handshake was received from the host. When this bit is set, the endpoint 0 transmit interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit will be automatically cleared at the beginning of the next Setup Stage Transaction. This bit is read/write and is cleared by power-on reset.
6 5 4
- - STSGE
Reserved Reserved In status stage
3
STALL
Stall
2
NACK
No acknowledge
1
ERROR
Error
0
ACK
Acknowledge
3-8
3.2.8
Endpoint 0 Transmit FIFO Flags Register
The transmit FIFO flags register is used to store bits which report status information about the transmit FIFO operating condition.
7 - - - - EMPT FULL UNDR 0 OVRR
BIT 7:4 3
MNEMONIC - EMPT
NAME Reserved Transmit FIFO empty Transmit FIFO full Transmit FIFO under-run Reserved for future use.
DESCRIPTION The transmit FIFO empty flag is set when the transmit FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. The transmit FIFO full flag is set when the transmit FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. The transmit FIFO under-run flag is set when the transmit FIFO is empty and the Function Control Logic attempts to read another byte from the FIFO. This will happen if the number of bytes actually written to the transmit FIFO is less than the value loaded into the transmit byte count register. When this bit is set, the endpoint 0 transmit interrupt bit is also set. To clear the FIFO under-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. The transmit FIFO over-run flag is set when the transmit FIFO is full and the local MCU attempts to write another byte to the FIFO. When this bit is set, the endpoint 0 transmit interrupt bit is also set. To clear the FIFO over-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset.
2
FULL
1
UNDR
0
OVRR
Transmit FIFO over-run
3.2.9
7
Endpoint 0 Receive FIFO
0 D7 D6 D5 D4 D3 D2 D1 D0
BIT 7:0
MNEMONIC D(7:0)
NAME Receive FIFO data
DESCRIPTION Endpoint 0 receive FIFO data is read from the receive FIFO on a byte-to-byte basis. These bits are read-only.
3.2.10
7 -
Endpoint 0 Receive Byte Count Register
0 - - - BCNT3 BCNT2 BCNT1 BCNT0
BIT 7:4 3:0
MNEMONIC - BCNT(3:0)
NAME Reserved Receive byte count Reserved for future use.
DESCRIPTION The receive byte count register is loaded with the number of bytes in the data packet received into the endpoint 0 receive FIFO for a valid Setup Stage transaction or OUT Transaction. The receive FIFO byte count register does not decrement as data is read from the FIFO. These bits are read-only and are cleared by power-on reset.
3-9
3.2.11
Endpoint 0 Receive Control Register
The receive control register is used to store bits which control various functions and operating modes of the Function Interface Logic within the TUSB2140 device.
7 RXCLR - - - RXSTL - RXFEN 0 RXEN
BIT 7
MNEMONIC RXCLR
NAME Receive clear
DESCRIPTION The receive clear bit is set to reset the receive FIFO pointers and flags. This bit should be set in response to a receive FIFO over-run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. Reserved for future use. Reserved for future use. Reserved for future use. The receive stall bit is set to enable a STALL handshake to be returned in response to the next valid OUT Transaction. This bit does not effect a Setup Stage Transaction. The Setup Stage Transaction must always be accepted, unless there is a data packet error or a time out error, so that a Clear Feature Endpoint Stall request can be received from the host. This bit is automatically cleared if a new Setup Stage Transaction is successfully received. This bit is read/write and is cleared by power-on reset. Reserved for future use. The receive FIFO enable bit is set to enable the reception of data into the receive FIFO when the next valid OUT Transaction occurs. This bit is automatically cleared when the local EP0 receive acknowledge status bit (ACK) is set. This bit is also automatically cleared if a new Setup Stage Transaction is successfully received or the EP0 receive clear bit (RXCLR) is set. If the receive enable bit is not set, the device returns a NACK handshake. If the receive stall control bit (RXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit does not effect a Setup Stage Transaction. The Setup Stage Transaction must always be accepted, unless there is a data packet error or a time-out error. This bit is read/write and is cleared by power-on reset. The receive enable bit is set to enable the receive endpoint. For endpoint 0, the Control Endpoint, both a receive and transmit endpoint are required. Therefore, the transmit enable and receive enable bits must both be set before the device will be enumerated. If either of these bits are not set, the function port will remain in the disconnected state. This bit is read/write and is cleared by power-on reset.
6 5 4 3
- - - RXSTL
Reserved Reserved Reserved Receive stall
2 1
- RXFEN
Reserved Receive FIFO enable
0
RXEN
Receive enable
3-10
3.2.12
Endpoint 0 Receive Status Register
The receive status register is used to store bits which report status information about the operating conditions of the Function Control Logic within the TUSB2140 device.
7 RXSEQ SETUP RXFSW STSGE STALL NACK ERROR 0 ACK
BIT
7
MNEMONIC
RXSEQ
NAME
Receive sequence
DESCRIPTION
The receive sequence bit is toggled by the Function Control Logic at the end of an Out Data Stage Transaction if a valid data packet is received and the data packet PID matches the expected PID. The receive sequence bit is initialized to a '1' at the end of a successful Setup Stage Transaction. This bit is read-only and is cleared by power-on reset. The setup stage transaction bit is set at the end of a successful Setup Stage Transaction to indicate that the data packet in the receive FIFO is a Setup Stage Transaction data packet. This bit is cleared by writing a "1" to this register. To read the receive FIFO, the local MCU must first clear the Setup Stage Transaction bit (SETUP). This bit is read/write and is cleared by power-on reset. The receive FIFO Setup Stage Transaction data packet write bit is set at the beginning of a Setup Stage Transaction and is cleared at the end of Setup Stage Transaction. This bit indicates that the receive FIFO is being over-written with data from the Setup Stage Transaction data packet. This bit, in conjunction with the setup stage bit (SETUP), is used to indicate when a new Setup Stage Transaction has occurred and data in the receive FIFO from a previous Out Data Stage Transaction may have been over-written. This bit is read-only and is cleared by power-on reset. The in status stage bit is set when the Function Control Logic detects the Status Stage Transaction of a Control Transfer. This bit will be automatically cleared at the beginning of the next Setup Stage Transaction. This bit is read-only and is cleared by power-on reset. The stall status bit is set at the end of an Out Transaction if a STALL handshake packet is returned to the host. The Function Control Logic will automatically return a STALL handshake to the host if a valid Out Transaction is received and the receive stall control bit is set. This stall status bit will automatically be updated at the end of the next valid Out Transaction. This bit is read-only and is cleared by power-on reset. The no acknowledge status bit is set at the end of an Out Transaction if a NACK handshake packet is returned to the host. The Function Control Logic will automatically return a NACK handshake to the host if a valid Out Transaction is received and the receive FIFO enable bit has not been set. This bit will be automatically updated at the end of the next valid Out Transaction. This bit is read-only and is cleared by power-on reset. The error status bit is set at the end of an Out Transaction if a timeout, bit-stuff, CRC, force receive or other errors occur. This bit will be automatically updated at the end of the next valid Out Transaction. This bit is read-only and is cleared by power-on reset. The acknowledge status bit is set at the end of an Out Transaction if the data packet was received successfully and an acknowledge handshake was sent to the host. When this bit is set, the endpoint 0 receive interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit will be automatically cleared at the beginning of the next Setup Stage Transaction. This bit is read/write and is cleared by power-on reset.
6
SETUP
Setup stage transaction
5
RXFSW
Receive FIFO setup stage transaction data packet write
4
STSGE
In status stage
3
STALL
Stall
2
NACK
No acknowledge
1
ERROR
Error
0
ACK
Acknowledge
3-11
3.2.13
Endpoint 0 Receive FIFO Flags Register
The receive FIFO flags register is used to store bits which report status information about the receive FIFO operating condition.
7 - - - - EMPT FULL UNDR 0 OVRR
BIT 7:4 3
MNEMONIC - EMPT
NAME Reserved Receive FIFO empty Receive FIFO full Receive FIFO under-run Reserved for future use.
DESCRIPTION The receive FIFO empty flag is set when the receive FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. The receive FIFO full flag is set when the receive FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. The receive FIFO under-run flag is set when the receive FIFO is empty and when the local MCU attempts to read a byte from the FIFO. When this bit is set, the endpoint 0 receive interrupt bit is also set. To clear the FIFO under-run condition, the receive FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 receive interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. The receive FIFO over-run flag is set when the receive FIFO is full and the Function Control Logic attempts to write another byte to the FIFO. When this bit is set, the endpoint 0 receive interrupt bit is also set. To clear the FIFO over-run condition, the receive FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 0 receive interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset.
2
FULL
1
UNDR
0
OVRR
Receive FIFO over-run
3.2.14
7
Endpoint 1 Transmit FIFO
0 D7 D6 D5 D4 D3 D2 D1 D0
BIT 7:0
MNEMONIC D(7:0)
NAME Transmit FIFO data
DESCRIPTION Endpoint 1 transmit FIFO data is written to the transmit FIFO on a byte-to-byte basis. These bits are write-only.
3.2.15
7 -
Endpoint 1 Transmit Byte Count Register
0 - - - BCNT3 BCNT2 BCNT1 BCNT0
BIT 7:4 3:0
MNEMONIC - BCNT(3:0)
NAME Reserved Transmit byte count Reserved for future use.
DESCRIPTION The transmit byte count register should be loaded with the number of bytes to be transmitted. The byte count should be the number of bytes in the data packet that was loaded into the transmit FIFO. When the local MCU writes to the byte count register, the EP1 transmit FIFO enable bit (TXFEN) will automatically be set. Also, the byte count register does not decrement as data is transmitted. These bits are read/write and are cleared by power-on reset.
3-12
3.2.16
Endpoint 1 Transmit Control Register
The transmit control register is used to store bits which control various functions and operating modes of the Function Interface Logic within the TUSB2140 device.
7 TXCLR TXSOW - - TXSTL - TXFEN 0 TXEN
BIT 7
MNEMONIC TXCLR
NAME Transmit clear
DESCRIPTION The transmit clear bit is set to reset the transmit FIFO pointers and flags. This bit should be set in response to a transmit FIFO over-run or under-run condition. After the FIFO pointers are reset, this bit will be automatically cleared. In addition, the FIFO empty flag will be set and the other FIFO flags will be cleared upon completion of the FIFO reset. This bit is read/write and is cleared by power-on reset. The transmit sequence bit over-write bit is set to enable the local MCU to write to the transmit sequence bit (TXSEQ). See the EP1TX Transmit Status Register. This bit is read/write and is cleared by power-on reset. Reserved for future use. Reserved for future use. The transmit stall bit is set to enable a STALL handshake to be returned in response to the next valid In Transaction. This bit is read/write and is cleared by power-on reset. Reserved for future use. The transmit FIFO enable bit is set to enable the transmission of data in the transmit FIFO when the next valid In Transaction occurs. This bit is automatically set when the local MCU writes to the EP1 transmit byte count register and is automatically cleared when the EP1 transmit acknowledge status bit (ACK) is set. This bit is also automatically cleared if the EP1 transmit clear bit (TXCLR) is set. If the transmit enable bit is not set, the device returns a NACK handshake. If the transmit stall control bit (TXSTL) is set, a STALL handshake is returned instead of a NACK handshake. This bit is read/write and is cleared by power-on reset. The transmit enable bit is set to enable the transmit endpoint. This bit is read/write and is cleared by power-on reset.
6
TXSOW
Transmit sequence bit over-write
5 4 3 TXSTL
- -
Reserved Reserved Transmit stall
2 1 TXFEN
-
Reserved Transmit FIFO enable
0
TXEN
Transmit enable
3-13
3.2.17
Endpoint 1 Transmit Status Register
The transmit status register is used to store bits which report status information about the operating conditions of the Function Control Logic within the TUSB2140 device.
7 TXSEQ - - - STALL NACK ERROR 0 ACK
BIT 7
MNEMONIC TXSEQ
NAME Transmit sequence
DESCRIPTION The transmit sequence bit value determines the data packet PID to be used for the next data packet to be transmitted during the next In Data Stage Transaction. This bit is automatically toggled at the end of a successful In Transaction. If this bit is a '0', a DATA0 PID is sent in the data packet. If this bit is a '1', a DATA1 PID is sent in the data packet. The local MCU can write to this bit if the transmit sequence bit over-write (TXSOW) is set. This bit is read/write and is cleared by power-on reset. Reserved for future use. Reserved for future use. Reserved for future use. The stall status bit is set at the end of an In Transaction if a STALL handshake packet is returned to the host instead of a data packet. The Function Control Logic will automatically return a STALL handshake to the host if a valid In Transaction is received and the transmit stall control bit is set. This stall status bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The no acknowledge status bit is set at the end of an In Transaction if a NACK handshake packet is returned to the host instead of a data packet. The Function Control Logic will automatically return a NACK handshake to the host if a valid In Transaction is received and there is not a data packet in the transmit FIFO ready to be transmitted. This bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The error status bit is set at the end of an In Transaction if a timeout, bit-stuff, CRC, force transmit or other errors occur. This bit will be automatically updated at the end of the next valid In Transaction. This bit is read-only and is cleared by power-on reset. The acknowledge status bit is set at the end of an In Transaction if the data packet in the transmit FIFO was sent successfully and an acknowledge handshake was received from the host. When this bit is set, the endpoint 1 transmit interrupt bit is also set. The acknowledge status bit should be cleared by the local MCU in order to clear the interrupt condition. This bit is read/write and is cleared by power-on reset.
6 5 4 3 STALL
- - -
Reserved Reserved Reserved Stall
2
NACK
No acknowledge
1
ERROR
Error
0
ACK
Acknowledge
3-14
3.2.18
Endpoint 1 Transmit FIFO Flags Register
The transmit FIFO flags register is used to store bits which report status information about the transmit FIFO operating condition.
7 - - - - EMPT FULL UNDR 0 OVRR
BIT 7:4 3
MNEMONIC - EMPT Reserved
NAME Transmit FIFO empty
DESCRIPTION Reserved for future use. The transmit FIFO empty flag is set when the transmit FIFO is empty. This bit is cleared when the FIFO is no longer empty. This bit is read-only and is set by power-on reset. The transmit FIFO full flag is set when the transmit FIFO is full. This bit is cleared when the FIFO is no longer full. This bit is read-only and is cleared by power-on reset. The transmit FIFO under-run flag is set when the transmit FIFO is empty and the Function Control Logic attempts to read another byte from the FIFO. This will happen if the number of bytes actually written to the transmit FIFO is less than the value loaded into the transmit byte count register. When this bit is set, the endpoint 1 transmit interrupt bit is also set. To clear the FIFO under-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 1 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset. The transmit FIFO over-run flag is set when the transmit FIFO is full and the local MCU attempts to write another byte to the FIFO. When this bit is set, the endpoint 1 transmit interrupt bit is also set. To clear the FIFO over-run condition, the transmit FIFO clear control bit should be set. After the FIFO has been cleared, this bit and the endpoint 1 transmit interrupt bit will be automatically cleared. This bit is read-only and is cleared by power-on reset.
2
FULL
Transmit FIFO full
1
UNDR
Transmit FIFO under-run
0
OVRR
Transmit FIFO over-run
3-15
4 Device Operation
The operation of the TUSB2140 is explained in the following sections. For additional information on USB, please refer to the Universal Serial Bus Specification version 1.0 dated January 19, 1996. Chapter 11 of the specification contains very detailed information on the hub operations.
4.1
Device Initialization
When a power-on reset is applied to the TUSB2140, the device is automatically configured as a stand-alone hub with five downstream ports. In addition, all of the registers associated with the embedded function are initialized as defined in Section 3.2, Register Functional Descriptions. Both the hub and the embedded function power-up with a default function address of zero, and the embedded function is disconnected. To connect the embedded function to the downstream port 5 of the hub, the MCU must set the receive enable bit (RXEN) to 1 and the transmit enable bit (TXEN) to a 1.
4.2
Hub
The hub within the TUSB2140 supports a maximum of 4 external downstream ports and the embedded function. If the embedded function is not connected to downstream port 5, then the hub functions as a four port stand-alone device. The hub is a separate logical device and contains a seperate control endpoint and interrupt endpoint from the embedded function. The hub automatically handles all USB standard device commands addressed to the hub function address. Because the hub is a state machine approach instead of being based on a micro-controller, the only software required to support the hub function is the generic USB driver, on the host side, that supports the hub-class.
4.3
Embedded Function
The embedded function within the TUSB2140 supports USB control and interrupt data transfers by providing FIFOs, control/status registers, and the USB bus interface to be used by a local MCU. The embedded function is a separate logical device, and therefore, the embedded function requires a unique function address. To enumerate the embedded function, the TUSB2140 hub must first be enumerated and configured. In additon, the embedded function must be connected to downstream port 5 of the hub, which is accomplished by setting the embedded function endpoint 0 receive enable bit (RXEN) and transmit enable bit (TXEN) to a 1.
4.3.1
Interrupt Handler
The interrupt handler monitors the various conditions that can cause interrupts and asserts the appropriate interrupt bit when an interrupt condition is pending. If one or more of the interrupt bits are set, the TUSB2140 interrupt output signal (IRQ) will be asserted until the interrupt condition(s) is cleared. The interrupt bits are enabled by setting the corresponding bit in the interrupt mask register. If the interrupt mask bit is cleared, the corresponding interrupt bit will still be set when an interrupt condition occurs. However, the IRQ output signal will not be asserted. This feature is provided for systems that detect pending interrupt conditions with a polling scheme rather than monitoring the IRQ output signal.
4.3.2
USB Reset
To reset the embedded function, the host initiates a port reset on the function port which sets the function reset interrupt bit. When a function reset occurs, all of the function interface logic within the TUSB2140 will be reset except the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN), the function reset interrupt bit (FRST) and all of the interrupt mask bits. When a USB reset occurs, the local MCU should respond by setting the default configuration then clearing the FRST interrupt bit.
4-1
4.3.3
Enumeration
After enumeration of the hub and the connection of the embedded function, the host should enable, reset, and set the function address of the embedded function. To enable the port, the host should first power-on the port, which should result in the PWRON5 output signal being asserted. When the embedded function has been enabled, the function enabled bit (FEN), bit 7 of the function address register, will also be set. When the host initiates the port reset for the embedded function, the function reset bit (FRST), bit 3 of the interrupt register, will be set. If the corresponding mask bit is a 1, then the IRQ output signal will be asserted. The local MCU should respond to the FRST by setting the default configuration for the device and then clearing the FRST interrupt bit. To set the function address, the host should initiate the set address command. The embedded function will automatically decode the set address command and set the function address within the embedded function to the address requested by the host.
4.3.4
Control Transfers
Control transfers to the embedded function require multiple transactions which use both the embedded function endpoint 0 receive and transmit endpoints. The three types of control transfers are Control Write, Control Write with No-Data Stage and Control Read. All USB commands, except the set address command, are passed by the embedded function logic to the local MCU which does the decoding. The set address command is handled completely by the embedded function. After the set address command is complete, the function address can be read by the local MCU from the function address register (see Firmware Development Flow Diagram in Appendix A).
4.3.4.1
Control Read Transfers
A Control Read Transfer is used by the host to read data from the embedded function. A Control Read Transfer requires a Setup Stage Transaction, at least one In Data Stage Transaction, and an Out Status Stage Transaction. As a result, the Setup Stage Transaction and the Out Status Stage Transaction use the endpoint 0 receive endpoint and the In Data Stage Transactions use the endpoint 0 transmit endpoint.
4.3.4.2
Control Write Transfers
A Control Write Transfer is used by the host to write data to the embedded function. A Control Write Transfer requires a Setup Stage Transaction, at least one Out Data Stage Transaction, and an In Status Stage Transaction. As a result, the Setup Stage Transaction and the Out Data Stage Transactions use the endpoint 0 receive endpoint and the In Status Stage Transaction uses the endpoint 0 transmit endpoint.
4.3.4.3
Control Write Transfers with No-Data Stages
A Control Write Transfer with No-Data Stages is used by the host to write data to the embedded function. A Control Write Transfer with No-Data Stages requires a Setup Stage Transaction, no Data Stage Transactions, and an In Status Stage Transaction. As a result, the Setup Stage Transaction uses the endpoint 0 receive endpoint and the In Status Stage Transaction uses the endpoint 0 transmit endpoint. The data written to the function by the host is contained in the Setup Stage Transaction data packet and is limited to two bytes.
4.3.5
Interrupt Transfers
The transfer of interrupt type data is accomplished by the TUSB2140 using the interrupt endpoint, which is transmit endpoint 1. In addition to the endpoint 1 transmit FIFO, the operation of transmit endpoint 1 requires the use of 4 registers, which are the endpoint 1 TX byte count register, TX control register, TX status register and TX FIFO flags register. The steps to be followed to transfer interrupt data are as follows: 1. The local MCU loads the data packet to be transmitted into the endpoint 1 transmit FIFO. The endpoint 1 transmit FIFO is 8 bytes deep, and therefore, the maximum data packet size is 8 bytes. If a FIFO over-run occurs while loading the data packet, the MCU sets the FIFO clear bit (TXCLR) to clear the FIFO. After the over-run condition is cleared, the MCU loads the data packet into the
4-2
FIFO again. The FIFO over-run condition results in the FIFO over-run bit (OVRR) being set and the endpoint 1 transmit interrupt bit (EP1TX) being set. The FIFO clear bit (TXCLR) is cleared automatically after the FIFO clear is complete. The MCU should poll the FIFO clear bit to determine when the FIFO clear is complete. After the FIFO clear is complete, the MCU should clear the FIFO over-run bit (OVRR), which automatically clears the endpoint 1 transmit interrupt bit (EP1TX). 2. Next, the local MCU loads the data packet byte count into the endpoint 1 transmit byte count register. Writing the byte count automatically sets the transmit FIFO enable bit (TXFEN) to enable the FCL to send the data packet when the next endpoint 1 In Transaction occurs. At the end of the In Transaction, if the data packet was sent successfully and an acknowledge (ACK) handshake was received from the host, the acknowledge status bit (ACK) and the endpoint 1 transmit interrupt bit (EP1TX) are set. First the interrupt register is read to determine that an endpoint 1 transmit interrupt (EP1TX) has occurred. Then the status register is read to determine that the source of the interrupt was the acknowledge bit (ACK). Note that the transmit FIFO enable bit (TXFEN) is automatically cleared when the ACK bit is set. Finally, the MCU clears the acknowledge status bit (ACK), which automatically clears the interrupt bit (EP1TX).
3.
4.3.6
Suspend and Remote Wake-up
The TUSB2140 embedded function supports both suspend and remote wake-up. The ability to support remote wake-up should be reported by the function to the host in the configuration descriptor for the embedded function. In addition, the host should be able to enable and disable the remote wake-up feature using the Set Feature Device and Clear Feature Device commands. The TUSB2140 will assert the function suspend interrupt bit (FSUSP) if either a global suspend of the entire bus or a selective suspend of the embedded function is detected by the hub. In order for the TUSB2140 to enter a low power suspend state, the local MCU must clear the FSUSP bit. In the low power suspend state, the power control logic within the TUSB2140 will assert the function suspend output signal, FUNCSUSP. In addition, to reduce power consumption to a minimum, the TUSB2140 will disable all clocks including the CLKOUT output signal. If the embedded function is not connected to the hub, the power control logic will enter the low power suspend state and will disable the clocks without interaction from the local MCU. The FUNCSUSP output signal will still be asserted when the low power suspend state is active to indicate a bus suspend. The remote wake-up function allows the local MCU or other logic to initiate a wake-up telling the host to resume USB operations. To initiate the remote wake-up, the active high WAKEUP input signal to the TUSB2140 should be asserted as shown in Figure 5-12.
4.3.7
I2C Interface
The TUSB2140 uses a bi-directional two-wire serial interface to access the internal registers and FIFOs used for the embedded function operations. This serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100 kbps and 400 kbps data transfer rates. The TUSB2140 is a slave only device on the bus with an assigned I2C device address as shown below in Table 4-1. Table 4-1. I2C Device Address
A6 0 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 R/W
4.3.7.1
Data Transfers
The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the TUSB2140 is a slave only device, and therefore, the SCL signal is an input only. The SDA signal is a bi-directional signal that uses an open-drain output to allow the TUSB2140 to be wire-ORed with other devices that use open-drain or open-collector outputs.
4-3
All read and write data transfers on the serial bus are initiated by a master device. The master device is also responsible for generating the clock signal used by the TUSB2140 for all data transfers. The data is transferred on the bus serially one bit at a time. However, the protocol requires that the address and data information be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 5-5. As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can only change states while the SCL signal is low. The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 5-6. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also, as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high. When the TUSB2140 is the device receiving address or data information, the TUSB2140 will acknowledge each byte received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the master device must stop driving the SDA signal. If the TUSB2140 is unable to receive a byte, the SDA signal will not be driven low and should be pulled high external to the TUSB2140 device. A high during the SCL period indicates a not-acknowledge to the master device. After receiving a not-acknowledge from the TUSB2140, the master device should generate a stop condition. The output acknowledge timing is shown in Figure 5-7. Read and write data transfers to the TUSB2140 internal registers are done using single byte data transfers. However, read and write data transfers to the TUSB2140 internal FIFOs can be done with either single or multiple byte data transfers.
4.3.7.2
Single Byte Write
As shown in Figure 5-8, a single byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit (refer to Table 4-1). The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit should be a 0. After receiving the correct I2C device address and the read/write bit, the TUSB2140 should respond with an acknowledge bit. Next, the master device should transmit the address byte corresponding to the TUSB2140 internal register or FIFO being accessed (see Section 3.1). After receiving the address byte, the TUSB2140 should again respond with an acknowledge bit. Next, the master device should transmit the data byte to be written to the register or FIFO being addressed. After receiving the data byte, the TUSB2140 should again respond with an acknowledge bit. Finally, the master device should transmit a stop condition to complete the single byte data write transfer.
4.3.7.3
Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to the TUSB2140 as shown in Figure 5-9. After receiving each data byte, the TUSB2140 should respond with an acknowledge bit.
4-4
4.3.7.4
Single Byte Read
As shown in Figure 5-10, a single byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit (refer to Table 4-1). For the data read transfer, both a write and a read are actually done. Initially, a write is done to transfer the address byte of the internal register or FIFO to be read. As a result, the read/write bit should be a 0. After receiving the I2C device address and the read/write bit the TUSB2140 should respond with an acknowledge bit. Also, after sending the address byte, the master device should transmit another start condition followed by the I2C device address and the read/write bit again. This time the read/write bit should be a 1 indicating a read transfer. After receiving the I2C device address and the read/write bit the TUSB2140 should again respond with an acknowledge bit. Next, the TUSB2140 should transmit the data byte from the register or FIFO being addressed. After receiving the data byte, the master device should transmit a not-acknowledge followed by a stop condition to complete the single byte data read transfer.
4.3.7.5
Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TUSB2140 to the master device as shown in Figure 5-11. Except for the last data byte, the master device should respond with an acknowledge bit after receiving each data byte.
4.4
Over-current Detection and Power Switching
The TUSB2140 provides an active low over-current input signal for each downstream port including the embedded function. External circuitry is required to detect an over-current condition for each port and to assert the appropriate over-current input. When an over-current input is asserted using individual port power management, the TUSB2140 will de-assert the power-on output signal corresponding to the over-current input. The external circuitry should remove power from the appropriate downstream port when the power-on output is de-asserted. In addition, the over-current condition will be reported to the host by the TUSB2140 hub controller. If the ganged port power management mode is used, the GANGED input to the TUSB2140 is set to a 1, then the power-on outputs are all de-asserted at the same time, when any of the over-current inputs are asserted.
4.5
Clock Output Generation
The TUSB2140 generates a clock output signal, CLKOUT, that is synchronous to the 48 MHz crystal input. The CLKOUT signal frequency is selected using the two clock select inputs, CLKSEL0 and CLKSEL1. As shown in Table 4-2, the CLKOUT frequency can be selected to be 12 MHz, 8 MHz, 6 MHz or 4 MHz. Table 4-2. Clock Output Signal Frequency
CLKSEL1 0 0 1 1 CLKSEL0 0 1 0 1 CLKOUT FREQUENCY 12 Mhz 8 Mhz 6 Mhz 4 Mhz
4.6
Power Supply Sequencing
Turning power supplies on and off with a mixed 5-V/3.3-V system is an important consideration. To avoid possible damage to the TUSB2140 device, proper power sequencing is required. The basic turn on requirement is that the 5-V and 3.3-V power supplies should start ramping from 0 V and reach 95 percent of the final voltage values within 25 ms of each other. The turn-off requirement is that the 5-V and 3.3-V power supplies should start ramping from the steady-state voltage and reach 5 percent of these values with 25 ms of each other. In addition, the difference between the two voltages should never exceed 3.6 V while turning on or off. Normally, in a mixed voltage system, the 3.3-V supply is generated from a voltage regulator running from the 5-V supply. A voltage regulator, such as TI's TPS7133, can be used to meet these power sequencing requirements.
4-5
5 Electrical Specifications
5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)
Supply voltage range, VCC3V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 3.8 V Supply voltage range, VCC5V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Input voltage range, VI: (3.3 VCC3V) . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC3V + 0.5 V (5 VCC5V) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC5V + 0.5 V Output voltage range, VO (3.3 VCC3V) . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC3V + 0.5 V Input clamp current, IIK, (VI < 0 V or VI > VCC3V) . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK, (VO < 0 V or VO > VCC3V) . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage levels are with respect to GND.
5.2
Recommended Operating Conditions
MIN NOM 3.3 5 MAX 3.6 5.25 VCC3V VCC5V VCC3V VCC3V 0.8 VCC3V VCC5V 0.8 0.8 115 22 (+5%) 12 1.5 0.8 0 2.5 6 UNIT V V V V V V V V V V V C Mb/s Mb/s V ns 3 4.75 0 0 0 2 0 2 2 02 0 0 22 (-5%)
Supply voltage, VCC3V Supply voltage, VCC5V Input voltage, TTL/LVCMOS, VI Input voltage, 5-V tolerant TTL, VI Output voltage, TTL/LVCMOS, VO High-level input voltage, signal-ended receiver, VIH(REC) Low-level input voltage, signal-ended receiver, VIL(REC) High-level input voltage, TTL/LVCMOS, VIH(TTL) High-level input voltage, 5-V tolerant TTL, VIH(TTL) Low-level input voltage, TTL/LVCMOS, VIL(TTL) Low-level input voltage, 5-V tolerant TTL, VIL(TTL) Operating junction temperature, TJ External series, differential driver resistor, R(DRV) Operating (dc differential driver) high speed mode, f(OPRH) Operating (dc differential driver) low speed mode, f(OPRL) Common mode, input range, differential receiver, V(ICR) Input transition times, tt, TTL/LVCMOS
5-1
5.3
Electrical Characteristics Over Recommended Ranges of Operating Free-Air Temperature and Supply Voltage (Unless Otherwise Noted)
PARAMETER TTL/LVCMOS TEST CONDITIONS IOH = - 4 mA IOH = - 0.1 mA R(DRV) = 15 k, to GND IOH = - 12 mA (without R(DRV)) IOL = 4 mA R(DRV) = 1.5 k to 3.6 V IOL = 12 mA (without R(DRV)) 0.8 V VICR 2.5 V 0.8 0.8 V VICR 2.5 V 0.8 V VICR 2.5 V V = VCC or GND 0 V VO VCC VO = 5.5 V TTL/LVCMOS TTL/LVCMOS USB data lines USB data lines VI = GND VI = VCC Static VOH or VOL 0.8 V VICR 2.5 V Normal operation Suspend mode 7.1 0.2 100 1 1 0.25 300 0.7 500 10 10 85 -1 1 19.9 MIN VCC3V - 0.6 2.4 2.8 VCC - 0.5 0.5 0.3 0.5 2 1.8 V V V V V mV A A A A A V mA A V MAX 3.6 UNIT
VOH
High-level output voltage USB data lines
3.6
V
TTL /LVCMOS VOL Low-level output voltage
USB data lines
VIT IT+ VIT IT- Vh hys IOZ
Positive input threshold voltage Negative-input threshold g voltage Input hysteresis y (VT+ - VT-) High-impedance output g current 5-V tolerant, 3-state output, high-impedance state current Low-level input current High-level input current Driver output impedance Differential input voltage Input supply current
TTL /LVCMOS Single-ended TTL /LVCMOS Single-ended TTL /LVCMOS Single-ended TTL/LVCMOS USB data lines
IOZH IIL IIH zo(DRV) VID ICC
Applies for input buffers with hysteresis Applies for open drain buffers
5-2
5.4
5.4.1
Timing Characteristics
Timing Characteristics for USB Transceivers
PARAMETER TEST CONDITIONS See Figure 5-1 and Figure 5-2 See Figure 5-1 and Figure 5-2 (tr/tf) x 100 MIN 4 4 90 1.3 MAX 20 20 110 2.0 UNIT ns ns % V
Full Speed Mode
tr tf t(RFM) VO(CRS) Transition rise time for DP or DM Transition fall time for DP or DM Rise/fall time matching Signal crossover output voltage
Low Speed Mode
PARAMETER tr tf t(RFM) VO(CRS) Transition rise time for DP to DM Transition fall time for DP to DM Rise/fall time matching Signal crossover output voltage TEST CONDITIONS CL = 50 pF to 350 pF, See Figure 1 and Figure 2 CL = 50 pF to 350 pF, See Figure 1 and Figure 2 (tr/tf) x 100 CL = 50 pF to 350 pF V(TERM) = 2.8 V DP 22 Full 15 k DM 22 15 k CL CL Low 1.5 k MIN 75 75 80 1.3 MAX 300 300 120 2.0 UNIT ns ns % V
Figure 5-1. Differential Driver Switching Load
DM VO(CRS) DP
90% 10% tr, tf
VOH VOL
Figure 5-2. Differential Driver Timing Waveforms
5-3
1.5 V ID - Differential Receiver Input Sensitivity - V 1.3
1
0.5
0.2 0 0 3 1 2 3.6 0.8 2.5 VICR - Common Mode Input Range - V 4
Figure 5-3. Differential Receiver Input Sensitivity vs. Common Mode Input Range
Logic high VIT+ VIT- Logic low
Vhys
VCC VIH
VIL 0V
Figure 5-4. Single-Ended Receiver Input Signal Parameter Definitions
5-4
5.4.2
Timing Characteristics for I2C Interface
PARAMETER TEST CONDITIONS STANDARD MODE MIN MAX 100 0 4 4.7 1000 300 250 0 4.7 4.7 4 4 100 0 1.3 0.6 0.6 0.6 FAST MODE MIN 0 0.6 1.3 300 300 MAX 400 kHz s s ns ns ns ns s s s s UNITS
fSCL tw(H) tw(L) tr tf tsu1 th1 tbuf tsu2 th2 tsu3
Clock frequency, SCL Pulse duration, SCL high Pulse duration, SCL low Rise time, SCL and SDA Fall time, SCL and SDA Setup time, SDA to SCL Hold time, SCL to SDA Bus free time between stop and start condition Setup time, SCL to start condition Hold time, start condition to SCL Setup time, SCL to stop condition
tw(H) SCL
tw(L)
tr
tf
tsu1 SDA Figure 5-5. SCL and SDA Timing
th1
SCL tsu2 SDA Start Condition Stop Condition th2 tsu3 tbuf
Figure 5-6. Start and Stop Conditions
5-5
5-6
SCL
1
2
8
9
SDA IN
SDA OUT Figure 5-7. Output Acknowledge
Start Condition
Acknowledge
Acknowledge
Acknowledge
SDA
A6
A5
A4
A3
A2
A1
A0 R/W ACK
*
*
*
A4
A3
A2
A1
A0
ACK D7
D6
D5
D4
D3
D2
D1
D0 ACK
I2C Device Address and Read/Write Bit * Don't Care Bits
FIFO or Register Address
Data Byte
Stop Condition
Figure 5-8. Single Byte Write Transfer
Start Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
SDA
A6
A5
A1
A0 R/W ACK
*
*
*
A4
A3
A1
A0
ACK D7
D6
D1
D0 ACK
D7
D6
D1
D0 ACK
I2C Device Address and Read/Write Bit * Don't Care Bits
FIFO or Register Address
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
Figure 5-9. Multiple Byte Write Transfer
Repeat Start Condition Start Condition Acknowledge Acknowledge Acknowledge
Not Acknowledge
SDA
A6
A5
A1
A0 R/W ACK
*
*
*
A4
A0
ACK
A6
A5
A1
A0 R/W ACK D7
D6
D1
D0 ACK
I2C Device Address and Read/Write Bit * Don't Care Bits
FIFO or Register Address
I2C Device Address and Read/Write Bit
Data Byte
Stop Condition
Figure 5-10. Single Byte Read Transfer
Repeat Start Condition Start Condition Acknowledge Acknowledge Acknowledge Acknowledge
Not Acknowledge
SDA
A6
A0 R/W ACK
*
*
*
A4
A0
ACK
A6
A0 R/W ACK D7
D0 ACK
D7
D6
D1
D0 ACK
I2C Device Address and Read/Write Bit * Don't Care Bits
FIFO or Register Address
I2C Device Address and Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
Figure 5-11. Multiple Byte Read Transfer
5.4.3
tw(H)
Timing Characteristics for Remote Wake-up
PARAMETER Pulse duration, WAKEUP high TEST CONDITIONS MIN 0.6 MAX 10 UNITS s
tw(H) WAKEUP
5-7
Figure 5-12. Remote Wake-Up
6 USB Overview Description
A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a single personal computer (See Figure 6-1).
PC With Root Hub
Monitor With 4-Port Hub (Self-Powered)
Keyboard With 4-Port Hub (Bus-Powered)
Modem
Telephone
Printer With 4-Port Hub (Self-Powered)
Left Speaker
Mouse
Right Speaker
Scanner
Digital Scanner
Figure 6-1. USB Tiered Configuration Example Another advantage of USB is that all peripherals are connected using a standardized 4-wire cable which provides both communication and power distribution. The three power configurations are Bus-Powered, Self-Power and High-Power mode. For all three configurations, 100 mA is the maximum current that may be drawn from the USB 5 V line during power-up. For Bus-Power mode, a hub can draw a maximum of 500 mA from the 5 V line of the USB cable. A Bus-Powered hub must always be connected downstream to a Self-Powered hub unless it is the only hub connected to the PC and there are no High-Powered functions connected downstream. In the Self-Power mode, the hub is connected to its own power supply and can supply up to 500 mA to each downstream port. High-Powered functions may draw a maximum of 500 mA and may only be connected downstream to Self-Powered hubs. Both Bus-Powered and Self-Powered hubs require over-current protection for all downstream ports. The two types of protection are individual port management (individual port basis) or ganged port management (multiple port basis). Individual port management requires power management devices for each individual downstream port, but adds robustness to your USB system because, in the event of an over-current condition, the USB Host will only power-down the port that has the condition. The ganged configuration uses fewer power management devices and thus has lower system costs, but in the event of an over-current condition on any of the downstream ports, all the ganged ports will be disabled by the USB Host. Using a combination of the BUSPWR and GANGED inputs, the TUSB2140 supports four modes of power management: Bus-Powered hub with either individual port power management or ganged port power management and the Self-Powered hub with either individual port power management or ganged port power management. Texas Instruments supplies the complete hub solution because we offer this TUSB2140, the TUSB2040 (4-port) and the TUSB2070 (7-port) hubs along with the power management chips needed to implement a fully USB Specification 1.0 compliant system. See Figure 6-4, 6-5 and 6-6 for example configurations.
6-1
6.1
Application Information
The following sections provide examples of how to connect the TUSB2140 chip for different working modes. The terminal number assigned for Figures 6-2, 6-4, 6-5 and 6-6 are for the TUSB2140N DIP package. If the TUSB2140PAG surface mount package is desired, see Section 1.2 for the correct pin-out. Figure 6-2 shows a typical application for the I2C pin-out portion of the TUSB2140. Depending on the clock rate needed for the MCU, the specific pin configuration for CLKSEL0 and CLKSEL1 is listed on Table 4-2. Since the first harmonic of most crystals is not 48-MHz, a tunning circuit such as in Figure 6-3 can be used to tune the crystal to 48-MHz which is required by the TUSB2140. Figures 6-4, 6-5 and 6-6 show typical applications for the hub pin-out portion of the TUSB2140.
TUSB2140 I2C Interface Tuning Circuit 29 Crystal 28 XTAL1 XTAL2 VCC 5V 6 OVRCUR5 PWRON5 36 40 Power Management Chips 5V 5.1 k 3.3 V 1.5 k 5 4 3 CLKSEL1 CLKSEL0 GND 39 SCL 38 SDA IRQ FUNCSUSP WAKEUP CLKOUT 37 35 1 2 Any Micro-Controller Unit (MCU) 5.1 k
Values for timing components are subject to change when using different crystals and PCBs. The crystal in this application is a 48-MHz US Crystal, P/N HC-18/U 48MHZ. Depending on the application, connect as shown in Figures 6-4, 6-5, or 6-6. NOTE: The CLKSEL1 and CLKSEL0 pins are configured for a 4.0 MHz output at the CLKOUT pin (see Table 4.2) NOTE: Terminal numbers shown are for the N package
Figure 6-2. Typical I2C Interface Connection to a Micro-Controller R70 22 k XTAL1 Y1 C66 47 pF L1 5.6 H XTAL2 C68 1000 pF C67 12 pF
NOTES: A. When tuning the crystal (Y1) for different board implementations, the capacitor (C67) is subject to change. Other components should remain the same.
Figure 6-3. Typical Crystal Tuning Circuit for the TUSB2140 USB Device
6-2
6.2
Bus-powered Hub, Ganged Port Power Management
A bus-powered TUSB2140 supports up to four downstream USB ports and is capable of supplying 100 mA of current for devices connected to each downstream port. Bus-powered hubs must implement power switching. Ganged power management utilizes the TPS2014 power switch device and provides overcurrent protection for downstream ports. Individual SN75240 transient suppressors reduce in-rush current and voltage spikes. The TPS7133 low-dropout voltage regulator provides a Power Good (PG) signal for reset at power-up. OVRCUR1 - OVRCUR5 inputs must be tied together for ganged mode operation.
TUSB2140 HUB Portion 15 Downstream Ports D+ A B DP2 TPS7133 5V 4.7 F 0.1 F GND 5V 19,33 3.3 V GND PG DP4 29 48-MHz Crystal XTAL1 DM4 PWRON1 Tuning Circuit 28 XTAL21 PWRON2 PWRON3 PWRON4 27 OCSOFF 9 7 32 25 120 F D+ Ferrite Beads D- GND 5V 4.7 F 22 23 TPS2014 8 34 31 26 Ferrite Beads GND OVRCUR1 24 RESET OVRCUR2 OVRCUR3 12,30 GND OVRCUR4 OC OUT D+ D- EN IN 1 F 5V 120 F VCC DM2 DP3 DM3 17 18 20 21 A B C D D+ D- Ferrite Beads GND 120 F C D Ferrite Beads D- GND 5V
BUSPWR Upstream Port 10 D+ 11 D- SN75240 AC BD DM0 DP0
GANGED DP1 DM1
16 13 14
3.3 V
SN75240
SN75240
5V
TPS2014, TPS7133, and SN75240 are Texas Instruments devices. Values for timing components subject to change when using different crystals and PCBs. Minimum value required per USB specification, version 1.0. NOTE A: Terminal numbers shown are for the N package
120 F
Figure 6-4. TUSB2140 Bus-Powered Hub, Ganged Port Power Management Application
6-3
6.3
Self-powered Hub, Ganged Port Power Management
A self-powered TUSB2140 can also be implemented using ganged port power management. This implementation is similar to the individual power management except one TPS2015 provides power switching and overcurrent protection for two ports. Although this is a more economical solution, a fault on one downstream port will cause power to be removed from all downstream ports.The TPS7133 low-dropout voltage regulator provides a Power Good (PG) signal for reset at power-up. OVRCUR1 - OVRCUR5 inputs must be tied together for ganged mode operation.
TUSB2140 HUB Portion 10 11 SN75240 AC BD TPS7133 4.7 F 0.1 F GND 5V 3.3 V GND PG 19,33 4.7 F VCC DP2 DM2 DP3 DM3 17 18 20 21 A B DP4 DM4 Tuning Circuit 28 XTAL2 5V 120 F D+ 0.1 F 24 12,30 RESET PWRON2 PWRON3 GND PWRON4 34 31 26 NC NC NC 5V 120 F D+ TPS2015 EN IN 0.1 F OC OUT 5V 120 F Ferrite Beads GND D- OC OUT D- Ferrite Beads GND 22 23 C D Ferrite Beads GND DP0 DM0 BUSPWR GANGED DP1 DM1 15 16 13 14 A B C D Ferrite Beads GND
Upstream Port D+ D-
3.3 V Downstream Ports D+ D-
5V
SN75240 5V 120 F
D+ D-
48-MHz Crystal
29
XTAL1
SN75240
TPS2015 PWRON1 27 OCSOFF 8 EN IN
OVRCUR1 OVRCUR2 OVRCUR3 OVRCUR4
9 7 32 25
5 V Board Power Supply
TPS2015, TPS7133, and SN75240 are Texas Instruments devices. Values for timing components subject to change when using different crystals and PCBs. Minimum value required per USB specification, version 1.0. NOTE A: Terminal numbers shown are for the N package
Figure 6-5. TUSB2140 Self-Powered Hub, Ganged Port Power Management Application
6-4
6.4
Self-powered Hub, Individual Port Power Management
A self-powered TUSB2140 is capable of supplying 500 mA of current for low-power or high-power devices connected to each downstream port. Self-powered hubs are required to implement overcurrent protection. Individual-port power management utilizes the TPS2014 power switching and overcurrent protection for each downstream port. Therefore, providing maximum robustness to the hub system. When the hub detects a downstream port fault, power is removed from the faulty port only, thus allowing other ports to continue normal operation. Individual SN75240 transient suppressors reduce in-rush current and voltage spikes. The TPS7133 low-dropout voltage regulator provides a Power Good (PG) signal for reset at power-up. .
TUSB2140 HUB Portion Upstream Port D+ D- SN75240 A 5V B C D TPS7133 4.7 F 0.1 F GND 5V 3.3 V GND PG 19,33 4.7 F VCC DP2 DM2 DP3 DM3 17 18 20 21 A B DP4 DM4 PWRON1 48-MHz Crystal 29 XTAL1 OC OUT D+ D- GND 22 23 TPS2014 8 EN IN 0.1 F 120 F 5V C D D+ D- GND 120 F 10 11 DP0 DM0 BUSPWR DP1 DM1 GANGED 15 13 14 16 A B C D GND 5V 3.3 V Downstream Ports D+ D-
SN75240
SN75240
Tuning Circuit
28
PWRON2 XTAL2 PWRON3 PWRON4
34 31 26
TPS2014 EN IN 0.1 F
27
OCSOFF 9 7 OC OUT 5V
OVRCUR1 OVRCUR2 24 RESET
TPS2014 EN IN 0.1 F
120 F D+ D-
OVRCUR3 12,30 GND OVRCUR4
32 OC 25
OUT
GND
TPS2014 EN IN 0.1 F 120 F OC OUT 5-V Board Power Supply 5V
TPS2014, TPS7133, and SN75240 are Texas Instruments devices. Values for timing components are subject to change when using different crystals and PCBs. Minimum value required per USB specification, version 1.0. NOTE A: Terminal numbers shown are for the N package
Figure 6-6. TUSB2140 Self-Powered Hub, Individual-Port Power Management Application
6-5
Appendix A Firmware Development
Overview of Firmware
The flowchart for the main structure of the software program is depicted in Figure A-1. Power up causes all bits in the interrupt register to be set to zeros which then sets the pin IRQ = 1 (no interrupt). After power up, the embedded function must then be enabled (connected logically) to the hub. Enabling the embedded function results from enabling endpoint 0. Endpoint 0 is enabled by setting the EP0 TXEN and EP0 RXEN bits to 1. The interrupt mask register bits then need to be set to 1 in order to allow the corresponding bits of the interrupt register to assert the IRQ signal. Each bit of the interrupt register corresponds to a different interrupt that could occur. The interrupt routines are EP0 transmit, EP0 receive, EP1 transmit, function reset, and function suspend. If any of the five interrupt routines are not desired, the corresponding bit in the interrupt mask register should remain a 0, thus disabling the interrupt bit from asserting the IRQ signal. If the interrupt endpoint (endpoint 1) functionality is desired, the endpoint 1 enable bit (EP1EN) should be set. Now that the proper bits have been set per the above paragraph, the micro-controller will then be in idle state and ready for an occurrence of an interrupt. Upon an interrupt (IRQ=0), the MCU will read the value stored in the interrupt register and based on the value, it will execute one of the five interrupt routines. However, the host controller may decide to initiate a reset or another setup transaction before the current interrupt routine has been completed. The reset or setup transaction will cause hardware to write 0 to all the bits in the interrupt register and the IRQ bit will be set to 1. Then, the hardware will set a bit in the interrupt register that signals the new interrupt conditions. If an error occurs, the ACK handshake may become corrupted which will cause the device to hang because the host and function may disagree on whether the transaction was completed successfully. (Please see the "Error Handling on the Last Data Transaction" section of the USB Specification for further explanation of error handling by the USB host.) In order to deal with errors, the software must implement a timeout timer which is used to tell the micro-controller when to check the STSGE bit of the EP0 TX status register. If the timer times out, the micro-controller should set the RXFEN bit to 1 in the EP0 RX control register. This will enable the FIFO to receive the data from the host once again.
A-1
Enable Endpoint 0 Set Interrupt Mask Register Bits If Endpoint 1 is needed, set EP1EN
No
Yes IRQ = 1 Time Out
No
Identify Interrupt By Reading Interrupt Register
Yes
Yes EP0TX No Yes EP0RX
No EP0 Transmit Service Routine Error Enable Stall EP0 Receive Service Routine
STSGE
Yes
Enable RX FIFO
No Yes EP1TX EP1 Transmit Service Routine
No Yes FRST Function Reset Service Routine
No Yes FSUSP No Clear Function Suspend Interrupt
Figure A-1. Flow Chart for TUSB2140 Firmware
A-2
Endpoint 0 Transmit Service Routine
The flow diagram for the endpoint 0 transmit service routine is shown in Figure A-2. After detecting the endpoint 0 transmit interrupt bit (EP0TX) has been set, the MCU should branch to the endpoint 0 transmit service routine. First, the endpoint 0 transmit status register should be read to determine the source of the interrupt. If a successful transmit transaction has occurred, the endpoint 0 transmit acknowledge bit (ACK) will be set. The MCU should clear the interrupt condition by clearing the ACK bit. Next, if the next transaction should be an In data stage, the MCU should load the endpoint 0 transmit FIFO with the next data packet, write the new byte count value to the endpoint 0 transmit byte count register, and reset the timeout timer. However, if the next transaction should be an Out status stage, the MCU should set the endpoint 0 receive FIFO enable bit (RXFEN) to allow the status stage to be successfully acknowledged. If the EP0TX interrupt resulted from an endpoint 0 transmit FIFO under-run or over-run condition, the endpoint 0 transmit FIFO under-run (UNDR) or over-run (OVRR) bit will be set, respectively. The under-run or over-run condition should be cleared by setting the endpoint 0 transmit clear bit (TXCLR).
EP0TX = 1 Check Transmit Status By Reading TX Status Register
No
ACK
Yes
No
UNDR
Clear Interrupt By Writing ACK = 0 in TX Status Register
In Data Yes OVRR Clear Transmit FIFO and Interrupt by Writing TXCLR = 1 in TX Control Register
Next Transaction Stage For EP0 SETUP Stop Timeout Timer
Out Status
No
EMPT Yes Load New Data to Transmit FIFO
No
Error Stall EP0
Write The Number of Data Bytes to TX Byte Count Register Which also Enables Transmit FIFO Enable EP0 Receive FIFO
Reset Timeout Timer
RETURN
Figure A-2. Endpoint 0 Transmit Interrupt Service Routine
A-3
Endpoint 0 Receive Service Routine
The flow diagram for the endpoint 0 receive service routine is shown in Figure A-3. After detecting that the endpoint 0 receive interrupt bit (EP0RX) has been set, the MCU should branch to the endpoint 0 receive service routine. First, the endpoint 0 receive status register should be read to determine the source of the interrupt. If a receive transaction has occurred, the endpoint 0 receive acknowledge bit (ACK) will be set. In addition, if the transaction was a setup stage transaction, the endpoint 0 receive setup stage transaction bit (SETUP) will also be set. The MCU should clear the ACK and SETUP bits to clear the interrupt. Note that the SETUP bit must be cleared to enable reading the endpoint 0 receive FIFO. Next, the endpoint 0 receive byte count should be read to determine the number of bytes in the FIFO. Then the FIFO data should be read based on the byte count value. If a FIFO under-run occurs while reading the FIFO, the endpoint 0 receive FIFO under-run bit (UNDR) will be set to indicate the condition. To clear an under-run condition, the MCU should set the endpoint 0 receive clear bit (RXCLR). After successfully reading the data packet from the receive FIFO, the MCU should branch to either the Setup Stage, Out Data Stage, or Out Status Stage routine based on the current transaction stage flags. In the Out Data Stage routine, the MCU should set the endpoint 0 receive FIFO enable bit (RXFEN) to allow the next data stage data packet to be received. However, if the last data stage is detected, then the MCU should write a value of zero to the endpoint 0 transmit byte count register, which will automatically set the endpoint 0 transmit FIFO enable bit (TXFEN). As a result, the TUSB2140 will acknowledge the next In status stage transaction from the host. In the Setup Stage routine, the MCU should decode the received data to determine the request type. In addition, the data stage length, direction of data transfer, and direction of status stage should be determined. The MCU should take the appropriate action for each control transfer based on this information. A control read for instance, requires the MCU to load data into the endpoint 0 transmit FIFO for each In data stage. The transmit FIFO can hold a maximum of eight bytes per In data stage transaction. Also, the MCU must enable the endpoint 0 receive FIFO to allow the control read Out status stage to be successfully acknowledged. During endpoint 0 receive operations, a receive FIFO over-run condition could occur, which is indicated by an endpoint 0 receive interrupt being generated and the endpoint 0 receive FIFO over-run bit (OVRR) being set. The over-run condition can be cleared by setting the endpoint 0 receive clear bit (RXCLR) in the control register. Once in the endpoint 0 service routine, if the MCU determines that neither the ACK bit or OVRR bit has been set, then the MCU should return to the main program. This scenario can occur when a new setup stage transaction is received while the MCU is branching from the main program to the receive service routine. When the new setup stage is received, the ACK bit will automatically be cleared.
A-4
EP0RX = 1 Check Receive Status By Reading Receive Status Register
Yes ACK SETUP = 1 SETUP or STSGE STSGE = 1
No
Check Overrun By Reading RX Flag Register
SETUP = 0 STSGE = 0 Setup Stage Clear Interrupt and Set Flag Data Stage Clear Interrupt Status Stage Clear Interrupt and Set Flag
OVRR Yes
No
Read The Number of Bytes of Data From RX Byte Count Register
Read Data From RXFIFO
UNDR No OUT Status
Yes
Clear RX FIFO By Enabling RX CLR in RX Control Register
Current Transaction Stage
OUT Data
SETUP Stop Timer Stop Timer No-Data CTL Write Next Stage Status CTL Read Enable RX FIFO Load TX FIFO and Write to TX Byte Count Reg. No Write 0 to TX Byte Count Reg. Enable RX FIFO Enable TX FIFO Reset Timeout Timer
CTL Write
Decode Command
Yes
RETURN
Figure A-3. Endpoint 0 Receive Interrupt Service Routine
A-5
Endpoint 1 Transmit Service Routine
The flow diagram for the endpoint 1 transmit service routine is shown in Figure A-4. After detecting the endpoint 1 transmit interrupt bit (EP1TX) has been set, the MCU should branch to the endpoint 1 transmit service routine. First, the endpoint 1 transmit status register should be read to determine the source of the interrupt. If a successful transmit transaction has occurred, the endpoint 1 transmit acknowledge bit (ACK) will be set. The MCU should clear the interrupt condition by clearing the ACK bit. Next, the MCU should load the endpoint 1 transmit FIFO with the next data packet and write the new byte count value to the endpoint 1 transmit byte count register. If the EP1TX interrupt resulted from an endpoint 1 transmit FIFO under-run or over-run condition, the endpoint 1 transmit FIFO under-run (UNDR) or over-run (OVRR) bit will be set, respectively. The under-run or over-run condition should be cleared by setting the endpoint 1 transmit clear bit (TXCLR).
EP1TX = 1 Check Transmit Status By Reading TX Status Register
No
ACK
Yes
No
UNDR
Yes
Clear Interrupt By Writing ACK = 0 in TX Status Register
Yes OVRR No
Clear Transmit FIFO and Interrupt by Writing TXCLR = 1 in TX Control Register
No
EMPT Yes
Error Stall EP1
Load New Data to Transmit FIFO
Write The Number of Data Bytes to TX Byte Count Register and Enable Transmit FIFO
RETURN
Figure A-4. Endpoint 1 Transmit Interrupt Service Routine
A-6
Function Reset Service Routine
After detecting the function reset interrupt bit (FRST) has been set, the MCU should branch to the function reset service routine. As a result of the TUSB2140 device receiving the USB function reset, all control and status registers will be cleared except the interrupt mask register bits, the endpoint 0 receive enable bit (RXEN), the endpoint 0 transmit enable bit (TXEN) and the function reset interrupt bit (FRST). To clear the function reset interrupt, the MCU should write 08h to the interrupt register.
Function Suspend Service Routine
When a global or selective suspend condition is detected by the TUSB2140 device, the function suspend interrupt bit (FSUSP) will be set. After detecting the FSUSP bit has been set, the MCU should complete the current routine being processed then write 10h to the interrupt register in order to clear the function suspend interrupt. As a result of the FSUSP bit being cleared by the MCU, the TUSB2140 device will enter the low-power suspend mode and will disable the device clocks.
A-7
Appendix B Mechanical Data
N (R-PDIP-T**)
24 PIN SHOWN A 24 13
PLASTIC DUAL-IN-LINE PACKAGE
0.560 (14,22) 0.520 (13,21)
1 0.060 (1,52) TYP
12 0.200 (5,08) MAX 0.020 (0,51) MIN 0.610 (15,49) 0.590 (14,99)
Seating Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.125 (3,18) MIN 0.010 (0,25) NOM
0- 15
PINS ** DIM A MAX
24 1.270 (32,26) 1.230 (31,24)
28 1.450 (36,83) 1.410 (35,81)
32 1.650 (41,91) 1.610 (40,89)
40 2.090 (53,09) 2.040 (51,82)
48 2.450 (62,23) 2.390 (60,71)
52 2.650 (67,31) 2.590 (65,79) 4040053 / B 04/95
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) B-1
PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17
PLASTIC QUAD FLATPACK
0,08 M
49
32
0,13 NOM 64 17
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95
16 0,25 0,05 MIN
Gage Plane
0- 7 0,75 0,45
Seating Plane 1,20 MAX 0,08 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
B-2

▲Up To Search▲

Price & Availability of SLLS264A

	To Download SLLS264A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .