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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
D D D D D D D D D D D D D D
28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 28 Data Channels and Clock-In Low-Voltage TTL 4 Data Channels and Clock-Out Low-Voltage Differential Operates From a Single 3.3-V Supply With 250 mW (Typ) ESD Protection Exceeds 6 kV 5-V Tolerant Data Inputs Selectable Rising or Falling Edge-Triggered Inputs Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the DS90C581
DGG PACKAGE (TOP VIEW)
description
The SN75LVDS83 FlatLink transmitter contains 28 29 four 7-bit parallel-load serial-out shift registers, a 7x clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7x) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level. The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 CLKSEL D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
D4 D3 D2 GND D1 D0 D27 LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP Y3M Y3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND
Copyright (c) 2000, Texas Instruments Incorporated
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
functional block diagram
Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD Y2P Y2M Y1P Y1M
D0, D1, D2, D3, D4, D6, D7
7
Y0P Y0M
D8, D9, D12, D13, D14, D15, D18
7
D19, D20, D21, D22, D24, D25, D26
7
Input Bus
CLK Parallel-Load 7-Bit Shift Register A,B, ...G SHIFT/LOAD CLK Y3P Y3M
D5, D10, D11, D16, D17, D23, D27
7
Control Logic SHTDN
7x Clock/PLL 7xCLK CLKIN CLKSEL CLK CLKINH RISING/FALLING EDGE CLKOUTP CLKOUTM
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
D0
CLKIN or CLKIN
CLKOUT
Previous Cycle
Current Cycle
D3 D2
Y0
D0-1
D7
D6
D4
Y1
D8-1
D18
D15
D14
D13
D12
Y2
D19-1
D26
D25
D24
D22
D21
Y3
D27-1
D23
D17
D16
D11
D10
Figure 1. SN75LVDS83 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
VCC
VCC 5 Dn or SHTDN 10 k 50
7V 300 k
INPUT
OUTPUT
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CC CC
D1 D0 D9 D8 D20 D19 D5 D27
EE EE
EEE EEE CC CC
Next Cycle
D7+1 D18+1 D26+1 D23+1
EE EE
EEE EEE
YnP or YnM
7V
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Output voltage range, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input voltage range, VI (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING
DGG 1377 mW 11.0 mW/C 822 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Differential load impedance, ZL Operating free-air temperature, TA 90 0 3 2 0.8 132 70 NOM 3.3 MAX 3.6 UNIT V V V C
timing requirements
MIN tc tw tt tsu th Cycle time, input clock Pulse duration, high-level input clock Transition time, input signal Setup time, data, D0 - D27 valid before CLKIN or CLKIN (see Figure 2) Hold time, data, D0 - D27 valid after CLKIN or CLKIN (see Figure 2) 3 1.5 14.7 0.4 tc NOM MAX 32.4 0.6 tc 5 UNIT ns ns ns ns ns
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT |VOD| |VOD| VOC(SS) VOC(PP) IIH IIL IOS IOZ Input threshold voltage Differential steady-state output voltage magnitude Change in the steady-state differential output voltage magnitude between opposite binary states Steady-state common-mode output voltage Peak-to-peak common-mode output voltage High-level input current Low-level input current Short circuit output current Short-circuit High-impedance state output current RL = 100 , See Figure 3 1.125 247 TEST CONDITIONS MIN TYP 1.4 454 50 1.375 150 25 10 24 12 10 280 72 90 MAX UNIT V mV mV V mV A A mA mA A A mA
See Figure 3 VIH = VCC VIL = 0 VO(Yn) = 0 VOD = 0 VO = 0 to VCC Disabled, All inputs at GND Enabled, RL = 100 , Gray-scale pattern (see Figure 4), VCC = 3.3 V, tc = 15.38 ns Enabled, RL = 100 , Worst-case pattern (see Figure 5), tc = 15.38 ns
ICC
Quiescent supply current
85 3
110
mA pF
CI Input capacitance All typical values are at VCC = 3.3 V, TA = 25C.
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER td0 td1 td2 td3 td4 td5 td6 tsk(o) td7 Delay time, CLKOUT to serial bit position 0 Delay time, CLKOUT to serial bit position 1 Delay time, CLKOUT to serial bit position 2 Delay time, CLKOUT to serial bit position 3 tc = 15.38 ns ( 0.2%), |Input clock jitter| < 50 ps, See Figure 6 Delay time, CLKOUT to serial bit position 4 Delay time, CLKOUT to serial bit position 5 Delay time, CLKOUT to serial bit position 6 Output skew, tn 1t 7c 2t 7c 3t 7c 4t 7c TEST CONDITIONS MIN - 0.2 TYP 0 1t 7c 2t 7c 3t 7c 4t 7c 5t 7c MAX 0.2 UNIT ns ns ns ns ns ns ns ns ns ps ps ns 1500 ps ms ns
* n tc 7
tc = 18.51 ns ( 0.2%), |Input clock jitter| < 50 ps, See Figure 6 tc = 15.38 0.75 sin (2500E3t) + 0.05 ns, See Figure 7 tc = 15.38 0.75 sin (23E6t) + 0.05 ns, See Figure 7
* 0.2 * 0.2 * 0.2 * 0.2 5 t * 0.2 7c 6 t * 0.2 7c
- 0.2 3.75 5.6 70 187 4t 7c
) 0.2 ) 0.2 ) 0.2 ) 0.2 ) 0.2 6 t ) 0.2 7c
0.2 7.75
Delay time, CLKIN to CLKOUT
tc(o) C cle time o tp t clock jitter ( ) Cycle time, output
tw tt ten tdis
Pulse duration, high-level output clock Transition time, differential output (tr or tf) Enable time, SHTDN to phase lock (Yn valid) Disable time, SHTDN to off state (CLKOUT low) See Figure 3 See Figure 8 See Figure 9 260
700 1 250
All typical values are at VCC = 3.3 V, TA = 25C. |Input clock jitter| is the magnitude of the change in the input clock period. Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles.
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
tsu Dn th
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Waveforms
49.9 1% (2 Places)
YP
VOD VOC CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC
YM
VOD(H) 0V VOD(L)
tf
VOC(SS)
VOC(SS)
(b) WAVEFORMS
Figure 3. Test Load and Voltage Waveforms for LVDS Outputs
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EEEE EEEE
100% 80% 20% 0% tr VOC(PP) 0V
EEEEE EEEEE
CLKSEL LOW CLKSEL HIGH
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
CLKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4-7, 12-15, 20-23 D24-27 NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown.
Figure 4. 16-Grayscale Test-Pattern Waveforms
tc CLKIN Even Dn Odd Dn
NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with CLKSEL low shown.
Figure 5. Worst-Case Test-Pattern Waveforms
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
td7 CLKIN (see Note A) CLKIN (see Note B)
CLKOUT
td0
Yn
td1
td2
td3 td4 td5 td6
2.5 V CLKIN 1.4 V 0.5 V td7 NOTES: A. This wave form is valid when CLKSEL is low. B. This wave form is valid when CLKSEL is high. td0 - td6 CLKOUT or Yn
Figure 6. SN75LVDS83 Timing Waveforms
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EE EEE EE EE EEE EE II II II
VOD(H) 0.00 V VOD(L) 9
EE EE EE EE EE EE EE EE II II II
EE EE III III III
SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
Reference
+
+ Modulation
VCO
Device Under Test
V(t) = A sin (2 f(mod) t)
HP8656B Signal Generator 0.1 MHz - 990 MHz
HP8665A Synthesized Signal Generator 0.1 MHz - 4200 MHz OUTPUT Modulation Input
Device Under Test
DTS2070C Digital Time Scope
CLKIN
CLKOUT
Input
RF Output
Figure 7. Output Clock Jitter Testing
CLKIN
Dn
ten SHTDN
Yn
CLKIN tdis SHTDN
CLKOUT
10
EEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEE
Invalid
Valid
Figure 8. Enable Time Waveforms
Figure 9. Disable Time Waveforms
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY
80 VCC = 3.6 V 70
I CC - Average Supply Current - mA
60 VCC = 3.3 V 50 VCC = 3 V 40 Grayscale Data Pattern RL = 100 TA = 25C 40 50 60 70
30 30
fclk - Clock Frequency - MHz
Figure 10
ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY
200 180 Zero-to-Peak Output Jitter - ps 160 140 120 100 80 60 40 20 0 0 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25C 0.5 1 1.5 2 2.5 3
f(mod) - Modulation Frequency - MHz
Figure 11
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
APPLICATION INFORMATION
Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK See Note A 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 17 SN75LVDS83 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL Y0M 48 100 Y0P 47 10 A0P 9 Cable Flat Panel Display SN75LVDS82 A0M
Y1M
46 100
11
A1M
Y1P
45
12
A1P
Y2M
42 100
15
A2M
Y2P
41
16
A2P
Y3M
38 100
19
A3M
Y3P
37
20
A3P
CLKOUTM
40 100
17
CLKINM
CLKOUTP
39
18
CLKINP
NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge. B. The five 100- terminating resistors are recommended to be 0603 types.
Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
APPLICATION INFORMATION
Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK See Note A 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 17 SN75LVDS83 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL Y0M 48 100 Y0P 47 9 A0P 8 Cable Flat Panel Display SN75LVDS86 A0M
Y1M
46 100
10
A1M
Y1P
45
11
A1P
Y2M
42 100
14
A2M
Y2P
41
15
A2P
Y3M
38
Y3P
37
CLKOUTM
40 100
16
CLKINM
CLKOUTP
39
17
CLKINP
NOTES: A. Connect this terminal to VCC for triggering to the rising edge of the input clock and to GND for the falling edge. B. The four 100- terminating resistors are recommended to be 0603 types.
Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application
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SN75LVDS83 FLATLINKTM TRANSMITTER
SLLS271C - MARCH 1997 - REVISED JULY 2000
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
48 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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