View SLLS273_1002787.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
D D D D D D
Supports Provisions of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus Performs the Function of a 1394 Cycle Master Supports 1394 Transfer Rates of 100, 200 and 400 Mbit/s Provides Three Sizes of Programmable FIFOs Provides PCI Bus Master Function for Supporting DMA Operations Compliant With PCI Specification 2.1
D D D D D
Provides PCI Slave Function for Read/Write Access of Internal Registers Supports the Plug-and-Play (PnP) Specification Provides an 8-/16-bit Zoom Video (ZV) Port for the Transferring of Video Data Directly to an External Motion Video Memory Area Operates from a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs High-Performance 176-Pin PQFP (PGF) Package
description
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400 Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and system designers to assign their own unique identification codes. An autoboot mode allows data-moving systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU. The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels are provided to accommodate programmable data types. PCLs can be chained together to form a channel control program that can be developed to support each DMA channel. Data can be stored in either big endian or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the best memory use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
description (continued)
The RAM, ROM, AUX, ZV, and general purpose I/O (GPIO) ports collectively implement the local bus interface. These ports are mapped into the PCI address can be accessed either through the PCI bus or internal DMA transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth. DMA packet control lists or other data that may be stored in external RAM or ROM attached to the local bus interface. This further reduces PCI use and generally improves performance. The ZV local bus port is designed to transfer data from 1394 video devices to an external device connected to the PCILynx ZV port. This interface provides a method of receiving 1394 digital camera packets directly to a ZV-compliant device attached to the local bus interface. Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal states and provides a convenient software debug capability. Programmable interrupts are available to inform driver software of important events such as 1394 bus resets and DMA-to-PCL transfer completion. The 3.3-V internal operation provides reduced power consumption while maintaining compatibility with 5-V signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
3.3V VCC NC pci_ad25 pci_ad24 pci_cbez3 GND pci_idselz 3.3V VCC pci_ad23 pci_ad22 pci_ad21 5V VCC pci_ad20 GND pci_ad19 pci_ad18 pci_ad17 pci_ad16 3.3V VCC pci_cbez2 GND pci_framez pci_irdyz pci_trdyz pci_devselz 3.3V VCC pci_stopz GND NC pci_perrz pci_serrz pci_par 3.3V VCC pci_cbez1 GND pci_ad15 pci_ad14 pci_ad13 pci_ad12 5V VCC pci_ad11 3.3V VCC pci_ad10 pci_ad9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
pci_ad26 GND pci_ad27 pci_ad28 3.3V VCC pci_ad29 pci_ad30 pci_ad31 GND pci_reqz pci_intaz 3.3V VCC pci_gntz pci_resetz 5V VCC pci_clk GND autoboot GND 3.3V VCC phy_clk50 GND phy_data7 phy_data6 phy_data5 phy_data4 GND phy_data3 phy_data2 phy_data1 phy_data0 3.3V VCC phy_lreq phy_ctl1 phy_ctl0 GND test_out link_cycleout 3.3V VCC link_cyclein 3.3V VCC 5V VCC seeprom_data seeprom_clk 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
PGF PACKAGE (TOP VIEW)
zv_data_valid zv_hsync GND zv_ext_clk 3.3V VCC zv_vsync zv_pix_clk gpio_data0 gpio_data1 gpio_data2 gpio_data3 GND NC aux_adr0 aux_adr1 aux_adr2 3.3V VCC aux_adr3 GND aux_adr4 aux_adr5 aux_adr6 aux_adr7 5V VCC aux_adr8 3.3V VCC aux_adr9 aux_adr10 aux_adr11 aux_adr12 GND aux_adr13 3.3V VCC aux_adr14 aux_adr15 aux_data0 aux_data1 GND aux_data2 3.3V VCC aux_data3 aux_data4 aux_data5 GND
NC - No internal connection
GND NC pci_ad8 pci_cbez0 3.3V VCC pci_ad7 GND pci_ad6 pci_ad5 pci_ad4 pci_ad3 3.3V VCC pci_ad2 pci_ad1 pci_ad0 5V VCC aux_intz aux_rdy 5V VCC aux_clk GND aux_rstz ram_csz rom_csz aux_csz 3.3V VCC aux_wez1 GND aux_wez0 aux_oez 3.3V VCC aux_data15 aux_data14 aux_data13 GND aux_data12 aux_data11 aux_data10 aux_data9 5V VCC aux_data8 3.3V VCC aux_data7 aux_data6
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
Terminal Functions
Terminal Name 3.3V VCC No. 1,8,19,26,33,42,49 56,70,75,86,93,100 107,116,128,136,138, 145,157,165,172 12,40,60,63 84,109,135,162 159 98,99,101,103-106 108,110-113,115 117-119 64 69 76-78,80-83,85,87 88,90-92,94,96,97 61 74 62 66 71,73 6,14,21,28,35,45 51,65,72,79,89,95 102,114,121,130,141 150,155,158,160,168 175 122-125 137 139 2,29,46,120 169-171,173,174,176 3,4,9-11,13,15-18 36-39,41,43,44,47,50 52-55,57-59 5,20,34,48 161 25 22 I/O I/O I 3.3-V power input Description
5V VCC autoboot aux_adr15-0
I I O
5-V tolerant power input. When interfacing with a 3.3-V parts, these terminals should be connected to 3.3-V power. Autoboot to select autoboot mode Auxiliary port address lines
aux_clk aux_csz aux_data15-0 aux_intz aux_oez aux_rdy aux_rstz aux_wez1-0 GND
O O I/O I O I O O I
Auxiliary port clock out (output at frequency of PCI clock) Auxiliary port chip select Auxiliary port bidirectional data bus to external logic Auxiliary port interrupt Auxiliary port output enable Auxiliary port ready indication (from external logic) Auxiliary port reset out Auxiliary port write strobes (to external logic) Ground
gpio_data3-0 link_cyclein link_cycleout N/C pci_ad31-0
I/O I O
Auxiliary port general purpose programmable I/O signals Optional external 8-kHz clock Cycle timer 8-kHz cycle clock out Not connected PCI multiplexed address/data bus signals
pci_cbez3-0 pci_clk pci_devselz pci_framez
I/O I I/O I/O
PCI multiplexed command/byte enable signals PCI system clock PCI device select PCI frame signal
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
Terminal Functions (continued)
Terminal Name pci_gntz pci_idselz pci_intaz pci_irdyz pci_par pci_perrz pci_reqz pci_resetz pci_serrz pci_stopz pci_trdyz phy_clk50 phy_ctl0 -1 phy_data0-7 phy_lreq ram_csz rom_csz seeprom_clk seeprom_data test_out zv_data_valid zv_ext_clk zv_hsync zv_pix_clk zv_vsync 164 7 166 23 32 30 167 163 31 27 24 156 142,143 146-149,151-154 144 67 68 133 134 140 132 129 131 126 127 No. I/O I I/O OD I/O I/O I/O O I OD I/O I/O I I/O I/O O O O I/O I/O O O I O O O Description PCI bus grant signal (from PCI bus arbiter) PCI initialization device select PCI system interrupt A. This is an open drain signal. PCI initiator-ready signal PCI parity signal PCI data-parity-error signal PCI master bus request (to PCI bus arbiter) PCI system reset PCI system-error signal. This is an open drain signal. PCI stop signal PCI target-ready signal 50-MHz system clock (from PHY chip) Phy-link bidirectional control lines Phy-link bidirectional data lines Phy-link request signal External RAM chip select External ROM chip select External serial EEPROM data clock External serial EEPROM read/write data line Test MUX out Zoom port data-valid signal Zoom port external clock input Zoom port horizontal-sync output Zoom port pixel clock Zoom port vertical-sync output
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
system block diagram
1394 Peripheral Devices
Personal Computer 1394 CD ROM Serial EEPROM PCI Data Bus 1394 Laser Printer
PCILynx-to-Phy Interface PCILynx (TSB12LV21A)
1394 3 Port Physical Layer Interface
1394 Desktop Camera
AUX Port Local Bus
1394 Digital VCR
Flash PROM (RPL ROM)
DMA Channel Control (SRAM)
User Defined Function (AUX)
ZV Port (Video)
1394 Video Cable Set-Top Box
PCI Host Bridge
Host Local Bus
Host CPU PCI Agent
Local Memory
PCI Agent
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
functional block diagram
seeprom_data seeprom_clk 32 pci_ad31 - pci_ad0 pci_cbez3 - pci_cbez0 pci_par pci_framez pci_irdyz pci_trdyz pci_devselz pci_stopz pci_idselz pci_perrz pci_serrz pci_reqz pci_gntz pci_clk pci_resetz pci_intaz Serial EPROM Interface 4 aux_clk aux_rstz aux_intz
/
4
/
PCI Master Local Bus Interface Logic PCI Slave
/
16
gpio_data3 - gpio_data0 aux_adr15 - aux_adr0
/
16
/
RAM ROM AUX ZV 2
aux_data15 - aux_data0 aux_oez
/
3
aux_wez1 - aux_wez0 aux_rdy
/
PCI Configuration Control and Status Registers 3
zv_hsync, zv_vsync, zv_pix_clk zv_data_valid
/
aux_csz, rom_csz, ram_csz zv_ext_clk
PCI Bus Logic DMA Engine
DMA Control and Status Registers
DMA Logic
General Receiver FIFO
Asynchronous Transmit FIFO
Isosynchronous Transmit FIFO FIFO Logic
Pointer Address Mapping Logic
FIFO Control and Status Registers
1394 Link Layer Control (LLC) Logic Cycle Timer 1394 Packet Transmit Control Logic CRC Logic Parallel-to-Serial Cycle Monitor 1394 Packet Receive Control Logic Serial-to-Parallel
2
/
8 Phy-Link Interface Logic
phy_ctl0 - phy_ctl1 phy_data0 - phy_data7 phy_clk50 phy_lreq link_cyclein link_cycleout
1394 LLC Control and Status Registers
/
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC(3V) (VCC = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.0 V Supply voltage range, VCC(5V) (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC(5v) +0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC(5v) + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage VCC voltage, Input voltage, VI VCC = 3 V VCC = 5 V 3 4.5 0 0 NOM 3.3 5 MAX 3.6 5.5 VCC(5v) VCC(3V) VCC(5V) UNIT V V V V
AAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA AAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A
Output voltage, VO High-level input voltage, VIH Low-level input voltage, g, VIL Rise time, input,tr time input t Fall time, input,tf time input t PCI terminals 0.475 x VCC(3V) 2 All other terminals PCI terminals PCI terminals PCI terminals VCC(5V) 0.325 VCC(3V) All other terminals All other terminals All other terminals 0.8 6 6 6 6 V ns ns Junction temperature, TJ 0 115 C 8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PCI interface switching characteristics, see Figure 1
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAA A A A A A AAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA A A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A AAAA A A AAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A AAAA A A A AAA A A A A A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A A A A AAAA A A AA A AAAAA A A A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAA A A A A A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A
PARAMETER MEASURED 40% to 40% 40% to 40% 40% to 40% 40% to 40% TEST CONDITION MIN 7 0 2 TYP MAX UNIT ns ns ns ns tsu1 th1 Setup time, pci_xx low or high to pci_clk high Hold time, pci_clk high to pci_xx low or high, pci_gntz low or high Delay time, pci_clk high to pci_xx low or high td1 tsu2 11 Setup time, pci_gntz low or high to pci_clk high 10 td2 Delay time, pci_clk high to pci_intaz low or high 40% to 40% 2 13 ns In this case, pci_xx refers to the following signals; pci_ad31-0, pci_cbez3-0, pci_par, pci_framez, pci_irdyz, pci_trdyz, pci_devselz, pci_stopz, pci_idselz, pci_perrz, pci_serrz, pci_reqz.
phy-link interface switching characteristics, see Figure 2
PARAMETER
MEASURED
TEST CONDITION
MIN 4 1 3 5 3
TYP
MAX
UNIT ns ns ns ns ns
tsu3 th2 td3 tsu4
Setup time, phy_xx low or high to phy_clk high
1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V
Hold time, phy_clk high to phy_xx, link_cyclein low or high Delay time, phy_clk high to phy_xx, phy_lreq low or high Setup time, phy_clk high to link_cyclein low or high
11
td4 Delay time, phy_clk high to lynk_cycleout low or high 1.3 V to 1.3 V In this case, phy_xx refers to the following bidirectional signals; phy_ctl1-0, phy_data7-0.
13
local bus switching characteristics, see Figure 3
PARAMETER
MEASURED
TEST CONDITION
MIN 0 0
TYP
MAX
UNIT ns ns ns
td5 td6 td7 td8 td9
Delay time, aux_clk high to aux_adr, aux_data15-0 (write), aux_oez valid
1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V
15 20
Delay time, aux_clk high to rom_csz, ram_csz, aux_csz valid Delay time, aux_wez0, aux_wez1 high (deasserted) to aux_adr, aux_data15-0 (write), aux_oez, rom_csz, ram_csz, aux_csz valid Delay time, aux_clk low to aux_wez0, aux_wez1 low (asserted)
0.5
1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V
0 0 2 5
10 10 15
ns ns ns ns
Delay time, aux_clk high to aux_wez0, aux_wez1 high (deasserted) Delay time, aux_clk high to gpio_data3-0 valid
td10 tsu5 tsu6 th3
Setup time, aux_adr, adr_data15-0 (write), auxoez, rom_csz, ram_csz, aux_csz valid before aux_wez0, aux_wez1 low (asserted) Setup time, aux_data15-0 (read), aux_rdyz, gpio_data3-0 valid before aux_clk high Hold time, aux_data15-0 (read), auxrdyz, gpio_data3-1 invalid after aux_clk high
1.3 V to 1.3 V 1.3 V to 1.3 V
10 0
ns ns
These signals are asserted asynchronously when a ZOOM port transfer imediately preceeds the local bus transfer. In all cases, the setup time to aux_wez and the number of waitstates remain the same.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAA AA A AAA A A A A A AAAA A A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA A A AAA A A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAA A A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA
PARAMETER MEASURED TEST CONDITION MINAAA TYPAAA MAXAAA UNIT 12 14 10 14 -1 -1 25 14 10 25 14 ns ns ns ns ns ns ns ns ns ns ns tsu7 th4 Setup time, zv_hsync low, zv_vsync, zv_data_valid high before zv_pix_clk high Hold time, zv_hsync high, zv_vsync, zv_data_valid low after zv_pix_clk low 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V 1.3 V to 1.3 V See Figure 4 See Figure 4 See Figure 4 See Figure 4 See Figure 5 See Figure 5 See Figure 6 See Figure 6 See Figure 6 See Figure 6 See Figure 6 tsu8 th5 td11 Setup time, aux_data7-0 valid before zv_pix_clk high or low Hold time, aux_data7-0 valid after zv_pix_clk high or low Delay time, zv_hsync low, zv_vsync, zv_data_valid high after zv_pix_clk low Delay time, aux_data7-0 invalid after zv_pix_clk low Setup time, zv_hsync low before zv_pix_clk high Hold time, zv_hsync high after zv_pix_clk high 3 5 td12 tsu9 th6 tsu10 tsu11 th7 Setup time, zv_vsync high before zv_pix_clk high Setup time, aux_data7-0 valid, zv_data_valid high before zv_pix_clk high Hold time, aux_data7-0 valid, zv_data-valid low after zv_pix_clk high 10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PARAMETER MEASUREMENT INFORMATION
pci_clk
td1 tsu1 pci_xx (Bidirectional (see Note A) td2 pci_intaz th1
tsu2
th1
pci_gntz NOTE A: In this case, pci_xx refers to the following bidirectional signals; pci_ad31-0, pci_cbez3-0, pci_par, pci_framez, pci_irdyz, pci_trdyz, pci_devselz, pci_stopz, pci_idselz, pci_perrz, pci_serrz, pci_reqz.
Figure 1. PCI Interface Timing Waveforms
phy_clk
td3 tsu3 phy_xx (Bidirectional (see Note A) td3 th2
phy_lreq
td4
link_cycleout
tsu4
th2
link_cyclein NOTE A: In this case, phy_xx refers to the following bidirectional signals; phy_ctl1-0, phy_data7-0.
Figure 2. Phy-Link Interface Timing Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PARAMETER MEASUREMENT INFORMATION
OUTPUTS aux_clk td5 DATA VALID
td6
rom_csz ram_csz aux_csz
DATA VALID
tsu5 td8
td9
aux_wez0 aux_wez1 td10 gpio_data7 - 0 Wait States = 0 DATA VALID Wait States > 0
INPUTS
tsu6 th3 DATA VALID DATA VALID DATA VALID
aux_data
aux_rdyz
gpio_data7 - 0
NOTE A: These signals are asserted asynchronlusly when a ZOOM port transfer immediately preceeds the local bus transfer. In all cases, the setup time to aux_wez and the number of waitstates reamins valid.
Figure 3. Local Bus Timing Waveforms
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII
td7 td9
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
IIIIIIIIII IIIIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIII IIIIII IIIIII
aux_adr15 - 0 aux_data15 - 0 (write) aux_oez (see Note A)
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns Internal Clock Source 15 ns
internal zv_pix_clk
zv_pix_clk (gated, 8 bit) tsu7 zv_hsync th4
zv_vsync
zv_data_valid
tsu8 aux_data15-0 (Write)
th5
tsu8
th5
8-BIT DATA VALID
8-BIT DATA VALID
NOTES: A. The data is in 8-bit mode and zv_pix_clk is in divide-by-2 mode. B. The timing for these waveforms is for write access to zoom address space. C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to zv_pix_clk at other times. D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with invert_zv_clk = 0. E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 4. Zoom Video IF Timing Waveforms (8 Bit, Divide-By-2 Mode)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIIIIII IIIIIIII
IIIIII IIIIII
13
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Internal zv_pix_clk
zv_pix_clk (gated, 16 bit) td11 zv_hsync td11
zv_vsync
zv_data_valid
td12
td12 16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-1 mode. B. The timing for these waveforms is for write access to zoom address space. C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to zv_pix_clk at other times. D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with invert_zv_clk = 0.
Figure 5. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-1 Mode)
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIIII IIIIII
IIII IIII
aux_data15-0 (16 bit only)
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns Internal Clock Source Internal zv_pix_clk (see Note A) zv_pix_clk (gated, 16 bit) tsu9 zv_hsync tsu10 zv_vsync th6 15 ns
zv_data_valid tsu9 aux_data15-0 (Write) th7
16-BIT DATA VALID
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-2 mode. B. The timing for these waveforms is for write access to zoom address space. C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to zv_pix_clk at other times. D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk terminal. The polarity shown in this figure is with invert_zv_clk = 0. E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 6. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-2 Mode)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII
15
IIIIIIIII IIIIIIIII
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
APPLICATION INFORMATION power supply sequencing
Turning power supplies on and off within a mixed 5-V/3.3-V system is an important consideration. A few basic rules need to be observed to avoid damaging PCILynx devices. Check with the manufacturers of all components used in the 3.3-V to 5-V interface to ensure that no unique device characteristics exist that would lead to more restrictive rules.
D
When the 3.3-V supply is turned on before turning on the 5-V supply. PCILynx output buffers in a logic 1 state can supply large amounts of current through their clamp diodes to the 5-V supply terminals (5V VCC ). This can lead to excessive power dissipation and violation of current density limits. However, if the 5-V supply is turned on before the 3.3-V supply, the maximum drain-to-gate voltage of the n-channel transistors in the 5-V tolerant buffers exceeds the recommended value and the effects of channel-hot carries can be accelerated. When turning on the power supply, all 3.3-V and 5-V supplies should start ramping up from 0 V and reach 95% of their end-point values within a 25-ms time window. All bus contention between the PCILynx and external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping is to ramp the 3.3-V supply followed by the 5-V supply. This order is not mandatory, but it allows a larger cumulative number of power-supply events than the reverse order. When turning off the power supply, all 3.3-V and 5-V supplies should start ramping down from steady state values and reach 5% of these values within a 25-ms window. All bus contention between the PCILynx and external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping is to ramp down the 5-V supply followed by the 3.3-V supply. This order is not mandatory, but it allows a larger cumulative number of power-supply off events than the reverse order. A cumulative total of 250 seconds of power supply turn-on and turn-off events is allowed during the operating lifetime of the PCILynx under worst-case conditions. Worst-case conditions are where the 5-V supply is ramped up before the 3.3-V supply and the 3.3-V supply is ramped down before the 5-V supply. If the maximum time window of the 25 ms is used, a total of 10,000 power supply on or off events can occur as long as the 25-ms time window is observed. An additional precaution must be observed when the PCILynx is connected to a 5-V IEEE 1394 physical-layer device that is powered from the 1394 cable. In this case, it is possible for the physical-layer device to have power while the PCILynx does not. It is essential that the physical-layer device must not supply a high signal on any terminal that connects to the PCILynx while the PCILynx power is off. This is normally achieved through the use of the link-power status terminal on the physical-layer device.
D
D
D
D
If any of these precautions and guidelines are not followed, the PCILynx device can experience possible failures related to overheating, accumulation of channel-hot carriers, and/or metal migration due to excessive current density.
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB12LV21A (PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 - APRIL 1997
MECHANICAL INFORMATION
PGF (S-PQFP-G176)
132 89
PLASTIC QUAD FLATPACK
133
88 0,27 0,17
0,08 M
0,50
0,13 NOM 176 45
1 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 1,45 1,35
44
Gage Plane
0,05 MIN
0,25 0- 7 0,75 0,45
Seating Plane 1,60 MAX 0,08 4040134 / B 03/95 NOTES: F. All linear dimensions are in millimeters. G. This drawing is subject to change without notice. H. Falls within JEDEC MO-136
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SLLS273

	To Download SLLS273 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .