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SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
D D D D D D D D D D
9 Channels for the Data and Control Paths of the Small Computer Systems Interface (SCSI) Supports Single-Ended and Low-Voltage Differential (LVD) SCSI CMOS Input Levels ('LVDM976) or TTL Input Levels ('LVDM977) Available Includes DIFFSENS Comparators on CDE0 Single-Ended Receivers Include Noise Pulse Rejection Circuitry Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch Low Disabled Supply Current 7 mA Maximum Power-Up/Down Glitch Protection Bus is High-Impedance With VCC = 1.5 V Pin-Compatible With the SN75976ADGG High-Voltage Differential Transceiver
DGG PACKAGE (TOP VIEW)
description
The SN75LVDM976 and SN75LVDM977 have nine transceivers for transmitting or receiving the signals to or from a SCSI data bus. They offer electrical compatibility to both the single-ended signaling of X3.277:1996-SCSI-3 Parallel Interface (Fast-20) and the new low-voltage differential signaling method of proposed standard 1142-D SCSI Parallel Interface - 2 (SPI-2).
INV/NON GND GND 1A 1DE/RE 2A 2DE/RE 3A 3DE/RE 4A 4DE/RE VCC GND GND GND GND GND VCC 5A 5DE/RE 6A 6DE/RE 7A 7DE/RE 8A 8DE/RE 9A 9DE/RE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CDE2 CDE1 CDE0 9B+ 9B- 8B+ 8B - 7B+ 7B - 6B+ 6B - VCC GND GND GND GND GND VCC 5B+ 5B - 4B+ 4B - 3B+ 3B - 2B+ 2B - 1B+ 1B -
The differential drivers are nonsymmetrical. The SCSI bus uses a dc bias on the line to allow terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD SCSI driver's output characteristics become nonsymmetrical. In other words, there is more assertion current than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the 'LVDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.
AVAILABLE OPTIONS PACKAGE TA TSSOP (DGG) CMOS INPUT LEVELS SN75LVDM976DGG SN75LVDM976DGGR TSSOP (DGG) TTL INPUTS LEVELS SN75LVDM977DGG SN75LVDM977DGGR
0C to 70C
The R suffix designates a taped and reeled package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
description (continued)
The signal symmetry requirements of the LVD-SCSI bus mean you can no longer obtain logical inversion of a signal by simply reversing the differential signal connections. This requires the ability to invert the logic convention through the INV/NON terminal. This input would be a low for SCSI controllers with active-high data and high for active-low data. In either case, the B+ signals of the transceiver must be connected to the SIGNAL+ line of the SCSI bus and the B- of the transceiver to the SIGNAL- line. The CDE0 input incorporates a window comparator to detect the status of the DIFFSENS line of a SCSI bus. This line is below 0.5 V, if using single-ended signals, between 1.7 V and 1.9 V if low-voltage differential, and between 2.4 V and 5.5 V if high-voltage differential. The outputs assume the characteristics of single-ended or LVD accordingly or place the outputs into high-impedance, when HVD is detected. This, and the INV/NON input, are the only differences to the trade-standard function of the SN75976A HVD transceiver. Two options are offered to minimize the signal noise margins on the interface between the communications controller and the transceiver. The SN75LVDM976 has logic input voltage thresholds of about 0.5 VCC. The SN75LVDM977 has a fixed logic input voltage threshold of about 1.5 V. The input voltage threshold should be selected to be near the middle of the output voltage swing of the corresponding driver circuit. The SN75LVDM976 and SN75LVDM977 are characterized for operation over an free-air temperature range of TA = 0C to 70C.
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SLLS292B - APRIL 1998 - REVISED JANUARY 2000
logic diagram (positive logic)
CDE1 LVD B INV/NON SE + - - + A 2.4 V (Internal) CDE0 0.5 V (Internal)
1DEb 1DE/RE 1A 1DEb 1DEa 1REb 1B - 1DEa 1REa 1REb 1REa 1B +
2A 2DE/RE 3A 3DE/RE 4A 4DE/RE INV/NON CDE2
Channel 2 Channel 3 Channel 4 SE LVD
2B - 2B + 3B - 3B + 4B - 4B +
5A 5DE/RE 6A 6DE/RE 7A 7DE/RE 8A 8DE/RE INV/NON 9DE/RE 9DEb 9DEa
Channel 5 Channel 6 Channel 7 Channel 8 SE LVD 9DEb 9REb
5B - 5B + 6B - 6B + 7B - 7B + 8B - 8B +
9A
9B - 9DEa 9REa 9B +
9REb 9REa
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logic diagrams and function tables
FUNCTION TABLE Inputs B- A DE/RE VID B+ (B+ - B-) VID 30 mV - 30 mV < VID < 30 mV VID -30 mV Open circuit NA DE/RE L L L L H H A NA NA NA NA L H B+ Z Z Z Z H L Outputs B- Z Z Z Z L H A L ? H ? Z Z
Figure 1. Inverting LVD Transceiver
NA
FUNCTION TABLE A DE/RE B- B- H L Open circuit B+ NA NA Inputs DE/RE L L L H H A NA NA NA L H B+ L L L L L Outputs B- Z Z Z H L A L H ? Z Z
Figure 2. Inverting Single-Ended Transceiver
A
B-
FUNCTION TABLE Input A L H L L Outputs B+ B- H L
B+
Figure 3. Inverting Single-Ended Driver
FUNCTION TABLE B- A B+ Input A L H Outputs B+ H L B- L H
Figure 4. Inverting LVD Driver
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SLLS292B - APRIL 1998 - REVISED JANUARY 2000
logic diagrams and function tables (continued)
FUNCTION TABLE B- A B+ Input A L H L H Outputs B+ B- H L
Figure 5. Noninverting LVD Driver
FUNCTION TABLE B- VID B+ Inputs (B+ - B -) VID 30 mV - 30 mV < VID < 30 mV VID -30 mV Open circuit NA DE/RE L L L L H H A NA NA NA NA L H B+ Z Z Z Z L H Outputs B- Z Z Z Z H L A H ? L ? Z Z
A DE/RE
Figure 6. Noninverting LVD Transceiver
NA
A DE/RE
B- Inputs B- H B+ L Open Circuit NA NA
FUNCTION TABLE Outputs A NA NA NA L H B+ L L L L L B- Z Z Z L H A H L ? Z Z
DE/RE L L L H H
Figure 7. Noninverting Single-Ended Transceiver
A
B- FUNCTION TABLE Input B+ A L H L L Outputs B+ B- L H
Figure 8. Noninverting Single-Ended Driver
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SLLS292B - APRIL 1998 - REVISED JANUARY 2000
1A 1DE/RE
1B- 1B+ 1A 1DE/RE
1B- 1B+ 1A
1B- 1B+
2A 2DE/RE
2B- 2B+ 2A 2DE/RE
2B- 2B+ 2A
2B- 2B+
3A 3DE/RE
3B- 3B+
3A 3DE/RE
3B- 3B+
3A
3B- 3B+
4A 4DE/RE
4B- 4B+ 4A 4DE/RE
4B- 4B+ 4A
4B- 4B+
5A 5DE/RE
5B- 5B+
5A
5B- 5B+
5A 5DE/RE
5B- 5B+
6A 6DE/RE
6B- 6B+ 6A
6B- 6B+ 6A 6DE/RE
6B- 6B+
7A 7DE/RE
7B- 7B+
7A
7B- 7B+
7A 7DE/RE
7B- 7B+
8A 8DE/RE
8B- 8B+ 8A
8B- 8B+ 8A 8DE/RE
8B- 8B+
9A 9DE/RE
9B- 9B+
9A 9DE/RE
9B- 9B+
9A 9DE/RE
9B- 9B+
Control Inputs CDE0 0.7 V < VI < 1.9 V L INV/NON CDE1 L CDE2 L (a)
Control Inputs CDE0 0.7 V < VI < 1.9 V L INV/NON CDE1 L CDE2 H (b)
Control Inputs CDE0 0.7 V < VI < 1.9 V L INV/NON CDE1 H CDE2 L (c)
Figure 9. Logic Diagrams
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1A
1B- 1B+
1A 1DE/RE
1B- 1B+
1A 1DE/RE
1B- 1B+
2A
2B- 2B+
2A 2DE/RE
2B- 2B+
2A 2DE/RE
2B- 2B+
3B- 3B- 3A 3B+ 3A 3DE/RE 3B+ 3A 3DE/RE
3B- 3B+
4A
4B- 4B+
4A 4DE/RE
4B- 4B+
4A 4DE/RE
4B- 4B+
5A
5B- 5B+
5A 5DE/RE
5B- 5B+
5A
5B- 5B+
6A
6B- 6B+
6A 6DE/RE
6B- 6B+
6A
6B- 6B+
7A
7B- 7B+
7A 7DE/RE
7B- 7B+
7A
7B- 7B+
8A
8B- 8B+ 9B- 9B+
8A 8DE/RE
8B- 8B+
8A
8B- 8B+
9A 9DE/RE
9A 9DE/RE
9B- 9B+
9A 9DE/RE
9B- 9B+
Control Inputs CDE0 0.7 V < VI < 1.9 V L INV/NON CDE1 H CDE2 H (a)
Control Inputs CDE0 0.7 V < VI < 1.9 V H INV/NON CDE1 L CDE2 L (b)
Control Inputs CDE0 0.7 V < VI < 1.9 V H INV/NON CDE1 L CDE2 H (C)
Figure 10. Logic Diagrams
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SLLS292B - APRIL 1998 - REVISED JANUARY 2000
1A 1A 1B- 1B+ 1DE/RE
1B-
1A 1DE/RE
1B-
1B+ 2A 2A 2B- 2B+ 2B+ 3B- 3B+ 3B+ 4A 4A 4B- 4B+ 4B+ 5A 5A 5B- 5B+ 5B+ 6A 6A 6B- 6B+ 6B+ 7A 7A 7B- 7B+ 7B+ 8A 8A 8B- 8B+ 8B+ 9A 9A 9DE/RE 9B- 9B+ 9B+ Control Inputs CDE0 VI < 0.5 V L INV/NON CDE1 L CDE2 L (b) Control Inputs CDE0 VI < 0.5 V INV/NON L CDE1 L CDE2 H (c) 9DE/RE 9B- 9A 9DE/RE 8DE/RE 8B- 8A 7DE/RE 7B- 7A 6DE/RE 6B- 6A 5DE/RE 5B- 5A 4DE/RE 4B- 4A 4DE/RE 3A 3DE/RE 3B- 3A 3DE/RE 2DE/RE 2B- 2A 2DE/RE
1B+ 2B-
2B+ 3B-
3A
3B+ 4B-
4B+ 5B- 5B+
6B- 6B+
7B- 7B+
8B- 8B+
9B-
9B+
Control Inputs CDE0 0.7 V < VI < 1.9 V H INV/NON CDE1 H CDE2 H (a)
Figure 11. Logic Diagrams
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1A
1B- 1B+
1A
1B- 1B+
1A 1DE/RE
1B-
1B+ 2A 2B- 2B+ 2A 2B- 2B+ 2B+ 3A 3B- 3B+ 4A 3A 3B- 3B+ 3B+ 4B- 4B+ 5A 5DE/RE 5B+ 6A 6DE/RE 6B+ 7A 7DE/RE 7B+ 8A 8DE/RE 8B+ 9A 9DE/RE 9B+ Control Inputs CDE0 VI < 0.5 V L INV/NON CDE1 H CDE2 L (a) Control Inputs CDE0 VI < 0.5 V INV/NON L CDE1 H CDE2 H (b) 9B- 9A 9DE/RE 9B+ Control Inputs CDE0 VI < 0.5 V INV/NON H CDE1 L CDE2 L (c) 8B- 8A 7B- 7A 6B+ 6B+ 7B- 7B+ 7B+ 8B- 8B+ 8B+ 9B- 9A 9DE/RE 9B+ 9B- 8A 8DE/RE 8B- 7A 7DE/RE 7B- 6B- 6A 5B+ 5B+ 6B- 6A 6DE/RE 6B- 4A 4B- 4B+ 4B+ 5B- 5A 5B- 5A 5DE/RE 5B- 4A 4DE/RE 4B- 3A 3DE/RE 3B- 2A 2DE/RE 2B-
Figure 12. Logic Diagrams
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1A 1DE/RE
1B-
1A
1B- 1B+
1A
1B- 1B+
1B+ 2A 2DE/RE 2B+ 2B+ 3A 3DE/RE 3B+ 3B+ 4A 4DE/RE 4B+ 4B+ 5A 5B- 5B+ 5B+ 6A 6B- 6B+ 6B+ 7A 7B- 7B+ 7B+ 8A 8B- 8B+ 8B+ 9A 9DE/RE 9B+ Control Inputs CDE0 VI < 0.5 V H INV/NON CDE1 L CDE2 H (a) Control Inputs CDE0 VI < 0.5 V H INV/NON CDE1 H CDE2 L (b) 9B- 9A 9DE/RE 9B+ Control Inputs CDE0 VI < 0.5 V H INV/NON CDE1 H CDE2 H (b) 9B- 9A 9DE/RE 9B+ 9B- 8A 8DE/RE 8B+ 8B- 8A 8B- 7A 7DE/RE 7B+ 7B- 7A 7B- 6A 6DE/RE 6B+ 6B- 6A 6B- 5A 5DE/RE 5B+ 5B- 5A 5B- 4B+ 4B- 4A 4B- 4A 4B- 3B+ 3B- 3A 3B- 3A 3B- 2B+ 2B- 2A 2B- 2A 2B-
Figure 13. Logic Diagrams
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1A High Z High Z
1B- 1B+ High Z
2A High Z High Z
2B- 2B+ High Z
3A High Z High Z
3B- 3B+ High Z
4A High Z High Z
4B- 4B+ High Z
5A High Z High Z
5B- 5B+ High Z
6A High Z High Z
6B- 6B+ High Z
7A High Z High Z
7B- 7B+ High Z
8A High Z High Z
8B- 8B+ High Z
9A High Z High Z
9B- 9B+ High Z
Control Inputs CDE0 VI > 2.5 V X INV/NON CDE1 X CDE2 X
Figure 14. Logic Diagrams
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input and output equivalent schematic diagrams
CDE1, CDE2, DE/RE Inputs VCC VCC 10uA Input 10uA Input A and INV/NON Inputs
CDE0 Input A Output VCC VCC
Input A
B+ Input Iref Iref 37 BP
B- Input
37 BN
Iref 113
Iref 113
VCC 15 15
VCC 15 113
VCC
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Terminal Functions
TERMINAL NAME 1A - 9A NO. 4,6,8,10, 19,21,23, 25,27 29,31,33, 35,37,46, 48,50,52 30,32,34, 36,38,47, 49,51,53 'LVDM976 Logic Level CMOS 'LVDM977 Logic Level TTL I/O I/O Termination Pullup DESCRIPTION 1A - 9A carry data to and from the communication controller.
1B - - 9B -
LVD or TTL
LVD or TTL
I/O
None
1B - to 9B - are the signals to and from the data bus. When INV/NON is low, the logic sense is the opposite that of the A input (inverted). When INV/NON is high, the logic sense is the same as the A input (noninverted). When in the LVD mode, 1B+ - 9B+ are signals to or from the data bus and follow the same logic sense as the A input when INV/NON is low (noninverted). The logic sense is opposite that of the A input (inverted) when INV/NON is high. When in single-ended mode, these terminals become a ground connection through a transistor and do not switch. CDE0 is the common driver enable 0. With the driver enabled and the CDE0 input less than 0.5 V, the driver output is single-ended mode. With the driver enabled and the CDE0 input between 0.7 V and 1.9 V the driver output is LVD mode. All drivers are disabled when the input is greater than 2.4 V. CDE1 is the common driver enable 1. When CDE1 is high, drivers 1 - 4 are enabled CDE2 is the common driver enable 2. When CDE2 is high, drivers 5 to 8 are enabled. 1DE/RE - 9DE/RE are direction controls that transmit data to the bus when it is high and CDE0 is below 2.2 V. Data is received from the bus when 1DE/RE - 9DE/RE, CDE1, and CDE2 are low. GND is the circuit ground.
1B+ - 9B+
LVD or GND
LVD or GND
I/O
None
CDE0
54
Trinary
Trinary
Input
None
CDE1 CDE2 1DE/RE - 9DE/RE
55 56 5,7,9,11, 20,22,24, 26,28 2,3,13,14, 15,16,17, 40,41,42, 43,44 1
CMOS CMOS CMOS
TTL TTL TTL
Input Input Input
Pulldown Pulldown Pulldown
GND
NA
NA
Power
NA
INV/NON
CMOS
CMOS
Input
Pullup
A high-level input to INV/NON inverts the logic to and from the A terminals. (i.e., the voltage at A terminal and the corresponding B - terminal are in phase.)
Supply voltage
VCC
12,18,39, 45
NA
NA
Power
NA
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SLLS292B - APRIL 1998 - REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (A, INV/NON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V (DE/RE, B+, B-, CDE0, CDE1, CDE2) . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.25 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65_C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND unless otherwise noted. DISSIPATION RATING TABLE PACKAGE DGG TA 25C POWER RATING 978 mW DERATING FACTOR ABOVE TA = 25C 10.8 mW/C TA = 70C POWER RATING 492 mW
recommended operating conditions (see Figure 15)
MIN Supply voltage, VCC High level input voltage, VIH voltage High-level Low-level Low level input voltage VIL voltage, Differential input voltage, |VID| Common-mode input voltage, VIC Differential output voltage bias, VOD(bias) High-level High level output current IOH current, Low-level Low level output current IOL current, Differential load impedance, ZL Operating free-air temperature, TA Differential Single-ended driver Receiver Single-ended driver Receiver 40 0 SN75LVDM976 SN75LVDM977 SN75LVDM976 SN75LVDM977 Differential receiver 0.03 0.7 -100 4.75 0.7 VCC 2 0.3 VCC 0.8 3.6 1.8 -125 -7 -2 48 2 65 70 NOM 5 MAX 5.25 UNIT V V V V V mV mA mA C
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IIH IIL High-level High level input current Low-level Low level input current CDE1 and CDE2 INV/NON CDE1 and CDE2 INV/NON Disabled LVD drivers enabled, ICC Supply current Single-ended drivers enabled, LVD receivers enabled, Singled-ended receivers enabled, CI Input capacitance Bus terminal CI Difference in input capacitance between B+ and B- All typical values are at VCC = 5 V, TA = 25C. No load No load No load No load 9.5 0.2 TEST CONDITIONS MIN TYP MAX 50 -50 50 - 50 7 26 10 26 7 pF F mA UNIT A A
VI = 0.2 sin (2 (1E06)t) + 0.5 0.01 V
DIFFSENS (CDE0) receiver electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIT1 VIT2 II Input threshold voltage Input threshold voltage Input current 0 V VI 2.7 V VCC = 0, 0 V VI 2.7 V TEST CONDITIONS MIN 0.5 1.9 TYP 0.6 2.1 MAX 0.7 2.4 1 1 UNIT V A A
II(OFF) Power-off input current All typical values are at VCC = 5 V, TA = 25C.
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LVD driver electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VI(1) = 0.96 V, VI(2) = 0.53 V, , , See Figure 16 , , VI(1) = 1.96 V, VI(2) = 1.53 V, See Figure 16 VI(1) = 0.96 V, VI(2) = 0.53 V, See Figure 16 VI(1) = 1.96 V, VI(2) = 1.53 V, See Figure 16 MIN 270 0.69|VOD(L) |+ 50 270 0.69|VOD(L) |+ 50 - 260 - 260 1.1 VI(1) = 1.41 V, VI(2) = 0.99 V, See Figure 17 - 400 - 400 1.2 50 TYP 460 500 MAX 780 1.45|VOD(L) |- 65 780 1.45|VOD(L) |- 65 - 640 mV - 640 1.5 120 V mV UNIT
VOD(H)
Driver differential high-level outg put voltage
VOD(L)
Driver differential low-level output voltage Steady-state common-mode output voltage Change in steady-state commonmode output voltage between logic states Peak-to-peak common-mode output voltage High-level High level input current Low level input current Low-level Power-off output current Short-circuit output current A DE/RE A DE/RE
VOC(SS) VOC(SS) VOC(PP) IIH IIL IO(OFF) IOS
mV
80 VIH = 3.3 V ('976) ( ) VIH = 2 V ('977) VIL = 1.6 V ( ('976) ) VIL = 0.8 V ('977) VCC = 0, 0 V VO 2.5 V 0 V VO 2.5 V -7
150
mV A A A mA A
50 - 30 8 1 24 1
IOZ High-impedance output current VO = 0 or 2.5 V All typical values are at VCC = 5 V, TA = 25C.
LVD driver switching characteristics over recommended operating conditions (unless otherwise noted) (See Figure 16)
PARAMETER tPLH tPHL tr tf tsk(p) tsk(lim) Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output Differential output signal rise time Differential output signal fall time Pulse skew (|tPHL - tPLH|) Skew limit VCC = 5 V, V 0.99 V VI2 = 0 99 V, VI1 = 1 41 V 1.41 V, 25 C TA = 25C TEST CONDITIONS MIN 2.9 2.9 1 1 3 3 TYP MAX 8.8 8.8 6 6 3.7 5.9 UNIT ns ns ns ns ns ns
tPHZ Propagation delay time, high-level to high-impedance output VI1 = 1.41 V, 50 ns VI2 = 0.99 V, See Figure 18 ten Enable time, receiver to driver 33 ns All typical values are at VCC = 5 V, TA = 25C. tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same ambient temperature.
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* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
single-ended driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VOH High-level High level output voltage B- B output B- output VOL Low-level output voltage B+ A DE/RE A DE/RE B- TEST CONDITIONS IOH = -7 mA, IOH = 0 mA VCC = 5 V, IOL = -25 mA IOL = 25 mA VIH = 3.3 V ( ('976), ), VIH = 2 V ('977) VIL = 1.6 V ( ('976), ), VIL = 0.8 V ('977) VCC = 0, VO = 0 or VCC 0 V VO 5.25 V -7 50 -30 8 1 1 See Figure 19 IOL = 48 mA MIN 2 TYP MAX 3.24 3.7 0.5 -0.5 0.5 UNIT V V V V A A A A
IIH IIL IO(OFF) IOZ
High-level High level input current Low-level Low level input current Power-off output current High-impedance output current
single-ended driver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tr tf tsk(p) tsk(lim) Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output Differential output signal rise time Differential output signal fall time Pulse skew (|tPHL - tPLH|) Skew limit VCC = 5 V, TA = 25C, See Figure 19 TEST CONDITIONS MIN 2.7 2.7 0.5 0.5 TYP MAX 8.2 8.2 4 4 3.4 5.5 UNIT ns ns ns ns ns ns
ten Enable time, receiver to driver 50 ns See Figure 20 tPLZ Propagation delay time, low-level to high-impedance output 30 ns All typical values are at VCC = 5 V, TA = 25C. tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same ambient temperature.
LVD receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- VOH VOL II II(OFF) IIH IIL IOZ Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage Low-level output voltage Input current, B+ or B- Power-off Input current, B+ or B- High-level input current, DE/RE Low-level input current, DE/RE High-impedance output current TEST CONDITIONS See Figure 21 IOH = -2 mA IOL = 2 mA VI = 0 V to 2.5 V VCC = 0, VI = 0 V to 2.5 V VIH = 3.3 V ('976), VIH = 2 V ('977) VIL = 1.6 V ('976), VIL = 0.8 V ('977) VO = 0 or VCC 8 30 3.7 0.5 1 1 50 MIN TYP MAX 30 -30 UNIT mV mV V V A A A A A
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* DALLAS, TEXAS 75265
17
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
LVD receiver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tsk(p) tr tf tsk(lim) tPHZ tPLZ Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output Pulse skew (|tPHL - tPLH|) Output signal rise time Output signal fall time Skew limit Propagation delay time, high-level to high-impedance output Propagation delay time, low-level to high-impedance output See Figure 18 VCC = 5 V, TA = 25C, See Figure 21 TEST CONDITIONS MIN 4.5 4.5 TYP MAX 10 10 3 8 8 5.5 42 20 UNIT ns ns ns ns ns ns ns ns
ten Enable time, driver to receiver 26 ns All typical values are at VCC = 5 V, TA = 25C. tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same ambient temperature.
single-ended receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- VOH VOL II II(OFF) IIH IIL IOZ Positive-going input voltage threshold Negative-going input voltage threshold High-level output voltage Low-level output voltage Input current Power-off Input current High-level input current Low-level input current High-impedance output current B- B- DE/RE DE/RE B- B- IOH = -2 mA IOL = 2 mA VI = 0 to VCC VCC = 0 V, VI = 0 to 5.25 V VIH = 3.3 V ('976), VIH = 2 V ('977) VIL = 1.6 V ('976), VIL = 0.8 V ('977) VO = 0 or VCC 8 -30 1 3.7 TEST CONDITIONS MIN TYP 1.6 1.1 4.6 0.3 0.5 1 1 50 MAX 1.9 UNIT V V V V A A A A A
single-ended receiver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tsk(p) tr tf tsk(lim) tPHZ tPLZ Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output Pulse skew (|tPHL - tPLH|) Output signal rise time Output signal fall time Skew limit Propagation delay time, high-level to high-impedance output Propagation delay time, low-level to high-impedance output See Figure 20 VCC = 5 V, TA = 25C, See Figure 22 TEST CONDITIONS MIN 7 7 TYP MAX 12.5 12.5 3.5 8 8 5.5 20 30 UNIT ns ns ns ns ns ns ns ns
ten Enable time, driver to receiver 48 ns tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same ambient temperature.
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
II B+ A IOB- VI B- VOB- VOD VOB+ VOC V OB) IOB+
) VOB*
2
Figure 15. Voltage and Current Definitions
50
100 Input 5V 1.3 V Open Open 0 V or 5 V A DE/RE CDE0 CDE1 CDE2 INV/NON B- CL = 10 pF VOD B+ CL = 10 pF 100 V2 + - 75 V1 + -
INPUT
0.7 VCC ('976) 2 V ('977) 0.3 VCC ('976) 0.8 V ('977)
Solid line is INV/NON at 0 V. Dashed line is INV/NON at 5 V.
tPLH
tPHL
100% OUTPUT 0V VOD(L) 20% 0% tf tr VOD(H) 80%
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns 5 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 16. Differential Output Signal Test Circuit, Timing, and Voltage Definitions
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19
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1 50 100
Input 5V 1.3 V Open Open 0 V or 5 V
A DE/RE CDE0 CDE1 CDE2 INV/NON
B-
37.5
VOC
B+
37.5
CL = 50 pF
100
V2
Input
0.7 VCC ('976) 2 V ('977) 0.3 VCC ('976) 0.8 V ('977) VOC(PP) VOC(SS)
Output
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns 5 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. C. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 17. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1
100 CL = 50 pF V 620 Input 1.3 V Open Open 0 V or 5 V A DE/RE CDE0 CDE1 CDE2 INV/NON CL = 50 pF B- 37.5 VOD B+ CL = 50 pF 37.5
100
V2 TEST CIRCUIT
V at 5 V, INV/NON at 0 V 0.7 VCC ('976) 2 V ('977) Input 50% 0.3 VCC ('976) 0.8 V ('977) ten(d) tPHZ(d) 0.4 V VOD 0V -0.12 V ten(d)
V at 0 V, INV/NON at 5 V 0.7 VCC ('976) 2 V ('977) 50% 0.3 VCC ('976) 0.8 V ('977) tPHZ(d) 0.4 V 0V -0.12 V
ten(d)
ten(r) 5V
ten(d)
ten(r) 5V 1.4 V 0.2 V
VA
1.4 V 0.2 V VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulsewidth = 500 ns 50 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 18. LVD Transceiver Enable and Disable Time Test Circuit and Definitions
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21
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
50
Input 0V 0V Open Open 0 V or 5 V
A DE/RE CDE0 CDE1 CDE2 INV/NON
IO B- CL = 10 pF VO 47 + -
2.5 V
INPUT
0.7 VCC ('976) 2 V ('977) 0.3 VCC ('976) 0.8 V ('977) tPLH tPHL
Solid line is INV/NON at a high-level input. Dashed line is INV/NON at a low-level input.
100% 80% OUTPUT 1.4 V 20% 0% tf tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns 5 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 19. Single-Ended Driver Switching Test Circuit
22
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
CL = 50 pF V 620 VA Input 0V Open Open 0 V or 5 V A DE/RE CDE0 CDE1 CDE2 INV/NON B- CL = 10 pF VB 47 + -
2.5 V
TEST CIRCUIT V and INV/NON at 5 V 0.7 VCC Input 50% 0.3 VCC ten(r) tPHZ(r) V and INV/NON at 0 V 0.7 VCC 50% 0.3 VCC
ten(r)
tPLZ(r)
VOL VA VOL 0.5 V tPLZ(d) ten(d) tPLZ(d) ten(d) 0.5 V
VB VOL 0.5 V VOLTAGE WAVEFORMS NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulsewidth = 500 ns 50 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 0.5 V VOL
Figure 20. Single-Ended Transceiver Enable and Disable Timing Measurements
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* DALLAS, TEXAS 75265
23
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
IIB+ 50
IO VIB VID
50 VIB- 0V 1.3 V Open Open 0 or 5 V DE/RE CDE0 CDE1 CDE2 INV/NON TEST CIRCUIT VIB VIB- IIB-
CL = 15 pF
VO
1.4 V 1V 0.4 V
VID
0V -0.4 V tPHL 80% 20% tf VOLTAGE WAVEFORMS tr tPLH VOH 50% VOL Solid line is INV/NON at a high-level input. Dashed line is INV/NON at a low-level input.
VO
NOTES: A. Note: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns 5 ns, Zo = 50 . B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 21. LVD Receiver Switching Characteristic Test Circuit
24
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
Input GND GND Open Open GND or VCC B- DE/RE CDE0 CDE1 CDE2 INV/NON
IO A CL = 15 pF VO
INPUT
2V Solid line is INV/NON at a high-level input. 1.4 V 0.8 V Dashed line is INV/NONat a low-level input.
tPLH
tPHL VOH 100% 80%
OUTPUT -1.4 V
20% VOL 0% tf tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns 5 ns. B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 22. Single-Ended Receiver Timing Test Circuit
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
25
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
APPLICATION INFORMATION
U1 `LVDM976 8.2 k, 1/8 W, 5% CDE0 U2 `LVDM976 CDE0 0.022 F, 6 V, 10% DIFFSENS
U3 `LVDM976 CDE0
Figure 23. Low-Pass Filter for Connecting DIFFSENS to CDE0
26
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* DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B - APRIL 1998 - REVISED JANUARY 2000
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
48 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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Copyright (c) 2000, Texas Instruments Incorporated

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