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 SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
D Low-Voltage Differential 50- Line Drivers D D D D D D D D D D D
and Receivers Signaling Rates up to 500 Mbps Bus-Terminal ESD Exceeds 12 kV Operates From a Single 3.3 V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 340 mV With a 50- Load Valid Output With as Little as 50-mV Input Voltage Difference Propagation Delay Times - Driver: 1.7 ns Typ - Receiver: 3.7 ns Typ Power Dissipation at 200 MHz - Driver: 50 mW Typical - Receiver: 60 mW Typical LVTTL Input Levels Are 5 V Tolerant Driver Is High Impedance When Disabled or With VCC < 1.5 V Receiver Has Open-Circuit Fail Safe Surface-Mount Packaging - D Package (SOIC) - DGK Package (MSOP) ('LVDM179 Only) The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 500 Mbps (per TIA/EIA-644 definition). These circuits are similar to TIA/ EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50- load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.
SN65LVDM179D (Marked as DM179 or LVM179) SN65LVDM179DGK (Marked as M79) (TOP VIEW)
VCC R D GND
1 2 3 4
8 7 6 5
A B Z Y
3 D 2 R
5 6 8 7
Y Z A B
SN65LVDM180D (Marked as LVDM180) (TOP VIEW)
NC R RE DE D GND GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC VCC A B Z Y NC
5 D 4 DE RE 2 R 3
9 10
Y Z
12 11
A B
SN65LVDM050D (Marked as LVDM050) (TOP VIEW) 15
14 13
description
1B 1A 1R RE 2R 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 1D 1Y 1Z DE 2Z 2Y 2D
1D 12 DE 9 2D 3 1R 4 RE 5 2R
1Y 1Z 2Y 2Z 1A 1B 2A 2B
10 11 2 1 6 7
SN65LVDM051D (Marked as LVDM051) (TOP VIEW) 15
14 13
1B 1A 1R 1DE 2R 2A 2B GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 1D 1Y 1Z 2DE 2Z 2Y 2D
1D 4 1DE 3 1R
1Y 1Z 1A 1B 2Y 2Z 2A 2B
2 1 10 11 12 6 5 7
9 2D 2DE 2R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
description (continued)
The intended application of these devices and signaling techniques is point-to-point and multipoint, baseband data transmission over a controlled impedance media of approximately 100 of characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are characterized for operation from -40C to 85C.
AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) SN65LVDM050D SN65LVDM051D -40C to 85C 40C SN65LVDM179D SN65LVDM180D SMALL OUTLINE (DGK) -- -- SN65LVDM179DGK --
NOTE:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics. Function Tables
SN65LVDM179 RECEIVER INPUTS VID = VA - VB VID 50 mV -50 MV < VID < 50 mV VID -50 mV Open OUTPUT R H ? L H
H = high level, L = low level, ? = indeterminate SN65LVDM179 DRIVER INPUT D L H Open OUTPUTS Y L H L Z H L H
H = high level, L = low level SN65LVDM180, SN65LVDM050, and SN65LVDM051 RECEIVER INPUTS VID = VA - VB VID 50 mV -50 MV < VID < 50 mV VID -50 mV Open X RE L L L L H OUTPUT R H ? L H Z
H = high level, L = low level, Z = high impedance, X = don't care
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
Function Tables (Continued)
SN65LVDM180, SN65LVDM050, and SN65LVDM051 DRIVER INPUTS D L H Open X DE H H H L OUTPUTS Y L H L Z Z H L H Z
H = high level, L = low level, Z = high impedance, X = don't care
equivalent input and output schematic diagrams
VCC VCC VCC 300 k 50 D or RE Input DE Input 7V 300 k 50 7V 10 k 5 Y or Z Output
7V
VCC
VCC
300 k
300 k 5
A Input
B Input 7V 7V 7V
R Output
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Voltage range (Y, Z, A, and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . CLass 3, A:12 kV, B:600 V All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see dissipation rating table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE D8 D14 or D16 DGK TA 25C POWER RATING 725 mW 950 mW 424 mW DERATING FACTOR ABOVE TA = 25C 5.8 mW/C 7.8 mW/C 3.4 mW/C TA = 85C POWER RATING 377 mW 494 mW
220 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage, VID V Common-mode input voltage, VIC (see Figure 6) C Operating free-air temperature, TA 0.1 ID 2 3 2 0.8 0.6 2.4 * V ID 2 NOM 3.3 MAX 3.6 UNIT V V V V
V C
-40
VCC-0.8 85
4
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
device electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER SN65LVDM179 TEST CONDITIONS No receiver load, driver RL = 50 Driver and receiver enabled, no receiver load, driver RL = 50 SN65LVDM180 Driver enabled, receiver disabled, RL = 50 Driver disabled, receiver enabled, no load Disabled ICC Supply current SN65LVDM050 Drivers and receivers enabled, no receiver loads, driver RL = 50 Drivers enabled, receivers disabled, RL = 50 Drivers disabled, receivers enabled, no loads Disabled SN65LVDM051 Drivers enabled, no receiver loads, driver RL = 50 Drivers disabled, No loads MIN TYP 10 10 9 1.7 0.5 19 16 4 0.5 19 4 MAX 15 15 13 5 2 27 24 6 1 27 6 mA mA mA UNIT mA
All typical values are at 25C and with a 3.3 V supply.
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VOD VOD VOC(SS) VOC(SS) VOC(PP) IIH IIL IOS IOZ IO(OFF) CIN Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage between logic states Peak-to-peak common-mode output voltage DE High-level High level input current Low-level Low level input current Short-circuit Short circuit output current High-impedance High impedance output current Power-off output current Input capacitance D DE D VIL = 0 8 V 0.8 VOY or VOZ = 0 V VOD = 0 V VOD = 600 mV VO = 0 V or VCC VCC = 0 V, VO = 3.6 V 3 VIH = 5 V See Figure 3 TEST CONDITIONS RL = 50 , See Figure 1 and Figure 2 MIN 247 -50 1.125 -50 50 -0.5 2 -0.5 2 7 7 1.2 TYP 340 MAX 454 50 1.375 50 150 -20 20 -10 10 10 10 1 1 1 mA A A A pF mV V mV mV A A A A UNIT
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- VOH VOL II II(OFF) IIH IIL IOZ Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage Low-level output voltage Input current (A or B inputs) Power-off input current (A or B inputs) High-level input current (enables) Low-level input current (enables) High-impedance output current See Figure 5 and Table 1 IOH = -8 mA IOL = 8 mA VI = 0 VI = 2.4 V VCC = 0 VIH = 5 V VIL = 0.8 V VO = 0 or 5 V 5 -50 2.4 0.4 -2 -1.2 -11 -3 20 10 10 10 -20 TEST CONDITIONS MIN TYP MAX 50 mV V V A A A A A A pF UNIT
CI Input capacitance All typical values are at 25C and with a 3.3-V supply.
driver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tr tf tsk(p) tsk(o) tsk(pp) tPZH tPZL tPHZ Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Differential output signal rise time Differential output signal fall time Pulse skew (|tpHL - tpLH|) Channel-to-channel output skew Part-to-part skew Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output See Figure 7 RL = 50, CL = 10 pF, F, See Figure 6 TEST CONDITIONS MIN TYP 1.7 1.7 0.6 0.6 250 100 1 6 6 4 10 10 10 MAX 2.7 2.7 1 1 UNIT ns ns ns ns ps ps ns ns ns ns
tPLZ Propagation delay time, low-level-to-high-impedance output 5 10 ns All typical values are at 25C and with a 3.3-V supply. tsk(o) is the maximum delay time difference between drivers on the same device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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SLLS324D - DECEMBER 1998 - REVISED JULY 2000
receiver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tsk(p) tsk(o) tsk(pp) tr tf tPZH tPZL tPHZ Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Pulse skew (|tpHL - tpLH|) Channel-to-channel output skew Part-to-part skew Output signal rise time Output signal fall time Propagation delay time, high-level-to-high-impedance output Propagation delay time, low-level-to-low-impedance output Propagation delay time, high-impedance-to-high-level output See Figure 7 CL = 10 pF, F, See Figure 6 CL = 10 pF, F See Figure 6 TEST CONDITIONS MIN TYP 3.7 3.7 0.1 0.2 1 0.7 0.9 2.5 2.5 7 1.5 1.5 MAX 4.5 4.5 UNIT ns ns ns ns ns ns ns ns ns ns
tPLZ Propagation delay time, low-impedance-to-high-level output 4 ns All typical values are at 25C and with a 3.3-V supply. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION driver
Driver Enable II Y A IOZ Z VI VOZ VOD VOY VOC V OY )V 2 OZ IOY
Figure 1. Driver Voltage and Current Definitions
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SLLS324D - DECEMBER 1998 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION driver (continued)
3.75 k Y Input DA Z 3.75 k VOD 50 + _ 0 Vtest 2.4 V
Input tPHL
2V 1.4 V 0.8 V tPLH
100% 80% Output VOD(H) 0V VOD(L) 20% 0% tf tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Driver Enable Y Input Z VOC CL = 10 pF (2 Places) VOC VOC(PP) VOC(SS) 25 , 1% (2 Places) 3V 0V
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
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SLLS324D - DECEMBER 1998 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION driver (continued)
25 , 1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY VOZ
DE
2V 1.4 V 0.8 V ~1.4 V 1.25 V 1.2 V tPZH tPHZ 1.2 V 1.15 V ~1 V tPZL D at 0.8 V and input to DE D at 2 V and input to DE
VOY or VOZ
VOZ or VOY
tPLZ NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION receiver
A V IA )V 2 VIA VIC B VIB VO IB VID R
Figure 5. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES (V) VIA 1.225 1.175 2.375 2.325 0.05 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.175 1.225 2.325 2.375 0 0.05 0.9 1.5 1.8 2.4 0 0.6 RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) VID 50 -50 50 -50 50 -50 600 -600 600 -600 600 -600 RESULTING COMMONMODE INPUT VOLTAGE (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3
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SLLS324D - DECEMBER 1998 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION receiver (continued)
VID VIA VIB CL 10 pF VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
-0.4 V tPHL tPLH VOH 1.4 V 0.4 V tf tr VOL
VO
2.4 V
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION receiver (continued)
1.2 V B 500 A Inputs RE CL 10 pF VO
+ -
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST
A 1V
2V RE 1.4 V 0.8 V tPZL tPZL tPLZ 2.5 V R VOL +0.5 V 1.4 V VOL 0V VTEST
A 1.4 V
2V RE 1.4 V 0.8 V tPZH tPZH tPHZ VOH 1.4 V 0V
R
VOH -0.5 V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE
2.5 VCC > 3.15 V VIC - Common-Mode Input Voltage - V VCC = 3 V
2
1.5
1
0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|- Differential Input Voltage - V
Figure 8
DRIVER DRIVER
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
4 VCC = 3.3 V TA = 25C 3 3.5
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
VCC = 3.3 V TA = 25C V OH - High-Level Output Voltage - V 3 2.5
V OL - Low-Level Output Voltage - V
2 1.5 1 .5 0
2
1
0 0 2 4 6 8 10 12 IOL - Low-Level Output Current - mA
0
-2
-4
-6
-8
IOH - High-Level Output Current - mA
Figure 9
Figure 10
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
RECEIVER RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
4 VCC = 3.3 V TA = 25C VOH - High-Level Output Voltage - V VOL - Low-Level Output Votlage - V 4 3 5
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
VCC = 3.3 V TA = 25C
3
2
2
1
1
0 0 -40 -60 IOH - High-Level Output Current - mA -20 -80
0 0 10 20 30 40 50 IOL - Low-Level Output Current - mA 60
Figure 11
DRIVER
Figure 12
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
t PLH - Low-To-High Propagation Delay Time - ns 2.5 t PLH - High-To-Low Propagation Delay Time - ns
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
2.5
2 VCC = 3 V
VCC = 3.3 V
2 VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V 1.5 -50 -30 50 30 70 TA - Free-Air Temperature - C -10 10 90
VCC = 3.6 V 1.5 -50 -30 10 -10 50 30 70 TA - Free-Air Temperature - C 90
Figure 13
Figure 14
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
RECEIVER RECEIVER
t PLH - High-To-Low Level Propagation Dealy Time - ns
4.5
t PLH - Low-To-High Level Propagation Delay Time - ns
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
4.5
VCC = 3 V 4 VCC = 3.3 V
4 VCC = 3 V
VCC = 3.3 V
3.5 VCC = 3.6 V
3.5 VCC = 3.6 V
3
3
2.5 -50
-30
50 30 70 TA - Free-Air Temperature - C
-10
10
90
2.5 -50
-30
10 -10 50 30 70 TA - Free-Air Temperature - C
90
Figure 15
Figure 16
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements.
1000
Transmission Distance - m
100
30% Jitter
5% Jitter 10
1
24 AWG UTP 96 (PVC Dielectric) 0.1 100k 1M Data Rate - Hz 10M 100M
Figure 17. Data Transmission Distance Versus Rate
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SLLS324D - DECEMBER 1998 - REVISED JULY 2000
APPLICATION INFORMATION fail safe
One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between -50 mV and 50 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different, however, in how it handles the open-input circuit situation. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-k resistors as shown in Figure 18. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level, regardless of the differential input voltage.
VCC
300 k A Rt = 100 (Typ) B
300 k
Y
VIT 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature.
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SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0-8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047/D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDM179, SN65LVDM180, SN65LVDM050, SN65LVDM051 HIGH SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS324D - DECEMBER 1998 - REVISED JULY 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,25 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0-6 0,69 0,41
Seating Plane 1,07 MAX 0,15 MIN 0,10
4073329/A 02/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated


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