View SLLS370A_1002853.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
D D D D D D D D D D D
One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Designed for Signaling Rates Up to 622 Mbps Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of the Four Banks Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100 Load Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks Propagation Delay Times <4.7 ns Output Skew is < 300 ps and Part-to-Part Skew <1.5 ns Total Power Dissipation Typically 470 mW With All Ports Enabled and at 200 MHz Driver Outputs or Receiver Input is High Impedance when Disabled or With VCC <1.5 V Bus-Pin ESD Protection Exceeds 12 kV Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
DGG PACKAGE (TOP VIEW)
description
37 The SN65LVDS116 is one differential line reciever 29 36 connected to sixteen differential line drivers that 30 35 implement the electrical characteristics of 31 34 low-voltage differential signaling (LVDS). LVDS, 32 33 as specified in EIA/TIA-644, is a data signaling technique that offers the low-power, low-noise coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
GND VCC VCC GND ENA ENA NC NC NC ENB ENB NC NC NC GND VCC VCC GND A B NC ENC ENC S0 S1 SM END END GND VCC VCC GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
A1Y A1Z A2Y A2Z A3Y A3Z A4Y A4Z B1Y B1Z B2Y B2Z B3Y B3Z B4Y B4Z C1Y C1Z C2Y C2Z C3Y C3Z C4Y C4Z D1Y D1Z D2Y D2Z D3Y D3Z D4Y D4Z
The intended application of this device and signaling technique is for point-to-point or multidrop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in system clock distribution. The SN65LVDS116 is characterised for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
logic diagram (positive logic)
A1Y A1Z A2Y S0 S1 SM ENA ENA A4Y A4Z B1Y B1Z B2Y B2Z B3Y ENB ENB B4Y A B B4Z C1Y C1Z C2Y C2Z C3Y ENC ENC C4Y C4Z D1Y D1Z D2Y D2Z D3Y END END D4Y D4Z D3Z C3Z B3Z A2Z A3Y A3Z
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
FUNCTION TABLE INPUT VID = VA - VB X VID 100 mV -100 mV < VID < 100 mV VID -100 mV X VID 100 mV -100 mV < VID < 100 mV VID -100 mV VID 100 mV -100 mV < VID < 100 mV VID -100 mV VID 100 mV -100 mV < VID < 100 mV VID -100 mV VID 100 mV -100 mV < VID < 100 mV SM H H H H H L L L L L L L L L L L EN L H H H X X X X X X X X X X X X EN X L L L H X X X X X X X X X X X S1 X X X X X L L L L L L H H H H H S0 X X X X X L L L H H H L L L H H AY Z H ? L Z H ? L Z Z Z Z Z Z Z Z AZ Z L ? H Z L ? H Z Z Z Z Z Z Z Z Z BY Z H ? L Z Z Z Z H ? L Z Z Z Z Z Z OUTPUT BZ Z L ? H Z Z Z Z L ? H Z Z Z Z Z Z CY Z H ? L Z Z Z Z Z Z Z H ? L Z Z Z CZ Z L ? H Z Z Z Z Z Z Z L ? H Z Z Z DY Z H ? L Z Z Z Z Z Z Z Z Z Z H ? L DZ Z L ? H Z Z Z Z Z Z Z Z Z Z L ? H
VID -100 mV L X X H H Z H = high level, L = low level, Z = high impedance, ? = indeterminate
equivalent input and output schematic diagrams
VCC VCC 300 k (EN and SM Only) 300 k 300 k Enable Inputs A Input 7V B Input 7V 7V 300 k 50 10 k 5 Y or Z Output 7V VCC
(EN, S0, and S1 Only)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Electrostatic discharge, Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B: 500 V All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 4 kV, B: 400 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING
DGG 2094 mW 16.7 mW/C 1089 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage, VID V Common-mode input voltage, VIC Operating free-air temperature, TA 0.1 ID 2 -40 3 2 0.8 3.6 V 2.4 - ID 2 NOM 3.3 MAX 3.6 UNIT V V V V V V C
VCC - 0.8 85
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VITH+ VITH- VOD VOD VOC(SS) VOC(SS) VOC(PP) ICC II II(OFF) IIH IIL IOS IOZ IO(OFF) CIN Positive-going differential input voltage threshold Negative-going differential input voltage threshold Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage between logic states Peak-to-peak common-mode output voltage Supply current Input current (A or B inputs) Power-off Input current (A or B inputs) High-level High level input current Low-level Low level input current Short circuit output current Short-circuit High-impedance output current Power-off output current ENx, S0, S1 ENx, SM ENx, S0, S1 ENx, SM Enabled, Disabled VI = 0 V VI = 2.4 V VCC= 1.5 V, VIH = 2 V VIL = 0 8 V 0.8 VOY or VOZ = 0 V VOD = 0 V VO = 0 V or VCC VCC = 1.5 V, VO = 3.6 V VI = 0.4 sin (4E6t) + 0.5 V VI= 2.4 V -2 -1.2 20 20 -20 10 -10 24 12 1 1 RL = 100 See Figure 3 TEST CONDITIONS See Figure 1 and Table 1 RL= 100, 100 VID= 100 mV, mV See Figure 1 and Figure 2 MIN -100 247 -50 1.125 -50 50 84 3.2 340 454 50 1.375 50 150 115 6 -20 mA A A A A mA A A mV V mV TYP MAX 100 UNIT mV
Input capacitance (A or B inputs) 5 pF CO Output capacitance (Y or Z outputs) VI = 0.4 sin (4E6t) + 0.5 V 9.4 All typical values are at 25C and with a 3.3 V supply. The non-algebraic convention, where the more positive (least negative) limit is designated minimum, is used in this data sheet for the input current (II) only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tr tf tsk(p) tsk(o) tsk(pp) tPZH tPZL tPHZ Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Differential output signal rise time Differential output signal fall time Pulse skew (|tPHL - tPLH|) Output skew, channel-to-channel Part-to-part skew Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output See Figure 5 RL = 100 , CL = 10 pF, See Figure 4 TEST CONDITIONS MIN 2.2 2.2 0.3 0.3 TYP 3.1 3.1 0.8 0.8 140 100 5.7 7.7 3.2 MAX 4.7 4.7 1.2 1.2 500 300 1.5 15 15 15 ns UNIT ns ns ps ns
tPLZ Propagation delay time, low-level-to-high-impedance output 3.2 15 ns All typical values are at 25C and with a 3.3 V supply. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH or tPHL measured at any two outputs. tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
IIA A IIB VIA VIB VID IOY Y IOZ VOD VOY VOZ VOC (VOY + VOZ)/2
B GND
Z
Figure 1. Voltage and Current Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES VIA 1.25 V 1.15 V 2.4 V 2.3 V 0.1 V 0V 1.5 V 0.9 V 2.4 V 1.8 V 0.6 V 0V VIB 1.15 V 1.25 V 2.3 V 2.4 V 0V 0.1 V 0.9 V 1.5 V 1.8 V 2.4 V 0V 0.6 V RESULTING DIFFERENTIAL INPUT VOLTAGE VID 100 mV -100 mV 100 mV -100 mV 100 mV -100 mV 600 mV -600 mV 600 mV -600 mV 600 mV -600 mV RESULTING COMMONMODE INPUT VOLTAGE VIC 1.2 V 1.2 V 2.35 V 2.35 V 0.05 V 0.05 V 1.2 V 1.2 V 2.1 V 2.1 V 0.3 V 0.3 V
Y Input Z VOD
3.75 k 100 3.75 k
0 V VTEST 2.4 V
Figure 2. VOD Test Circuit
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Y Input Input Z 50 pF VOC VO 49.9 1% (2 Places) VI VI VOC(PP) 1.4 V 1V VOC(SS)
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
VIB Input VIA tPLH VOD 100 1 % Output CL = 10 pF (2 Places) 0V VOD(L) 20% 0% tf tr VOD(H) 1.4 V 1.2 V 1V tPHL 100% 80%
A Input B
Y
Z
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, Pulsewidth = 10 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
1 V or 1.4 V Y 49.9 1% (2 Places)
Z 1.4 V or 1 V CL = 10 pF (2 Places) VOY VOZ + - EN EN S0 S1 SM 1.2 V
Inputs
Input
2V 1.4 V 0.8 V
VOY or VOZ
tPZH
tPHZ 100%, 1.4 V 1.3 V 0%, 1.2 V
tPZL
tPLZ
100%, 1.2 V VOZ 1.1 V or 0%, 1 V VOY NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs SWITCHING FREQUENCY
t PLH - Low-To-High Propagation Delay Time - ns 220 200 I CC - Supply Current - mA 180 VCC = 3.6 V 160 VCC = 3.3 V 140 VCC = 3 V 120 100 80 0 50 100 150 200 All Outputs Loaded and Enabled 250 300 350 400 f - Frequency - MHz 3.8 3.7 3.6 3.5 VCC = 3.3 V 3.4 VCC = 3.6 V 3.3 3.2 3.1 -50 VCC = 3 V
LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
-25
0
25
50
75
100
TA - Free-Air Temperature - C
Figure 6
HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
t PHL - High-To-Low Propagation Delay Time - ns 3.7 3.6 3.5 3.4 3.3 VCC = 3.6 V 3.2 3.1 3.0 2.9 -50 VCC = 3.3 V VCC = 3 V
Figure 7
-25
0
25
50
75
100
TA - Free-Air Temperature - C
Figure 8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
Figure 9. Typical Differential Eye Pattern at 400 Mbps
PEAK-TO-PEAK OUTPUT JITTER vs SIGNALING RATE
800 700 Peak-To-Peak Output Jitter - ps 600 500 400 300 200 100 0 0 VID = 600 mV, VIC = 0.3 V VID = 100 mV, VIC = 0.05 V VID = 400 mV, VIC = 1.4 V
VID = 600 mV, VIC = 2.1 V VID = 100 mV, VIC = 2.35 V 50 100 150 200 250 300 350 400 450 500 Signaling Rate - Mbps
Figure 10. Typical Peak-To-Peak Output Jitter vs VID and VIC
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
An LVDS receiver can be used to receive various other types of logic signals. Figure 11 through Figure 19 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD 25 50 A 50 B 1/2 VDD 0.1 F LVDS Receiver
Figure 11. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
VDD 50 A 50 B 1.35 V < VTT < 1.65 V 0.1 F LVDS Receiver
Figure 12. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD 1 k 50
50 A
B
2 k
0.1 F
LVDS Receiver
Figure 13. Gunning Transceiver Logic (GTL)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Z0 Z0
A
B 1.47 V < VTT < 1.62 V 0.1 F LVDS Receiver
Figure 14. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
50
120
120
ECL
33
33 A
50 B 51 51
LVDS Receiver
Figure 15. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
5V
5V
50
82
82
ECL
100
100 A
50 B 33 33
LVDS Receiver
Figure 16. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V 7.5 k A
B
7.5 k
0.1 F
LVDS Receiver
Figure 17. 3.3-V CMOS
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
13
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
5V
5V 10 k 560 A
B 560
3.3 k
0.1 F
LVDS Receiver
Figure 18. 5-V CMOS
5V
5V 10 k 470 A
B
3.3 V
4 k
0.1 F
LVDS Receiver
Figure 19. TTL
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65LVDS116 16-PORT LVDS REPEATER
SLLS370A - SEPTEMBER 1999 - REVISED SEPTEMBER 1999
MECHANICAL DATA
DGG (R-PDSO-G**)
48 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: B. C. D. E.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SLLS370A

	To Download SLLS370A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .