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TLK2500 Serdes EVM Kit Setup and Usage
User's Guide
March 2000
Mixed Signal Products
SLLU007A
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Notational Conventions
Preface
Read This First
About This Manual
This manual should be used to determine how to setup and use the TLK2500 evaluation module in order to evaluate the TLK2500 device.
How to Use This Manual
This document contains the following chapters:
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Chapter 1 -- Introduction Chapter 2 -- TLK2500 EVM Board Configuration Chapter 3 -- PCB Construction and Characteristics Appendix A -- Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications Appendix B -- NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver data sheet
Notational Conventions
This document uses the following conventions.
-
Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter's. Examples use a bold version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Here is an example of a system prompt and a command that you might enter:
C: csr -a /user/ti/simuboard/utilities
Read This First
iii
Trademarks
-
In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: .asect "section name", address .asect is the directive. This directive has two parameters, indicated by section name and address. When you use .asect, the first parameter must be an actual section name, enclosed in double quotes; the second parameter must be an address.
-
Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you don't enter the brackets themselves. Here's an example of an instruction that has an optional parameter: LALK 16-bit constant [, shift] The LALK instruction has two parameters. The first parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma. Square brackets are also used as part of the pathname specification for VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
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Braces ( { and } ) indicate a list. The symbol | (read as or) separates items within the list. Here's an example of a list: { * | *+ | *- } This provides three choices: *, *+, or *-. Unless the list is enclosed in square brackets, you must choose one item from the list.
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Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.
Trademarks
TI is a trademark of Texas Instruments Incorporated. NetLight and SpeedBlaster are trademarks of Lucent Technologies Inc.
iv
Running Title--Attribute Reference
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TLK2500 EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TLK2500 EVM Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Typical Test and Setup Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 Optical Interfacing and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PCB Construction and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver . . . . . . . . . . B-1
2
3 A B
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
2-1 2-2 2-3 2-4 2-5 2-6 3-1 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 TLK2500 Serial Loop-Back Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2500 Serial Loop-Back Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2500 Serial PRBS BERT Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2500 Serial PRBS BERT Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optical Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2500EVM to Laser Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 2-5 2-6 2-7 2-8
TLK2500 EVM Layer Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 TLK2500 EVM Transceiver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Optical Transceiver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Top Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 GND Layers 2 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Power Plane 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Bottom Layer 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 Top Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Detail of Top Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 GND Layers 2 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 Detail of GND Layers 2 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 Power Plane 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14 Detail of Power Plane 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15 Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16 Detail of Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17 Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18 Detail of Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19
vi
Running Title--Attribute Reference
Tables
2-1 2-2 3-1 3-2 A-1 Default Transceiver Board Configuration as Shipped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Configuration Changes Necessary for DC Coupling of the High Speed Signals . . . . . . . . 2-2 TLK2500 EVM TTL Bus PCB Transmission Line Characteristics . . . . . . . . . . . . . . . . . . . . 3-2 TLK2500 Differential Pair PCB Transmission Line Characteristics . . . . . . . . . . . . . . . . . . . 3-2 TLK2500 EVM Transceiver Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Contents
vii
viii
Chapter 1
Introduction
The Texas Instruments (TI) TLK2500 serdes evaluation module (EVM) board is used to evaluate the TLK2500 device(VQFP) and associated optical interface (NetLightTM) for point-to-point data transmission applications. The board enables the designer to connect 50- parallel buses to both transmitter and receiver connectors. The TLK2500, using high speed PLL technology, serializes, encodes (8b/10b), and transmits data along one differential pair. The receiver part of the device deserializes, decodes and presents data on the parallel bus. The high speed (up to 2.5 Gbps) data lines interface to four 50- controlled-impedance SMA connectors. The designer can either use this copper interface directly or loop back to the laser module section for an optical interface(not provided).
Topic
1.1
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction
1-1
Introduction
1.1 Introduction
The board can be used to evaluate device parameters while acting as a guide for high-speed board layout. The evaluation board can be used as daughter boards that are plugged into new or existing designs. Since the TLK2500 operates over a wide range of frequencies, the designer will need to optimize his or her design for the frequency of interest. Additionally, the designer may wish to use buried transmission lines and provide additional noise attenuation and EMI suppression to optimize their end product. As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled to 50 for both the high-speed differential serial and parallel data connections. In addition, impedance mismatches are reduced by designing the component pad size to be as close as possible to the width of the connecting transmission lines. Vias are minimized and, when necessary, placed as close as possible to the device drivers. Since the board contains both serial and parallel transmission lines, care was taken to control both impedance and trace length mismatch (board skew). Overall, the board layout is designed and optimized to support high-speed operation. Thus, understanding impedance control and transmission line effects are crucial when designing high-speed boards. Some of the advanced features offered by this board include:
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PCB (printed-circuit board) is designed for high-speed signal integrity. Flexibility-The PCB can be configured for copper or optical interfaces. SMA and parallel fixtures are easily connected to test equipment. All input/output signals are accessible for rapid prototyping. Analog and digital power planes can be supplied through separate banana jacks for isolation or can be combined using ferrite bridging networks. Series termination resistors provide parallel RD outputs. Onboard capacitors provide ac coupling of high-speed signals.
1.2 TLK2500 EVM Kit Contents
TLK2500 EVM board TLK2500 EVM kit documentation (This document)
1-2
Chapter 2
TLK2500 EVM Board Configuration
The TLK2500 EVM board gives the developer various options for operation, many of which are jumper selectable. Other options can be either soldered into the EVM or connected through input connectors. The TX and RX parallel connectors, J1-J4 of Figures 8 and 10 in Appendix A, provide a connection for both transmitted and received data. The reference clock is supplied through the SMA connector J8, and jumper J5 must be installed between pins 1 and 2. A direct clock connection can also be made to J5 pins 1 and 3. The high-speed serial data is transmitted through the J13 and J14 SMA connectors. The received recovered clock (RX_CLK) is output through J15 header. Received data connects through SMA connectors J17 and J23 on the RX side of the board. Header J7 provides static signals (normally pulled high) to configure the device for different modes of operation. The J20 header indicates the optical transmitter has detected a signal and J21 allows the operator to disable the optical transceiver. The power planes are split three ways to provide power for different parts of the board. This prevents coupling of switching noise between the analog and digital sections of the TLK2500 and provides voltage isolation for the laser section. The laser section of the board requires 3.3 volts and is energized through the VCC connector. The VDD and VDDA connectors require 2.5 volts and are joined together by a removable ferrite bead L3 that is installed in the default configuration. Thus, only the VDD connection is necessary to energize the TLK2500 device in the default configuration. In all sections of the board, the ground planes are common and each ground plane is tied together at every component ground connection. For a detailed schematic and layout see TLK2500EVM Schematic, Optical Transceiver Schematic and Board Layer Stack-up in Appendix A.
Topic
2.1 2.2
Page
Typical Test and Setup Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Optical Interfacing and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
TLK2500 EVM Board Configuration
2-1
The board is normally delivered in a default configuration that requires external clock and data inputs. The TLK2500 is shipped with jumpers for default operation. Table 2-1 shows the default configuration for sending data.
Table 2-1. Default Transceiver Board Configuration as Shipped
Designator J5 J7 J7 J7 J7 J7 J7 J7 L3 C24, C25 C22, C23 Function GTX CLK SEL TESTEN PRBSEN LCKREFN ENABLE TXER LOOPEN TXEN Condition Jumper installed - Provides a method of supplying a input clock to the board Jumper installed (Logic 0) Disables the TLK2500 test mode Jumper installed (Logic 0) Disables the TLK2500 PRBS internal production test mode Jumper not installed (Logical 1) Locks to received clock Jumper not installed (Logical 1) Enables the device for normal operation Jumper installed (Logic 0) Puts the TLK2500 in a state to transmit TX bus data. Jumper installed (Logic 0) Disables the TLK2500 internal loop back mode Jumper not installed (Logical 1) Puts the TLK2500 in a state to transmit TX bus data.
VDD- bridge -VDDA Joins VDD and VDDA power planes TX ac coupling capacitors RX ac coupling capacitors These capacitors (normally installed) are provided to ac couple the transmitted signal. These capacitors (normally installed) are provided to ac couple the received signal
Note:
For details, see TLK2500 data sheet
Table 2-2. Configuration Changes Necessary for DC Coupling of the High Speed Signals
Designator C24, C25 C22, C23 R34 R33 R37, R38 Function TX ac coupling capacitors TX ac coupling capacitors RX bias resistor RX bias resistor TX termination network Condition or Changes Necessary for DC Coupling Install zero ohm resistors Install zero ohm resistors. Install zero ohm resistor. Uninstall resistor (open circuit) Uninstall resistors (open circuit) - Termination and pullup is achieved at the receiver. Differential swing is increased.
2-2
Typical Test and Setup Configurations
2.1 Typical Test and Setup Configurations
The following configurations are used to evaluate and test the TLK2500 transceiver. The first configuration is a serial loopback of the high-speed signals shown in Figure 2-1. The serial loopback allows the designer to evaluate most of the functions of both transmitter and receiver sections of the TLK2500 device. To test a system, a parallel bit error rate tester (BERT) generates a predefined parallel bit pattern. The pattern is connected to the transmitter through parallel connectors TD0-TD15. Additionally, two control pins TX_ER and TX_EN are configured by the BERT for valid data transmission (TX_ER low and TX_EN high). The TLK2500 device encodes, serializes, and presents the data on the high-speed serial pair. The serial TX data is then looped back to the receiver side and the device deserializes, decodes and presents the data on the receive side RD0-RD15. The data and indication bits (RX_DV and RX_ER) are received by the BERT and compared against the transmitted pattern and monitored for valid data and errors. If any bit errors are received, a bit error rate is evaluated at the parallel receive BERT.
Figure 2-1. TLK2500 Serial Loop-Back Test Configuration
Jumper Selection GND TESTEN PRBSEN LCKREFN J7 ENABLE TX_ER LOOPEN TX_EN GND EXT INPUT Channel 1 O/P HP8133A Pulse Generator (Asynchronous to BERT)
Parallel BERT Frequency = 75-125 MHz GTX_CLK CLK OUT TD 0-15 TX Data Out 0-17 18 bits CLK IN RX Data In 0-17 18 bits Reciever BERT TX_EN TX_ER RX CLK RX_ER RX_DV RD 0-15 RX+ RX- TX+ TX-
TLK2500EVM Evaluation Board
TLK2500 EVM Board Configuration
2-3
Typical Test and Setup Configurations
If a parallel BERT is not available, the designer can take advantage of the built in test mode of the device, see Figure 2-2. If the designer asserts the PRBSEN pin high this results in a pseudo random bit pattern to be transmitted. This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid pattern is indicated by the PRBSPASS pin indicating high. This test only validates the high-speed serial portion of the device and system interconnects. The PRBS pattern is compatible with most serial BERT test equipment. This function allows the operator to isolate and test the transmitter and receiver independently. A typical configuration is shown in Figure 2-3. The dashed lines represent optional connections that can be made monitoring eye patterns and measuring jitter.
Figure 2-2. TLK2500 Serial Loop-Back Test Configuration
Jumper Selection GND TESTEN PRBSEN LCKREFN ENABLE TX_ER LOOPEN TX_EN GND J7 Channel 1 O/P HP8133A Pulse Generator EXT INPUT TRIGGER OUT HP83480 or Tek 11801 Digital Oscilloscope
CH1 CH2 Trigger
GTX_CLK PRBS 2^7-1
Channel 1
TX- TX+
TDS820 Digital Oscilloscope
PRBS_PASS RD 0-15
RX+ RX- PRBS 2^7-1
TLK2500EVM Evaluation Board
2-4
Typical Test and Setup Configurations
Figure 2-3. TLK2500 Serial PRBS BERT Test Configuration
Jumper Selection GND TESTEN PRBSEN LCKREFN ENABLE TX_ER LOOPEN TX_EN GND J7 Channel 1 O/P HP8133A Pulse Generator EXT INPUT TRIGGER OUT CLK/20 HP83480 or Tek 11801 Digital Oscilloscope
CH1 CH2 Trigger
GTX_CLK Channel 1 PRBS 2^7-1 TX- TX+
Serial BERT HP7004A 3 Gbps Reciever BERT Data In
Transmitter BERT TDS820 Digital Oscilloscope PRBS_PASS RD 0-15 RX+ RX- PRBS 2^7-1 Data Out Data Out CLK OUT
TLK2500EVM Evaluation Board
A board-to-board communication link is a practical method of evaluating the TLK2500 in a system-like environment as shown in Figure 2-4. A Parallel BERT or a logic analyzer can be used to provide and monitor signals to and from the transceiver pairs. The BERT would need to configure the TX_ER and TX_EN signals for data transmission before any data is sent. On the receive side the RX_ER and RX_DV can monitor the device for errors. Both GTX_CLK sources must have the same frequency within 200 PPM for asynchronous operation. Synchronous operation can be achieved by using either the BERT or a synchronized pulse generator to supply both boards with GTX_CLK inputs.
TLK2500 EVM Board Configuration
2-5
Typical Test and Setup Configurations
Figure 2-4. TLK2500 Serial PRBS BERT Test Configuration
Jumper Selection EVM #1 GND TESTEN PRBSEN LCKREFN ENABLE TX_ER LOOPEN TX_EN GND J7 TESTEN PRBSEN LCKREFN ENABLE TX_ER LOOPEN TX_EN GND Asynchronous Synchronous J7 HP8133A Pulse Generator (Asynchronous to BERT) EXT INPUT Trigger EVM #2 GND
Channel 1 O/P
GTX_CLK TD 0-15 TX_EN TX_ER TX+ TX- RX+ RX-
GTX_CLK 16 bits RD 0-15 RX_ER Rx_DV
2 bits
RX+ RD 0-15 RX-
TX+ TX-
RX_CLK TD 0-15
Channel 1
TLK2500EVM #1 Evaluation Board EVM1 PRBS Disabled
TLK2500EVM #2 Evaluation Board EVM2 PRBS Disabled
18 bits Parallel BERT Frequency = 75-125 MHz TX Data Out 0-17 CLK Out Transmitter BERT CLK IN RX Data In 0-17
Board configued to send IDLE pattern: TX_EN = 0 TX_ER = 0
18 bits Reciever BERT
2-6
Optical Interfacing and Configuration
2.2 Optical Interfacing and Configuration
An interface between the TLK2500EVM and an optical transceiver can be achieved in many ways depending on the design of the optics module and its associated interface circuitry. Direct connection is achieved only if the optical interface supports the current mode logic levels of the TLK2500 device (VDD - 1 V). If the optics module does not support or can not be biased to the CML levels then ac coupling must be used. Both ac and dc coupling schemes are shown in Figure 2-5. The Laser Module Section of the EVM is configured as an ac-coupled optics module. The board is shipped with an ac-coupled output and all that is required is external loopback cabling.
Figure 2-5. Optical Interface Configuration
DC Coupling
DC Coupling
VDD CMLDC bias levels voltage (VDD-1 V) TLK2500 TX Optical Module
50
AC Coupling
AC Coupling VDD Biased to CML Levels VCC Optical Module
50
50
TLK2500 TX 50 Biased to PECL Levels
The Laser Module Section is isolated from the rest of the board and requires external loopback as shown in Figure 2-6. This makes for a versatile system where the laser can be connected independently to other EVM systems.
TLK2500 EVM Board Configuration
2-7
Optical Interfacing and Configuration
Figure 2-6. TLK2500EVM to Laser Module Configuration
2-8
TLK2500 EVM Board Configuration
Chapter 3
PCB Construction and Characteristics
The PCB characteristics are calculated and based on the layer construction and trace width of the board. This should be useful in determining the proper interface to the EVM and establishing system timing.
PCB Construction and Characteristics
3-1
Table 3-1. TLK2500 EVM TTL Bus PCB Transmission Line Characteristics
Device Pin No./Des. 62 - TXD0 63 - TXD1 64 - TXD2 2 - TXD3 3 - TXD4 4 - TXD5 6 - TXD6 7 - TXD7 10 - TXD8 11 - TXD9 12 - TXD10 14 - TXD11 15 - TXD12 16 - TXD13 17 - TXD14 19 - TXD15 51 - RXD0 50 - RXD1 49 - RXD2 47 - RXD3 46 - RXD4 45 - RXD5 44 - RXD6 42 - RXD7 40 - RXD8 39 - RXD9 37 - RXD10 36 - RXD11 35 - RXD12 34 - RXD13 32 - RXD14 31 - RXD15 Note: Connector Pin Label TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 TD10 TD11 TD12 TD13 TD14 TD15 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 Trace Width (inches) 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 0.0118 Length (inches) 1.887 1.884 1.904 1.898 1.903 1.899 1.901 1.906 1.860 1.908 1.884 1.912 1.903 1.910 1.911 1.901 1.814 1.804 1.802 1.862 1.866 1.876 1.880 1.865 1.860 1.860 1.863 1.872 1.816 1.855 1.809 1.821 Capacitance (pF) 5.2 5.2 5.3 5.3 5.3 5.3 5.3 5.3 5.2 5.3 5.2 5.3 5.3 5.3 5.3 5.3 5.0 5.0 5.0 5.2 5.2 5.2 5.2 5.2 5.2 5.2 5.2 5.2 5.0 5.2 5.0 5.1 Inductance (nH) 14.1 14.1 14.3 14.2 14.2 14.2 14.2 14.3 13.9 14.3 14.1 14.3 14.2 14.3 14.3 14.2 13.6 13.5 13.5 13.9 14.0 14.0 14.1 14.0 13.9 13.9 13.9 14.0 13.6 13.9 13.9 13.6 Impedance () 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 51.9 Line Delay (ps) 272.1 271.7 274.7 273.7 274.4 273.8 274.1 274.8 268.2 275.1 271.7 275.7 274.4 275.4 275.6 274.1 26.6 260.3 259.9 268.5 269.1 270.5 271.1 268.9 268.2 268.2 268.6 269.9 261.9 267.5 260.9 262.9
All values presented in this table are theoretical calculated values and may not reflect actual measured parameters.
Table 3-2. TLK2500 Differential Pair PCB Transmission Line Characteristics
Device Pin No. 60 - DOUTTXP 59 - DOUTTXN 54 - DINRXP 53 - DINRXN Note: Connector Pin No. TXP TXP RXP RXN Trace Width (inches) 0.025 0.025 0.025 0.025 Length (inches) 2.390 2.363 2.889 2.883 Impedance () 51.2 51.2 51.2 51.2 Line Delay (ps) 347.5 343.6 420.1 419.2
All values presented in this table are theoretical calculated values and may not reflect actual measured parameters.
3-2
Figure 3-1. TLK2500 EVM Layer Construction
Layer 1 14 Mil Layer 2 5 Mil Layer 3 21 Mil Layer 4 05 Mil Layer 5 07 Mil Layer 6 VDD1 VDD2 GND2 Solder 50 GND1 Top 50
Notes: 1) All cores consist of 1 oz. Cu. 2) Trace width A) 25 mils (for 50 Layer 1) B) 11.8 mils (for 50 Layer 6) 3) Overall board thickness is 62 mils 5 mil 4) Copper and solder mask adds approximately 10 mils to the overall board thickness. 5) Impedance is 50 5% 6) Material is G-Tek. Dielectric constant = 3.9 7) For overall thickness: add 1.2 to 1.4 mils for each metal layer in the stack-up.
PCB Construction and Characteristics
3-3
3-4
Appendix A
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
This appendix contains schematics and corresponding bill of materials for the TLK2500EVM transceiver board along with board layouts. Specifications for the NetLightTM 1417K4A 1300 nm laser assembly are also included.
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
A-1
Figure A-1. TLK2500 EVM Transceiver Schematic
VDD GND J19 VDD 10u C12 0.01 C6 0.01 C5 0.01 C4 0.01 C3 0.01 C2 100p C32 100p C33 100p C34 100p C35 100p C36 100p C37 10k 10k 10k 10k 10k 10k 10k 10k VDD C21 0.01 R33 825 R34 R41 200 100 R25 R26 R27 R28 R29 R30 R31 R32 J1 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 VDD C14 0.01 R4 VDD C18 0.01 VDDA1 VDDA1 51 C19 0.01 C20 0.01 1 3 5 7 9 11 13 15 J3 2 4 6 8 10 12 14 16 49.9 49.9 C26 0.01 R37 R38 C25 0.01 VDDA2 C24 0.01 J13 C38 J14 TXP 0.01 VDDA2 TXN 0.01 VDDA1 RXP C39 VDDA2 0.01 C40 RXN J23 C23 R36 49.9 0.01 VDDA1 0.01 C41 J22
J17 C22
0.01 R35 49.9
0.01 C51 VDDA2
R5
VDD
open R22 R3 R21 0 49.9 1 2 J8 R24 GTX_CLK 0.01 C42 VDD J2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 VDD R6 10k 10k 10k 10k 10k 10k 10k 10k R7 R8 R13 R14 R15 R16 R17 R18 R19 R20 VDD R9 R10 R11 R12 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k L1 0.01 1 3 VDD 0.01 C16 R1 2 J6 VDDA1 0.01 4 0 3 R2 J5 R23 C15 0.01 VDD VDD
51
J15
51
C17
0.01
51
J4 1 3 5 7 9 11 13 15 VDDA2 0.01 C10 C13 L2 0.01 C11 C9 2 4 6 8 10 12 14 16
51
2
4 6 8 10 12 14 J16 L3
4.7 C8
J7 3 5 7 1 9 11 13
0.01 VDDA 0.01 VDD C1 C7
A-2
Figure A-2. Optical Transceiver Schematic
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
A-3
Table A-1.TLK2500 EVM Transceiver Bill of Materials
Item 1 2 3 4 5 6 Qty 1 1 4 1 4 40 Mfg / Dist. Digi-Key Digi-Key Digi-Key Digi-Key Newark Digi-Key Mfg Part No. S2011-02-ND S2011-07-ND ECS-T1DX475R S1111-03-ND 39N867 PCC1784CT-ND Ref Des J6 J7 J1, J2, J3, J4 J5 J16,J18,J19, J22 C1-C7, C9-C11, C13-C26, C29, C31, C38-C51 C8,C27, C28,C30 C12 L1 - L3 J15, J20 U2 R21, R24 R6-R12 R15-R20, R25-R32 R23, R35, R36, R37, R38 R39, R40 R34, R41 R33 R22 R1, R2, R3, R4, R5 Description 2x2 HEADER 2x7 HEADER 2x8 HEADER 3 PIN JUMPER Banana Jack CAPACITOR, SMT603 Value or Function 0.1 x 0.1 CENTERS 0.1 x 0.1 CENTERS 0.1 x 0.1 CENTERS 0.1 CENTERS 100 V, 5%, 0.1 F 25 V, 5%, 0.01 F
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
4 1 3 2 1 2 7 16 5 2 2 1 1 5 9 4 4 1 6
Digi-Key Digi-Key Digi-Key Digi-Key LUCENT Digi-Key ANY Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key N/A
PCC1842CT-ND PCC1894CT-ND 240-1018-1ND S1111-02-ND 1417K4A LAS TSW-110-07-G-D P4.75KLTC-ND P10.0KLTC-ND P49.9LCT-ND P130LTC-ND P200LTC-ND P825LTC-ND N/A MNR14 E0AB J 510
CAPACITOR, SMT0603 CAPACITOR, SMT0805 FERRITE BEAD 805 500ma JUMPER Laser Transceiver RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 RESISTOR, SMT, 0402 Resistor R-PAC(4) SMA END-LAUNCH
25 V, 5%, 4.7 F 25 V, 5%, 10 F 600 HEADER, 1x2, 0.1 CENTER 2.5 Gbps 0 4.7 k 10 k 49.9 130 200 825 OPEN 51 422
Newark Newark Newark TI Digi-Key
142-0711-821 92N4922 30F082 TLK2500 PCC101ACVCT-ND U1 C32-C37 STANDOFF
Standoff 0.5' 4-40 thread Machine Screw 4-40 x 3/8' TI TLK2500 DUT CAPACITOR, SMT 0603 64 PIN VQFP 25 V, 20%, 100 pF
A-4
Figure A-3. Top Layer 1
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
A-5
Figure A-4. GND Layers 2 and 5
A-6
Figure A-5. Power Plane 1
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
A-7
Figure A-6. Bottom Layer 6
A-8
Figure A-7. Bottom Layer 7
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications
A-9
Figure A-8. Top Layer 1
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-10
R2
R1
R21
R23 R3 Pin 1 R4
Figure A-9. Detail of Top Layer 1
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications A-11
R5
R22 open
0
R24 0
Figure A-10. GND Layers 2 and 5
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-12
Figure A-11. Detail of GND Layers 2 and 5
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications A-13
Figure A-12. Power Plane 1
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-14
Figure A-13. Detail of Power Plane 1
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications A-15
Figure A-14. Bottom Layer 6
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-16
Figure A-15. Detail of Bottom Layer 6
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications A-17
Figure A-16. Bottom Layer 6
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-18
Figure A-17. Detail of Bottom Layer 6
Schematics, Board Layouts, and Suggested Optics and Cable Assembly Specifications A-19
Schematics, Board Layouts, and Suggested Optiacs and Cable Assembly Specifications
A-20
Appendix B
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
The document shown in this appendix is an advanced information data sheet from Lucent Technologies Inc.
Topic
Page
NetLight 1417K4A 1300 nm Laser 2.5 Gbits/s Speedmaster Transceiver Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Lucent, NetLight, and Speedmaster are a trademarks of Lucent Technologies Inc.
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-1
B-2
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-3
B-4
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-5
B-6
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-7
B-8
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-9
B-10
NetLightTM 1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTM Transceiver
B-11
B-12

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