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PRELIMINARY
W207B
Spread Spectrum FTG for SiS540 and 630 Chipsets
Features
* Maximized EMI Suppression using Cypress's Spread Spectrum technology * Single-chip system frequency synthesizer for SiS540 and SiS630 core logic chip sets * Three copies of CPU output * Seven copies of PCI output * One 48-MHz output for USB * One 24-/48-MHz selectable output for SIO * Two buffered reference outputs * 14 SDRAM outputs provide support for 3 DIMMs I2CTM interface for programming Table 1. Pin Selectable Frequency CPU SDRAM PC FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz) 0 0 0 0 66.6 100.0 33.3 0 0 0 1 100.2 100.2 33.4 0 0 1 0 150.3 100.2 37.6 0 0 1 1 133.6 100.2 33.4 0 1 0 0 66.8 111.3 33.4 0 1 0 1 100.2 133.6 33.4 0 1 1 0 100.2 150.3 33.4 0 1 1 1 133.3 133.3 33.3 1 0 0 0 66.6 66.6 33.3 1 0 0 1 83.3 83.3 27.8 1 0 1 0 97.0 97.0 32.3 1 0 1 1 95.0 95.0 31.7 1 1 0 0 95.0 126.7 31.7 1 1 0 1 112.0 112.0 37.3 1 1 1 0 122.0 91.5 30.5 1 1 1 1 122.0 122.0 30.5 SS -0.6% 0.45% OFF 0.45% OFF 0.45% OFF -0.6% -0.6% OFF -0.6% 0.45% OFF OFF -0.6% -0.6%
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps CPU to CPU Output Skew: ........................................ 175 ps PCI to PCI Output Skew: ............................................ 500 ps CPU to PCI Output Skew (CPU leads): ................... 1 to 4 ns CPU to SDRAM Output Skew: .................................... 500 ps VDDQ3: .................................................................... 3.3V5% VDDQ2: .................................................3.3V5% or 2.5V5%
Block Diagram
VDDQ3 REF1 X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration [1]
REF0_2X/FS3
/ 13
SDRAM0:13
VDDQ2 PLL 1 / 3 CPU0:2 VDDQ3 PCI0/FS1 PCI1/FS2 PCI2 PCI3 PCI4
SDATA SCLK
VDDQ3 REF0_2X/FS3* GND X1 X2 VDDQ3 PCI0/FS1* PCI1/FS2* PCI2 GND PCI3 PCI4 PCI5 PCI6 VDDQ3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDATA I2C SCLK
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REF1 VDDQ2 CPU0 CPU1 GND CPU2 VDDQ3 SDRAM13 SDRAM12 GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDRAM7 SDRAM6 VDDQ3 SDRAM5 SDRAM4 VDDQ3 48MHz_2X/FS0* SIO/CPU3.3#_2.5*
W207B
I2C Logic
PCI5 PCI6 Note: 1. Internal 100-k pull-down resistors present on inputs marked with *. Design should not rely solely on internal pull-down resistors to set I/O pins LOW.
PLL2
x1//2
VDDQ3 48MHz_2X/FS0
SIO/CPU3.3#_2.5 I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 27, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:2 PCI0/FS1 Pin No. 46, 45, 43 7 Pin Type O I/O Pin Description
W207B
CPU Clock Outputs: See Tables 1 and 5 for detailed frequency information. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 0/Frequency Selection 1: PCI clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. Shortly after initial power-up the pin is sampled as an input to determine CPU, SDRAM, and PCI operating frequencies. PCI Clock Outputs 1/Frequency Selection 2: PCI clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. Shortly after initial power-up the pin is sampled as an input to determine CPU, SDRAM, and PCI operating frequencies. PCI Clock Outputs 2 through 6: PCI clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. 48-MHz_2X Output/Frequency Select 0: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. This output has double drive strength. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 1. This output does not have Spread Spectrum modulation. Super I/O Output/CPU Voltage Select: This output is used as the clock input for Super I/O. Upon power-up its input will be latched. If the input is high, CPU0:2 will be configured for 2.5V operations, otherwise they are configured for 3.3V. Fixed 14.318 Output 1: This pin provides a fixed frequency signal determined by the reference signal provided at the X1/X2 pins. Fixed 14.318 Output 0/Frequency Selection 3: This pin provides a fixed frequency signal determined by the reference signal provided at the X1/X2 pins. It has a double drive strength output buffer. Shortly after initial power-up the pin is sampled as an input to determine CPU, SDRAM, and PCI operating frequencies. SDRAM Clock Outputs: These fourteen dedicated outputs provide the SDRAM clocks for 3 memory DIMM. The swing is set by VDDQ3.
PCI1/FS2
8
I/O
PCI2:6 48MHz_2X/ FS0
9, 11, 12, 13, 14 26
O I/O
SIO/ CPU3.3#_2.5 REF1 REF0_2X/FS3
25
I/O
48 2
O I/O
SDRAM0:13
17, 18, 20,21, 28, 29, 31, 32, 34, 35, 37, 38, 40, 41 24 23 4
O
SCLK SDATA X1
I I/O I
Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and SIO output. Connect to 3.3V supply. Power Connection: Power supply for CPU0:2 output buffers. Connect to 2.5V, or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
X2 VDDQ3
5 1, 6, 15, 19, 27, 30, 36, 42 47 3, 10, 16, 22, 33, 39, 44
I P
VDDQ2 GND
P G
2
PRELIMINARY
Overview
The W207B is a spread spectrum system timing generator designed to support SiS540 and 630 core logic chip sets. It is a highly integrated device, providing clock outputs for CPU, core logic, super I/O, PCI, and up to three SDRAM DIMMs.
W207B
each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next the output buffer is enabled, converting all l/O pins into operating clock outputs. The 2-ms timer starts when VDDQ3 reaches 2.0V. The input bits can only be reset by turning VDDQ3 off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is < 40 (nominal) which is minimally affected by the 10-k strap to ground or VDDQ3. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDDQ3 should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When each clock output is enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDDQ3 has stabilized. If VDDQ3 has not yet reached full value, output frequency initially may be below target but will increase to target once VDDQ3 voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Functional Description
I/O Pin Operation Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon power-up each I/O pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and each pin then becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDDQ3. Connection to ground sets a "0" bit, connection to VDDQ3 sets a "1" bit. Figure 1 and Figure 2 show two suggested methods for strapping resistor connection. Upon W207B power-up, the first 2 ms of operation is used for input logic selection. During this period, each clock output buffer is three-stated, allowing the output strapping resistor on
VDD Output Strapping Resistor 10 k (Load Option 1) W207B Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Series Termination Resistor Clock Load
10 k (Load Option 0)
Q
Data Latch
Figure 1. Selection Through Resistor Load Option
3
PRELIMINARY
Jumper Options
W207B
VDD 10 k W207B Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Resistor Value R
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
CPU/PCI Frequency Selection CPU frequency is selected with I/O pins 26, 7, 8, and 2 (48MHz_2X/FSO, PCI0/FS1, PCI1/FS2, and REF_2X/FS3, respectively). Refer to Table 1 for CPU/PCI frequency programming information. Alternatively, frequency selections are available through the serial data interface. Refer to Table 5 on page 8. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The device outputs are CMOS-type which provide railto-rail output swing. To accommodate the limited voltage swing required by some processors, the output buffers of CPU0:2 use a special VDDQ2 power supply pin that can be tied to 2.5V nominal. Crystal Oscillator The device requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is (VDDQ3)/2. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The device incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference frequency accuracies within 100 ppm. To achieve similar accuracies with a crystal calling for a greater load, external capacitors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal. Dual Supply Voltage Operation The device is designed for dual power supply operation. Supply pin VDDQ3 is connected to a 3.3V supply and supply power to the internal core circuit and to the clock output buffers, except for outputs CPU0:2. Supply pins VDDQ2 may be connected to either a 2.5V or 3.3V supply, although device specifications may not be provided for both configurations.
4
PRELIMINARY
Serial Data Interface
The device features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W207B initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLK. In motherboard applications, SDATA and SCLK are typically driven by two logic outputs of the chipset. Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W207B
Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the device in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. Provides CPU/PCI frequency selections beyond the options that are provided by the frequency selection pin power-on default selection. Frequency is changed in a smooth and controlled fashion. Puts all clock outputs into a high-impedance state. All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Frequency Selection
Output Three-state Test Mode (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the device to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the device is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the device, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the device, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W207B registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 4
5
PRELIMINARY
Writing Data Bytes Each bit in the data bytes controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0-6 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 Pin No. -----Pin Name -----Control Function BYTE0_SEL3 BYTE0 _SEL2 BYTE0 _SEL1 BYTE0 _SEL0 FS0:3 override 0 Refer to Table 5 Refer to Table 5 Refer to Table 5 Refer to Table 5 Select operating frequency by FS 3:0 Select operating frequency by BYTE0_SEL (3:0) -Three-state all outputs 24 MHz ---Active Active Active --Active Active Active Active Active Active Active Active Active Active Active Active Active Active Data Byte 0 Bit Control 1
W207B
7. Table 4 gives the bit formats for registers located in Data Bytes 0-6. Table 5 details additional frequency selections that are available through the serial data interface.
Default 0 0 0 0 0
2 1 0 Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0
Data Byte 3
-------43 45 46 --14 13 12 11 9 8 7 32 31 29 28 21 20 18
-------CPU2 CPU1 CPU0 --PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1
BYTE0_SEL4 (Reserved) Test Mode SI0_SEL (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable -Normal 48 MHz ---Low Low Low --Low Low Low Low Low Low Low Low Low Low Low Low Low Low
Refer to Table 5
0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1
6
PRELIMINARY
Table 4. Data Bytes 0-6 Serial Configuration Map (continued) Affected Pin Bit(s) 0 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 5 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 --------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) --------------------48 2 ------REF1 REF0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable ------Low Low ------Active Active 25 26 41 40 38 37 35 34 SIO 48MHz SDRAM13 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Low Low Low Low Low Low Low Low Active Active Active Active Active Active Active Active Pin No. 17 Pin Name SDRAM0 Control Function Clock Output Disable 0 Low Bit Control 1 Active
W207B
Default 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
7
PRELIMINARY
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0 Bit 3 = 1 Bit 2 SEL_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 7 SEL_3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 SEL_2 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.6 100.2 150.3 133.6 66.8 100.2 100.2 133.3 66.6 83.3 97.0 95.0 95.0 112.0 122.0 122.0 66.8 100.0 96.2 133.3 75.0 83.3 105.0 133.6 110.0 166.0 166.0 95.0 140.0 145.0 97.0 160.0 SDRAM 100.0 100.2 100.2 100.2 111.3 133.6 150.3 133.3 66.6 83.3 97.0 95.0 126.7 112.0 91.5 122.0 100.2 100.0 96.2 100.0 100.0 124.9 140.0 133.6 146.7 110.7 120.0 95.0 140.0 145.0 129.3 160.0 PCI 33.3 33.4 37.6 33.4 33.4 33.4 33.4 33.3 33.3 27.8 32.3 31.7 31.7 37.3 30.5 30.5 33.4 33.3 32.1 33.3 37.5 41.6 35.0 33.4 36.7 33.2 33.2 31.7 35.0 36.2 32.33 32.0 Output Frequency
W207B
Spread Spectrum -0.6% 0.45% OFF 0.45% OFF 0.45% OFF -0.6% -0.6% OFF -0.6% 0.45% OFF OFF -0.6% -0.6% OFF -0.6% OFF -0.6% OFF OFF OFF OFF OFF OFF OFF -0.6% OFF OFF -0.6% OFF
8
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W207B
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0C to +70C, VDDQ3 = VDDQ2 = 3.3V5% (3.135-3.465V) Parameter Description Test Condition Supply Current IDD Combined 3.3V Supply Current CPU0:2 =133 MHz Outputs Loaded[2] 350 mA Min. Typ. Max. Unit
Logic Inputs (All referenced to VDDQ3 = 3.3V) Input Low Voltage VIL VIH IIL IIH VOL VOH IOL Input High Voltage Input Low Current[3] Input High Current[3] Output Low Voltage Output High Voltage Output Low Current CPU0:2 SDRAM0:13 PCI0:6 REF0 REF1 48/24 MHZ IOH Output High Current CPU0:2 SDRAM0:13 PCI0:6 REF0 REF1 48/24 MHz Crystal Oscillator VTH CLOAD CIN,X1 X1 Input Threshold Voltage[4] Load Capacitance, Imposed on External Crystal[5] X1 Input Capacitance[6] Pin X2 unconnected 1.65 18 28 VOH = 1.5V IOL = 1 mA IOH = -1 mA VOL = 1.5V 3.1 55 80 55 60 45 55 55 80 55 60 45 55 75 110 75 75 60 75 85 120 85 85 65 85 2.0
0.8 10 10 50 105 155 105 90 75 105 125 175 125 110 90 125
V V A A mV V mA
Clock Outputs
mA
V pF pF
Notes: 2. All clock outputs loaded with 6" 60 transmission lines with 22-pF capacitors. 3. W207B logic inputs have internal pull-up devices (pull-ups not full CMOS level). 4. X1 input threshold voltage (typical) is VDDQ3/2. 5. The W207B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
9
PRELIMINARY
3.3V DC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0C to +70C, VDDQ3 = VDDQ2 = 3.3V5% (3.135-3.465V) (continued) Parameter CIN COUT LIN VIL VIH IIL IIH IOL CIN CSDATA CSCLOCK Description Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Input Low Voltage Input High Voltage Input Low Current Input High Current Sink Current into SDATA or SCLK, Open Drain N-Channel Device On Input Capacitance of SDATA and SCLK Total Capacitance of SDATA Bus Total Capacitance of SCLK Bus No internal pull-up/ down on SCLK No internal pull-up/ down on SCLK IOL = 0.3VDD 6 10 400 400 0.7VDD 10 10 Test Condition Except X1 and X2 Min. Typ. Max. 5 6 7 0.3VDD
W207B
Unit pF pF nH V V A A mA pF pF pF
Pin Capacitance/Inductance
Serial Input Port
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.456V), VDDQ2 = 2.5V5% (2.375-2.625V) Parameter Supply Current IDD-3.3V IDD-2.5 Logic Inputs VIL VIH IIL IIH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current[3] Input High Current[3] Output Low Voltage Output High Voltage Output Low Current: CPU0:2 SDRAM0:13 PCI0:6 REF0 REF1 SIO IOH Output High Current: CPU0:2 SDRAM0:13 PCI0:6 REF0 REF1 SIO IOL = 1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V 10 3.1 55 60 45 55 40 80 55 60 45 55 45 80 75 75 60 75 65 120 85 85 65 85 70 110 105 90 75 105 95 175 125 110 90 125 105 155 mA 2.0 10 10 50 0.8 V V A A mV V mA Combined 3.3V Supply Current Combined 2.5V Supply Current CPU0:2 = 133 MHz Outputs Loaded[2] CPU0:2= 133 MHz Outputs Loaded[2] 300 50 mA mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs
PRELIMINARY
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0C to +70C, VDDQ3 = V DDQ2 = 3.3V5% (3.135-3.465V), fXTL = 14.31818 MHz Spread Spectrum function turned off
W207B
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, (Lump Capacitance Test Load = 20 pF) Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/ Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 20 5.2 5 1 1 45 4 4 55 250 CPU = 66.6 MHz 15 TBD 3.0 2.8 1 1 45 4 4 55 250 CPU = 100 MHz 10.0 TBD 1.87 1.67 1 1 45 4 4 55 250 CPU = 133 MHz Unit ns TBD MHz ns ns V/ns V/ns % ps 7.5 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
175 3
ps ms
Zo
30
15
20
30
15
20
30
11
PRELIMINARY
SDRAM Clock Outputs, (Lump Capacitance Test Load = 30 pF) Test Condition/ Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V 175 500 1 1 45 SDRAM = 66.6 MHz Min. 15 TBD 4 4 55 250 1 1 45 SDRAM = 100 MHz 10.0 TBD 4 4 55 250 1 1 45 7.5 TBD SDRAM = 133 MHz
W207B
Parameter tP f tR tF tD tJC
Description Period Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle
Typ. Max. Min.
Typ. Max. Min.
Typ. Max. Unit ns MHz 4 4 55 250 V/ns V/ns % ps
tSK tSK
Output Skew
175 500
175 500
ps ps
CPU to SDRAM Covers all CPU/SDRAM Clock Skew outputs. Measured on rising edge at 1.5V. Frequency Stabilization from Power-up (cold start) AC Output Impedance Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 15
fST
3
3
3
ms
Zo
20
10
15
20
10
15
20
12
PRELIMINARY
PCI Clock Outputs, PCI0:6 (Lump Capacitance Test Load = 30 pF) PCI = 33.3 MHz Parameter tP f tH tL tR tF tD tJC tSK tO fST Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 20 1 2 12 12 1 1 45 Min. 30 33.3 Typ.
W207B
Max.
Unit ns MHz ns ns
4 4 55 500 500 4 3
V/ns V/ns % ps ps ns ms
Zo
30
REF0_2X Clock Output (Lump Capacitance Test Load = 45 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 17 20 1 1 45 Min. Typ. 14.318 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
25
REF1 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 25 1 1 45 Min. Typ. 14.318 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
35
13
PRELIMINARY
SIO Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 20 1 1 40 Min. Typ.
W207B
Max.
Unit MHz ppm
48.008/24.004 +167 57/17, 57/34 4 4 55 3
V/ns V/ns % ms
Zo
30
Serial Input Port Parameter fSCLOCK tSTHD tLOW tHIGH tDSU tDHD tR tF tSTSU tSPF tSP Description SCLOCK Frequency Start Hold Time SCLOCK Low Time SCLOCK High Time Data Set-up Time Data Hold Time Rise Time, SDATA and SCLOCK Fall Time, SDATA and SCLOCK Stop Set-up Time Bus Free Time between Stop and Start Condition Allowable Noise Spike Pulse Width (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) From 0.3VDD to 0.7VDD From 0.7VDD to 0.3VDD 4.0 4.7 50 Test Condition/Comments Normal Mode Min. 0 4.0 4.7 4.0 250 0 1000 300 Typ. Max. 100 Unit kHz s s s ns ns ns ns s s ns
14
PRELIMINARY
2.5V AC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V), VDDQ2= 2.5V5% (2.375-2.625V), fXTL = 14.31818 MHz Spread Spectrum function turned off
W207B
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, (Lump Capacitance Test Load = 20 pF) Parameter tP f tH tL tR tF tD tJC Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/ Comments Measured on rising edge at 1.25V Determined by PLL divider ratio Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 12 20 5.2 5 0.8 0.8 45 3 3 55 250 CPU = 66.6 MHz 15 TBD 3.0 2.8 0.8 0.8 45 3 3 55 250 CPU = 100 MHz 10.0 TBD 1.87 1.67 0.8 0.8 45 3 3 55 250 CPU = 133 MHz Unit ns TBD MHz ns ns V/ns V/ns % ps 7.5 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
175 3
ps ms
Zo
30
12
20
30
12
20
30
Ordering Information
Ordering Code W207B Document #: 38-00847 Package Name H Package Type 48-pin SSOP (300 mils)
15
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W207B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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