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| W28J161B/T 16M(1M x 16) BOOT BLOCK FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3 2. FEATURES ......................................................................................................................................... 3 3. PRODUCT OVERVIEW ...................................................................................................................... 4 4. BLOCK DIAGRAM .............................................................................................................................. 5 Block Organization ........................................................................................................................... 5 5. PIN CONFIGURATIONS..................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 6 7. PRINCIPLES OF OPERATION........................................................................................................... 7 Data Protection ................................................................................................................................ 7 8. BUS OPERATION ............................................................................................................................... 9 Read................................................................................................................................................. 9 Output Disable ................................................................................................................................. 9 Standby ............................................................................................................................................ 9 Reset ................................................................................................................................................ 9 Read Identifier Codes .................................................................................................................... 10 Write ............................................................................................................................................... 11 9. COMMAND DEFINITIONS................................................................................................................ 11 Read Array Command ................................................................................................................... 13 Read Identifier Codes Command................................................................................................... 13 Read Status Register Command ................................................................................................... 13 Clear Status Register Command ................................................................................................... 14 Block Erase Command .................................................................................................................. 14 Full Chip Erase Command ............................................................................................................. 14 Word Write Command.................................................................................................................... 15 Block Erase Suspend Command ................................................................................................... 15 Word Write Suspend Command .................................................................................................... 16 Set Block and Permanent Lock-Bit Commands............................................................................. 16 Clear Block Lock-Bits Command ................................................................................................... 17 Block Locking by the #WP ............................................................................................................. 17 -1- Publication Release Date: April 7, 2003 Revision A4 W28J161B/T 10. DESIGN CONSIDERATIONS ......................................................................................................... 27 Three-Line Output Control ............................................................................................................. 27 Power Supply Decoupling .............................................................................................................. 27 VPP Trace on Printed Circuit Boards .............................................................................................. 27 VDD, VPP, #RESET Transitions ....................................................................................................... 27 Power-Up/Down Protection............................................................................................................ 28 Power Dissipation .......................................................................................................................... 28 Data Protection Method ................................................................................................................. 28 11. ELECTRICAL SPECIFICATIONS ................................................................................................... 29 Absolute Maximum Ratings* .......................................................................................................... 29 Operating Conditions ..................................................................................................................... 29 Capacitance ................................................................................................................................... 29 AC Input/Output Test Conditions ................................................................................................... 30 DC Characteristics ......................................................................................................................... 31 AC Characteristics - Read-only Operations(1) .............................................................................. 33 AC Characteristics - Write Operations(1) ...................................................................................... 34 Alternative #CE - Controlled Writes(1)........................................................................................... 36 Reset Operations ........................................................................................................................... 38 Block Erase, Full Chip Erase, Word Write And Lock-Bit Configuration Performance(3)............... 39 12. ADDITIONAL INFORMATION......................................................................................................... 40 Recommended Operating Conditions............................................................................................ 40 13. ORDERING INFORMATION........................................................................................................... 42 14. PACKAGE DIMENSION.................................................................................................................. 42 48-Ball TFBGA (measurements in millimeters) ............................................................................. 42 15. VERSION HISTORY ....................................................................................................................... 43 -2- W28J161B/T 1. GENERAL DESCRIPTION The W28J161B/T Flash memory chip is a high-density, cost-effective, nonvolatile, read/write storage device suited for a wide range of applications. It operates off of VDD = 2.7V to 3.6V, with VPP of 2.7V to 3.6V or 11.7V to 12.3V. This low voltage operation capability enbales use in low power applications. The IC features a boot, parameter and main-blocked architecture, as well as low voltage and extended cycling. These features provide a highly flexible device suitable for portable terminals and personal computers. Additionally, the enhanced suspend capabilities provide an ideal solution for both code and data storage applications. For secure code storage applications, such as networking where code is either directly executed out of flash or downloaded to DRAM, the device offers four levels of protection. These are: absolute protection, enabled when VPP VPPLK; selective hardware blocking; flexible software blocking; or write protection. These alternatives give designers comprehensive control over their code security needs. The device is manufactured using 0.25 m process technology. It comes in chip-size package: the 0.75 mm pitch 48-ball TFBGA, which makes it ideal for small real estate applications. 2. FEATURES * Low Voltage Operation - Word Write Suspend to Read - Block Erase Suspend to Word Write - Block Erase Suspend to Read * Enhanced Data Protection Features - VDD = VPP = 2.7V to 3.6V Single Voltage * 16bit I/O Interface * High-Performance Read Access Time - 90 nS (VDD = 2.7V to 3.6V) * Operating Temperature - Absolute Protection with VPP VPPLK - Block Erase, Full Chip Erase, Word Write and Lock-Bit Configuration Lockout during Power Transitions - Block Locking with Command and #WP - Permanent Locking * Automated Block Erase, Full Chip Erase, Low - -40 C to +85 C * Low Power Management - 2 A (VDD = 3.0V)Typical Standby Current - Automatic Power Savings Mode Decreases ICCR in Static Mode - 120 A (VDD = 3.0V, TA =+25 C, f=32kHz)Typical Read Current * Optimized Array Blocking Architecture Power Management Word Write and Lock-Bit Configuration - Command User Interface (CUI) - Status Register (SR) * SRAM-Compatible Write Interface * Chip-Size Packaging - Two 4k-word Boot Blocks - Six 4k-word Parameter Blocks - Thirty-one 32k-word Main Blocks - Top or Bottom Boot Location * Extended Cycling Capability - 0.75 mm pitch 48-Ball TFBGA * Nonvolatile Flash Technology * CMOS Process (P-type silicon substrate) * Not designed or rated as radiation hardened - Minimum 100,000 Block Erase Cycles * Enhanced Automated Suspend Options -3- Publication Release Date: April 7, 2003 Revision A4 W28J161B/T 3. PRODUCT OVERVIEW The W28J161B/T is a high-performance 16M-bit Boot Block Flash memory organized as 1M-word of 16 bits. The 1M-word of data is arranged in two 4k-word boot blocks, six 4k-word parameter blocks and thirty-one 32k-word main blocks which are individually erasable, lockable and unlockable insystem. The memory map is shown in Figure 3. The dedicated VPP pin gives complete data protection when VPP VPPLK. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, word write and lock-bit configuration operations. A block erase operation erases one of the device's 32k-word blocks typically within 1.2s (3V VDD, 3V VPP), 4k-word blocks typically within 0.6s (3V VDD, 3V VPP) independent of other blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word increments of the device's 32k-word blocks typically within 33 S (3V VDD, 3V VPP), 4k-word blocks typically within 36 S (3V VDD, 3V VPP). Word write suspend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and #WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word write operations, while the permanent lock-bit gates block lock-bit modification and locked block alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear Block LockBits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase, full chip erase, word write or lock-bit configuration operation is finished. The access time is 90 nS (tAVQV) over the operating temperature range (-40 C to +85 C) and VDD supply voltage range of 2.7V to 3.6V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 2 A (CMOS) at 3.0V VDD. When #CE and #RESET pins are at VDD, the ICC CMOS standby mode is enabled. When the #RESET pin is at VSS, reset mode is enabled which minimizes power consumption and provides write protection. A reset time (tPHQV) is required from #RESET switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are recognized. With #RESET at VSS, the WSM is reset and the status register is cleared. Overwriting a "0" to a bit already holding a data "0" may render this bit un-erasable. In order to avoid this potential "stuck bit" failure, when re-programming (changing data from "1" to "0") the following should be followed: * * Program "0" for the bit in which you want to change data from "1" to "0". Program "1" for the bit which is already holding a data "0". (Note: Since only an erase process can change the data from "0" to "1", programming "1" to a bit holding a data "0" will not change the data). For example, changing data from "10111101" to "10111100" requires "11111110" programming. -4- W28J161B/T 4. BLOCK DIAGRAM DQ0 -DQ15 Output Buffer Input Buffer I/O Logic Identifier Register Output Multiplexer Status Register Data Register Command User Interface VDD #CE #WE #OE #RESET #WP Data Comparator A0-A19 Input Buffer Y Decoder Y-Gating Write State Machine RY/#BY Program/Erase Voltage Switch VPP Parameter Block 0 Parameter Block 1 Parameter Block 2 Parameter Block 3 Parameter Block 4 Parameter Block 5 Boot Block 0 Boot Block 1 Address Latch X Decoder Main Block 29 Address Counter Figure 1. Block Diagram Block Organization This product features an asymmetrically blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times. For the address locations of the blocks, see the memory map in Figure 3. Boot Blocks: The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller-based system. This boot block 4k words (4,096words) features hardware controllable write protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the VPP, #RESET, #WP pins and block lock-bit. Parameter Blocks: The boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each boot block component contains six parameter blocks of 4k words (4,096 words) each. The protection of the parameter block is controlled using a combination of the VPP, #RESET and block lock-bit. Main Blocks: The reminder is divided into main blocks for data or code storage. Each 16M-bit device contains thirty-one 32k words (32,768 words) blocks. The protection of the main block is controlled using a combination of the VPP, #RESET and block lock-bit. Main Block 30 Main Block 0 Main Block 1 32K-Word (64K-Byte) Main Blocks x 31 VDD VSS -5- Publication Release Date: April 7, 2003 Revision A4 W28J161B/T 5. PIN CONFIGURATIONS 1 2 A11 3 A8 4 Vpp 5 #WP 6 A19 7 A7 8 A4 A B C D E F A13 A14 A10 #WE #RESET A18 A17 A5 A2 0.75mm pitch 48-Ball TFBGA Pinout A15 A12 A9 NC NC A6 A3 A1 8 x 8 mm TOP VIEW A16 DQ14 DQ5 DQ11 DQ2 DQ8 #CE A0 VDD DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 VSS VSS DQ7 DQ13 DQ4 VDD DQ10 DQ1 #OE Figure 2. 0.75 mm pitch TFBGA 48-Ball Pinout 6. PIN DESCRIPTION SYM. A0 - A19 DQ0 - DQ15 #CE TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A15 - A19: Main Block Address. A12 - A19: Boot and Parameter Block Address. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. #CE-high deselects the device and reduces power consumption to standby levels. RESET: Resets the device internal automation. #RESET-high enables normal operation. When driven low, #RESET inhibits write operations which provides data protection during power transitions. Exit from reset mode sets the device to read array mode. #RESET must be VIL during power-up. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the #WE pulse. WRITE PROTECT: When #WP is VIL, boot blocks cannot be written or erased. When #WP is VIH, locked boot blocks can not be written or erased. #WP is not affected parameter and main blocks. INPUT/ OUTPUT INPUT #RESET #OE #WE #WP INPUT INPUT INPUT INPUT -6- W28J161B/T Pin Description, Continued SYM. TYPE NAME AND FUNCTION BLOCK ERASE, FULL CHIP ERASE, WORD WRITE OR LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words or configuring lock-bits. With VPP VPPLK, memory contents cannot be altered. Block erase, full chip erase, word write and lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. Applying 12V 0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block. VPP may be connected to 12V 0.3V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With VDD VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VDD voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. VPP SUPPLY VDD SUPPLY SUPPLY VSS NC Table 1 7. PRINCIPLES OF OPERATION The W28J161B/T flash memory includes an on-chip WSM to manage block erase, full chip erase, word write and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, word write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset mode (see Bus Operations section), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erase, full chip erase, word write and lock-bit configurations. All functions associated with altering memory contents (block erase, full chip erase, word write, lock-bit configuration, status and identifier codes) are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, word write and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, word write and lockbit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location. Data Protection When VPP VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, full chip erase, word write or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VDD is below the write lockout voltage VLKO or when #RESET is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and word write operations. Refer to Table 5 for write protection alternatives. Publication Release Date: April 7, 2003 Revision A4 -7- W28J161B/T [A19-A0] Top Boot 4KW/8KB Boot Block 0 4KW/8KB Boot Block 1 4KW/8KB Parameter Block 0 4KW/8KB Parameter Block 1 4KW/8KB Parameter Block 2 4KW/8KB Parameter Block 3 4KW/8KB Parameter Block 4 4KW/8KB Parameter Block 5 32KW/64KB Main Block 0 32KW/64KB Main Block 1 32KW/64KB Main Block 2 32KW/64KB Main Block 3 32KW/64KB Main Block 4 32KW/64KB Main Block 5 32KW/64KB Main Block 6 32KW/64KB Main Block 7 32KW/64KB Main Block 8 32KW/64KB Main Block 9 32KW/64KB Main Block 10 32KW/64KB Main Block 11 32KW/64KB Main Block 12 32KW/64KB Main Block 13 32KW/64KB Main Block 14 32KW/64KB Main Block 15 32KW/64KB Main Block 16 32KW/64KB Main Block 17 32KW/64KB Main Block 18 32KW/64KB Main Block 19 32KW/64KB Main Block 20 32KW/64KB Main Block 21 32KW/64KB Main Block 22 32KW/64KB Main Block 23 32KW/64KB Main Block 24 32KW/64KB Main Block 25 32KW/64KB Main Block 26 32KW/64KB Main Block 27 32KW/64KB Main Block 28 32KW/64KB Main Block 29 32KW/64KB Main Block 30 [A19-A0] FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 Bottom Boot 32KW/64KB Main Block 30 32KW/64KB Main Block 29 32KW/64KB Main Block 28 32KW/64KB Main Block 27 32KW/64KB Main Block 26 32KW/64KB Main Block 25 32KW/64KB Main Block 24 32KW/64KB Main Block 23 32KW/64KB Main Block 22 32KW/64KB Main Block 21 32KW/64KB Main Block 20 32KW/64KB Main Block 19 32KW/64KB Main Block 18 32KW/64KB Main Block 17 32KW/64KB Main Block 16 32KW/64KB Main Block 15 32KW/64KB Main Block 14 32KW/64KB Main Block 13 32KW/64KB Main Block 12 32KW/64KB Main Block 11 32KW/64KB Main Block 10 32KW/64KB Main Block 9 32KW/64KB Main Block 8 32KW/64KB Main Block 7 32KW/64KB Main Block 6 32KW/64KB Main Block 5 32KW/64KB Main Block 4 32KW/64KB Main Block 3 32KW/64KB Main Block 2 32KW/64KB Main Block 1 32KW/64KB Main Block 0 4KW/8KB Parameter Block 5 4KW/8KB Parameter Block 4 4KW/8KB Parameter Block 3 4KW/8KB Parameter Block 2 4KW/8KB Parameter Block 1 4KW/8KB Parameter Block 0 4KW/8KB Boot Block 1 4KW/8KB Boot Block 0 FFFFF FF000 FEFFF FE000 FDFFF FD000 FCFFF FC000 FBFFF FB000 FAFFF FA000 F9FFF F9000 F8FFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000 Figure 3. Memory Map -8- W28J161B/T 8. BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Read Information can be read from any block, identifier codes or status register independent of the VPP voltage. #RESET can be at VIH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: #CE, #OE, #WE, #RESET and #WP. #CE and #OE must be driven active to obtain data at the outputs. #CE is the device selection control, and when active enables the selected memory device. #OE is the data output (DQ0 - DQ15) control and when active drives the selected memory data onto the I/O bus. #WE must be at VIH, #RESET must be at VIH, and #WP must be at VIL or VIH. Figure 14 illustrates read cycle. Output Disable With #OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 - DQ15) are placed in a high-impedance state. Standby Setting #CE to a logic-high level (VIH) deselects the device and places it in standby mode, which substantially reduces device power consumption. DQ0 - DQ15 outputs are placed in a high impedance state independent of #OE. If deselected during block erase, full chip erase, word write or lock-bit configuration, the device continues functioning, and it continues to consume active power until the operation is completed. Reset Setting #RESET to VIL initiates the reset mode. In read modes, setting #RESET at VIL deselects the memory, places output drivers in a highimpedance state and turns off all internal circuits. #RESET must be held low for a minimum of 100 nS. A delay (tPHQV) is required after return from reset until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode status register is set to 80H, and all blocks are locked. During block erase, full chip erase, word write or lock-bit configuration modes, #RESET at VIL will abort the operation. RY/#BY remains low until the reset operation is complete. Memory contents at the aborted location are no longer valid since the data may be partially erased or written. A delay (tPHWL) is required after #RESET goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert #RESET during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, word write or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Winbond's flash memory solutions allow proper CPU initialization following a system reset through the use of the #RESET input. In this application, #RESET is controlled by the same #RESET signal that resets the system CPU. -9- Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Read Identifier Codes The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting. [A19-A0] FFFFF FF003 FF002 FF001 FF000 FEFFF FE003 FE002 FE001 FE000 FDFFF FD003 FD002 FD001 FD000 FCFFF F9000 F8FFF F8003 F8002 F8001 F8000 F7FFF F0003 F0002 F0001 F0000 EFFFF 08000 07FFF 00004 00003 00002 00001 00000 Top Boot Reserved for Future Implementation Boot Block 0 Lock Configuration Code Reserved for Future Implementation Boot Block0 Reserved for Future Implementation Boot Block 1 Lock Configuration Code Reserved for Future Implementation Boot Block1 Reserved for Future Implementation Parameter Block 0 Lock Configuration Code Reserved for Future Implementation Parameter Block0 (Parameter Blocks 1 through 4) Reserved for Future Implementation Parameter Block 5 Lock Configuration Code Reserved for Future Implementation Parameter Block5 Reserved for Future Implementation Main Block 0 Lock Configuration Code Reserved for Future Implementation Mani Block0 (Main Blocks 1 through 29) Reserved for Future Implementation Permanent Lock Configuration Code Main Block 30 Lock Configuration Code Device Code Manufacturer Code Mani Block 30 [A19-A0] FFFFF F8003 F8002 F8001 F8000 F7FFF 10000 0FFFF 08003 08002 08001 08000 07FFF 07003 07002 07001 07000 06FFF 03000 02FFF 02003 02002 02001 02000 01FFF Bottom Boot Reserved for Future Implementation Main Block 30 Lock Configuration Code Reserved for Future Implementation Main Block30 (Main Blocks 1 through 29) Reserved for Future Implementation Main Block 0 Lock Configuration Code Reserved for Future Implementation Mani Block0 Reserved for Future Implementation Parameter Block 5 Lock Configuration Code Reserved for Future Implementation Parameter Block5 (Parameter Blocks 1 through 4) Reserved for Future Implementation Parameter Block 0 Lock Configuration Code Reserved for Future Implementation Parameter Block0 Reserved for Future Implementation 01003 01002 01001 01000 00FFF 00004 00003 00002 00001 00000 Boot Block 1 Lock Configuration Code Reserved for Future Implementation Boot Block1 Reserved for Future Implementation Permanent Lock Configuration Code Boot Block 0 Lock Configuration Code Device Code Manufacturer Code Boot Block 0 Figure 4. Device Identifier Code - 10 - W28J161B/T Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VDD = 2.7V to 3.6V and VPP = VPPH1/2, the CUI additionally controls block erase, full chip erase, word write and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Full Chip Erase command requires appropriate command data and an address within the device. The Word Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. A write occurs when #WE and #CE are active (low). The address and data needed to execute a command are latched on the rising edge of #WE or #CE, whichever occurs first. Standard microprocessor write timings are used. Figures 15 and 16 illustrate #WE and #CE controlled write operations. 9. COMMAND DEFINITIONS When VPP VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Setting VPPH1/2 = VPP enables successful block erase, full chip erase, word write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Table 2 Bus Operations MODE Read (note 7) Output Disable Standby Reset (note 3) Read Identifier Codes (note 7) Write (note 5, 6, 7) Notes: 1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK voltages. 3. #RESET at VSS 0.2V ensures the lowest power consumption. 4. See Read Identifier Code Command section for details. 5. Command writes involving block erase, full chip erase, word write or lock-bit configuration are reliably executed when VPP = VPPH1/2 and VDD = 2.7V to 3.6V. 6. Refer to Table 3 for valid DIN during a write operation. 7. Never hold #OE low and #WE low at the same timing. (note 1, 2) #RESET VIH VIH VIH VIL VIH VIH #CE VIL VIL VIH X VIL VIL #OE VIL VIH X X VIL VIH #WE VIH VIH X X VIH VIL ADDRESS X X X X See Figure 4 X VPP X X X X X X DQ0 - 15 DOUT High Z High Z High Z Note 4 DIN - 11 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Table 3. Command Definitions(10) COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume Set Block Lock-Bit Clear Block Lock-Bits Set Permanent Lock-Bit Notes: 1. BUS operations are defined in Table 2. 2. X = Any valid address within the device. IA = Identifier Code Address: see Figure 4. BA = Address within the block being erased. WA = Address of memory location to be written. 3. ID = Data read from identifier codes. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first). 4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and permanent lock configuration codes. See Read Identifier Code Command section for details. 5. If #WP is VIL, boot blocks are locked without block lock-bits state. If #WP is VIH, boot blocks are locked by block lockbits. The parameter and main blocks are locked by block lock-bits without #WP state. 6. Either 40H or 10H are recognized by the WSM as the word write setup. 7. The clear block lock-bits operation simultaneously clears all block lock-bits. 8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done. 9. Once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. Commands other than those shown above are reserved by Winbond for future device implementations and should not be used. BUS CYCLES REQ'D. 1 2 (note 4) 2 1 2 (note 5) 2 2 (note 5, 6) 1 (note 5) 1 (note 5) 2 (note 8) 2 (note 7, 8) 2 (note 9) FIRST BUS CYCLE Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) X X X X X X X X X X X X Data(3) FFH 90H 70H 50H 20H 30H 40H or 10H B0H D0H 60H 60H 60H SECOND BUS CYCLE Oper(1) Read Read Write Write Write Addr(2) IA X BA X WA Data(3) ID SRD D0H D0H WD Write Write Write BA X X 01H D0H F1H - 12 - W28J161B/T Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, word write or lock-bit configuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the VPP voltage and #RESET can be VIH. Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and permanent lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and #RESET can be VIH. Following the Read Identifier Codes command, the following information can be read: Table 4. Identifier Codes CODE Manufacture Code Device Code Top Boot Bottom Boot ADDRESS [A19 - A0] 00000H 00001H DATA [DQ15 - DQ0] 00B0H 00E8H 00E9H DQ0 = 0 DQ0 = 1 DQ1 - 15 DQ0 = 0 DQ0 = 1 DQ1 - 15 Block Lock Configuration * Block is Unlocked * Block is Locked * Reserved for Future Use Permanent Lock Configuration * Device is Unlocked * Device is Locked ed * Reserved for Future Use 00003H BA(1)+2 Note: BA selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. Read Status Register Command The status register may be read to determine when a block erase, full chip erase, word write or lockbit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of #OE or #CE, whichever occurs last. #OE or #CE must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. #RESET can be VIH. - 13 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Clear Status Register Command Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. #RESET can be VIH. This command is not functional during block erase or word write suspend modes. Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (all bits within the block being set to "1"). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase for boot blocks requires that #WP = VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleared the corresponding block lock-bit. If block erase is attempted when the excepting above conditions, SR.1 and SR.5 will be set to "1". Full Chip Erase Command This command followed by a confirm command erases all of the unlocked blocks. A full chip erase setup (30H) is first written, followed by a full chip erase confirm (D0H). After a confirm command is written, device erases the all unlocked blocks block by block. This command sequence requires appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle full chip erase sequence is written, the device automatically outputs status register data when can be read (see Figure 6). The CPU can detect full chip erase completion by analyzing the output data of the status register bit SR.7. When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. If error is detected on a block during full chip erase operation, WSM stops erasing. Full chip erase operation start from lower address block, finish the higher address block. Full chip erase can not be suspended. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VDD = 2.7V to - 14 - W28J161B/T 3.6V and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If full chip erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful full chip erase requires for boot blocks that #WP is VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must clear the corresponding block lock-bit. If all blocks are locked, SR.1 and SR.5 will be set to "1". Word Write Command Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of #WE). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word write event by analyzing the status register bit SR.7. When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word writes can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write for boot blocks requires that #WP = VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, the corresponding block lock-bit must be cleared. If word write is attempted under these conditions, SR.1 and SR.4 will be set to "1". Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data that must be read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). The period tWHR12 defines the block erase suspend latency. When Block Erase Suspend command writes to the CUI, if block erase is finished, the device is placed in read array mode. Therefore, after Block Erase Suspend command writes to the CUI, Read Status Register command (70H) has to write to CUI, and then status register bit SR.6 should be checked to confirm that the device is in suspend mode. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. To program data in other blocks, a Word Write command sequence can also be issued during erase suspend. Using the Word Write Suspend command (reference the Word Write Suspend Command subsection), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to "0". However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear. After the Erase Resume command is written, the device automatically outputs status register data when read Publication Release Date: April 7, 2003 Revision A4 - 15 - W28J161B/T (see Figure 8). VPP must remain at VPPH1/2 (the same VPP level used for block erase) while block erase is suspended. #RESET must also remain at VIH. #WP must also remain at VIL or VIH (the same #WP level used for block erase). Block erase cannot resume until word write operations initiated during block erase suspend have completed. If the time from Block Erase Resume command write to the CUI till Block Erase Suspend command write to the CUI is short, it can be repeated. In addition, erase time be prolonged. Word Write Suspend Command The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, sending the Word Write Suspend command causes the WSM to suspend the Word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). The period tWHR11 defines the word write suspend latency parameters. When Word Write Suspend command writes to the CUI, the device is placed in read array mode if word write is finished. Therefore, after Word Write Suspend command writes to the CUI, the Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be checked to confirm the device is in suspend mode. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Figure 9). VPP must remain at VPPH1/2 (the same VPP level used for word write) while in word write suspend mode. #RESET must also remain at VIH. #WP must also remain at VIL or VIH (the same #WP level used for word write). If the period from Word Write Resume command write to Word Write Suspend command write is too short, it can be repeated, and the write time will be prolonged. Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and #WP pin. The block lock-bits and #WP pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Permanent Lock-Bit command sets the permanent lock-bit. After the permanent lock-bit is set, block lock-bits and locked block contents cannot be altered. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). The WSM then executes the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 10). The CPU can detect the completion of the set lock-bit event by analyzing the status register bit SR.7. - 16 - W28J161B/T When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VDD = 2.7V to 3.6V and VPP = VPPH1/2. In the absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail. Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. If the permanent lock-bit is not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the permanent lock-bit is set, block lock-bits cannot be cleared. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect completion of the clear block lock-bits event by reading the status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VDD = 2.7V to 3.6V and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be set to "1" and the operation will fail. If a clear block lock-bits operation is aborted due to VPP or VDD transitioning out of valid range or #RESET active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared. Block Locking by the #WP This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable two boot blocks are locked when #WP = VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. If #WP is VIH and block lock-bit is not set, boot block can be programmed or erased normally (Unless VPP is below VPPLK). #WP is valid only two boot blocks, other blocks are not affected. - 17 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Table 5. Write Protection Alternatives OPERATION VPP VPPLK #RESET X VIL Block Erase or Word Write > VPPLK PERMANENT LOCK-BIT X X BLOCK LOCK-BIT X X 0 VIH X 1 VPPLK X VIL Full Chip Erase > VPPLK X X X X #WP X X VIL VIH VIL VIH X X VIL VIH X X VIH VPPLK Set Block Lock-Bit > VPPLK X VIL VIH X VIL > VPPLK VIH X VIL VIH X X 0 1 X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X EFFECT All Blocks Locked. All Blocks Locked. 2 Boot Blocks Locked. Block Erase and Word Write Enabled. Block Erase and Word Write Disabled. Block Erase and Word Write Disabled. All Blocks Locked. All Blocks Locked. All Unlocked Blocks are Erased. 2 Boot Blocks and Locked Blocks are NOT Erased. All Unlocked Blocks are Erased. Locked Blocks are NOT Erased. Set Block Lock-Bit Disabled. Set Block Lock-Bit Disabled. Set Block Lock-Bit Enabled. Set Block Lock-Bit Disabled. Clear Block Lock-Bits Disabled. Clear Block Lock-Bits Disabled. Clear Block Lock-Bits Enabled. Clear Block Lock-Bits Disable. Set Permanent Lock-Bit Disabled. Set Permanent Lock-Bit Disabled. Set Permanent Lock-Bit Enabled. VPPLK Clear Block Lock-Bits VPPLK Set Permanent Lock-Bit > VPPLK - 18 - W28J161B/T Table 6. Status Register Definition WSMS 7 BESS 6 ECBLBS 5 WWSLBS 4 VPPS 3 WWSS 2 Notes: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS (ECBLBS) 1 = Error in Block Erase, Full Chip Erase or Clear Block Lock-Bits 0 = Successful Block Erase, Full Chip Erase or Clear Block Lock-Bits SR.4 = WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS) 1 = Error in Word Write or Set Block/Permanent Lock-Bit 0 = Successful Word Write or Set Block/Permanent LockBit SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = WORD WRITE SUSPEND STATUS (WWSS) 1 = Word Write Suspended 0 = Word Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Lock-Bit, Permanent Lock-Bit and/or #WP Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Check SR.7 to determine block erase, full chip erase, word write or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase or lock-bit configuration attempt, an improper command sequence was entered. DPS 1 R 0 SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after Block Erase, Full Chip Erase, Word Write or Lock-Bit Configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1/2. SR.1 does not provide a continuous indication of permanent and block lock-bit and #WP values. The WSM interrogates the permanent lock-bit, block lock-bit and #WP only after Block Erase, Full Chip Erase, Word Write or Lock-Bit Configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/or #WP is VIL. Reading the block lock and permanent lock configuration codes after writing the Read Identifier Codes command indicates permanent and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. - 19 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Bus Operation Start Command Read Status Register Comments Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write Write 70H Read Standby 0 Read Status Register SR.7= Write Write Read Standby No Suspend Block Erase Loop Yes Erase Setup Erase Confirm 1 Write 20H Data = 20H Addr = X Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write D0H, Block Address Read Status Register Suspend Block Erase SR.7= 1 Full Status Check if Desired Block Erase Complete 0 Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode. Full STATUS CHECK PROCEDURE Bus Operation Read Status Register Data(See Above) 1 Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Standby Standby SR.3= 0 SR.1= 0 SR.4,5= 0 SR.5= 0 Vpp Range Error 1 Standby Device Protect Error 1 Command Sequence Error Standby 1 Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Block Erase Sucessfully Figure 5. Automated Block Erase Flowchart - 20 - W28J161B/T Start Bus Operation Write Command Read Status Register Comments Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 70H Read Read Status Register Standby 0 SR.7= 1 Write 30H Write Write Read Standby Full Chip Erase Setup Full Chip Erase Confirm Data = 30H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write D0H Read Status Register SR.7= 1 Full Status Check if Desired Full Chip Erase Complete 0 Full status check can be done after each full chip erase. Write FFH after the last operation to place device in read array mode. Full STATUS CHECK PROCEDURE Bus Operation Read Status Register Data(See Above) 1 Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect (All Blocks are locked) Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1 = Full Chip Erase Error Standby Vpp Range Error SR.3= 0 SR.1= 0 SR.4,5= 0 SR.5= 0 Full Chip Erase Successfully Standby 1 Device Protect Error Standby 1 Command Sequence Error Standby 1 Full Chip Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Full Chip Erase Flowchart - 21 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Start Bus Operation Write Command Read Status Register Comments Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Data = 40H or 10H Addr = X Data = Data to Be Written Addr = Location to Be written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 70H Read Standby 0 Read Status Register SR.7= Write Write Read Standby No Suspend Word/Byte Write Loop Yes 1 Write 40H or 10H Setup Word Write Word Write Write Word/Byte Data and Adddress Read Status Register 0 Suspend Word/Byte Write Repeat for subsequent word writes. SR full status check can be done after each word write, or after a sequence of word writes. Write FFH after the last word write operation to place device in read array mode. SR.7= 1 Full Status Check if Desired Word/Byte Write Complete Full STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 Bus Operation Standby Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Check SR.4 1 = Data Write Error SR.3= 0 SR.1= 0 SR.4= 0 Word/Byte Write Successfully Vpp Range Error Standby 1 Device Protect Error Standby 1 Word/Byte Write Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 7. Automated Word Write Flowchart - 22 - W28J161B/T Start Bus Operation Write Read Command Erase Suspend Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Write B0H Read Status Register 0 Standby SR.7= 1 SR.6= 1 Read Read Array Data Read or Word/Byte Write? 0 Block Erase Complete Standby Word/Byte write Wore/Byte Write Loop Write Erase Resume Data = D0H Addr = X No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 8. Block Erase Suspend/Resume Flowchart - 23 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Start Bus Operation Command Write B0H Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Word Write Suspended 0 = Word Write Completed Write Read Word Write Suspend Read Status Register 0 SR.7= 1 Standby 0 SR.2= 1 Word/Byte Write Completed Standby Write Read Array Data = FFH Addr = X Read Array locations other than that being written. Write FFH Read Read Array Data Write Done Reading Yes Write D0H Write FFH No Word Write Resume Data = D0H Addr = X Word/Byte Write Resumed Read Array Data Figure 9. Word Write Suspend/Resume Flowchart - 24 - W28J161B/T Start Bus Operation Write Read Command Read Status Register Comments Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 70H Read Status Register Standby 0 SR.7= 1 Write 60H Write Set Block/ Permanent Lock-Bit Setup Set Block or Permanent Lock-Bit Confirm Data = 60H Addr = X Data = 01H(Block), F1H(Permanent) Addr = Block Address(Block), Device Address(Permanent) Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write 01H/F1H Block/Device Address Read Status Register Write Read 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete Standby Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. Full STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 Bus Operation Command Standby Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Permanent Lock-Bit is Set (Set Block Lock-Bit Operation) Check SR.4, 5 SR.3= 0 SR.1= 0 SR.4,5= 0 SR.4= 0 Vpp Range Error Standby 1 Device Protect Error Standby 1 Command Sequence Error Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error 1 Standby Set Lock-Bit Error Set Lock-Bit Successfully SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 10. Set Block and Permanent Lock-Bit Flowchart - 25 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Bus Operation Start Write Read Standby Command Read Status Register Write 70H Comments Data = 70H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Read Status Register Write SR.7= 0 Write Read 1 Write 60H Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm Data = 60H Addr = X Data = D0H Addr = X Write D0H Read Status Register Status Register Data Check SR.7 Standby 1 = WSM Ready 0 = WSM Busy Write FFH after the Clear Block Lock-Bits operation to place device in read array mode. SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete 0 Full STATUS CHECK PROCEDURE Bus Operation Read Status Register Data(See Above) 1 Command Standby Vpp Range Error SR.3= 0 SR.1= 0 SR.4,5= 0 SR.5= 0 Clear Block Lock-Bits Successfully Standby 1 Device Protect Error Standby Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Permanent Lock-Bit is Set Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error 1 Command Sequence Error Standby 1 Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 11. Clear Block Lock-Bits Flowchart - 26 - W28J161B/T 10. DESIGN CONSIDERATIONS Three-Line Output Control This device will often be used in large memory arrays. Winbond provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable #CE while #OE should be connected to all memory devices and the system's #READ control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. #RESET should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of #CE and #OE. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between VDD and VSS and between VPP and VSS. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VDD and VSS. The bulk capacitor will overcome voltage drops caused by PC board trace inductance. VPP Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for word writing and block erasing. Use similar trace widths and layout considerations given to the VDD power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. VDD, VPP, #RESET Transitions Block erase, full chip erase, word write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2 range, VDD falls outside of a valid 2.7V to 3.6V range, or #RESET VIH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If #RESET transitions to VIL during block erase, full chip erase, word write or lock-bit configuration, SR.7 will remain "0" until the reset operation is complete. Then, the operation will abort and the device will enter reset mode. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or #RESET transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or #CE transitions or WSM actions. Its state is read array mode upon power-up, after exit from reset mode or after VDD transitions below VLKO. - 27 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Power-Up/Down Protection The device is designed to offer protection against accidental block erase, full chip erase, word write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power supply (VPP or VDD) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VDD voltages above VLKO when VPP is active. Since both #WE and #CE must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while #RESET = VIL regardless of its control inputs state. Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. Data Protection Method On some systems, noise having a level exceeding the limit dictated in the specification may be generated under specific operating conditions. Such noise, when induced onto #WE signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against undesired overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block When a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against overwriting. By setting a #WP low, only the 2 boot blocks can be protected against overwriting. By using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). The permanent lock bit can be used to prevent false block bit setting. For further information on setting/resetting lock-bit, refer to the specification. 2) Data protection through VPP When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the specification. 3) Data protection through #RESET When the #RESET is kept low during read mode, the flash memory will be in reset mode, write protecting all blocks. When the #RESET is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. For the details of #RESET control, refer to the specification. - 28 - W28J161B/T 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word Write and Lock-Bit Configuration ................................................................................................ -40C to +85C (1) Storage Temperature During under Bias .............................. ..................................................................................... -40C to +85C During non Bias .............................. ..................................................................................... .. -65C to +125C Voltage On Any Pin (except VDD and VPP) ......... .......................................................................................... .. -0.5V to VDD +0.5V(2) VDD Supply Voltage......................... .................................................................................. ....... -0.2V to +4.6V(2) VPP Supply Voltage......................................................................................................... .... -0.2V to +13.0V(2, 3) Output Short Circuit Current............. ....................................................................................................100 mA(4) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Notes: 1. Operating temperature is for extended temperature product defined by this specification. 2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins are VDD +0.5V which, during transitions, may overshoot to VDD +2.0V for periods <20 nS. 3. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 nS. Applying 12V 0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block. VPP may be connected to 12V 0.3V for a total of 80 hours maximum. 4. Output shorted for no more than one second. No more than one output shorted at a time. Operating Conditions Temperature and VDD Operating Conditions PARAMETER Operating Temperature SYMBOL TA VDD MIN. -40 2.7 MAX. +85 3.6 UNIT C V TEST CONDITION Ambient Temperature VDD Supply Voltage (2.7V to 3.6V) Capacitance TA = +25 C, f = 1 MHz PARAMETER Input Capacitance Output Capacitance Note: Sampled, not 100% tested. SYMBOL CIN COUT TYP. 7 9 MAX. 10 12 UNIT pF pF CONDITION VIN = 0.0V VOUT = 0.0V - 29 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T AC Input/Output Test Conditions 2.7 INPUT 0.0 1.35 TEST POINTS 1.35 OUTPUT AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 nS. Figure 12. Transient Input/Output Reference Waveform for VDD = 2.7V to 3.6V +1.3V (IN914) R L =3.3K ohm DEVICE UNDER TEST C L Includes Jig Capacitance CL OUT Figure 13. Transient Equivalent Testing Load Circuit Test Configuration Capacitance Loading Value Test Configuration VDD = 2.7V to 3.6V CL(pF) 50 - 30 - W28J161B/T DC Characteristics PARAMETER Input Load Current (note 1) Output Leakage Current (note1) SYM. ILI ILO TEST CONDITIONS VDD = VDD Max. VIN = VDD or VSS VDD = VDD Max. VOUT = VDD or VSS CMOS Level Inputs VDD = VDD Max. #CE = #RESET= VDD 0.2V TTL Level Inputs VDD = VDD Max. #CE = #RESET = VIH CMOS Level Inputs VDD = VDD Max. #CE = VSS 0.2V #RESET = VSS 0.2V CMOS Level Inputs VDD = VDD Max., #CE= VSS, f = 5 MHz, IOUT = 0 mA TTL Level Inputs VDD = VDD Max., #CE = VSS, f = 5 MHz, IOUT = 0 mA ICCW VPP = 2.7V - 3.6V VPP = 11.7V - 12.3V VPP = 2.7V - 3.6V VPP = 11.7V - 12.3V #CE = VIH VPP VDD VPP > VDD CMOS Level Inputs VDD = VDD Max. #CE = VSS 0.2V #RESET = VSS 0.2V VPP = 2.7V - 3.6V VPP = 11.7V - 12.3V VPP = 2.7V - 3.6V VPP = 11.7V - 12.3V 10 8 5 5 4 4 1 2 10 0.1 0.1 12 2 0.2 2 2 15 VDD = 2.7V - 3.6V Typ. Max. 0.5 0.5 15 2 15 15 25 30 17 12 17 12 6 15 200 5 5 40 30 25 20 200 UNIT A A A mA A A mA mA mA mA mA mA mA A A A A mA mA mA mA A VDD Standby Current (note 1, 5) VDD Auto Power-Save Current (note 1, 4, 5) VDD Reset Power-Down Current (note 1) ICCS ICCAS ICCD VDD Read Current (note 1, 5) ICCR VDD Word Write or Set Lock- Bit Current (note 1, 6) VDD Block Erase, Full Chip Erase or Clear Block Lock-Bits Current (note 1, 6) VDD Word Write or Block Erase Suspend Current (note 1, 2) VPP Standby or Read Current (note 1) VPP Auto Power-Save Current (note 1, 4, 5) VPP Reset Power-Down Current (note 1) VPP Word Write or Set Lock- Bit Current (note 1, 6) VPP Block Erase, Full Chip Erase or Clear Block Lock-Bits Current (note 1, 6) VPP Word Write or Block Erase Suspend Current (note 1) ICCE ICCWS ICCES ICCWS ICCWR ICCWAS ICCWD ICCWW ICCWE ICCWWS VPP = VPPH1/2 ICCWES - 31 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T DC Characteristics (Continued) PARAMETER Input Low Voltage (note 6) Input High Voltage (note 6) Output Low Voltage (note 6) Output High Voltage (TTL) (note 6) SYM. VIL VIH VOL VOH1 TEST CONDITIONS VDD = 2.7V - 3.6V Min. -0.5 2.0 Max. 0.8 VDD +0.5 0.4 2.4 0.85 VDD VDD -0.4 1.0 2.7 11.7 2.0 3.6 12.3 UNIT V V V V V V V V V V VDD = VDD Min. IOL = 2.0 mA VDD = VDD Min. IOH = -2.0 mA VDD = VDD Min. IOH = -2.5 mA VDD = VDD Min. IOH = -100 A Output High Voltage (CMOS) (note 6) VPP Lockout during Normal Operations (note 3, 6) VPP during Block Erase, Full Chip Erase, Word Write or Lock-Bit Configuration Operations VPP during Block Erase, Full Chip Erase, Word Write or Lock-Bit Configuration Operations (note 7) VDD Lockout Voltage Notes: VOH2 VPPLK VPPH1 VPPH2 VLKO 1. All currents are in RMS unless otherwise noted. Typical values at nominal VDD voltage and TA = +25 C. 2. ICCWS and ICCES are specified with the device de-selected. If read or word written while in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW , respectively. 3. Block erases, full chip erase, word writes and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1(max.) and VPPH2 (min.) and above VPPH2(max.). 4. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more than 300ns while read mode. 5. About all of pin except describe Test Conditions, CMOS level inputs are either VDD 0.2V or VSS 0.2V, TTL level inputs are either VIL or VIH. 6. Sampled, not 100% tested. 7. Applying 12V 0.3V to VPP during erase/write can only be done for a maximum of 1000 cycles on each block. VPP may be connected to 12V 0.3V for a total of 80 hours maximum. - 32 - W28J161B/T AC Characteristics - Read-only Operations(1) VDD = 2.7V - 3.6V, TA = -40 C to +85 C PARAMETER Read Cycle Time Address to Output Delay #CE to Output Delay (note 2) #RESET High to Output Delay #OE to Output Delay (note 2) #CE to Output in Low Z (note 3) #CE High to Output in High Z (note 3) #OE to Output in Low Z (note 3) #OE High to Output in High Z (note 3) Output Hold from Address, #CE or #OE Change, Whichever Occurs First (note 3) SYM. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH MIN. 90 MAX. 90 90 600 40 UNIT nS nS nS nS nS nS nS nS nS nS 0 40 0 15 0 Notes: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact on tELQV.. 3. Sampled, not 100% tested. Address(A) #CE(E) VIH VIL VIH VIL Standby Device Address Selection Address Stable Data Valid t AVAV t EHQZ VIH #OE(G) V IL #WE(W) VIH VIL HIGH Z t AVQV t ELQV tELQX t GLQV tGLQX tGHQZ tOH DATA(D/Q) V OH (DQ0-DQ15) VOL V DD V IH V IL Valid Output HIGH Z t PHQV #RESET(P) Figure 14. AC Waveform for Read Operations - 33 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T AC Characteristics - Write Operations(1) VDD = 2.7V to 3.6V, TA = -40 C to +85 C PARAMETER Write Cycle Time #RESET High Recovery to #WE Going Low (note 2) #CE Setup to #WE Going Low #WE Pulse Width #WP VIH Setup to #WE Going High (note 2) VPP Setup to #WE Going High (note 2) Address Setup to #WE Going High (note 3) Data Setup to #WE Going High (note 3) Data Hold from #WE High Address Hold from #WE High #CE Hold from #WE High #WE Pulse Width High #WE High to SR.7 Going "0" Write Recovery before Read VPP Hold from Valid SRD (note 2, 4) #WP VIH Hold from Valid SRD (note 2, 4) Notes: SYM. tAVAV tPHWL tELWL tWLWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHR0 tWHGL tQVVL tQVSL MIN. 90 1 10 50 100 100 50 50 0 0 10 30 MAX. UNIT nS S nS nS nS nS nS nS nS nS nS nS 100 0 0 0 nS nS nS nS 1. Read timing characteristics during block erase, full chip erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, word write or lock-bit configuration. 4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word write or lock-bit configuration success (SR.1/3/4/5 = 0). - 34 - W28J161B/T 1 Address(A) VIH VIL 2 A IN t AVAV 3 A IN t AVWH 4 5 6 VIH #CE(E) VIL VIH #OE(G) VIL #WE(W) VIH VIL VIH VIL t WHAX tELWL tWHEH t WHGL t WHWL t WHQV1,2,3,4 DATA(D/Q) HIGH Z t PHWL t WLWH t DVWH t WHDX D IN D IN t WHR0 t Valid SRD D IN SR.7(R) ("1") ("0") t SHWH t QVSL #WP(S) VIH VIL VIH #RESET(P) VIL t VPWH t QVVL VPPH1/2 VPP (V) VPPLK VIL Figure 15. AC Waveform for #WE-Controlled Write Operations Notes: 1. VDD power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. - 35 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Alternative #CE - Controlled Writes(1) VDD = 2.7V to 3.6V, TA = -40 C to +85 C PARAMETER Write Cycle Time #RESET High Recovery to #CE Going Low (note 2) #WE Setup to #CE Going Low #CE Pulse Width #WP VIH Setup to #CE Going High (note 2) VPP Setup to #CE Going High (note 2) Address Setup to #CE Going High (note 3) Data Setup to #CE Going High (note 3) Data Hold from #CE High Address Hold from #CE High #WE Hold from #CE High #CE Pulse Width High #CE High to SR.7 Going "0" Write Recovery before Read VPP Hold from Valid SRD (note 2, 4) #WP VIH Hold from Valid SRD (note 2, 4) Notes: SYM. tAVAV tPHEL tWLEL tELEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHR0 tEHGL tQVVL tQVSL MIN. 90 1 0 65 100 100 50 50 0 0 0 25 MAX. UNIT nS S nS nS nS nS nS nS nS nS nS nS 100 0 0 0 nS nS nS nS 1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE times should be measured relative to the #CE waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, word write or lock-bit configuration. 4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word write or lock-bit configuration success (SR.1/3/4/5 = 0). - 36 - W28J161B/T 1 Address(A) VIH VIL 2 A IN t AVAV tEHEL tELEH tDVEH 3 A IN t AVEH 4 5 6 VIH #CE(E) VIL VIH #OE(G) VIL #WE(W) VIH VIL VIH VIL t WLEL t EHAX t EHGL t EHWH t EHDX D IN D IN t EHR0 t t EHQV1,2,3,4 Valid SRD DATA(D/Q) HIGH Z t PHEL D IN SR.7(R) ("1") ("0") #WP(S) VIH VIL VIH VIL t SHEH t QVSL #RESET(P) t VPEH t QVVL VPPH1/2 VPP (V) VPPLK VIL Figure 16. AC Waveform for #CE-Controlled Write Operations Notes: 1. VDD power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. - 37 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T Reset Operations High Z RY/#BY(R) ("1") ("0") V OL #RESET(P) V IH V IL t PLPH (A)Reset During Read Array Mode ("1") ("0") t PLR1 RY/#BY(R) (SR.7) #RESET(P) V IH V IL t PLPH (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration 2.7V VDD V IL V IH V IL (C)#RESET Rising Timing t 2VPH #RESET(P) Figure 17. AC Waveform for Reset Operation Reset AC Specifications PARAMETER #RESET Pulse Low Time (note 2) #RESET Low to Reset during Block Erase, Full Chip Erase, Word Write or Lock-Bit Configuration (note 1, 2) VDD 2.7V to #RESET High (note 2, 3) Notes: 1. If #RESET is asserted while a block erase, full chip erase, word write or lock-bit configuration operation is not executing, the reset will complete within 100ns. 2. A reset time, tPHQV, is required from the later of SR.7 going "1" or #RESET going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 3. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also has been in stable there. SYM. MIN. 100 MAX. UNIT nS tPLPH tPLR1 t2VPH 30 100 S nS - 38 - W28J161B/T Block Erase, Full Chip Erase, Word Write And Lock-Bit Configuration Performance(3) VDD = 2.7V to 3.6V, TA = -40 C to +85 C SYM. tWHQV1 tEHQV1 PARAMETER 32k word Block 4k word Block 32k word Block 4k word Block 32k word Block 4k word Block NOTE 2 2 2 2 2 2 2 2 2 4 4 5 VPP = 2.7V - 3.6V Min. Typ.(1) Max. 33 36 1.1 0.15 1.2 0.6 42 56 1 6 16 600 200 200 4 0.5 6 5 210 200 5 15 30 VPP = 11.7V - 12.3V Min. Typ.(1) Max. 20 27 0.66 0.12 0.9 0.5 32 42 0.69 6 16 600 15 30 UNIT S S S S S S S S S S S S Word Write Time Block Write Time (In word mode) tWHQV2 tEHQV2 Block Erase Time Full Chip Erase Time tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHR11 tEHR11 tWHR12 tEHR12 tERES Notes: Set Lock-Bit Time Clear Block Lock-Bits Time Word Write Suspend Latency Time to Read Block Erase Suspend Latency Time to Read Latency Time from Block Erase Resume Command to Block Erase Suspend Command 1. Typical values measured at TA = +25 C and VDD = 3.0V, VPP = 3.0V or 12.0V. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. A latency time is required from issuing suspend command(#WE or #CE going high) until SR.7 going "1". 5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than tERES and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation. - 39 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T 12. ADDITIONAL INFORMATION Recommended Operating Conditions At Device Power-Up AC timing illustrated in Figure 18 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VDD (p) #RESET Vpp *2 V (min) DD Vss VIH VIL tVR *1 t2VPH tR tPHQV (V) VPPH1/2 Vss VIH VIL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL tR or tF tAVQV tR or t F (A) ADDRESS Valid Address tF t ELQV tR #CE (E) #WE (W) tF t GLQV tR #OE (G) #WP (S) DATA (D/Q) HIGH Z Valid Output *1 t5VPH for the device in 5V operations. *2 To prevent the unwanted writes, system designers should consider the VPP switch, which connects VPP to VSS during read operations and VPPH1/2 during write or erase operations. Figure 18. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. - 40 - W28J161B/T Rise and Fall Time PARAMETER VDD Rise Time (note 1) Input Signal Rise Time (note 1, 2) Input Signal Fall Time (note 1, 2) Notes: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR(Max.) and tF(Max.) for #RESET are 50s/V SYMBOL MIN. 0.5 MAX. 30000 1 1 UNIT S/ V S/ V S/ V tVR tR tF Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure 19(b). The acceptable glitch noises are illustrated in Figure 19(a). Input Singal V IH (Min.) Input Singal V IH (Min.) VIL (Max.) Input Singal V IL (Max.) Input Singal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure 19. Waveform for Glitch Noises See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.). - 41 - Publication Release Date: April 7, 2003 Revision A4 W28J161B/T 13. ORDERING INFORMATION PART NO. W28J161BB90L W28J161TB90L Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ACCESS TIME (nS) 90 90 OPERATING TEMPERATURE (C) -40 C to 85 C -40 C to 85 C BOOT BLOCK Bottom Boot Top Boot PACKAGE 48-Ball TFBGA 48-Ball TFBGA 14. PACKAGE DIMENSION 48-Ball TFBGA (measurements in millimeters) 8765 4 3 21 CONTROL DIMENSIONS ARE IN MILLIMETER SYMBOL MILLIMETER INCH MIN. NOM. MAX. MIN. NOM. MAX. A A1 D D2 E E2 y b e 0.20 0.25 1.05 - - 0.042 0.30 0.008 0.010 0.012 8.20 0.312 0.320 0.328 0.210 7.80 8.00 5.25 BASIC 7.80 8.00 8.20 0.312 0.320 0.328 0.150 BASIC 0.004 BASIC 3.75 BASIC 0.10 BASIC 0.37 0.40 0.43 0.015 0.016 0.017 0.030 BASIC 0.75 BASIC - 42 - W28J161B/T 15. VERSION HISTORY VERSION A1 A2 A3 A4 DATE May 27, 2002 Aug. 5, 2002 Nov. 18, 2002 Apr. 7, 2003 PAGE All 15 40 All Initial Issued Update description and correct typo Specify the device ID for top and bottom boot parts Correct the typo in Figure 18 Update description and correct typo DESCRIPTION Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 43 - Publication Release Date: April 7, 2003 Revision A4 |
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