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W83195BR-25 Step-less Frequency Solano 815 Clock Gen. 3-DIMM, with S.S.T.
Date: 02/19/2003
Revision: 2.0
W83195BR-25 Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. All 02/Apr 02/19/2003 1.0 2.0 Dates Version Web Version n.a. 1.0 2.0 Main Contents All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Update new form
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
TABLE OF CONTENT
1. GENERAL DESCRIPTION ..................................................................................... 1 2. PRODUCT FEATURES .......................................................................................... 1 3. PIN CONFIGURATION........................................................................................... 2 4. PIN DESCRIPTION................................................................................................. 2
4.1 CRYSTAL I/O ........................................................................................................................................ 2 4.2 CPU, SDRAM, PCI, IOAPIC CLOCK OUTPUTS ................................................................................ 3 4.3 I2C CONTROL INTERFACE ................................................................................................................ 3 4.4 FIXED FREQUENCY OUTPUTS......................................................................................................... 4 4.5 POWER PINS........................................................................................................................................ 4
5. FREQUENCY SELECTION BY HARDWARE ........................................................ 5 6. SERIAL CONTROL REGISTERS........................................................................... 6
6.1 REGISTER 0: CPU FREQUENCY SELECT REGISTER................................................................... 8 6.2 REGISTER 1: CPU CLOCK REGISTER (1 = ACTIVE, 0 = INACTIVE) ............................................ 8 6.3 REGISTER 2: SDRAM CLOCK REGISTER (1 = ACTIVE, 0 = INACTIVE)....................................... 8 6.4 REGISTER 3: PCI CLOCK REGISTER (1 = ACTIVE, 0 = INACTIVE) .............................................. 9 6.5 REGISTER 4: ADDITIONAL REGISTER (1 = ACTIVE, 0 = INACTIVE)............................................ 9 6.6 REGISTER 5: SDRAM CLOCK REGISTER (1 = ACTIVE, 0 = INACTIVE)....................................... 9 6.7 REGISTER 6 WATCHDOG TIMER REGISTER ...............................................................................10 6.8 REGISTER 7: M/N PROGRAM REGISTER......................................................................................10 6.9 REGISTER 8: M/N PROGRAM REGISTER......................................................................................10 6.10 REGISTER 9: SPREAD SPECTRUM PROGRAMMING REGISTER ...........................................11 6.11 REGISTER 10: DIVISOR AND STEP-LESS ENABLE REGISTER ...............................................11 6.12 REGISTER 11: WINBOND CHIP ID REGISTER (READ ONLY)................................................12 6.13 REGISTER 12: WINBOND CHIP ID REGISTER (READ ONLY)................................................12
7. SPECIFICATIONS ................................................................................................ 13
7.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................13 7.2 ELECTRONICAL CHARACTERISTICS---INPUT/OUTPUT .............................................................13 7.3 ELECTRONICAL CHARACTERISTICS OF CPU CLOCK ...............................................................14 7.4 ELECTRONICAL CHARACTERISTICS OF 3V66 CLOCK ..............................................................14 7.5 ELECTRONICAL CHARACTERISTICS OF SDRAM CLOCK..........................................................15 7.6 ELECTRONICAL CHARACTERISTICS OF PCI CLOCK.................................................................15 7.7 ELECTRONICAL CHARACTERISTICS OF 48MHZ, REF CLOCK .................................................16
8. ORDERING INFORMATION ................................................................................ 17 9. HOW TO READ THE TOP MARKING.................................................................. 17 10. PACKAGE DRAWING AND DIMENSIONS ....................................................... 18
-IPublication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
1. GENERAL DESCRIPTION
The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83195BR-25 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. The W83195BR-25 provides step less frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also skew of CPU, SDRAM and 3V66 clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
* * * * * * * * * * * * * 2 CPU clocks (2.5V) 3 3V-66 clocks (3.3V) 12 SDRAM clocks for 3 DIMMs(3.3V) 8 PCI synchronous clocks. Optional single or mixed supply: (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz I2C 2-Wire serial interface and I2C read back 0.25% center and 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes (Mode as Tri-state or Normal) 48 MHz for USB 24 MHz for super I/O Packaged in 56-pin SSOP
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
3. PIN CONFIGURATION
VDDR Xin Xout VSS VSS 3V66-0 3V66-1 3V66-2 VDD3 VDDP PCICLK0/ FS0& PCICLK1/ *FS1 PCICLK2/SEL24_48* VSS PCICLK3^/Mode1* PCICLK4^ PCICLK5^ VDDP PCICLK6^ PCICLK7 VSS PD#/RESET$ *SDCLK *SDATA VDDS SDRAM 11 SDRAM 10 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/ FS4&^ VddA IOAPIC VDDC CPUCLK0 CPUCLK1 VSS VSS SDRAM 0 SDRAM 1 SDRAM 2 VDDS SDRAM 3 SDRAM 4 SDRAM 5 VSS SDRAM 6 SDRAM 7 SDRAM_F VDDS VSS 24_48MHz/ FS2& 48MHz/ *FS3 ^ VDD48 VDDS SDRAM 8 SDRAM 9 VSS
4. PIN DESCRIPTION
Buffer type symbol IN OUT I/O # & * Input Output Bi-directional Pin Active Low Internal 120K pull-down Internal 120k pull-up Description
4.1 Crystal I/O
PIN 2 3 Xin Xout Pin Name Type IN OUT Description Crystal input with internal loading capacitors (36pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (36pF).
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
PIN 52,51 22 Pin Name CPUCLK [0:1] PD# RESET$ IOAPIC Type OUT IN OUT OUT OUT Description Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. Mode1*=1, Power Down mode when driven low. Mode1*=0, RESET# open drain (4ms low active pulse when Watch Dog time out) Clock outputs synchronous with PCI clock and powered by VddA. SDRAM clock outputs.
54
38,48,47,46 SDRAM_F, SDRAM ,44,43,42, [0:11] 40,39,31,30 ,27, 26 11 PCICLK0 FS0&
OUT IN
12
PCICLK1 *FS1
OUT IN
13
PCICLK2 *SEL24_48
OUT IN
15
PCICLK3 Mode1*
OUT IN OUT OUT
16,17,19,20 PCICLK [4:7] 6,7,8 3V66 [0:2]
3.3V 33MHz PCI clock during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). Low skew (< 250ps) PCI clock outputs. Latched input for SEL24_48 at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. Low skew (< 250ps) PCI clock outputs. Latched input for Mode* pin at initial power up for the output PD# /RESET# output selection. Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset.
4.3 I2C Control Interface
PIN 24 23 Pin Name *SDATA *SDCLK Type I/O IN
2
Description Serial data of I C 2-wire control interface with internal pullup resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor.
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
4.4 Fixed Frequency Outputs
PIN 56 Pin Name REF0 FS4& Type OUT IN Description 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 24MHz or 48MHz output clock. Default is 24MHz. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 48MHz output clock. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1).
35
24_48MHz FS2&
OUT IN
34
48MHz FS3*
OUT IN
4.5 Power Pins
PIN 53,55 33 9 10,18 1 45,37,32,25 4,5,14,21,28,29,36, 41, 49.50 Pin Name VddC,VddA Vdd48 Vdd3 VddP VddR VddS Vss Description Power supply for CPU & IOAPIC, 2.5V or 3.3V. Power supply for 48MHz output,3.3V. Power supply for 3V_66 output, 3.3V. Power supply for PCICLK, 3.3V. Power supply for REF0, 3.3V. Power supply for SDRAM_F, SDRAM [0:11], nominal 3.3V. Circuit Ground.
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
5. FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU (MHz) SDRAM (MHz) 3V66(MHz) PCI (MHz) IOAPIC (MHz) 55.00 82.50 55.00 27.50 13.75 60.00 90.00 60.00 30.00 15.00 66.80 100.20 66.80 33.40 16.70 68.33 102.50 68.33 34.17 17.08 70.00 105.00 70.00 35.00 17.50 72.00 108.00 72.00 36.00 18.00 75.00 112.50 75.00 37.50 18.75 77.00 115.50 77.00 38.50 19.25 83.30 83.30 55.53 27.77 13.88 90.00 90.00 60.00 30.00 15.00 100.30 100.30 66.87 33.43 16.72 103.00 103.00 68.67 34.33 17.17 112.50 112.50 75.00 37.50 18.75 115.00 115.00 76.67 38.33 19.17 120.00 120.00 80.00 40.00 20.00 125.00 125.00 83.33 41.67 20.83 128.00 128.00 64.00 32.00 16.00 130.00 130.00 65.00 32.50 16.25 133.70 133.70 66.85 33.43 16.71 137.00 137.00 68.50 34.25 17.13 140.00 140.00 70.00 35.00 17.50 145.00 145.00 72.50 36.25 18.13 150.00 150.00 75.00 37.50 18.75 153.33 153.33 76.67 38.33 19.17 125.00 93.75 62.50 31.25 15.63 130.00 97.50 65.00 32.50 16.25 133.70 100.28 66.85 33.43 16.71 137.00 102.75 68.50 34.25 17.13 140.00 105.00 70.00 35.00 17.50 145.00 108.75 72.50 36.25 18.13 150.00 112.50 75.00 37.50 18.75 153.33 115.00 76.67 38.33 19.17
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6. SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2...) will be valid and acknowledged. Frequency Table Setting by I2C (SEL5 ~ SEL0) SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU SDRAM 3V66 PCI (MHz) IOAPIC (MHz) (MHz) (MHz) (MHz) 0 0 0 0 0 0 55.00 82.50 55.00 27.50 13.75 0 0 0 0 0 1 60.00 90.00 60.00 30.00 15.00 0 0 0 0 1 0 66.80 100.20 66.80 33.40 16.70 0 0 0 0 1 1 68.33 102.50 68.33 34.17 17.08 0 0 0 1 0 0 70.00 105.00 70.00 35.00 17.50 0 0 0 1 0 1 72.00 108.00 72.00 36.00 18.00 0 0 0 1 1 0 75.00 112.50 75.00 37.50 18.75 0 0 0 1 1 1 77.00 115.50 77.00 38.50 19.25 0 0 1 0 0 0 83.30 83.30 55.53 27.77 13.88 0 0 1 0 0 1 90.00 90.00 60.00 30.00 15.00 0 0 1 0 1 0 100.30 100.30 66.87 33.43 16.72 0 0 1 0 1 1 103.00 103.00 68.67 34.33 17.17 0 0 1 1 0 0 112.50 112.50 75.00 37.50 18.75 0 0 1 1 0 1 115.00 115.00 76.67 38.33 19.17 0 0 1 1 1 0 120.00 120.00 80.00 40.00 20.00 0 0 1 1 1 1 125.00 125.00 83.33 41.67 20.83 0 1 0 0 0 0 128.00 128.00 64.00 32.00 16.00 0 1 0 0 0 1 130.00 130.00 65.00 32.50 16.25 0 1 0 0 1 0 133.70 133.70 66.85 33.43 16.71 0 1 0 0 1 1 137.00 137.00 68.50 34.25 17.13 0 1 0 1 0 0 140.00 140.00 70.00 35.00 17.50 0 1 0 1 0 1 145.00 145.00 72.50 36.25 18.13 0 1 0 1 1 0 150.00 150.00 75.00 37.50 18.75 0 1 0 1 1 1 153.33 153.33 76.67 38.33 19.17 0 1 1 0 0 0 125.00 93.75 62.50 31.25 15.63 0 1 1 0 0 1 130.00 97.50 65.00 32.50 16.25 0 1 1 0 1 0 133.70 100.28 66.85 33.43 16.71 0 1 1 0 1 1 137.00 102.75 68.50 34.25 17.13 0 1 1 1 0 0 140.00 105.00 70.00 35.00 17.50 0 1 1 1 0 1 145.00 108.75 72.50 36.25 18.13 0 1 1 1 1 0 150.00 112.50 75.00 37.50 18.75 0 1 1 1 1 1 153.33 115.00 76.67 38.33 19.17
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
CPU (MHz) 66.8 135.00 142.00 143.00 144.00 146.00 147.00 148.00 100.20 156.00 158.00 160.00 135.00 139.00 141.00 142.00 143.00 144.00 146.00 147.00 148.00 149.00 153.00 157.00 159.00 162.00 164.00 170.00 175.00 180.00 190.00 200.40
SDRAM (MHz) 133.00 135.00 142.00 143.00 144.00 146.00 147.00 148.00 133.00 156.00 158.00 160.00 101.25 104.25 105.75 106.50 107.25 108.00 109.50 110.25 111.00 111.75 114.75 117.75 119.25 121.50 123.00 127.50 116.67 120.00 190.00 133.60
3V66 (MHz) 66.80 67.50 71.00 71.50 72.00 73.00 73.50 74.00 66.80 78.00 79.00 80.00 67.50 69.50 70.50 71.00 71.50 72.00 73.00 73.50 74.00 74.50 76.50 78.50 79.50 81.00 82.00 85.00 58.30 60.00 63.33 66.80
PCI (MHz) 33.40 33.75 35.50 35.75 36.00 36.50 36.75 37.00 33.40 39.00 39.50 40.00 33.75 34.75 35.25 35.50 35.75 36.00 36.50 36.75 37.00 37.25 38.25 39.25 39.75 40.50 41.00 42.50 29.15 30.00 31.67 33.40
IOAPIC (MHz) 16.70 16.88 17.75 17.88 18.00 18.25 18.38 18.50 16.70 19.50 19.75 20.00 16.88 17.38 17.63 17.75 17.88 18.00 18.25 18.38 18.50 18.63 19.13 19.63 19.88 20.25 20.50 21.25 14.58 15.00 15.83 16.70
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6.1 Register 0: CPU Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL3 (Frequency table selection by software via I2C) SSEL2 (Frequency table selection by software via I2C) SSEL1 (Frequency table selection by software via I2C) SSEL0 (Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit (2, 7:4) SSEL4 (Frequency table selection by software via I2C) SSEL5 (Frequency table selection by software via I2C) 0 = Running 1 = Tristate all outputs
6.2 Register 1: CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X X X X X 0 0 1 Pin FS0# FS1# FS2# FS3# FS4# 1 = 0.25% Center type Spread Spectrum Modulation 0 = 0.5% Center type Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled 1 = Center type Spread Spectrum Modulation 0 = Down type Spread Spectrum Modulation Description
6.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 39 40 42 43 44 46 47 48 Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive)
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 20 19 17 16 15 13 12 11 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description
6.5 Register 4: Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 8 7 6 26 27 30 31 38 3V66_2(Active / Inactive) 3V66_1(Active / Inactive) 3V66_0(Active / Inactive) SDRAM11 (Active / Inactive) SDRAM10 (Active / Inactive) SDRAM9 (Active / Inactive) SDRAM8 (Active / Inactive) SDRAM_F (Active / Inactive) Description
6.6 Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin 51 52 Description CSkew2 (CPU to SDRAM skew program bit) CSkew1 (CPU to SDRAM skew program bit) CSkew0 (CPU to SDRAM skew program bit) CASkew2 (CPU to 3V66 skew program bit) CASkew1 (CPU to 3V66 skew program bit) CASkew0 (CPU to 3V66 skew program bit) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive)
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6.7 Register 6 Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Enable Count Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0 Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY)
6.8 Register 7: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 0 0 0 0 0 Pin N value bit 8 Test 1(Please do not modify) Test 0 (Please do not modify) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 Description
6.9 Register 8: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 Description
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6.10 Register 9: Spread Spectrum Programming Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 Description
6.11 Register 10: Divisor and Step-less Enable Register
Bit 7 @PowerUp 0 Pin Description 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/M Ratio SEL3 Ratio SEL2 Ratio SEL1 Ratio SEL0 Reserved Reserved Reserved Ratio Bit 3 DS0 0 1 0 1 0 1 0 1 x x CPU 4 3 2 2 6 3 6 4 2 2 SDRAM 4 3 3 2 4 4 3 3 2 4 3V66 6 6 6 6 6 6 6 6 4 6
6 5 4 3 2 1 0
X X X X 0 0 0
-
Bit6 DS3 0 0 0 0 0 0 0 0 1 1
Register10 Bit3-6 Bit 5 Bit 4 DS2 DS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 x 1 x
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
6.12 Register 11: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 0 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID
(Read Only)
Description
6.13 Register 12: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 1 0 0 1 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID
(Read Only)
Description
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
7. SPECIFICATIONS 7.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65C to + 150C - 55C to + 125C 0C to + 70C
7.2 Electronical Characteristics---Input/Output
Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0C to +70C Parameter Input Low Voltage Input High Voltage Input Low Current Input Low Current Input High Current Input Capacitance Symbol VIL VIH IIL IIL IIH CIN COUT CINX Operating Supply Current Power Down Supply Current Settling Time Delay Idd3 Idd2 Ts tPZH,tPZH tPLZ,tPZH 1 1 27 Min Vss-0.3 2.0 -5 -200 -5 5 5 6 45 100 600 3 mS 10 10 nS nS Typ Max 0.8 Vdd+0.3 Units Vdc Vdc A A A pF pF pF MA A From first crossing to 1% target freq. Output enable delay Output enable delay Logic inputs Output capacitance Xin and Xout CPU = 66.6 MHz PCI = 33.3 Mhz with load No pull-up resistors Pull-up resistros Test Conditions
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
7.3 Electronical Characteristics of CPU Clock
Vdd=2.5V +/- 5%; CL=10-20pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Pull-Up Current Min Pull-Up Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH IOH(min) IOH(max) TRF(min) TRF(max) Dt TSK Tsc-c 45 0.4 1.6 55 175 250 2.0 27 -27 -27 -27 30 -27 Min 13.5 13.5 Typ Max 40 40 0.4 Units Ohm Ohm V V MA MA MA MA ns ns % ps ps Vout = 1.0 V Vout = 2.0V 10pF Load 20pF Load VT=1.25V VT=1.25V VT=1.25V IOL=1mA IOH=-1mA Test Conditions
7.4 Electronical Characteristics of 3V66 Clock
Vdd=3.3V +/- 5%; CL=10-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) Dt TSK Tsc-c 45 2.4 30 -33 0.4 1.6 55 175 500 38 -33 Min 15 15 Typ Max 55 55 0.55 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V IOL=1mA IOH=-1mA Test Conditions
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
7.5 Electronical Characteristics of SDRAM Clock
Vdd=3.3V +/- 5%; CL=20-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) Dt TSK Tsc-c 45 2.4 54 -54 0.4 1.6 55 250 250 54 -45 Min 13.5 13.5 Typ Max 40 40 0.45 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V IOL=1mA IOH=-1mA Test Conditions
7.6 Electronical Characteristics of PCI Clock
Vdd=3.3V +/- 5%; CL=10-30pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TRF(min) TRF(max) Dt TSK Tsc-c 45 2.4 30 -33 0.5 2.0 55 500 500 38 -33 Min 15 15 Typ Max 55 55 0.55 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V IOL=1mA IOH=-1mA Test Conditions
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
7.7 Electronical Characteristics of 48MHz, REF Clock
Vdd=3.3V +/- 5%; CL=10-20pF Parameter Ouput Impedance Ouput Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current RiseTime Fall Time Duty Cycle Skew Jitter Symbol RDSP RDSN VOL VOH IOL IOH TR TF Dt TSK Tsc-c 45 2.4 29 -29 1.8 1.7 27 -23 4 4 55 500 1000 Min 20 20 Typ Max 55 55 0.4 Units Ohm Ohm V V MA MA ns ns % ps ps 10pF Load 20pF Load VT=1.5V VT=1.5V VT=1.5V IOL=1mA IOH=-1mA Test Conditions
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
8. ORDERING INFORMATION
Part Number W83195BR-25 Package Type 56 PIN SSOP Production Flow Commercial, 0C to +70C
9. HOW TO READ THE TOP MARKING
W83195BR-25 28051234 814GAB
1st line: Winbond logo and the type number: W83195BR-25 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G A B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: February 2003 Revision 2.0
W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
10. PACKAGE DRAWING AND DIMENSIONS
.035 .045
.045 .055 0.40/0.50 DIA
SYMBOL
DIMENSION IN MM
DIMENSION IN INCH
EHE
END VIEW
A A1 A2 b c D HE E e L L1 Y
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
A2
A
Y SEATING e
SIDE VIEW
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
A1
b
PARTING LINE
c
DETAIL"A"
0
0
L L1
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use.
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Publication Release Date: February 2003 Revision 2.0

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