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Low Noise/Low Power
X9418
Dual 2-Wire EEPOTTM Nonvolatile Digital Potentiometer
FEATURES * * * * Two EEPOTs in One Package Two-Wire Serial Interface Hardware Write Protection, WP Register Oriented Format --Direct Read/Write Wiper Position --Store as Many as Four Positions per Pot Power Supplies --VCC = 2.7V to 5.5V --V+ = 2.7V to 5.5V --V- = -2.7V to -5.5V Low Power CMOS --Standby Current < 1mA --Ideal for Battery Operated Applications High Reliability --Endurance - 100,000 Data Changes per Register --Register Data Retention - 100 years 8 Bytes of E2PROM memory 10K Ohm Resistor Array Resolution: 64 Taps each Pot 24-Pin Plastic DIP, 24-Lead TSSOP and 24-Lead SOIC Packages DESCRIPTION The X9418 integrates two nonvolatile EEPOTs, digitally controlled potentiometers, on a monolithic CMOS microcircuit. The X9418 contains two resistor arrays, each composed of 63 resistive elements. Between each element and at either end are tap points accessible to the wiper elements. The position of the wiper element on the array is controlled by the user through the two wire serial bus interface. Each resistor array has associated with it a Wiper Counter Register and four 6 bit data registers that can be directly written and read by the user. The contents of the Wiper Counter Register set the position of the wiper on the resistor array. Power-up recalls the contents of data register R0 to the Wiper Counter Register.
*
*
*
* * * *
FUNCTIONAL DIAGRAM
R0 R1
WP
WIPER COUNTER REGISTER (WCR) R2 R3
VH0
VL0 VW0
SCL SDA
A0 A1 A2 A3
INTERFACE AND CONTROL CIRCUITRY
8 DATA
R0 R1
WIPER COUNTER RESISTOR ARRAY REGISTER POT1 (WCR) R2 R3
VW1
VH1
VL1
7028 FM1
7060-1.1 2/24/99 T1/C0/D0
1
Characteristics subject to change without notice
X9418
PIN DESCRIPTIONS PIN CONFIGURATION
DIP/SOIC VCC VL0 VH0 VW0 A2 WP SDA A1 VL1 VH1 VW1 V SS 1 2 3 4 5 6 7 8 9 10 11 12 X9418 24 23 22 21 20 19 18 17 16 15 14 13 V+ NC NC NC A0 NC A3 SCL NC NC NC VSDA A1 VL1 VH1 VW1 VSS NC NC NC VSCL A3 1 2 3 4 5 6 7 8 9 10 11 12 X9418 24 23 22 21 20 19 18 17 16 15 14 13 WP A2 VW0 VH0 VL0 VCC NC NC NC V+ A0 NC
Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9418.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0-A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9418. A maximum of 16 devices may occupy the 2-wire serial bus.
7028 FM2
PIN NAMES Symbol
SCL SDA A0-A3 VH0-VH1, VL0-VL1 VW0-VW1 WP V+,VVCC VSS NC
Description
Serial Clock Serial Data Device Address Potentiometers (terminal equivalent) Potentiometers (wiper equivalent) Hardware Write Protection Analog Supplies System Supply Voltage System Ground No Connection
7028 FRM T01
Potentiometer Pins VH (VH0 - VH1), VL (VL0 - VL1) The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
VW (VW0 - VW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Wiper Counter Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the EEPOT analog section.
2
X9418
PRINCIPLES OF OPERATION The X9418 is a highly integrated microcircuit incorporating two resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the EEPOT potentiometers. Serial Interface The X9418 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9418 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9418 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9418 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.
The X9418 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9418 will respond with a final acknowledge. Array Description The X9418 is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH and VL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9418 this is fixed as 0101[B]. Figure 1. Slave Address
DEVICE TYPE IDENTIFIER
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
7028 FM3
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9418 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9418 to respond with an acknowledge. The A0-A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
3
X9418
Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms E2PROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9418 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9418 is still busy with the write operation no ACK will be returned. If the X9418 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence
7028 FM5
the two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format
REGISTER SELECT
I3
I2
I1
I0
R1
R0
0
P0
INSTRUCTIONS
WIPER COUNTER REGISTER SELECT
NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING
ISSUE START
The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P0) select which one of the two potentiometers is to be affected by the instruction. Bit 1 is defined to be 0. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a data register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9418; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected data register). The sequence of operations is shown in Figure 4.
ISSUE SLAVE ADDRESS
ISSUE STOP
ACK RETURNED? YES
NO
FURTHER OPERATION? YES ISSUE INSTRUCTION
NO
ISSUE STOP
PROCEED
PROCEED
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Instruction Structure The next byte sent to the X9418 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of
4
X9418
Figure 3. Two-Byte Command Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 0 P0 A C K S T O P
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The Increment/Decrement command is different from the other commands. Once the command is issued and the X9418 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA Table 1. Instruction Set
Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register
Notes: (7)
is HIGH, the selected wiper will move one resistor segment towards the VH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.
I3 1 1 1 1 1
I2 0 0 0 1 1
I1 0 1 1 0 0
Instruction Set I0 R1 R0 1 0 1 0 1 0 0 1/0 1/0 1/0 0 0 1/0 1/0 1/0
P1 0 0 0 0 0
P0 1/0 1/0 1/0 1/0 1/0
Operation Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and R1-R0 Write new value to the Data Register pointed to by P0 and R1-R0 Transfer the contents of the Data Register pointed to by P0 and R1-R0 to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by R1-R0 Transfer the contents of both Data Registers pointed to by R1-R0 to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by R1-R0 Enable Increment/decrement of the Control Latch pointed to by P0
7028 FM T02
1
1
1
0
1/0
1/0
0
1/0
0
0
0
1
1/0
1/0
0
0
1
0
0
0
1/0
1/0
0
0
0
0
1
0
0
0
0
1/0
1/0 = data is one or zero
5
X9418
Figure 4. Three-Byte Command Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 0 P0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P
7028 FM7
Figure 5. Increment/Decrement Command Squence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0
X
X 0 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
R1 R0
7028 FM8
Figure 6. Increment/Decrement Timing Limits
INC/DEC CMD ISSUED SCL
t WRID
SDA
VW
VOLTAGE OUT
7028 FM9
6
X9418
Figure 7. Acknowledge Response from Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
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Figure 8. Detailed Potentiometer Block Diagram
SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 8 REGISTER 1 6
SERIAL BUS INPUT C O U N T E R D E C O D E
VH
PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR)
REGISTER 2
REGISTER 3
IF WCR = 00[H] THEN VW = VL IF WCR = 3F[H] THEN VW = VH
INC/DEC LOGIC UP/DN MODIFIED SCL UP/DN CLK VL
VW
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7
X9418
DETAILED OPERATION Both EEPOT potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four data registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9418 contains two Wiper Counter Registers, one for each EEPOT potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9418 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile data registers. These can be read or written directly by the host and data can be transferred between any of the four data registers and the control latch. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-bit), non-volatile:
D5 NV (MSB) D4 NV D3 NV D2 NV D1 NV D0 NV (LSB)
Four 6-bit Data Registers for each EEPOT. (eight 6-bit registers in total). * {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. Wiper Counter Register, (6-bit), volatile:
WP5 V (MSB) WP4 V WP3 V WP2 V WP1 V WP0 V (LSB)
One 6-bit Wiper Counter Register for each EEPOT. (Four 6-bit registers in total.) * {D5~D0}: These bits specify the wiper position of the respective EEPOT. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR.
8
X9418
Instruction Format
Notes: (1) (2) (3) (4) (5) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C P K10010000 wiper position S (sent by slave on SDA) A WWWWWW C 00PPPPPP K 543210 M A C K S T O P
7028 FM T03
Write Wiper Counter Register
device S device type T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C P K10100000 wiper position S (sent by master on SDA) A WWWWWW C K00PPPPPP 543210 S A C K S T O P
7028 FM T04
Read Data Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C RR P K10111000 wiper position S (sent by slave on SDA) A WWWWWW C 00PPPPPP K 543210 M A C K S T O P
7028 FM T05
Write Data Register
S device type device instruction wiper S T identifier addresses opcode addresses A A C RR P R0101AAAA 1100 0 3210K 10 0 T wiper position S (sent by master on SDA) A WWWWWW C 00PPPPPP K 543210 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P
7028 FM T06
XFR Data Register to Wiper Counter Register
device instruction wiper S device type S T identifier addresses opcode addresses A A C RR P R0101AAAA 1101 0 3210K 10 0 T S A C K S T O P
7028 FM T07
9
X9418
XFR Wiper Counter Register to Data Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C RR P K11101000 S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
7028 FM T08
Increment/Decrement Wiper Counter Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C P K00100000 increment/decrement S (sent by master on SDA) A C I/ I/ I/ I/ KDD. . . .DD S T O P
7028 FM T09
Global XFR Data Register to Wiper Counter Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C RR K00011000 S A C K S T O P
7028 FM T10
Global XFR Wiper Counter Register to Data Register
S device type device T identifier addresses A R0101AAAA 3210 T instruction wiper S opcode addresses A C RR 1000 00 K 10 S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
7028 FM T11
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS 120 RESISTANCE (K) Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
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WAVEFORM
100 80 60 40 20 0 0
VCC MAX RMIN = =1.8KW IOL MIN tR RMAX = CBUS MAX. RESISTANCE
MIN. RESISTANCE
20
40
60
80 100 120
BUS CAPACITANCE (pF)
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10
X9418
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias.......................... -65C to +135C Storage Temperature............................... -65C to +150C Voltage on SDA, SCL or any Address Input with Respect to VSS .....................................-1V to +7V Voltage on V+ (referenced to VSS) ............................... 10V Voltage on V- (referenced to VSS) ............................... -10V (V+) - (V-) ..................................................................... 12V Any VH ............................................................................ V+ Any VL ...............................................................................VLead Temperature (Soldering, 10 seconds)..............300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
Min.
0C -40C
Max.
+70C +85C
7028 FMT12
Device
X9418 X9418-2.7
Supply Voltage (VCC) Limits
5V 10% 2.7V to 5.5V
7028 FMT13
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
RTOTAL IW RW V+ VVTERM Power Rating Wiper Current Wiper Resistance Voltage on V+ Pin Voltage on V- Pin X9418 X9418-2.7 X9418 X9418-2.7 +4.5 +2.7 -5.5 -5.5 V-140
(4) (1)
Parameter
End to End Resistance
Min.
-20 -3
Typ.
Max.
+20 50 +3
Units
% mW mA W V V V dBV %
Test Conditions
25C, each pot Wiper Current = 1mA
150
250 +5.5 +5.5 -4.5 -2.7 V+
Voltage on any VH or VL Pin Noise Resolution Absolute Linearity
Ref: 1kHz Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI]
7028 FMT14
1.6 -1 -0.2 300 +1 +0.2
MI(3) MI(3) ppm/C
Relative Temperature Coefficient of Resistance
Linearity (2)
11
X9418
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL
Parameter
VCC Supply Current (Nonvolatile Write) VCC Supply Current (Move Wiper, Write, Read) VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Min.
Typ.
Max.
1 100 1 10 10
Units
mA mA mA mA mA V V V
Test Conditions
fSCL = 400KHz, SDA = Open, Other Inputs = VSS fSCL = 400KHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC
VCC x 0.7 -0.5
VCC x 0.5 VCC x 0.1 0.4
IOL = 3mA
7028 FMT15
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH - VL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION Parameter
Minimum Endurance Data Retention
Min.
100,000 100
Units
Data Changes per Register Years
7028 FMT16
CAPACITANCE Symbol
CI/O CIN
(5) (5)
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, and SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
7028 FMT17
POWER-UP TIMING Symbol
tPUR(6) tPUW
(6)
Parameter
Power-up to Initiation of Read Operation Power-up to Initiation of Write Operation
Max.
1 5
Units
ms ms
7028 FMT18
A.C. TEST CONDITIONS Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
7028 FMT19
EQUIVALENT A.C. LOAD CIRCUIT
5V 1533W SDA OUTPUT 100pF 100pF 2.7V
Notes: (5) This parameter is periodically sampled and not 100% tested (6) tPUR and tPUW are the delays required from the time the third (last) power supply (Vcc, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (7) The bias order of power supply (Vcc, V+ and V-) don't care. 12
7028 FM14
X9418
AC TIMING (over recommended operating conditions)
Symbol fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) WP, A0, A1, A2 and A3 Setup Time WP, A0, A1, A2 and A3 Hold Time 100 50 50 1300 0 0 2500 600 1300 600 600 600 100 30 300 300 900 Parameter Min. Max. 400 Units kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol tWR Parameter High-voltage Write Cycle Time (Store Instructions) Typ. 5 Max. 10 Units ms
7028 FMT21
EEPOT TIMING
Symbol tWRPO tWRL tWRID Parameter Wiper Response Time After The Third (Last) Power Supply Is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction) Min. Max. 10 10 10 Units ms ms ms
7028 FMT22
Notes: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
13
X9418
TIMING DIAGRAMS FIGURE 1. START and STOP Timing
g
(START) tR SCL tSU:STA SDA tHD:STA tR tF tSU:STO tF
(STOP)
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FIGURE 2. Input Timing tCYC SCL tLOW SDA tSU:DAT FIGURE 3. Output Timing SCL tHD:DAT tBUF
7028 FM16
tHIGH
SDA tAA FIGURE 4. EEPOT Timing (for All Load Instructions) (STOP) SCL tDH
7028 FM17
SDA
LSB tWRL
VWx
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14
X9418
FIGURE 5. EEPOT Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec tWRID
VWx
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FIGURE 6. Write Protect and Device Address Pins Timing (START) SCL ... (Any Instruction) ... ... tSU:WPA WP A0, A1 A2, A3
7028 FM20
(STOP)
SDA
tHD:WPA
15
X9418
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.265 (32.13) 1.230 (31.24)
0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 1.100 (27.94) REF. 0.080 (2.03) 0.065 (1.65)
SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.162 (4.11) 0.140 (3.56)
0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.065 (1.65) 0.040 (1.02)
0.022 (0.56) 0.014 (0.36)
0.625 (15.87) 0.600 (15.24)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
16
X9418
24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.290 (7.37) 0.299 (7.60) PIN 1 INDEX
0.393 (10.00) 0.420 (10.65)
PIN 1
0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49)
(4X) 7
0.092 (2.35) 0.105 (2.65)
0.050 (1.27)
0.003 (0.10) 0.012 (0.30)
0.050" TYPICAL
0.010 (0.25) X 45 0.020 (0.50)
0 - 8 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27)
0.050" TYPICAL 0.420"
FOOTPRINT
0.030" TYPICAL 24 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X9418
24-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.303 (7.70) .311 (7.90)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0 - 8 .020 (.50) .030 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
18
X9418
ORDERING INFORMATION X9418 Device Y P T V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package P24 = 24-Lead Plastic DIP S24 = 24-Lead SOIC V24 = 24-Lead TSSOP Potentiometer Organization Pot 0 Pot 1 W = 10KW 10KW
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 19

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