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X9428
XDCPTM Digitally Controlled Potentiometer
FEATURES * Two-Wire Serial Interface * Hardware Write Protection, WP * Register Oriented Format --Directly Read/Write Wiper Position --Store as Many as Four Positions * Power Supplies --VCC = 2.7V to 5.5V --V+ = 2.7V to 5.5V --V- = -2.7V to -5.5V * Direct Write Cell --Endurance - 100,000 Data Changes per Register --Register Data Retention - 100 years * 16 Bytes of E2PROM memory * 3 Resistor Array Values --2K Ohms to 50K Ohms Mask Programmable * Resolution: 64 Taps each Pot * 24-Pin Plastic DIP, 24-Lead TSSOP and 24-Lead SOIC Packages * Low Power CMOS --Standby Current < 1A DESCRIPTION The X9428 nonvolatile XDCP, digitally controlled potentiometer contains a resistor array, composed of 63 resistive elements. Between each element and at either end are tap points accessible to the wiper elements. The position of the wiper element on the array is controlled by the user through the two wire serial bus interface. The resistor array has associated with it a nonvolatile control latch and four 6 bit data registers that can be directly written and read by the user. The contents of the control latch controls the position of the resistor array/wiper.
FUNCTIONAL DIAGRAM
R0 R1
R2
SCL SDA
WIPER COUNTER REGISTER (WCR) R3
VH
VL VW
A0 A1 A2 A3
INTERFACE AND CONTROL CIRCUITRY
8 DATA
(c)Xicor, Inc. 1994, 1995, 1996 Patents Pending 70290-1.1 9/23/99 EP
1
Characteristics subject to change without notice
X9428
PIN DESCRIPTIONS Analog Supply V+, VThe Analog Supply V+, V- are the supply voltages for the XDCP analog section. PIN CONFIGURATION
DIP/SOIC VCC A2 VL VH VW SDA WP V SS 1 2 3 4 5 6 7 8 X9428 16 15 14 13 12 11 10 9 V+ NC A0 NC A1 SCL NC V-
Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9428.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0-A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9428. A maximum of 16 devices may occupy the 2-wire serial bus.
PIN NAMES Symbol
SCL SDA A0-A2 VH, VL VW WP V+,VVCC Vss NC
Description
Serial Clock Serial Data Device Address Potentiometers (terminal equivalent) Potentiometers (Wiper equivalent) Hardware Write Protection Analog and Voltage Follower Supplys System Supply Voltage System Ground No Connection
Potentiometer Pins VH (VH0 - VH1), VL (VL0 - VL1) The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
VW (VW0 - VW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer and the non-inverting input of the voltage follower. Hardware Write Protect Input WP The WP pin when low prevents nonvolatile writes to the wiper and voltage follower control latchs.
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X9428
PRINCIPLES OF OPERATION The X9428 is a highly integrated microcircuit incorporating a resistor array and associated registers and counters and the serial interface logic providing direct communication between the host and XDCP. Serial Interface The X9428 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9428 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9428 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9428 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9428 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9428 will respond with a final acknowledge. Array Description The X9428 is comprised a resistor array containing 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH and VL inputs). At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW) output. Within the array only one switch may be turned on at a time. These switches are controlled by a nonvolatile control latch (NCL). The six bits of the NCL are decoded to select, and enable, one of sixtyfour switches. The NCL may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the NCL. These data registers and the NCL can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9428 this is fixed as 0101[B]. Figure 1. Slave Address
DEVICE TYPE IDENTIFIER
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A2 inputs. The X9428 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9428 to respond with an acknowledge. The A0-A2 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
3
X9428
Acknowledge Polling The disabling of the inputs, during the internal non-volatile write operation, can be used to take advantage of the typical 5ms E2PROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9428 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9428 is still busy with the write operation no ACK will be returned. If the X9428 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits are reserved and not used. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Control Latch and one of the data registers. A transfer from a data register to a Control Latch is essentially a write to a static RAM. The response of the wiper to this action will be delayed tSTPWV. A transfer from Control Latch current wiper position, to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and its associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9428; either between the host and one of the data registers or directly between the host and the Control Latch. These instructions are: Read Control Latch, read the current wiper position of the pot Write Control Latch, change current wiper position of the pot Read Data Register, read the contents of the selected nonvolatile register; Write Data Register, write a new value to the selected data register. The sequence of operations is shown in Figure 4. Instruction Structure The next byte sent to the X9428 contains the instruction and register pointer information as shown in Figure 2. Figure 2. Instruction Byte Format
REGISTER SELECT
I3
I2
I1
I0
R1
R0
X
X
INSTR UCTIONS
RESERVED
NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING
ISSUE START
ISSUE SLA VE ADDRESS
ISSUE ST OP
ACK RETURNED? YES
NO
FURTHER OPERA TION? YES ISSUE INSTR UCTION
NO
ISSUE ST OP
PROCEED
PROCEED
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X9428
Figure 3. Two-Byte Command Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 X X A C K S T O P
The Increment/Decrement command is different from the other commands. Once the command is issued and the X9428 has responded with an acknowledge, the master can clock the wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) Table 1. Instruction Set
I3
1 1 1 1 1
while SDA is HIGH, the wiper will move one resistor segment towards the VH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the wiper will move one resistor segment towards the VL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.
Instruction
Read Control Latch Write Control Latch Read Data Register Write Data Register XFR Data Register to Control Latch XFR Control Latch to Data Register Global XFR Data Register to Control Latch Global XFR Control Latch to Data Register Increment/Decrement Wiper
Notes: (7) (8)
I2
0 0 0 1 1
Instruction Set I1 I0 R1 R0
0 1 1 0 0 1 0 1 0 1 N/A N/A 1/0 1/0 1/0 N/A N/A 1/0 1/0 1/0
X
N/A N/A N/A N/A N/A
X
N/A N/A N/A N/A N/A
Operation
Read the contents of the Control Latch pointed to by P1-P0 Write new value to the Control Latch pointed to by P1-P0 Read the contents of the Register pointed to by P1-P0 and R1-R0 Write new value to the Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Register pointed to by P1-P0 and R1-R0 to its associated Control Latch Transfer the contents of the Control Latch pointed to by P1-P0 to the Register pointed to by R1-R0 Transfer the contents of all four Data Registers pointed to by R1-R0 to their respective Control Latch Transfer the contents of all Control Latchs to their respective data Registers pointed to by R1-R0 Enable Increment/decrement of the Control Latch pointed to by P1-P0
1
1
1
0
1/0
1/0
N/A
N/A
0 1 0
0 0 0
0 0 1
1 0 0
1/0 1/0 N/A
1/0 1/0 N/A
N/A N/A N/A
N/A N/A N/A
1/0 = data is one or zero N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)
5
X9428
Figure 4. Three-Byte Command Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 X X A C K CM D W D5 D4 D3 D2 D1 D0 A C K S T O P
Figure 5. Increment/Decrement Command Squence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0
X
X X A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
R1 R0 X
Figure 6. Increment/Decrement Timing Limits
INC/DEC CMD ISSUED SCL
t CLWV
SDA
VW
VOLTAGE OUT
6
X9428
Figure 7. Acknowledge Response from Receiver
SCL FR OM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 8. Detailed Potentiometer Block Diagram
SERIAL DATA PATH FR OM INTERFACE CIRCUITR Y REGISTER 0 8 REGISTER 1 6
SERIAL BUS INPUT C O U N T E R D E C O D E
VH
PARALLEL BUS INPUT WIPER COUNTER REGISTER
REGISTER 2
REGISTER 3
IF WCR = 00[H] THEN VW = VL IF WCR = 3F[H] THEN VW = VH
INC/DEC LOGIC UP/DN MODIFIED SCL UP/DN CLK VL
VW
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X9428
DETAILED OPERATION The XDCP is controlled by the serial interface and is associated with a Control Latch and four data registers. A detailed discussion of the register organization and array operation follows. Control Latch The X9428 Control Latch for the XDCP can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the Control Latch can be altered in four ways: it may be written directly by the host via the Write Control Latch instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction and it is loaded with the contents of its data register zero (R0) upon powerup. The Control Latch is a volatile register; that is, its contents are lost when the X9428 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at powerdown. Data Registers The potentiometer has four nonvolatile data registers. These can be read or written directly by the host and data can be transferred between any of the four data registers and the control latch. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Wiper Register, WR (6-bit), non-volatile:
WP5 NV (MSB) WP4 NV WP3 NV WP2 NV WP1 NV WP0 NV (LSB)
* {WP5~WP0}: This is used to store one of the 64 wiper position (0 ~ 63).
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X9428
Instruction Format
Notes: Notes: Notes: Notes: Notes: Notes: (1) (2) (3) (4) (5) (6) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "DA3 ~ DA0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). In dual XDCP devices, "P1" is a "0" for testing purpose but physically it is a "don't care" condition.
Read Wiper Control Latch (RW)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C K1001XXXX wiper position S (sent by slave on SDA) A WWWWWW C K00PPPPPP 543210 M A C K S T O P
Load Wiper Control Latch (LW)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C K1010XXXX wiper position S (sent by master on SDA) A WWWWWW C KXXPPPPPP 543210 S A C K S T O P
Read Wiper Register (RR)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C RR K101110XX wiper position S (sent by slave on SDA) A WWWWWW C K00PPPPPP 543210 M A C K S T O P
Store Wiper Register (SR)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C RR K110010XX wiper position S (sent by master on SDA) A WWWWWW C KXXPPPPPP 543210 S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
Load Wiper Register to Wiper Latch (LRW)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C RR K110110XX S A C K S T O P
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X9428
Store Wiper Latch to Wiper Register (SWR)
device S device type identifier addresses T A DDDD R0101AAAA T 3210 instruction wiper S opcode addresses A C RR K111010XX S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
Increment/Decrement Wiper Latch (INCDEC)
S T A R T device type identifier 0 1 0 instruction S opcode A DDDDC 1AAAAK0010 3210 device addresses wiper addresses X X X increment/decrement S (sent by master on SDA) A C I/ I/ XK . . . . I/ I/ DD DD S T O P
SYMBOL TABLE
Figure 9. Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance RESISTANCE (K) 120 100 80 60 40 20 0 0
MIN. RESISTANCE R MIN =
WAVEFORM
VCC MAX =1.8K IOL MIN tR CBUS
R MAX =
MAX. RESISTANCE
20
40
60
80 100 120
BUS CAPACITANCE (pF)
10
X9428
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias-65C to +135C Storage Temperature-65C to +150C Voltage on SCK, SCL or any Address Input with Respect to VSS-1V to +7V Voltage on any VH or VL Referenced to VSS 8V V = |VH-VL|16V V+, V- 6V Lead Temperature (Soldering, 10 seconds)300C RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min.
0C -40C
Max.
+70C +85C
Supply Voltage
X9428 X9428-2.7
Limits
5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
RTOTAL IW RW Vv+ VvVTERM
Parameter
End to End Resistance Power Rating Wiper Current Wiper Resistance Voltage on V+ Pin Voltage on V- Pin Voltage on any VH or VL Pin Noise Resolution (4) Absolute Linearity (1) Relative Linearity (2) Temperature Coefficient
Min.
-20 -3
Typ.
Max.
+20 50 +3
Units
% mW mA V V V dB/\/Hz % Ref: 1V
Test Conditions
25C, each pot Wiper Current = 1mA
150 2.7 -5.5 V<-120 1.6 -1 -0.2 300
250 +5.5 -2.7 V+
+1 +0.2
MI(3) MI(3) ppm/C
Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI]
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X9428
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC ISB ILI ILO VIH VIL VOL
Notes:
Parameter
VCC Supply Current (Active) VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Min.
Typ.
3 1
Max.
Units
mA A
Test Conditions
fSCL = 100KHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC
10 10 VCC x 0.7 -0.5 VCC x 0.5 VCC x 0.1 0.4
A A V V V
IOL = 3mA
(1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH - VL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION Parameter
Minimum Endurance Data Retention
Min.
100,000 100
Units
Data Changes per Register Years
CAPACITANCE Symbol
CI/O CIN
(5) (5)
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, and SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
POWER-UP TIMING Symbol
tPUR
(6) (6)
Parameter
Power-up to Initiation of Read Operation Power-up to Initiation of Write Operation
Max.
1 5
Units
ms ms
tPUW
A.C. TEST CONDITIONS Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Level
Notes:
EQUIVALENT A.C. LOAD CIRCUIT
VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
SDA OUTPUT 100pF 5V 1533 2.7V
(5) This parameter is periodically sampled and not 100% tested (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 12
X9428
AC TIMING
Symbol fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT (4) tR (3) tF (3) tAA tDH TI tBUF tSU:WPA tHD:WPA I2C Clock Frequency I C Clock Cycle Time I C Clock High Time I2C Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time I2C Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) WP, A0, A1, A2 Setup Time WP, A0, A1, A2 Hold Time 100 50 50 1300 0 0
2 2
Parameter
Min. 2500 600 1300 600 600 600 100 0
Max. 400
Units KHz nS nS nS nS nS nS nS nS
300 300 900
nS nS nS nS nS nS nS nS
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol tWR Parameter High-voltage Write Cycle Time (Store Instructions) Typ. 5 Max. 10 Units mS
EEPOT TIMING
Symbol tWRPO (2) tWRL tWRID
Notes:
Parameter Wiper Response Time After The Third (Last) Power Supply Is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
Min.
Max. 10 10 10
Units uS uS uS
(7) tPOR and tPOW are the delays required from the time the third (last) power supply (Vcc, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (8) The bias order of power supply (Vcc, V+ and V-) don't care. (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
13
X9428
TIMING DIAGRAMS I2C Timing Figure 10. START and STOP Timing
g
(START) tR SCL tSU:STA SDA Figure 11. Input Timing tCYC SCL tHIGH tHD:STA tR tF tSU:STO tF
(STOP)
tLOW SDA tSU:DAT Figure 12. Output Timing SCL tHD:DAT tBUF
SDA tAA Figure 13. XDCP Timing (for All Load Instructions) (STOP) SCL tDH
SDA
LSB tWRL
VWx
14
X9428
Figure 14. XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec tWRID
VWx
Figure 15. Write Protect and Device Address Pins Timing (START) SCL ... (Any Instruction) ... ... tSU:WPA WP A0, A1 A2 tHD:WPA (STOP)
SDA
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X9428
ORDERING INFORMATION X9428 Device Y P T V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package P = 16-Lead Plastic DIP S = 16-Lead SOIC V = 16-Lead TSSOP Potentiometer Organization Y = 2K W = 10K U = 50K M = 2K
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
2.
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