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| xr MARCH 2003 PRELIMINARY XRT83L314 REV. P1.0.1 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT GENERAL DESCRIPTION The XRT83L314 is a fully integrated 14-channel longhaul and short-haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR's LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). FIGURE 1. BLOCK DIAGRAM OF THE XRT83L314 Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS generation/ detection, Network Loop Code generation/detection, TAOS, DMO, and diagnostic loopback modes. APPLICATIONS * * * * * * * * * * T1 Digital Cross Connects (DSX-1) ISDN Primary Rate Interface CSU/DSU E1/T1/J1 Interface T1/E1/J1 LAN/WAN Routers Public Switching Systems and PBX Interfaces T1/E1/J1 Multiplexer and Channel Banks Integrated Multi-Service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse Multiplexing for ATM (IMA) Wireless Base Stations 1 of 14 Channels NLCD Generation Driver Monitor TCLK TPOS TNEG HDB3/B8ZS Encoder Tx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen Line Driver TTIP TRING Analog Loopback Remote Loopback Digital Loopback QRSS Generation & Detection RCLK RPOS RNEG HDB3/B8ZS Decoder Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer Rx Equalizer RTIP RRING Rx Equalizer Control NLCD Detection AIS & LOS Detector DMO RLOS ICT TEST Test Microprocessor Interface Programmable Master Clock Synthesizer 8kHzOUT MCLKE1out MCLKT1out MCLKE1Nout MCLKT1Nout RxON RxTSEL [10:0] [7:0] TxON uPCLK uPTS2 uPTS1 uPTS0 CS[5:1] RD_WE RDY_TA WR_R/W Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com MCLKin ADDR CS ALE DATA Reset INT XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.1 xr PRELIMINARY FEATURES * Selectable receiver sensitivity from 0 to 36dB cable loss in T1 @ 772kHz, and 0 to 43dB cable loss in E1 @ 1,024kHz. * Fully integrated 14-Channel short haul and long haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications. * Receive monitor mode handles 0 to 29dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1. * T1/E1/J1 short haul, long haul, and clock rate are per port selectable through software without changing components. * Receiver line attenuation indication output in 1dB steps. * Internal Impedance matching on both receive and transmit for 75 (E1), 100 (T1), 110 (J1), and 120 (E1) applications are per port selectable through software without changing components. * Loss of signal (RLOS) according to ITU-T G.775/ ETS300233 (E1) and ANSI T1.403 (T1/J1). * Power down on a per channel basis with independent receive and transmit selection. * Programmable receive slicer threshold (45%, 50%, 55%, or 68%) for improved receiver interference immunity. * Five pre-programmed transmit pulse settings for T1 short haul applications, as well as an arbitrary programmable waveform generator for custom transmit pulse shaping per channel. * Programmable data stream muting upon RLOS detection. * On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel. * Arbitrary pulse generator for T1 short haul and T1 long haul modes per channel. * On-Chip digital clock recovery circuit for high input jitter tolerance. * Transmit line build outs (LBO) for T1 long haul applications from 0dB to -22.5dB in three -7.5dB steps on a per channel basis. * QRSS pattern generator and detection for testing and monitoring. * On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis. * Error and bipolar violation insertion and detection. * Transmit all ones (TAOS) and in-band network loop up and loop down code generation. * Independent Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive and transmit paths * Automatic loop code detection for remote loopback activation. * On-Chip frequency multiplier generates T1 or E1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 4X, 8X T1 or E1) * Supports local analog, remote, digital, and dual loopback modes. * Low Power dissipation: 170mW per channel (50% density). * Driver failure monitor output (DMO) alerts of possible system or external component problems. * 250mW per channel maximum power dissipation (100% density). * Transmit outputs and receive inputs may be "High" impedance for protection or applications on a per channel basis. redundancy * Single 3.3V supply operation (3V to 5V I/O tolerant). * Support for automatic protection switching. * 1:1 and 1+1 protection without relays. * 304-Pin TBGA package * -40C to +85C Temperature Range * Supports gapped clocks for mapper/multiplexer applications. PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRT83L314IB PACKAGE TYPE 304 Lead TBGA OPERATING TEMPERATURE RANGE -40C to +85C 2 23 WRB_RWB TCLK_8 TPOS_10 TPOS_7 DGND_DRV RVDD_7 RTIP_7 RRING_7 RGND_7 RGND_6 RRING_6 RTIP_6 RVDD_6 MCLKOUT_T1 MCLKIN MCLKOUT_E1 MCLKE1xN TCLK_5 ICTB unnamed.12 22 A B C RGND_5 RRING_5 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A[10] CSB CSB4 unnamed.2 RESETB CSB1 CSB5 TPOS_8 TNEG_9 TNEG_10 TCLK_7 VDDPLL_21 RCLK_7 TVDD_7 TRING_7 TRING_6 TVDD_6 RCLK_6 MCLKT1xN TPOS_6 TCLK_3 TCLK_4 TPOS_4 INTB DGND_DRV unnamed.17 xr RGND_8 A[8] DVDD_DRV CSB3 ALE_AS TNEG_8 TCLK_9 TNEG_7 VDDPLL_22 RNEG_7 TTIP_7 DGND_6_7 TTIP_6 RNEG_6 GNDPLL_22 GNDPLL_21 TNEG_6 TNEG_3 TNEG_4 TPOS_5 DVDD_PRE TRING_5 PRELIMINARY RRING_8 TRING_8 unnamed.7 DVDD_PRE CSB2 RDB_DSB TPOS_9 TCLK_10 DGND_PRE RPOS_7 TGND_7 DVDD_6_7 TGND_6 RPOS_6 DVDD_DRV EIGHT_KHZ TCLK_6 TPOS_3 TNEG_5 TEST unnamed.13 TVDD_5 D RTIP_5 RTIP_8 RVDD_8 TVDD_8 A[9] unnamed.11 TTIP_5 RVDD_5 E RCLK_5 RVDD_4 RVDD_9 RCLK_8 TTIP_8 TGND_8 TGND_5 RNEG_5 F RNEG_4 RCLK_4 RTIP_4 PIN OUT OF THE XRT83L314 RTIP_9 RCLK_9 RNEG_8 RPOS_8 RPOS_5 G RPOS_4 TTIP_4 TRING_4 RRING_4 RRING_9 TVDD_9 RNEG_9 RPOS_9 H TGND_4 TVDD_4 DVDD_3_4_5 RGND_4 RGND_9 TRING_9 TTIP_9 TGND_9 J AVDD_BIAS DVDD_DRV unnamed.14 unnamed.16 DVDD_8_9_10 unnamed.1 unnamed.3 unnamed.4 K DGND_PRE AGND_BIAS DGND_3_4_5 unnamed.10 DGND_8_9_10 unnamed.6 DGND_DRV DGND_PRE L TGND_3 TTIP_3 TRING_3 RGND_3 XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT 3 TGND_10 RGND_10 TRING_10 TTIP_10 Bottom View M RPOS_3 RNEG_3 TVDD_3 RRING_3 RRING_10 TVDD_10 RNEG_10 RPOS_10 N RPOS_2 RNEG_2 RCLK_3 RTIP_3 RTIP_10 RCLK_10 RNEG_11 RPOS_11 P TGND_2 TTIP_2 RCLK_2 RVDD_3 RVDD_10 RCLK_11 TTIP_11 TGND_11 R DGND_1_2 TVDD_2 RVDD_2 RTIP_2 RTIP_11 RVDD_11 TVDD_11 TRING_11 T TVDD_1 DGND_DRV TRING_2 RRING_2 RRING_11 DVDD_DRV DVDD_11_12 DGND_11_12 U TGND_1 TRING_1 DVDD_1_2 RGND_2 RGND_11 TRING_12 TVDD_12 TGND_12 V RPOS_1 TTIP_1 RGND_1 RRING_1 RRING_12 RGND_12 TTIP_12 RPOS_12 W TPOS_0 TNEG_1 D[3] DVDD_PRE DMO RNEG_1 RVDD_1 RTIP_1 RTIP_12 RCLK_12 RNEG_12 DVDD_PRE A[1] A[7] TCLK_12 TCLK_13 RXTSEL RPOS_13 TGND_13 DGND_13_0 TGND_0 RPOS_0 GNDPLL_12 Y RCLK_0 DGND_DRV TNEG_2 TPOS_1 D[4] D[7] RDY_DTACKB RCLK_1 unnamed.9 RVDD_12 unnamed.5 UPTS0 A[2] A[6] TPOS_12 TNEG_11 DVDD_DRV DVDD_UP RNEG_13 TTIP_13 DVDD_13_0 TTIP_0 RNEG_0 AA RVDD_0 DGND_PRE TNEG_0 TPOS_2 D[0] D[2] D[6] UPCLK RLOS DGND_DRV UPTS1 A[3] A[5] RXOFF TPOS_11 TPOS_13 VDDPLL_12 DGND_UP RCLK_13 TVDD_13 TRING_13 TRING_0 TVDD_0 AB RTIP_0 GNDPLL_11 TCLK_0 TCLK_2 TCLK_1 D[1] D[5] DVDD_DRV unnamed.0 REV. P1.0.1 UPTS2 A[0] A[4] TXOFF TNEG_12 TCLK_11 TNEG_13VDDPLL_11 RVDD_13 RTIP_13 RRING_13 RGND_13 RGND_0 RRING_0 AC XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.1 xr PRELIMINARY ORDERING INFORMATION PRODUCT NUMBER XRT83L314IB PACKAGE 304 LEAD TBGA OPERATING TEMPERATURE RANGE -400C to +850C PACKAGE DIMENSIONS (DIE DOWN) 22 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L A1 Feature/Mark D D1 M N P R T U V W Y AA AB AC D1 D (A1 corner feature is mfger option) P SEATING PLANE e A1 A b A2 Note: The control dimension is in millimeter. INCHES MIN MAX 0.051 0.067 0.018 0.028 0.031 0.071 0.004 0.012 1.213 1.228 1.100 BSC 0.024 0.035 0.050 BSC MILLIMETERS MIN MAX 1.30 1.70 0.45 0.70 0.80 1.80 0.10 0.30 30.80 31.20 27.94 BSC 0.60 0.90 1.27 BSC SYMBOL A A1 A2 P D D1 b e 4 xr XRT83L314 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.1 PRELIMINARY REVISION HISTORY REVISION # P1.0.0 P1.0.1 DATE 02/14/03 03/27/03 DESCRIPTION First release of the 14-Channel LIU Preliminary Datasheet Added the 16-bit LCV Counter Details for Revision B Silicon NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet March 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 5 |
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