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| bq2005 Fast-Charge IC for Dual-Battery Packs Features (R) Sequential fast charge and conditioning of two NiCd or NiMH nickel cadmium or nickel-metal hydride battery packs Hysteretic PWM switch-mode current regulation or gated control of an external regulator Easily integrated into systems or used as a stand-alone charger Pre-charge qualification of temperature and voltage Direct LED outputs display battery and charge status Fast-charge termination by temperature/ time, -V, maximum voltage, maximum temperature, and maximum time Optional top-off and pulsetrickle charging General Description The bq2005 Fast-Charge IC provides comprehensive fast charge control functions together with high-speed switching power control circuitry on a monolithic CMOS device for sequential charge management in dual battery pack applications. Integration of closed-loop current control circuitry allows the bq2005 to be the basis of a cost-effective solution for stand-alone and systemintegrated chargers for batteries of one or more cells. Switch-activated discharge-beforecharge allows bq2005-based chargers to support battery conditioning and capacity determination. High-efficiency power conversion is accomplished using the bq2005 as a hysteretic PWM controller for switch-mode regulation of the charging current. The bq2005 may alterna- tively be used to gate an externally regulated charging current. Fast charge may begin on application of the charging supply, replacement of the battery, or switch depression. For safety, fast charge is inhibited unless/until the battery temperature and voltage are within configured limits. Temperature, voltage, and time are monitored throughout fast charge. Fast charge is terminated by any of the following: n (R) (R) (R) (R) (R) Rate of temperature rise (T/t) Negative delta voltage (-V) Maximum voltage Maximum temperature Maximum time n n n n (R) After fast charge, optional top-off and pulsed current maintenance phases are available. Pin Connections Pin Names DCMDA Discharge command input, battery A DVEN -V enable Timer mode select 1 Timer mode select 2 Temperature cut-off Temperature sense input, battery A/B Battery voltage input, battery A/B Sense resistor input , battery A/B FCCA, FCCB VSS VCC MODA, MODB Fast charge complete output, battery A/B System ground 5.0V 10% power Charge current control output, battery A/B DISA Discharge control output, battery A Charge status output, battery A/B DCMDA DVEN TM1 TM2 TCO TSA TSB BATA BATB SNSA 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 FCCB CHB MODB MODA VCC VSS FCCA CHA DISA SNSB CHA, CHB TM1 TM2 TCO TSA, TSB BATA, BATB SNSA, SNSB 20-Pin DIP or SOIC PN200501.eps SLUS079-JUNE 1999 F 1 bq2005 Pin Descriptions DCMDA Discharge-before-charge control input, battery A DCMDA controls the discharge-before-charge function of the bq2005. A negative-going pulse on DCMDA initiates a discharge to EDV followed by a charge if conditions allow. By tying DCMD A to ground, automatic discharge-before-charge is enabled on every new charge cycle start. DVEN -V enable input This input enales/disables -V charge termination. If DVEN is high, the -V test is enabled. If DVEN is low, -V test is disabled. The state of DVEN may be changed at any time. TM1- TM2 Timer mode inputs TM1 and TM2 are three-state inputs that configure the fast charge safety timer, -V holdoff time, and that enhance/disable top-off. See Table 2. TCO Temperature cutoff threshold input Input to set maximum allowable battery temperature. If the potential between TSA and SNSA or TSB and SNSB is less than the voltage at the TCO input, then fast charge or top-off charge is terminated for the corresponding battery pack. TSA, TSB Temperature sense inputs Input, referenced to SNSA or SNSB, respectively, for an external thermistor monitoring battery temperature. BATA, BATB Voltage inputs The battery voltage sense input, referenced to SNSA,B, respectively. This is created by a high-impedance resistor divider network connected between the positive and the negative terminals of the battery. SNSA, SNSB Charging current sense inputs, SNSA,B controls the switching of MODA,B based on the voltage across an external sense resistor in the current path of the battery. SNS is the reference potential for the TS and BAT pins. If SNS is connected to VSS, MOD switches high at the beginning of charge and low at the end of charge. VCC CHA, CHB DISA Discharge control output Push-pull output used to control an external transistor to discharge battery A before charging. Charge status outputs Push-pull outputs indicating charging status for batteries A and B, respectively. See Figure 1 and Table 2. FCCA, FCCB Fast charge complete outputs Open-drain outputs indicating fast charge complete for batteries A and B, respectively. See Figure 1 and Table 2. MODA, MODB Charge current control outputs MODA,B is a push-pull output that is used to control the charging current to the battery. MODA,B switches high to enable charging current to flow and low to inhibit charging current fl ow to b a tteri es A a nd B, respectively. VCC supply input 5.0 V, 10% power input. Vss Ground 2 bq2005 Functional Description Figure 3 shows a block diagram and Figure 4 shows a state diagram of the bq2005. Discharge-Before-Charge The DCMD A input is used to command dischargebefore-charge via the DISA output. Once activated, DISA becomes active (high) until VCELL falls below VEDV where: VEDV = 0.475 VCC 30mV at which time DISA goes low and a new fast charge cycle begins. The DCMDA input is internally pulled up to VCC (its inactive state). Leaving the input unconnected, therefore, results in disabling discharge-before-charge. A negative going pulse on DCMDA initiates discharge-before-charge at any time regardless of the current state of the bq2005. If DCMDA is tied to VSS, discharge-beforecharge will be the first step in all newly started charge cycles. Battery Voltage and Temperature Measurements Battery voltage and temperature are monitored for maximum allowable values. The voltage presented on the battery sense input, BATA,B, must be divided down to between 0.95 VCC and 0.475 VCC for proper operation. A resistor-divider ratio of: RB1 N = -1 RB2 2.375 is recommended to maintain the battery voltage within the valid range, where N is the number of cells, RB1 is the resistor connected to the positive battery terminal, and RB2 is the resistor connected to the negative battery terminal. See Figure 1. Note: This resistor-divider network input impedance to end-to-end should be at least 200k and less than 1M. A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a low-cost temperature-to-voltage transducer. The temperature sense voltage input at TSA,B is developed using a resistor-thermistor network between VCC and VSS. See Figure 1. Both the BATA,B and TSA,B inputs are referenced to SNSA,B, so the signals used inside the IC are: VBAT(A,B) - VSNS(A,B) = VCELL(A,B) and VTS(A,B) - VSNS(A,B) = VTEMP(A,B) Starting A Charge Cycle A new charge cycle is started by (see Figure 2): 1. 2. VCC rising above 4.5V VCELL falling through the maximum cell voltage, VMCV where: VMCV = 0.95 VCC 30mV If DCMDA is tied low, a discharge-before-charge will be executed as the first step of the new charge cycle. Otherwise, pre-charge qualification testing will be the first step. The battery must be within the configured temperature and voltage limits before fast charging begins. Negative Temperature Coefficient Thermister VCC RT1 PACK+ PACK + bq2005 BATA,B RB1 TSA,B bq2005 SNSA,B RT2 N T C PACK - RB2 SNSA,B PACK- Fg2005-1.eps Figure 1. Voltage and Temperature Monitoring 3 bq2005 The valid battery voltage range is VEDV < VBAT < VMCV. The valid temperature range is VHTF < VTEMP < VLTF, where: VLTF = 0.4 VCC 30mV VHTF = [(1/4 VLTF) + (3/4 VTCO)] 30mV VTCO is the voltage presented at the TCO input pin, and is configured by the user with a resistor divider between VCC and ground. The allowed range is 0.2 to 0.4 VCC. If the temperature of the battery is out of range, or the voltage is too low, the chip enters the charge pending state and waits for both conditions to fall within their allowed limits. The MODA,B output is modulated to provide the configured trickle charge rate in the charge pending state. There is no time limit on the charge pending state; the charger remains in this state as long as the voltage or temperature conditons are outside of the allowed limits. If the voltage is too high, the chip goes to the battery absent state and waits until a new charge cycle is started. Fast charge continues until termination by one or more of the five possible termination conditions: n n n n n Delta temperature/delta time (T/t) Negative delta voltage (-V) Maximum voltage Maximum temperature Maximum time Discharge Charge Pending* Fast Charging Top-Off (Optional) Pulse-Trickle (Optional (Pulse-Trickle) Battery A) DISA 4s 260 s Switch-mode MODA,B Configuration 34s Note* 4s 260 s or External MODA,B Regulation 34s Note* CHA,B Status Output FCCA,B Status Output Battery within temperature/voltage limits. Battery discharged to 0.475 * VCC. Battery outside temperature/voltage limits. Discharge-Before-Charge started *See Table 3 for pulse-trickle period. T200501.eps Figure 2. Charge Cycle Phases 4 bq2005 Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table Corresponding Fast-Charge Rate C/4 C/2 1C 2C 4C C/2 1C 2C 4C Note: TM1 Low Float High Low Float High Low Float High TM2 Low Low Low Float Float Float High High High Typical Fast-Charge and Top-Off Time Limits 360 180 90 45 23 180 90 45 23 Typical -V/MCV Hold-Off Time (seconds) 137 820 410 200 100 820 410 200 100 Top-Off Rate Disabled Disabled Disabled Disabled Disabled C/16 C/8 C/4 C/2 Typical conditions = 25C, VCC = 5.0V. -V Termination If the DVEN input is high, the bq2005 samples the voltage at the BAT pin once every 34s. If VCELL is lower than any previously measured value by 12mV 4mV, fast charge is terminated. The -V test is valid in the range VMCV - (0.2 VCC) < VCELL < VMCV. Temperature Sampling Each sample is an average of 16 voltage measurements taken 57s apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is 16%. Voltage Sampling Each sample is an average of 16 voltage measurements taken 57s apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is 16%. Maximum Voltage, Temperature, and Time Anytime VCELL rises above VMCV, CHG goes high (the LED goes off) immediately. If the bq2005 is not in the voltage hold-off period, fast charging also ceases immediately. If VCELL then falls back below VMCV before tMCV = 1s (maximum), the chip transitions to the Charge Complete state (maximum voltage termination). If VCELL remains above VMCV at the expiration of tMCV, the bq2005 transitions to the Battery Absent state (battery removal). See Figure 4. Maximum temperature termination occurs anytime the voltage on the TS pin falls below the temperature cut-off threshold VTCO. Charge will also be terminated if VTEMP rises above the minimum temperature fault threshold, VLTF, after fast charge begins. Maximum charge time is configured using the TM pin. Time settings are available for corresponding charge rates of C/4, C/2, 1C, and 2C. Maximum time-out termination is enforced on the fast-charge phase, then reset, and enforced again on the top-off phase, if selected. There is no time limit on the trickle-charge phase. Voltage Termination Hold-off A hold-off period occurs at the start of fast charging. During the hold-off period, -V termination is disabled. This avoids premature termination on the voltage spikes sometimes produced by older batteries when fast-charge current is first applied. T/t, maximum voltage and maximum temperature terminations are not affected by the hold-off period. T/t Termination The bq2005 samples at the voltage at the TS pin every 34s, and compares it to the value measured two samples earlier. If VTEMP has fallen 16mV 4mV or more, fast charge is terminated. The T/t termination test is valid only when VTCO < VTEMP < VLTF. Top-off Charge An optional top-off charge phase may be selected to follow fast charge termination for the C/2 through 4C rates. This phase may be necessary on NiMH or other 5 bq2005 battery chemistries that have a tendency to terminate charge prior to reaching full capacity. With top-off enabled, charging continues at a reduced rate after fast-charge termination for a period of time selected by the TM1 and TM2 input pins. (See Table 2.) During top-off, the CC pin is modulated at a duty cycle of 4s active for every 30s inactive. This modulation results in an average rate 1/8th that of the fast charge rate. Maximum voltage, time, and temperature are the only termination methods enabled during top-off. selected), and then maintenance charging on both. If only battery A is present, the charge cycle begins on A and continues until fast charge termination even if a battery is inserted in channel B in the meantime. A new battery insertion in channel B while A is in the top-off phase terminates top-off on A and begins a new charge cycle on B. If A is configured for or commanded to discharge-before-charge, the discharge may take place while channel B is the active charging channel. When the discharge is complete, if B is still the active channel battery A enters the Charge Pending state until A becomes the active channel. Pulse-Trickle Charge Pulse-trickle charging follows the fast charge and optional top-off charge phases to compensate for selfdischarge of the battery while it is idle in the charger. The configured pulse-trickle rate is also applied in the charge pending state to raise the voltage of an overdischarged battery up to the minimum required before fast charge can begin. In the pulse-trickle mode, MOD is active for 260s of a period specified by the settings of TM1 and TM2. See Table 1. The resulting trickle-charge rate is C/64 when top-off is enabled and C/32 when top-off is disabled. Both pulse trickle and top-off may be disabled by tying TM1 and TM2 to VSS. Charge Current Control The bq2005 controls charge current through the MODA,B output pin. The current control circuitry is designed to support implementation of a constant-current switching regulator or to gate an externally regulated current source. When used in switch mode configuration, the nominal regulated current is: IREG = 0.225V/RSNS Charge current is monitored at the SNSA,B input by the voltage drop across a sense resistor, RSNS, between the low side of the battery pack and ground. RSNS is sized to provide the desired fast charge current. If the voltage at the SNSA,B pin is less than VSNSLO, the MODA,B output is switched high to pass charge current to the battery. When the SNSA,B voltage is greater than VSNSHI, the MODA,B output is switched low--shutting off charging current to the battery. VSNSLO = 0.04 VCC 25mV VSNSHI = 0.05 VCC 25mV When used to gate an externally regulated current source, the SNSA,B pin is connected to VSS, and no sense resisitor is required. Charge Status Indication Charge status is indicated by the CHG output. The state of the CHG output in the various charge cycle phases is shown in Figure 4 and illustrated in Figure 2. Temperature status is indicated by the TEMP output. TEMP is in the high state whenever VTEMP is within the temperature window defined by the VLTF and VHTF temperature limits, and is low when the battery temperature is outside these limits. In all cases, if VCELL exceeds the voltage at the MCV pin, both CHG and TEMP outputs are held high regardless of other conditions. CHG and TEMP may both be used to directly drive an LED. Pack Sequencing If both batteries A and B are present when a new charge cycle is started, the charge cycle starts on battery B and B remains the active channel until fast charge termination. Then battery A will be fast charged, followed by a top-off phase on B (if selected), a top-off phase on A (if 6 bq2005 TM1 TM2 TCO OSC TIMING CONTROL TCO TCO CHECK CHECK - FCC FCC CH CH A B A B V TS - V SNS A/D DISPLAY CONTROL LTF CHECK LTF CHECK - TSA TSB SNSA A/D DCMD A DVEN CHARGE CONTROL STATE MACHINE V BAT - V SNS SNSB EDV EDV CHECK CHECK MCV CHECK MCV CHECK - DISCHARGE CONTROL MOD CONTROL - BATA BATB DIS A MOD A MOD B V CC V SS BD2005 Figure 3. Block Diagram 7 bq2005 New Charge Cycle Started by either one of: VCC rising to valid level Battery replacement (VCELL falling through V MCV) VEDV < VCELL < VMCV Charge Pending DCMDA tied to ground? (channel A only) No or channel B Battery Voltage? VCELL < VEDV Rising edge on DCMD A Yes VCELL < VEDV VCELL > VMCV Discharge CH A = 1/8s flash FCC A = high VCELL > VMCV VTEMP > VLTF or Trickle VTEMP < VHTF Battery CHG = 1/8s Temperature? flash FCC = high VHTF < VTEMP < VLTF VCELL > VMCV VEDV < VCELL < VMCV and VHTF < VTEMP < VLTF Fast CHG = low FCC = high VCELL > VMCV Trickle CHG = high FCC = high VCELL > VMCV VCELL < VMCV Battery Absent t> tMCV Trickle CHG = high FCC = high - V or T/ t or VTEMP < VTCO or Maximum Time Out Top-off selected? No VCELL > VMCV Trickle CHG = high FCC = low Charge Complete Yes Top-off CHG = high FCC = low VTEMP < VTCO or Maximum Time Out SD2005 Figure 4. State Diagram 8 bq2005 Absolute Maximum Ratings Symbol VCC VT TOPR TSTG TSOLDER TBIAS Note: Parameter VCC relative to VSS DC voltage applied on any pin excluding VCC relative to VSS Operating ambient temperature Storage temperature Soldering temperature Temperature under bias Minimum -0.3 -0.3 -20 -55 -40 Maximum +7.0 +7.0 +70 +125 +260 +85 Unit V V C C C C 10 sec max. Commercial Notes Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Thresholds Symbol VSNSHI VSNSLO VLTF VHTF VEDV VMCV VTHERM -V (TA = TOPR; VCC 10%) Rating 0.05 * VCC 0.04 * VCC 0.4 * VCC (1/4 * VLTF) + (3/4 * VTCO) 0.475 * VCC 0.95 * VCC 16 12 Tolerance 0.025 0.010 0.030 0.030 0.030 0.030 4 4 Unit V V V V V V mV mV VTEMP VLTF inhibits/ terminates charge VTEMP VHTF inhibits charge VCELL < VEDV inhibits fast charge VCELL > VMCV inhibits/ terminates charge Notes Parameter High threshold at SNSA,B resulting in MODA,B = Low Low threshold at SNSA,B resulting in MODA,B = High Low-temperature fault High-temperature fault End-of-discharge voltage Maximum cell voltage TS input change for T/t detection BAT input change for -V detection 9 bq2005 Recommended DC Operating Conditions (TA = 0 to +70C) Symbol VCC VCELL VBAT VTEMP VTS VTCO VIH Parameter Supply voltage BAT voltage potential Battery input TS voltage potential Thermistor input Temperature cutoff Logic input high Logic input high Logic input low Logic input low Logic output high Logic output low Supply current DISA, MODA,B source DISA, FCCA,B, MODA,B, CHA,B sink Input leakage Logic input low source Logic input high source TM1, TM2 tri-state open detection Input current to BATA,B when battery is removed Minimum 4.5 0 0 0 0 0.2 * VCC 2.0 VCC - 0.3 VCC - 0.5 -5.0 5.0 -70.0 Typical 5.0 1.0 Maximum 5.5 VCC VCC VCC VCC 0.4 * VCC 0.8 0.3 0.5 3.0 1 -400 70.0 Unit V V V V V V V V V V V V mA mA mA A A A A A DCMDA, DVEN TM1, TM2 DCMDA, DVEN TM1, TM2 DISA, MODA,B, IOH -5mA DISA, FCCA,B, CHA,B, MODA,B, IOL 5mA Outputs unloaded @VOH = VCC - 0.5V @VOL = VSS + 0.5V DVEN, V = VSS to VCC DCMDA, V = VSS TM1, TM2, V = VSS to VSS + 0.3V TM1, TM2, V = VCC - 0.3V to VCC TM1, TM2 should be left disconnected (floating) for Z logic input state. VCC = 5.0V; TA = 25C; input should be limited to this current when input exceeds VCC. VTS - VSNS VBAT - VSNS Notes VIL VOH VOL ICC IOH IOL IL IIL IIH IIZ -2.0 - 2.0 IBAT Note: - - -20 A All voltages relative to VSS, except as noted. 10 bq2005 Impedance Symbol RBATA,B RTSA,B RTCO RSNSA,B Parameter Battery A/B input impedance TSA,B input impedance TCO input impedance SNSA,B input impedance Minimum 50 50 50 50 Typical Maximum Unit M M M M Timing Symbol tPW dFCV tREG tMCV Note: (TA = 0 to +70C; VCC 10%) Parameter Pulse width for DCMDA, pulse command Time base variation MOD output regulation frequency Maximum voltage termination time limit Minimum 1 -16 Typical Maximum 16 300 1 Unit s % kHz s Time limit to distinguish battery removed from charge complete Notes Pulse start for discharge-beforecharge VCC = 4.5V to 5.5V Typical is at TA = 25C, VCC = 5.0V. 11 bq2005 PN: 20-Pin DIP 20-Pin PN(DIP) Dimension Minimum A 0.160 A1 0.015 B 0.015 B1 0.055 C 0.008 D 1.010 E 0.300 E1 0.230 e 0.300 G 0.090 L 0.115 S 0.055 All dimensions are in inches. Maximum 0.180 0.040 0.022 0.065 0.013 1.060 0.325 0.280 0.370 0.110 0.135 0.080 D E1 E A B1 A1 L C e S G B 12 bq2005 S: 20-Pin SOIC 20-Pin S (SOIC) Dimension Minimum A 0.095 A1 0.004 B 0.013 C 0.008 D 0.500 E 0.290 e 0.045 H 0.395 L 0.020 All dimensions are in inches. Maximum 0.105 0.012 0.020 0.013 0.515 0.305 0.055 0.415 0.040 e D B E H A C .004 L A1 13 bq2005 Data Sheet Revision History Change No. 3 4 4 4 5 Notes: Page No. 9 5 5, 9 All 9 Description VSNSLO rating Corrected sample period Corrected -V threshold Nature of Change Was VSNSHI - (0.01 * VCC); is 0.04 * VCC Was: 32s; Is: 34s Was: 13mV Is: 12mV Revised and expanded format of this Clarification data sheet TOPR Deleted industrial temperature range. Change 3 = Sept. 1996 D changes from Nov. 1993 C. Change 4 = Nov. 1997 E changes from Sept. 1996 D. Change 5 = June 1999 F changes from Nov. 1997 E. 14 bq2005 Ordering Information bq2005 Package Option: PN = 20-pin narrow plastic DIP S = 20-pin SOIC Device: bq2005 Dual-Battery Fast-Charge IC 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subj ect to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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