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DV2002L2/TL2
Fast Charge Development System
Control of LM317 Linear Regulator Features
a a a a bq2002/T fast-charge control evaluation and development Charge current sourced from an on-board linear regulator (up to 1.5A) Fast charge of 4, 5, 6, 8, and 10 NiCd or NiMH cells (contact Benchmarq for other cell counts) Fast-charge termination by negative delta voltage (-V) or peak voltage detect (bq2002) or T/t (bq2002T) Maximum temperature and maximum time safety terminations -V/peak voltage detect, hold-off, top-off, maximum time, and number of cells are jumper-configurable Inhibit fast charge by a logic-level input
a a a
General Description
The DV2002L2/TL2 Development System provides a development environment for the bq2002 and bq2002T Fast-Charge ICs. The DV2002L2/TL2 incorporates a bq2002/T and a linear regulator to provide fast charge control for 4 to 10 NiCd or NiMH cells. The fast charge is terminated by any of the following: T/t, maximum temperature, maximum time, or an inhibit command for the bq2002T; or -V/peak voltage, maximum temperature, maximum time, and inhibit command for the bq2002. Jumper settings select the top-off and maximum time limits. The user provides a power supply and batteries. The user configures the DV2002L2/TL2 for the number of cells and maximum charge time (with or without topoff). Please review the bq2002T or bq2002 data sheet before using the DV2002L2/TL2 board.
Connection Descriptions
JP4 THERM BAT- BAT+ GND DC JP3 NOC JP2 INH JP1 TM Thermistor connection Battery ground Positive battery terminal Ground from charger supply DC input from charger supply Select number of cells Inhibit input Timer, etc. Setting
3/98
Rev. C Board
1
DV2002L2/TL2 Fixed Configuration
The DV2002L2/TL2 board has the following fixed characteristics: VCC (4.75-5.25V) is regulated on-board from the supply at connector JP4 (DC:GND). LED indicates charge status. Charge initiates on the later application of the battery or DC, which provides VCC to the bq2002/T.
Jumper-Selectable Configuration
The DV2002L2/TL2 must be configured as described below. INH (JP2): Enables/disables charge inhibit (see bq2002/T data sheet). Jumper Setting [12]3 1[23] Pin State Disabled (high) Enabled (low)
Table 1. Lookup Table for R7 Selection
Input Voltage to 25V
TM (JP1): Selects fast charge safety time/top-off (see bq2002/T data sheet). Jumper Setting [12]3 1[23] 123 Pin State High Low Float
Current 1A 1.5A
Resistance 1.25 0.83
Wattage 2W 2W
As shipped from Benchmarq, the DV2002L2/TL2 linear regulator is configured to a charging current of 1.25A. This current level is controlled by the value of sense resistor R7 by the relationship: ICHG = 1.25V R7
Number of Cells (JP3): A resistor-divider network is provided to select 4 to 10 cells (the resulting resistor value equals N - 1 cells). RB1 is a 100K resistor, and RB2 (RB20-RB25) is jumper-selected. Closed Jumper R13 R12 R11 R10 R9 Number of Cells 10 8 6 5 4
The value of R7 at shipment is 1. This resistor can be changed depending on the application. The suggested maximum ICHG for the DV2002L2/TL2 board is 1.5A. U2 must be mounted to an appropriate heat sink. The maximum cell voltage (MCV) is scaled to 2V/cell. With the provided NTC thermistor connected between THERM and BAT-, TCO = 50C. The thermistor is identified by the serial number suffix as follows: Identifier K1 (blank) F1 O1 S1 Thermistor Keystone RL0703-5744-103-S1 Philips 2322-640-63103 Fenwal Type 16, 197-103LA6-A01 Ozhumi 150-108-00(4) Semetic 103AT-2 4.
Rev. C Board
Temperature Disable: Connecting a 10K resistor between THERM and BAT- disables temperature control.
Setup Procedure
1. 2. 3. Configure TM, INH, and number-of-cells (NOC) jumpers. Connect the provided thermistor or a 10K resistor between THERM and BAT-. Attach the battery pack to BAT+ and BAT-. For temperature control, the thermistor must contact the cells. Attach DC current source to DC (+) and GND (-) connections in JP4.
2
DV2002L2/TL2 Recommended DC Operating Conditions
Symbol IDC VDC VBAT VTH Description Maximum input current Maximum input voltage BAT input voltage THERM input voltage Minimum 4.0 + VBAT or 10 0.5 Typical Maximum 1.5 18 + VBAT or 25 24 5 Unit A V V V
DV2002L2/TL2 Board Schematic
JP4 665 1% T 1 2 3 4 5 6 THERM BATBAT+ GND DC R1 390 Q1 2N4403 VCC 4 CELLS R9 301K 1% D1 1N751A C1 100UF 6.3V R15 VCC VCC C4 1000UF 35V 10K U2 LM317T R5 16.2K 1% RT12 VCC R6 3.6K VCCJP1 STATUS D2 H L TIMER
1 TM 2 3 LED BAT 4 VSS VIN VOUT ADJ
5 CELLS R10 402K 1%
6 CELLS R11 499K 1%
8 CELLS R12 698K 1%
10 CELLS R13 909K 1%
SEMITEC
D3 1N5400 JP3 BAT
R7 R8 240 1.0 2W R14 100K 1%
VCC
R2 2K
VCC
R3 100K
U1
8 CC 7 INH 6 VCC 5 TS
VCC
R16 100K
Q2 2N3904
R17 100K C5 0.01UF C3 0.1UF JP2 INH R18 26.1K 1% RT2
BQ2002T R4 100K
C2 0.1UF
DV2002TL2, REV C, 5/2/97
Rev. C Board
3
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Copyright (c) 1999, Texas Instruments Incorporated

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