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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
D Supply Current of 220 nA (Typ) D Precision Supply Voltage Supervision D D D D D
Range: 1.8 V, 2.5 V, 3.0 V, 3.3 V Power-On Reset Generator With Selectable Delay Time of 10 ms or 200 ms Push/Pull RESET Output (TPS3836), RESET Output (TPS3837), or Open-Drain RESET Output (TPS3838) Manual Reset 5-Pin SOT-23 Package Temperature Range -40C to 85C
D Applications Include
- Applications Using Low-Power DSPs, Microcontrollers, or Microprocessors - Portable/Battery-Powered Equipment - Intelligent Instruments - Wireless Communication Systems - Notebook Computers - Automotive Systems
TPS3836, TPS3838 DBV PACKAGE (TOP VIEW) CT 1 2 3 4 RESET 5 VDD
description
GND
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT.
MR
TPS3837 DBV PACKAGE (TOP VIEW) CT GND MR 1 2 3 4 RESET 5 VDD
When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to VDD the delay time is typically 200 ms. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider. The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and TPS3838 integrates an active-low open-drain RESET output.
TPS3836K33 VDD CT RESET MR T GND
MSP430 VCC Xin RST Xout VSS Quartz 32 kHz Lithium Battery 3.6 V
TYPICAL OPERATING CIRCUIT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
description (continued)
The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in a 5-pin SOT-23 package. The TPS3836, TPS3837, TPS3838 families are characterized for operation over a temperature range of -40C to 85C.
PACKAGE INFORMATION TA DEVICE NAME TPS3836E18DBVR TPS3836E18DBVT TPS3836J25DBVR TPS3836L30DBVR TPS3836K33DBVR TPS3837E18DBVR 40C -40C to 85C TPS3837J25DBVR TPS3837L30DBVR TPS3837K33DBVR TPS3838E18DBVR TPS3838J25DBVR TPS3838L30DBVR TPS3836J25DBVT TPS3836L30DBVT TPS3836K33DBVT TPS3837E18DBVT TPS3837J25DBVT TPS3837L30DBVT TPS3837K33DBVT TPS3838E18DBVT TPS3838J25DBVT TPS3838L30DBVT THRESHOLD VOLTAGE 1.71 V 2.25 V 2.64 V 2.93 V 1.71 V 2.25 V 2.64 V 2.93 V 1.71 V 2.25 V 2.64 V 2.93 V SYMBOL PDNI PDSI PCAI PDTI PDOI PDRI PCBI PDUI PDQI PDPI PCCI PDVI
TPS3838K33DBVR TPS3838K33DBVT The DBVR passive indicates tape and reel of 3000 parts. The DBVT passive indicates tape and reel of 250 parts. ORDERING INFORMATION
TPS383
6
E
18
DBV
R
Reel Package Nominal Supply Voltage Typical Reset Threshold Voltage Functionality Family
FUNCTION TABLE TPS3836, TPS3837, TPS3838 VDD > VIT RESET RESET MR L L H 0 1 0 L L L H H H H L
H 1 TPS3836 and TPS3838 TPS3837
2
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
functional block diagram
VDD R3 MR CT
R1 S1
C1 + -
Reset Logic and Timer
Reset (TPS3837-Push-Pull) Reset (TPS3836-Push-Pull TPS3838-Open-Drain)
R2 C2
S2
Band-Gap Reference
S3
C3 Refresh Timer GND
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
timing diagram
A VDD VIT B C D E F G
< 1.1 V t
MR
t
RESET
t Undefined Output td td td Undefined Output
4
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t=1000 h continuously DISSIPATION RATING TABLE PACKAGE DBV TA <25C POWER RATING 437 mW DERATING FACTOR ABOVE TA = 25C 3.5 mW/C TA = 70C POWER RATING 280 mW TA = 85C POWER RATING 227 mW
recommended operating conditions at specified temperature range
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Input transition rise and fall rate at MR, t/V Operating free-air temperature range, TA -40 1.6 0 0.7 x VDD 0.3 x VDD 100 85 MAX 6 VDD + 0.3 UNIT V V V V ns/V C
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER RESET (TPS3836) RESET (TPS3837) RESET (TPS3836/8) RESET (TPS3837) TPS3836/8 Power-up Power up reset voltage (see Note 2) TPS3837 TPS383xE18 TPS383xJ25 VIT Negative-going input threshold voltage ( (see N t 3) Note lt TPS383xL30 TPS383xK33 1.7 V < VIT < 2.5 V Vhys Hysteresis at VDD input in ut MR (see Note 4) CT IIL IOH IDD Low level input Low-level in ut current High-level output current MR (see Note 4) CT TPS3838 2.5 V < VIT < 3.5 V 3.5 V < VIT < 5 V MR = 0.7 x VDD, CT = VDD = 6 V MR = 0 V, CT = 0 V, VDD = VIT + 0.2 V, VDD > VIT, VDD > VIT, VDD < VIT VDD = 6 V VDD = 6 V VOH = VDD VDD < 3 V VDD > 3 V VDD = 6 V -40 -25 -130 -25 220 250 10 30 -200 TA = -40C to 85C 40C TEST CONDITION VDD = 3.3 V, VDD = 6 V, VDD = 1.8 V, VDD = 3.3 V, VDD = 1.8 V, VDD = 3.3 V, VDD = 3.3 V, VDD = 6 V, VDD 1.1 V, VDD 1.1 V, IOH = -2 mA IOH = -3 mA IOH = -1 mA IOL = -2 mA IOL = 1 mA IOL = 2 mA IOL = 2 mA IOL = 3 mA IOL = 50 A IOH = -50 A 0.8 x VDD 1.66 2.18 2.56 2.84 1.71 2.25 2.64 2.93 30 40 50 -60 -100 25 -340 25 25 400 450 15 nA A k A nA A nA nA mV 1.74 2.29 2.69 2.99 V MIN 0.8 x VDD TYP MAX UNIT
VOH
High-level High level output voltage
V
VOL
Low level output voltage Low-level
04 0.4
V
0.2 V
IIH
High level input High-level in ut current
Su ly Supply current Internal pullup resistor at MR
CI Input capacitance at MR, CT VI = 0 V to VDD 5 pF NOTES: 2. The lowest voltage at which RESET output becomes active. tr, VDD 15 s/V 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 F) should be placed near the supply terminal. 4. If manual reset is unused, MR should be connected to VDD to minimize current consumption.
6
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
timing requirements at RL = 1 M, CL = 50 pF, TA = 25_C
PARAMETER at VDD tw Pulse width at MR TEST CONDITIONS VIH = VIT + 0.2 V, VDD VIT + 0.2 V, VIH = 0.7 x VDD VIL = VIT - 0.2 V VIL = 0.3 x VDD, MIN 6 1 TYP MAX UNIT s s
switching characteristics at RL = 1 M, CL = 50 pF, TA = 25_C
PARAMETER TEST CONDITIONS VDD VIT + 0.2 V, MR = 0.7 x VDD, CT = GND, See timing diagram td Delay time VDD VIT + 0.2 V, MR = 0.7 x VDD, CT = VDD , See timing diagram VDD to RESET delay (TPS3836, (TPS3836 TPS3838) VDD to RESET delay (TPS3837) MR to RESET delay (TPS3836, TPS3838) MR to RESET delay (TPS3837) VIL = VIT - 0.2 V, VIH = VIT + 0.2 V VIL = 1.6 V VIL = VIT - 0.2 V, VIH = VIT + 0.2 V VIL = 1.6 V VDD VIT + 0.2 V, VIL = 0.3 x VDD, VIL = 0.7 x VDD MIN TYP MAX UNIT
5
10
15 ms
100
200
300
tPHL
Pro agation Propagation (delay) time, high to low level out ut high-to-low-level output
10 50 10 50 0.1 0.1
s
tPLH
Pro agation Propagation (delay) time, low to high level out ut low-to-high-level output
s
tPHL tPLH
Propagation (delay) time, high-to-low-level output Propagation (delay) time, low-to-high-level output
s s
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE IDD IMR VOL VOH Supply current Manual reset current Low-level output voltage High-level output voltage Normalized reset threshold voltage Minimum pulse duration at VDD vs Supply voltage vs Manual reset voltage vs Low-level output current vs High-level output current vs Free-air temperature vs VDD Threshold overdrive 1 2 3 4 5 6
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs SUPPLY VOLTAGE
10 MR = Open CT = GND 8 IDD - Supply Current - A TA = 85C IMR - Manual Reset Current - A 100
MANUAL RESET CURRENT vs MANUAL RESET VOLTAGE
VDD = 6 V CT = GND 0 TA = -40C -100 TA = 0C
TA = 25C 6 TA = 0C 4 TA = -40C 2
-200 TA = 25C -300 TA = 85C
-400
0 0 2 4 6 VDD - Supply Voltage - V
-500 -2 0 2 4 6 VMR - Manual Reset Voltage - V
Figure 1
Figure 2
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
2.0 VDD = 2 V MR = OPEN CT = GND 1.5 TA = 25C 1.0 TA = 85C TA = 0C 0.5 TA = -40C 2.0
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
VDD = 2 V MR = OPEN CT = GND 1.5 TA = 85C TA = 25C 1.0 TA = 0C 0.5 TA = -40C 0.0
0.0 0 1 2 3 4 5 6 7 IOL - Low-Level Output Current - mA
VOH - High-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
0
1
2
3
4
5
Figure 3
IOH - High-Level Output Current - mA
Figure 4
8
POST OFFICE BOX 655303
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
TYPICAL CHARACTERISTICS
NORMALIZED RESET THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE
1.001 Normalized Reset Threshold Voltage - V
1
0.999
0.998
0.997
CT = GND, MR = Open
0.996
0.995 -40
-15 10 35 60 TA - Free-Air Temperature - C
85
Figure 5
MINIMUM PULSE DURATION AT VDD vs VDD THRESHOLD OVERDRIVE
22 20 Minimum Pulse Duration at VDD - s 18 16 14 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 MR = Open CT = GND TA = 25C
VDD - Threshold Overdrive - V
Figure 6
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TPS3836E18, TPS3836J25, TPS3836L30, TPS3836K33, TPS3837E18, TPS3837J25 TPS3837L30, TPS3837K33, TPS3838E18, TPS3838J25, TPS3838L30, TPS3838K33 NANOPOWER SUPERVISORY CIRCUITS
SLVS292 - JUNE 2000
MECHANICAL DATA
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,95 5 4
0,50 0,30
0,20 M
1,70 1,50
3,00 2,60
0,15 NOM
1 3,00 2,80
3
Gage Plane
0,25 0-8 0,55 0,35
Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/E 05/99
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178
10
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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