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TLV320VD30 VDSL CODEC
SLWS086 - JUNE 1999
D D D D D D D D
General-Purpose Analog Interface Circuit for VDSL System 12 Bit, 22 MHz ADC and DAC Provides 11 MHz Bandwidth Performance Supports Central Office and Remote Terminal Applications Excellent Power Management by Enabling/Disabling Major Functional Blocks When in Power Control Mode Remote Activation Feature With Selectable Wake-Up Tone Frequency Integrated Equalizer to Partially Compensate for the Roll Off in Twisted Pair Telephone Cable Numerically Controlled Oscillator With Resolution <1 ppm, Range of 250 ppm Using External Crystal
D D D D D D D D D D D
26 dB RFI Suppression Programmable Receive Amplifier Operating From 0 dB to 20 dB, in Steps of 1 dB Programmable Transmitter Output Power Level From -13 dBm to 11 dBm Enable/Disable of All Major Blocks During Power Mode Digital Loopback Test Mode Internal Voltage References Serial Control Port Conversion Rate up to 22.08 MHz Selectable Offset Binary or 2s Complement Data Format 3.3 V Operation 80-Pin PN Package
description
The TLV320VD30 is an analog front end (AFE) device for VDSL systems. The TLV320VD30 provides a transmitter and a receiver. Both the transmitter and receiver have up to 11 MHz-bandwidth performance. The device can be used for central office and remote VDSL applications. The transmitter consists of a 12-bit/22 MHz DAC and a programmable line driver interface. The receiver consists of a 12-bit/22 MHz ADC, a programmable gain amplifier, a compromise equalizer, and an RFI cancellation circuit. The device includes a tone detect circuit, and a numerically controlled crystal oscillator. The TLV320VD30 provides two parallel ports for fast data transfers and a serial port for device control. The parallel ports are 12-pin ports with data transfer rates of up to 22 MHz per 12-bit word. One parallel port is dedicated to DAC input, the other parallel port is dedicated to ADC output. The serial port supports both write and read operations. The serial data transfer rate is 1.38 MHz per bit. Data is transferred in 16-bit words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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PN PACKAGE (TOP VIEW)
RSET GUARDGND GUARDVDD AVDD3 AGND3 SENSETXP TXP TXBIASP AVDD2 RXP RXM AGND2 TXBIASM TXM SENSETXM TDVREFM TDVREFP VBG AGND4 AVDD4 XIN XOUT CLKIN EXTCLKEN RESET TEST3 RFIADAPTEN TXENABLE RXENABLE SENABLE SIN DVDD DGND DAC<11> DAC<10> DAC<9> DAC<8>
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 45 6 40 39 38 37 36 35 34 33 32
TESTM VCM TESTP
31 30 29 28 27 26 25 24 23 22
TLV320VD30PN
21 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VCMSENSEM VCMSENSEP TESTCLK AGND1 AVDD1 ADCGNDREF NC ADCGND ADCVDD GUARDGND GUARDVDD TONEDETECT DGNDIO DVDDIO ADC<11> ADC<10> ADC<9> ADC<8> ADC<7> ADC<6>
NC - No internal connection
2
DAC<7> DAC<6> DAC<5> DAC<4> DAC<3> DAC<2> DAC<1> DAC<0> DVDDIO CLK DGNDIO SOUT SCLK SREADY ADC<0> ADC<1> ADC<2> ADC<3> ADC<4> ADC<5>
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TLV320VD30 VDSL CODEC
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functional block diagram
DAC<11:0> TXP TXM SENSETXP SENSETXM
12 bits
DAC
Line Driver Interface
CLKIN XIN NCXO XOUT 9 bits CLKOUT
M U X
TXPOWER 3 bits
RFI Cancel 2 bits Compromise Equalizer I Q
VCMSENSEM VCMSENSEP RFIADAPTEN
RXP PGA RXM
ADC<11:0> 12 bits TXENABLE RXENABLE TONEDETECT SENABLE SCLK SIN SOUT SREADY
ADC
Power Control
5 bits Tone Detect NCXO
Serial Control BUS
TXPOWER CEQ PGA
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Terminal Functions
TERMINAL NAME ADC<0,11> ADCGND ADCGNDREF ADCVDD AGND1 AGND2 AGND3 AGND4 TESTM TESTP TESTCLK AVDD1 AVDD2 AVDD3 AVDD4 CLK CLKIN DAC<11:0> NO. 15-26 33 35 32 37 49 56 62 43 41 38 36 52 57 63 10 66 77,78, 79,80, 1-8 76 11 28 75 9 27 67 31 59 30 58 34 68 70 60 50 51 72 69 13 73 I I I/O I I I I O I I O I I I/O I/O I/O I/O O DESCRIPTION Digital receive data. Data format can be straight offset binary or 2s complement. Data output on falling edge of clock. Analog ADC ground ADC ground reference Analog ADC VDD, 3.3 V Analog ground Analog ground Analog ground Analog ground Reserved for test. No connection. Reserved for test. No connection. Reserved for test. No connection. Analog VDD, 3.3 V Analog VDD, 3.3 V Analog VDD, 3.3 V Analog VDD, 3.3 V System clock, 22.08 MHz External clock input Digital transmit data. Data format can be straight offset binary or 2s complement. Data input on rising edge of clock. Digital ground Digital I/O ground Digital I/O ground Digital VDD, 3.3 V Digital I/O VDD, 2.5 V/3.3 V Digital I/O VDD, 2.5 V/3.3 V External Clock Enable Isolation ground. Isolation ground Isolation VDD, 3.3 V Isolation VDD No connection Device reset RFI cancellation adapt enable Resistor current set requires an external 621 , 1% resistor Receiver input (-) Receiver input (+) Receive enable (active high). RXENABLE signal provides a minimum of 5 s warning of an impending receive burst. This signal remains High until the DMT engine has received the last ADC data word. Reserved for test. No connection. Serial bus clock (frequency = CLK/16 or 1.38 MHz) Serial bus enable (active high). SENABLE high indicates that the DSP interface is requesting activation of the serial input.
DGND DGNDIO DGNDIO DVDD DVDDIO DVDDIO EXTCLKEN GAURDGND GUARDGND GUARDVDD GUARDVDD NC RESET RFIADAPTEN RSET RXM RXP RXENABLE TEST3 SCLK SENABLE
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Terminal Functions (Continued)
TERMINAL NAME SENSETXM SENSETXP SIN SOUT SREADY TDVREFM TDVREFP TONEDETECT TXM TXP TXBIASM TXBIASP TXENABLE VBG VCM VCMSENSEM VCMSENSEP XIN XOUT NO. 46 55 74 12 14 45 44 29 47 54 48 53 71 61 42 40 39 64 65 I/O I/O I/O I O O I/O I/O O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O DESCRIPTION Transmitter current sense(-). Connects to external line driver. Transmitter current sense(+). Connects to external line driver. Serial bus input Serial bus output. SOUT is high impedance when SENABLE is low. SREADY indicates when the device is ready to output serial data. Tone detector reference V(-). Connects to an external resistor divider. Tone detector reference V(+). Connects to an external resistor divider Wake-up tone detector output. Remains low when the tone detector is disabled. When the tone detector is enabled, goes high when a wake-up tone is present. Transmitter output (-). Connects to external line driver. Transmitter output (+). Connects to external line driver. Transmitter bias current (-). Connects to external line driver. Transmitter bias current (+). Connects to external line driver. Transmitter enable (active high). TXENABLE signal provides up to 5 s of warning of an impending transmit burst. This signal remains High until the last TX data word has been registered. Voltage bandgap reference, 1.25 V. Requires an external 0.1 F capacitor. Common mode voltage reference. Connects to an internally generated 1.5 V reference, requires an external 0.1 F bypass capacitor. Reference for VCMSENSEM Transformer common mode input signal used by the RFI canceller. Connects to transformer line-side center tap through an external attenuator. 22.08 MHz crystal input 22.08 MHz crystal output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, AVDD, DVDD, DVDDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to AVDD+0.5 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD+0.5 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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recommended operating conditions
power supply
MIN AVDD Supply voltage DVDD DVDDIO TX active (see Note 1) Power dissipation RX active RX standby mode Power-down mode, PSRR (see Note 2) Frequency = 150 kHz TX/RX disabled 3 3 NOM 3.3 3.3 2.5/3.3 110 500 100 60 -45 dB 200 700 mW MAX 3.6 3.6 V UNIT
NOTES: 1. Does not include line driver. 2. PSRR measurement are made with the TX and RX channels idle and a 400 mVpp signal.
digital inputs/outputs
MIN High-level High level input voltage VIH voltage, Low-level Low level input voltage VIL voltage, High-level High level input current, IIH current Low-level Low level input current, IiL current High-level High level output voltage VOH voltage, Low level output voltage VOL Low-level voltage, High-level High level output current IOH current, Low-level Low level output current, IOL current DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V DVDD, DVDDIO = 3.3 V DVDD = 3.3 V, DVDDIO = 2.5 V 1 1 1 1 2.4 2 0.6 0.6 100 100 100 100 2.4 2 0.6 0.6 NOM MAX UNIT V V A A V V mA mA
clock inputs
MIN Input clock frequency Input clock duty cycle 45% NOM 22.08 50% 55% MAX UNIT MHz
reference voltage
MIN VCM (common mode) VBG (band gap) AVDD = 3.3 V AVDD = 3.3 V 1.4 1.20 1.25 NOM MAX 1.6 1.30 UNIT V V
NCXO
MIN Step size Range AVDD = 3.3 V AVDD = 3.3 V 200 250 NOM MAX 1 UNIT ppm ppm
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electrical characteristics over recommended operating free-air temperature range, TA = 255C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 22.08 MHz (unless otherwise noted)
TXDAC
PARAMETER Signal bandwidth Conversion rate AC Performance Single tone Transmit 2nd harmonic Transmit 3rd harmonic THD SNR SNDR (see Note 3) 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at 0 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at -6 dbfs 1.4 MHz at -12 dbfs 1.4 MHz at -18 dbfs 1.4 MHz at -24 dbfs 1.4 MHz at -30 dbfs Channel delay NOTE 3: Signal-to-noise and distortion -77 -75 -64 -56 -46 -54 -51 -42 -31 -22 -10 90 -60 -67 -58 -55 -45 -53 -50 -41 -30 -20 -9 -55 -67 -54 -54 -44 -51 -49 -40 -29 -21 -8 150 dB dB dB dB dB dB dB dB dB dB dB nS TEST CONDITIONS MIN 43k TYP 11.04M 22.08 MAX UNIT Hz MHz
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electrical characteristics over recommended operating free-air temperature range, TA = 255C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 22.08 MHz (unless otherwise noted) (continued)
RXADC channel characteristics
PARAMETER Signal bandwidth Conversion rate CMRR PGA gain error AC Performance Single tone Transmit 2nd harmonic Transmit 3rd harmonic THD SNR 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at -3 dbfs 1.4 MHz at 0 dbfs 1.4 MHz at -3 dbfs SNDR (see Note 3) 1.4 MHz at -6 dbfs 1.4 MHz at -12 dbfs 1.4 MHz at -18 dbfs 1.4 MHz at -24 dbfs RX total deviation Missing tone test RX missing tone 2.72 MHz RX missing tone 5.52 MHz RX missing tone 8.28 MHz RX CEQ-00 MAG at 4 MHz Compromise equalizer RX CEQ-01 MAG at 4 MHz RX CEQ-10 MAG at 4 MHz RX CEQ-11 MAG at 4 MHz Channel delay NOTE 3: Signal-to-noise and distortion -68 -66 -64 -59 -59 -58 -52 -40 -28 -21 2.38 -60 -53 -65 -37 -36 -34 -32.5 150 -66 -65 -62 -58 -58 -57 -51 -39 -25 -18 2.42 -48 -47 -54 -64 -63 -61 -57 -57 -56 -50 -38 -24 -13 2.45 -44 -43 -50 -36 -34.5 -33 -31 200 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB nS -50 TEST CONDITIONS MIN 43k TYP 11.04M 22.08 -44 -37 1 MAX UNIT Hz MHz dB dB
RFI cancellation
PARAMETER At 4 MHz At 8 MHz TEST CONDITIONS MIN -45 -45 TYP MAX -20 -25 UNIT dB dB
receiver (RX+, RX-)
PARAMETER Voltage range Input current AVDD = 3.3 V TEST CONDITIONS AVDD = 3.3 V, VCM ~1.5 V MIN TYP MAX VCM2 10 UNIT V mA
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detailed description
device functions The following sections describe the functions of the device.
transmit block
Transmit block contains the DAC and a special class AB line-driver interface that connects to external bipolar transistors and the center-tapped transformer to obtain peak output current of 200 mA, peak voltage of 11 Vpp differential with a 110 load. This circuit has been specially designed to deliver average power of 11 dBm (11 mW) to a 110 W reference impedance twisted-pair line with good linearity and low power consumption in a single bandwidth up to 11 MHz. Additionally the power level can be adjusted downward in 4 steps of 6 dB. To conserve power, this block is only enabled when the device is in the transmit mode. It is activated when the external TXENABLE signal is registered by the control logic. When this occurs, the control logic simultaneously generates a TXRESET signal that remains asserted for approximately 5 s after TXENABLE is asserted. The TXRESET signal causes the transmitter to force 25 mV across the two external sense resistors, defining the Vout = 0 state. When TXRESET is released, the transmit output follows the input data until the TXENABLE signal is released, at which time the transmitter is powered down. The transmitter output power level can be adjusted between -13 and 11 dBm (into 110 ) in increments of 6 dB. This is accomplished by programming bits 5:3 of mode control register (register 3). The digital format of the TX<11:0> input data can either be straight offset binary or 2s complement, as determined by the MSBINV bit, bit 1 of mode control register (register 3). The transmit path of the AFE utilizes a class AB current output configuration. Because of the class AB operation, the output signal must be generated by two separate channels--one channel which generates positive values of the transmit signal and the other channel responsible for negative values. Each channel consists of an 11 bit DAC and a TxAmp, which provides the base current for the external bipolar output devices. Given a 12 bit digital input in straight offset binary format (i.e., midscale = 1000 0000 0000 = 0 V differential), the MSB of the input data determines which DAC is activated for a given code. The remaining 11 bits control the collector current level in the activated channel, which results in 12 bits of programmability. Each 11 bit DAC has 2048 programmable output levels. To maintain symmetry, an input code of 0 results in an output of step of 1/2 LSB. When the transmitter output is evaluated differentially, this results in a 1 LSB transition when crossing the midpoint of the transfer function (i.e., when switching from one DAC to the other). The following table identifies some of the critical input codes and their corresponding output values: Table 1. Input Codes and Output Values
TX<11:0> 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 (4095) (4094) (2049) (2048) (2047) (2046) (1) (0) RsenseP Vidle + 2047 1/2 LSBs Vidle + 2046 1/2 LSBs Vidle + 1 1/2 LSBs Vidle + 1/2 LSBs Vidle Vidle Vidle Vidle Vidle Vidle Vidle Vidle Vidle + 1/2 LSBs Vidle + 1 1/2 LSBs Vidle + 2046 1/2 LSBs Vidle + 2047 1/2 LSBs RsenseM RsenseP - RsenseM 2047 1/2 LSBs 2046 1/2 LSBs 1 1/2 LSBs 1/2 LSBs -1/2 LSBs -1 1/2 LSBs -2046 1/2 LSBs -2047 1/2 LSBs
External low pass filtering is needed for noise reduction. A minimum requirement is a fourth order Butterworth low pass filter with cutoff frequency between 11 MHz and 12 MHz.
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detailed description (continued)
TXENABLE tcc CLKIN tcd 5 s Default tu td
CLKOUT ts DAC<11:0> th
Figure 1. Timing Sequence of the DAC
RXENABLE tcc CLKIN tcd 5 s Default tu td
CLKOUT t1
ADC<11:0>
Figure 2. Timing Sequence of the ADC
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detailed description (continued)
Table 2. Clock Timing
MIN tcc tu td tr tf tcd t1 ts th 0 0 0 0 tu + tr - tcd - 5 tcc - tcd - 20 tcc - tcd - 4 42 19 19 2 2 MAX UNITS ns ns ns ns ns ns ns ns ns
tone detector
In both VDSL transceiver unit-central office end (VTU-O) and VDSL transceiver unit-remote terminal end(VTU-R) units, much of the analog system will be in power down mode unless it is in use. So, a special signal is needed to indicate that a unit is requesting activation. The tone detector detects this special signal. Therefore it is enabled only in the receive standby mode. During this time, the tone detector constantly monitors the received signal for the presence of a wake up tone, The tone frequency can be either 172.5 kHz or 345 kHz (bins 4 and 8, respectively, where bin is the frequency plane that split up into blocks of frequencies of 43.125 kHz). The wake up tone should be at least 225 s duration. In the upstream direction, when a remote unit requests activation, it will send a 172.5 kHz frequency sinusoid, corresponding to bin 4. In the absence of noise, the peak amplitude of the received wake up tone can very from 7 mV for a long line to 100 mV for a short line. The choice of tone frequency is determined by the TDBIN register bit, bit 0 of the mode control register (register 3), a logic 0 sets the frequency to 172.5 kHz (bin 4), and a logic 1 sets the frequency to 345 kHz (bin 8). The tone detector block also has large clamp switches, which are closed when either the transmitter is enabled or the receiver is being reset to keep the internal voltages within the supply rails when transmitting.
PGA/MDAC
The PGA/MDAC block is a low noise, low distortion amplifier that performs several functions. Primarily, The PGA/MDAC is a variable gain amplifier that increases the strength of the receive signal from 0 dB to 20 dB in increments of 1 dB. The gain is controlled using bits 4:0 of the RX control register (register 1). In addition, when RFI cancellation is enabled, this block performs the weighting of the I and Q common mode signals and sums them with the receive signal.
compromise equalizer
The compromise equalizer (CEQ) provides signal gain to the frequencies in the upper end of the signal band to compensate for the high frequency attenuation in the line. Because of large processing tolerances, the corner frequency has two bits of programmability. The compromise equalizer implements the following transfer function: H(f) = k (s + z)2 / (s + p)2 When selected, or when it is bypassed by register control, H(f) = 1. The compromise equalizer can be bypassed by setting bit 7 of RX control register (register 1) to 1 and can be tuned by programming bits 5,6 of the same register.
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detailed description (continued)
RFI canceller
The RFI canceller block reduces the magnitude of RFI present in the received signal to the same power level as the smallest desired signal. It is assumed that the interferer is related to the common mode signal present on the line. An attenuated form of this common mode signal is used by the RFI canceller to generate differential I and Q signals which are weighted and summed with the RX signal in the PGA block. The output of the PGA is mixed with each of the I and Q signals in a correllator, whose output is used to drive a digital integrator (12 bit up/down counters) in the control block. The counter outputs determine the I/Q weighting coefficients that are used by the PGA. The RFI canceller adapts for 25 s every 475 s during quiet frames after receiving. When the line is in use, the coefficients are held constant, as shown in Figure 3.
Superframe Period = 500 s RX Quiet TX Quiet RX Quiet
Update Enable 25 s
Update Enable 25 s
Figure 3. A VDSL Super Frame
ADC
The ADC block uses a pipeline architecture to convert the analog Rx signal into 12 bit digital data. The analog input is first converted into discrete time data by the sample and hold. A 5-bit flash ADC then quantizes the signal to 5 bits, which provides the 5 MSBs of the final 12-bit word. These 5 bits are also used to drive a 5-bit DAC; the output is subtracted from the original input signal. The residual voltage is then amplified by the first subrange amplifier, and the resulting signal is used to perform another analog-to-digital-to-analog conversion to obtain the middle 5 bits of the final 12-bit word. The process is repeated one final time in the third ADC, which is only 4 bits.
NCXO
The numerically controlled oscillator (NCXO) block is responsible for controlling the system clock used by both the AFE and the DMT engine. When the external EXTCLKEN terminal is LOW and a 22.08 MHz crystal is connected between the XIN and XOUT terminals, the system clock is generated internally and has 9 bits of tuning resolution, with approximately 1 ppm of resolution per bit. When EXTCLKEN is HI, the NCXO block is powered down and an external clock source (CLKIN) is used as the system clock.
POR
In the absence of an external reset signal, the POR block is responsible for generating an internal reset signal when the chip is initially powered. It functions in conjunction with its I/O pad cell, which is responsible for level shifting the external logic level (which could be 2.5 V) up to the internal core voltage of 3.3 V nominal. Reset interval is 25 s.
bandgap
The bandgap block generates a nominal 1.25-V reference voltage that is relatively insensitive to variations in temperature, supply voltage, and processing.
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control logic
power mode description The control logic is responsible for controlling all of the possible power modes available on the ASIC. External control of the power mode can be achieved through either a combination of the external TXENABLE and RXENABLE input terminals or through the power mode register bit accessible via the serial interface.
external power control
When the power mode register bit (Reg7<0>) is set high, control of the operational power mode is achieved through the external TXENABLE and RXENABLE input terminals as described in Figure 4.
POR/ External RESET 11 00 nn = TXENABLE, RXENABLE
RX Standby 11 11 RX Quiet 01
TX Quiet 10
0x
TX Reset
RX Reset
x0
Timer
Timer
TX
RX
Figure 4. State Diagram for External Power Mode Control By defining separate states for TX Quiet and RX Quiet, it is possible to adapt the RFI canceller during the RX Quiet state without having to power up the RFI canceller during the TX Quiet state. The remaining modes are defined in Table 3. Table 3. Power Modes
UNIT DAC Line driver RFI canceller Tone detector PGA ADC CEQ NCXO Serial bus X X X X X X X X X TRANSMIT X X X X X RECEIVE RxSTANDBY TEST X X X X X X X X X
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serial bus power control
When the power mode register bit (Reg7<0>) is set low, control of the each of the following major functional blocks is obtained through their individual enable register bits in Register 7.
D D D D D D
RFI canceller PGA CEQ ADC Transmitter Tone detector
serial interface operation A serial interface has been included to allow both read and write access of the 7 internal 12-bit registers. The serial clock (SCLK) is generated internally and operates at 1.38 MHz (22.08 MHz system clock divided by 16). Data is transferred across the interface in groups of 16 bits each, the order of which is as shown in Table 4, (lsb first): Table 4. Data Transfer Order
SerBit<0> R/W (Read = 1, Write = 0) SerBit<1> Reg<0> SerBit<2> Reg<1> SerBit<3> Reg<2> SerBit<4> Data<0> SerBit<5> ... SerBit <15> Data<1> ... Data<11>
A read or write operation is initiated when the SENABLE input terminal is sampled high on the rising edge of SCLK. The incoming data is then captured over the following 16 rising edges of SCLK. The first bit determines whether a read or write is to take place (read = 1, write = 0). The next 3 bits determine the address of the register to be accessed. If a write operation is chosen, the remaining 12 bits of SIN data represent the data to be written to the addressed register, thus completing the write operation. This is shown in Figure 5.
SCLK
SENABLE
SIN
0
1
2
3
4
13
14
15
Figure 5. Register Write Operation Timing Diagram If a read operation has been selected, these 12 data bits are ignored. For a read operation, the SREADY output terminal is asserted for one clock cycle immediately following the clocking of SerBit<15> followed by 16 bits of data on the SOUT output terminal in the order outlined above. SerData<0> is always 1 in this case for read, and the Reg<2:0> field indicates the data register being read. This is shown in Figure 6.
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serial interface operation (continued)
SCLK
SREADY
SOUT
register map
REGISTER/ BIT 0 Default 1 Default 2 Default 3 Default 4 Default 5 Default 6 Default 7 Default 1 1 1 0 0 1 1
11
IIIII IIIII IIIII
10 9 RSTTIME<3:0> 1 0 0 0 0 0 0 0 0 0 0 0 RSTDEF 1 1
0
1
2
3
4
11
12
13
14
15
Figure 6. Register Read Operation Timing Diagram
8
7
6
5
4
3
2
1
0
****************************** NOT USED ****************************** ****************************** NOT USED ****************************** CeqBP 1 1 CEQ<1:0> 0 0 1 PGA Gain <4:0> (Default = 20 dB) 0 1 0 0
NCXO<8:0> 0 0 0 0 0 TxPower <2:0> 0 0 0 0 Up/Dn 0 0 Icoeff<11:0> 0 0 0 0 0 0 0 0 0 0 Up/Dn Cntl 0 0 Up./Dn Inv 0 0 0 Loop Back 0 0 MSB INV 0 0 TDBIN 0 RFIon line 0
Reserve for Test 0 0
RFIstep<1:0> 0 0
Qcoeff<11:0> 0 0 0 TD Enable 1 0 ADC Enable 1 0 Ceq Enable 1 0 PGA Enable 1 0 RFI Enable 1 0 TX Enable 1 0 Power Mode 1
Reserved for Test 1 1
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SLWS086 - JUNE 1999
detail of the internal registers
Name: Rx Control
BITS 11:8 ACCESS RW NAME RSTTIME
Register Address: 1
No. of Bits: 12
DESCRIPTION
When the reset counter is in register control mode (RSTDEF = 0), these bits are used to control the duration of the RESET counter. The reset duration can be calculated using treset = [dec(RSTTIME<3:0>) + 1] x 362 ns. The default value of RSTTIME = 1101 (13d), which results in a 5.068 s delay. Controls the operational mode of the CEQ: 0: CEQ spectrum shaping enabled 1: Bypass [flat frequency response] (default) Controls the tuning of the CEQ output spectrum: 00: Max gain at 4 MHz (default) 01: 10: 11: Min gain at 4 MHz Controls the gain of the PGA 00000: 0 dB 00001: 1 dB 00010: 2 dB * * 10010: 18 dB 10011: 19 dB 10100: 20 dB (default) 10101: 0 dB * * 11111: 0 dB
7
RW
CEQBP
6:5
RW
CEQ<1:0>
4:0
RW
PGAGAIN
Name: NCXO Control
BITS 11:3 ACCESS RW NAME NCXO
Register Address: 2
No. of Bits: 12
DESCRIPTION
Controls the tuning of the NCXO: 0 0000 0000: Max. CLK frequency 1 0000 0000: Nominal CLK frequency (default) 1 1111 1111: Min. CLK frequency
2:0
RW
Reserved
Name: Mode Control
BITS 11:6 5:3 ACCESS RW RW NAME Reserved TXPOWER
Register Address: 3
No. of Bits: 12
DESCRIPTION
These bits select the output power level of the transmitter: 000: 11 dBm (default) 001: 5 dBm 010: -1 dBm 011: -7 dBm 1xx: -13 dBm In test mode, determines whether digital loopback is enabled: 0: Loopback disabled (default) 1: Loopback enabled This bit determines the digital format of the Tx/Rx digital data: 0: Straight offset binary (default) 1: 2s complement This bit selects the wake up tone frequency: 0: Bin 4 [172.5 kHz] (default) 1: Bin 8 [345 kHz]
2
RW
LOOPBACK
1
RW
MSBINV
0
RW
TDBIN
16
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TLV320VD30 VDSL CODEC
SLWS086 - JUNE 1999
detail of the internal registers (continued)
Name: RFI Cntrl/Test
BITS 11.6 5 ACCESS RW RW NAME Reserved Up/down Reserved for test When up/down Cntl is high, this bit selects the direction of the 12 bit I/Q counters: 0: Down (default) 1: Up When in test mode, this bit controls the source of 12 bit I/Q counter control: 0: Correlator output (default) 1: Up/down register bit Controls whether the 12 bit I/Q counter inputs are inverted: 0: No inversion (default) 1: Counter inputs inverted. Controls adaptation rate of the I/Q coefficients: 00 = COUNT<11:4> (default) 01 = COUNT<10:3> 10 = COUNT<9:2> 11 = COUNT<8:1> Disables RFI canceller: 0: RFI canceller disabled (default) 1: RFI canceller enabled
Register Address: 4
No. of Bits: 12
DESCRIPTION
4
RW
Up/down Cntl
3
RW
Up/down Inv
2:1
RW
RFIstep
0
RW
RFIonline
Name: I Coefficients
BITS 11:0 ACCESS RW NAME Icoeff
Register Address: 5
No. of Bits: 12
DESCRIPTION
Controls the weighting of the I common mode component summed with the Rx signal.
Name: Q Coefficients
BITS 11:0 ACCESS RW NAME Qcoeff
Register Address: 6
No. of Bits: 12
DESCRIPTION
Controls the weighting of the Q common mode component summed with the Rx signal.
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TLV320VD30 VDSL CODEC
SLWS086 - JUNE 1999
detail of the internal registers (continued)
Name: Power Modes
BITS 11.10 9:7 ACCESS RW RW NAME Reserved RSTDEF Determines source of RESET counter coefficients: 0: TSTTIME<3:0> 1: Hard-wired value (default) Reserved for test Enables/disables tone detector in power mode: 0: Disabled 1: Enabled (default) Enables/disables ADC in power mode: 0: Disabled 1: Enabled (default) Enables/disables CEQ in power mode: 0: Disabled 1: Enabled (default) Enables/disables PGA in power mode: 0: Disabled 1: Enabled (default) Enables/disables RFI canceller in power mode: 0: Disabled 1: Enabled (default) Enables/disables transmitter in power mode: 0: Disabled 1: Enabled (default) Determine source of power mode control: 0: Power mode control registers 1: External RXEN and TXEN (default)
Register Address: 6
No. of Bits: 12
DESCRIPTION
8:7 6
RW RW
Reserved TD Enable
5
RW
ADC Enable
4
RW
CEQ Enable
3
RW
PGA Enable
2
RW
RFI Enable
1
RW
TX Enable
0
RW
POWERMODE
18
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TLV320VD30 VDSL CODEC
SLWS086 - JUNE 1999
APPLICATION INFORMATION
The high throughput VDSL can be easily made compatible with SONET and ATM-based services. VDSL can be used in a business or campus environment for providing high-speed digital transmission connections. Similarly, a VDSL system can be used to interconnect users within any concentrated area for high speed intranet use. Figure 7 gives a block level system representation. This system is capable of providing up to 52 Mb/s over unshielded twisted pair at ranges of 300-1500m.
Data Interface (DI)
DMT Engine
Analog Front End
Transformer Filter
Line
RAM
DSP
Figure 7. System Block Diagram
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19
TLV320VD30 VDSL CODEC
SLWS086 - JUNE 1999
MECHANICAL DATA
PN (S-PQFP-G80)
0,27 0,17 41
PLASTIC QUAD FLATPACK
0,50 60
0,08 M
61
40
80
0,13 NOM 21
1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,45 1,35
20
Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
20
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

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