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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
D D D D D D D D D
Organization . . . 4 194 304 x 32 Single 5-V Power Supply (10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes Eight 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2048 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
D D
Presence Detect Performance Ranges:
ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tAA tCAC CYCLE (MAX) (MAX) (MAX) (MIN) '497BBK32-60 60 ns 30 ns 15 ns 110 ns '497BBK32-70 70 ns 35 ns 18 ns 130 ns '497BBK32-80 80 ns 40 ns 20 ns 150 ns
D D D D
Low Power Dissipation Operating Free-Air-Temperature Range 0C to 70C Gold-Tabbed Version Available: TM497BBK32 Tin-Lead (Solder) Tabbed Version Available: TM497BBK32S
description
The TM497BBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4 194 304 x 8 in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ, 4 194 304 x 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The TM497BBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The TM497BBK32 SIMM features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0C to 70C.
operation
The TM497BBK32 operates as eight TMS417400DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle.
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
BK SINGLE-IN-LINE PACKAGE ( TOP VIEW )
(SIDE VIEW )
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A10 CAS0 - CAS3 DQ0 - DQ31 NC PD1 - PD4 RAS0, RAS2 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM497BBK32 70 ns 60 ns PD1 (67) VSS VSS VSS PD2 (68) NC NC NC PD3 (69) NC VSS NC PD4 (70) VSS NC NC
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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 RASx RAS0 RAS0 RAS2 RAS2 CASx CAS0 CAS1 CAS2 CAS3
single-in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497BBK32: Nickel plate and gold plate over copper Contact area for TM497BBK32S: Nickel plate and tin-lead over copper
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SMMS433B - JANUARY 1993 - REVISED JUNE 1995
TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
functional block diagram
A0 - A10 RAS0 W CAS0 11 RAS2 CAS1 11 4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4 11 4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4 CAS2 11 4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4 CAS3 11 4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4
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Template Release Date: 7-11-94
DQ0 - DQ3
DQ8 - DQ11
DQ16 - DQ19
DQ24 - DQ27
11
4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ4 - DQ7
4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ12 - DQ15
4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ20 - DQ23
4Mx4 A0 - A10 RAS W CAS OE DQ1 - DQ4
DQ28 - DQ31
TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle '497BBK32-60 MIN 2.4 0.4 80 10 880 MAX '497BBK32-70 MIN 2.4 0.4 80 10 800 MAX '497BBK32-80 MIN 2.4 0.4 80 10 720 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
880
800
720
mA
ICC4
560
480
400
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Input capacitance, address inputs Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, write-enable input MIN MAX 40 28 14 56 7 UNIT pF pF pF pF pF
Co(DQ) Output capacitance on DQ pins NOTE 5: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOH Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low-impedance state Output disable time from start of CAS high 0 3 0 15 '497BBK32-60 MIN MAX 30 15 35 60 0 3 0 18 '497BBK32-70 MIN MAX 35 18 40 70 0 3 0 20 '497BBK32-80 MIN MAX 40 20 45 80 UNIT ns ns ns ns ns ns ns
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'497BBK32-60 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page-mode, RAS low Pulse duration, non-page-mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W-low before CAS high Setup time, W-low before RAS high Setup time, W-low before CAS low Setup time, W-high before RAS low (CBR refresh only) 110 40 60 100 000 60 15 10 40 10 0 0 0 0 15 15 0 10 10 000 10 000 MAX '497BBK32-70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 100 000 10 000 10 000 MAX '497BBK32-80 MIN 150 50 80 80 20 10 60 10 0 0 0 0 20 20 0 10 100 000 10 000 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be tCP.
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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'497BBK32-60 MIN tCAH tRHCP tDH tRAH tRCH tRRH tWCH tWRH tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Hold time, column address after CAS low Hold time, RAS high from CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Refresh time interval Transition time 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. 3 10 35 10 10 0 0 10 10 10 5 60 5 15 30 30 20 0 15 32 30 3 45 30 MAX '497BBK32-70 MIN 15 40 15 10 0 0 15 10 10 5 70 5 15 35 35 20 0 18 32 30 3 52 35 MAX '497BBK32-80 MIN 15 45 15 10 0 0 15 10 10 5 80 5 15 40 40 20 0 20 32 30 60 40 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
device symbolization
TM497BBK32
-SS
YYMMT
YY MM T -SS
= Year Code = Month Code = Assembly Site Code = Speed Code
NOTE: The location of the part number may vary.
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TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE
SMMS433B - JANUARY 1993 - REVISED JUNE 1995
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Copyright (c) 1998, Texas Instruments Incorporated

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