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TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
D D D D D D D D
Organization . . . 4 194 304 x 9 Single 5-V Power Supply (10% Tolerance) 30-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes One 4-Megabit and Two 16-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2048 Cycles) All Inputs, Outputs, and Clocks Fully TTL Compatible 3-State Outputs Performance Ranges:
ACCESS ACCESS TIME TIME (tRAC) t(AA) (MAX) (MAX) 60 ns 30 ns 70 ns 35 ns 80 ns 40 ns ACCESS READ OR TIME WRITE (tCAC) CYCLE (MAX) (MIN) 15 ns 110 ns 18 ns 130 ns 20 ns 150 ns
U SINGLE-IN-LINE PACKAGE ( TOP VIEW )
D D D D D
'497EU9-60 '497EU9-70 '497EU9-80
Common CAS Control for Eight Common Data-In and Data-Out Lines Separate CAS Control for One Separate Pair of Data-In and Data-Out Lines Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
VCC CAS DQ1 A0 A1 DQ2 A2 A3 VSS DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 A10 DQ6 W VSS DQ7 NC DQ8 Q9 RAS CAS9 D9 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
description
The TM497EU9 is a 4M-byte dynamic random-access memory (RAM) organized as 4 194 304 x 9 bits [bit nine (D9, Q9) is generally used for parity and is controlled by CAS9] in a 30-pin leadless single-in-line memory module (SIMM). The SIMM is composed of two TMS417400DJ, 4 194 304 x 4-bit dynamic RAMs, each in a 24/26-lead plastic small-outline J-lead (SOJ) package, and one TMS44100DJ, 4 194 304 x 1-bit dynamic RAM in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors.
PIN NOMENCLATURE A0 - A10 CAS, CAS9 DQ1 - DQ8 D9 NC Q9 RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out Data In No Connection Data Out Row-Address Strobe 5-V Supply Ground Write Enable
The TM497EU9 is available in the U single-sided, leadless module for use with sockets and is characterized for operation from 0C to 70C.
A0 - A9 address lines must be refreshed every 16 ms.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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1
TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
operation
The TM497EU9 operates as two TMS417400DJs and one TMS44100DJ connected as shown in the functional block diagram (refer to the TMS417400 and TMS44100 data sheets for details of their operation). The common I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition, the ten least significant row addresses ( A0- A9) must be refreshed every 16 ms as required by the TMS44100. power up To achieve proper operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR) cycle.
single-in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
A0 - A10 RAS CAS W 11 4M x 4 A0 - A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE 3 6 10 13 DQ1 DQ2 DQ3 DQ4
11
4M x 4 A0 - A10 DQ1 RAS DQ2 DQ3 CAS DQ4 W OE
16 20 23 25
DQ5 DQ6 DQ7 DQ8
11 CAS9
4M x 1 A0 - A10 RAS CAS W
D Q
29 26
D9 Q9
2
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TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle '497EU9-60 MIN 2.4 0.4 10 10 325 MAX '497EU9-70 MIN 2.4 0.4 10 10 290 MAX '497EU9-80 MIN 2.4 0.4 10 10 260 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
6
6
6 mA
3
3
3
ICC3
Average refresh current (RAS-only or CBR) (see Note 3) Average page current (see Note 4)
325
290
260
mA
ICC4
210
180
150
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(D) Ci(R) Ci(C) Ci(W) Co(DQ) Input capacitance, A0 - A10 Input capacitance, data input (D9) Input capacitance, strobe input (RAS) Input capacitance, strobe inputs capacitance Input capacitance, W Output capacitance (DQ1 - DQ8) CAS CAS9 MIN MAX 15 5 21 14 7 21 7 7 UNIT pF pF pF pF pF pF pF
Co(Q) Output capacitance (Q9) NOTE 5: VCC = 5 V 0.5 V, and the bias on pin under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOH Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low-impedance state Output disable time, start of CAS high 0 3 0 15 '497EU9-60 MIN MAX 30 15 35 60 0 3 0 18 '497EU9-70 MIN MAX 35 18 40 70 0 3 0 20 '497EU9-80 MIN MAX 40 20 45 80 UNIT ns ns ns ns ns ns ns
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
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TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCAH tDH tRAH tRCH tRRH tWCH tWRH tRHCP tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Cycle time, random read or write (see Note 7) Cycle time, page mode read or write (see Notes 7 and 8) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high before RAS low (CBR refresh only) Hold time, column address after CAS low Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) Hold time, RAS high from CAS precharge Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low Delay time, CAS low to RAS high Refresh time interval Transition time All cycle times assume tT = 5 ns. To assure tPC min, tASC should be tCP. Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to assure access time. 3 '497EU9-60 MIN 110 40 60 100 000 60 15 10 40 10 0 0 0 0 15 15 0 10 10 10 10 0 0 10 10 35 10 5 60 5 15 30 30 20 0 15 32 30 3 45 30 10 000 10 000 MAX '497EU9-70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 15 15 10 0 0 15 10 40 10 5 70 5 15 35 35 20 0 18 32 30 3 52 35 100 000 10 000 10 000 MAX '497EU9-80 MIN 150 50 80 80 20 10 60 10 0 0 0 0 20 20 0 10 15 15 10 0 0 15 10 45 10 5 80 5 15 40 40 20 0 20 32 30 60 40 100 000 10 000 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
NOTES: 7. 8. 9. 10.
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TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE
SMMS499A - FEBRUARY 1994 - REVISED JUNE 1995
device symbolization
TM497EU9 -SS YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed
NOTE: The location of the part number may vary.
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Copyright (c) 1998, Texas Instruments Incorporated

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