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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
D D D D D D D D D D
Organization TM124FBK32F . . . 1 048 576 x 32 TM248GBK32F . . . 2 097 152 x 32 Single 5-V Power Supply (10% Tolerance) 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket TM124FBK32F - Utilizes Two 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Package TM248GBK32F - Utilizes Four 16M-Bit DRAMs in Plastic SOJ Package Long Refresh Period 16 ms (1 024 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Extended Data Out (EDO) Operation With CAS-Before-RAS ( CBR), RAS-Only, Hidden Refresh, and Self Refresh
D D D
Presence Detect JEDEC First Generation 72-Pin SIMM Pinout Performance Ranges:
ACCESS TIME tRAC (MAX) '124FBK32F-60 60 ns '124FBK32F-70 70 ns '124FBK32F-80 80 ns '248GBK32F-60 60 ns '248GBK32F-70 70 ns '248GBK32F-80 80 ns ACCESS ACCESS EDO TIME TIME CYCLE tAA tCAC tHPC (MAX) (MAX) (MIN) 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns
D D D D
Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C Gold-Tabbed Versions Available: TM124FBK32F TM248GBK32F Tin-Lead Solder-Tabbed Versions Available: TM124FBK32U TM248GBK32U
description
TM124FBK32F The TM124FBK32F is a 4M-byte DRAM organized as four times 1 048 576 x 8 in a 72-pin SIMM. The SIMM is composed of two TMS418169DZ 1 048 576 x 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet (literature number SMKS886). The TM124FBK32F SIMM is available in the single-sided BK-leadless module for use with sockets. TM248GBK32F The TM248GBK32F is an 8M-byte DRAM organized as four times 2 097 152 x 8 in a 72-pin SIMM. The SIMM is composed of four TMS418169DZ 1 048 576 x 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet (literature number SMKS886). The TM248GBK32F SIMM is available in the double-sided BK-leadless module for use with sockets.
operation
The TM124FBK32F operates as two TMS418169DZs connected as shown in the functional block diagram and in Table 1. The TM248GBK32F operates as four TMS418169DZs connected as shown in the functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
BK SINGLE IN-LINE MEMORY MODULE ( TOP VIEW )
TM124FBK32F ( SIDE VIEW )
TM248GBK32F ( SIDE VIEW )
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A9 CAS0 - CAS3 DQ0 - DQ31 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM124FBK32F 70 ns 60 ns 80 ns TM248GBK32F 70 ns 60 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) VSS VSS VSS NC NC NC PD3 (69) NC VSS NC NC VSS NC PD4 (70) VSS NC NC VSS NC NC
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 RASx SIDE 1 RAS0 RAS0 RAS2 RAS2 SIDE 2 RAS1 RAS1 RAS3 RAS3 CASx CAS0 CAS1 CAS2 CAS3
Side 2 applies to the TM248GBK32F and the TM248GBK32U.
single in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124FBK32F and TM248GBK32F: Nickel plate and gold plate over copper Contact area for TM124FBK32U and TM248GBK32U: Nickel plate and tin/lead over copper
functional block diagram (TM124FBK32F and TM248GBK32F, side 1)
A0 - A9 RAS0 W 10 RAS2
10
CAS0 CAS1
1M x 16 A0 -A9 DQ0 - DQ7 RAS W LCAS DQ8 - UCAS DQ15
10 DQ0 - DQ7 CAS2 CAS3
DQ8 - DQ15
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15
DQ16 - DQ23 DQ24 - DQ31
functional block diagram (TM248GBK32F, side 2)
A0 - A9 RAS1 W 10 RAS3
10
CAS1 CAS0
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15
10 DQ8 - DQ15 DQ0 - DQ7 CAS3 CAS2
1M x 16 A0 -A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15
DQ24 - DQ31
DQ16 - DQ23
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124FBK32F, TM124FBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W TM248GBK32F, TM248GBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After one memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, tHPC = MIN, CAS cycling RAS low, '124FBK32F - 60 MIN 2.4 0.4 10 10 MAX '124FBK32F - 70 MIN 2.4 0.4 10 10 MAX '124FBK32F - 80 MIN 2.4 0.4 10 10 MAX UNIT V V A A
IO
Output current (leakage) Read- or write-cycle current (see Note 3)
ICC1
380
360
340
mA
4
4
4
mA
ICC2
Standby current
2
2
2
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average EDO current (see Note 4)
380
360
340
mA
ICC4
200
180
160
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle '248GBK32F - 60 MIN 2.4 0.4 10 20 384 MAX '248GBK32F - 70 MIN 2.4 0.4 10 20 364 MAX '248GBK32F - 80 MIN 2.4 0.4 10 20 344 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After one memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
8
8
8
mA
4
4
4
mA
ICC3
Average refresh current (RAS only or CBR) (see Notes 3 and 5) Average EDO current (see Note 4)
760
720
680
mA
ICC4
204
184
164
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH 5. Measured with both sides in CBR cycle
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Input capacitance, A0 - A9 Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, W '124FBK32F MIN MAX 12 8 8 16 8 '248GBK32F MIN MAX 22 8 15 30 15 UNIT pF pF pF pF pF
Co(DQ) Output capacitance on DQ0 - DQ31 NOTE 6: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tRAC tCPA tCLZ tREZ Access time from column address Access time from CAS low Access time from RAS low Access time from column precharge CAS to output in low-impedance state Output disable time after RAS high (see Note 7) 0 3 3 15 15 '124FBK32F - 60 '248GBK32F - 60 MIN MAX 30 15 60 35 0 3 3 18 18 '124FBK32F - 70 '248GBK32F - 70 MIN MAX 35 18 70 40 0 3 3 20 20 '124FBK32F - 80 '248GBK32F - 80 MIN MAX 40 20 80 45 ns ns ns ns ns ns ns UNIT
tWEZ Output disable time after W low (see Note 7) NOTE 7: tREZ and tWEZ are specified when the output is no longer driven.
EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124FBK32F - 60 '248GBK32F - 60 MIN tHPC tPRWC tCSH tDOH tCAS tWPE tCP Cycle time, EDO page-mode read or write Cycle time, EDO read-write Hold time, CAS from RAS Hold time, output from CAS Pulse duration, CAS Pulse duration, W (output disable only) Precharge time, CAS 25 80 50 3 10 5 5 10 000 MAX '124FBK32F - 70 '248GBK32F - 70 MIN 30 90 55 3 12 5 5 10 000 MAX '124FBK32F - 80 '248GBK32F - 80 MIN 35 100 60 3 15 5 5 10 000 MAX ns ns ns ns ns ns ns UNIT
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124FBK32F - 60 '248GBK32F - 60 MIN tRC tRWC tRASP tRAS tRP tWP tRASS tRPS tASC tASR tDS tRCS Cycle time, random read or write (see Note 8) Cycle time, read-write Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, RAS high (precharge) Pulse duration, W low Pulse duration, self refresh entry from RAS low Pulse duration, RAS precharge after self refresh Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low 110 150 60 60 40 10 100 110 0 0 0 0 10 100 000 10 000 MAX '124FBK32F - 70 '248GBK32F - 70 MIN 130 175 70 70 50 10 100 130 0 0 0 0 12 100 000 10 000 MAX '124FBK32F - 80 '248GBK32F - 80 MIN 150 200 80 80 60 10 100 150 0 0 0 0 15 100 000 10 000 MAX ns ns ns ns ns ns s ns ns ns ns ns ns UNIT
tCWL Setup time, W low before CAS high NOTE 8: The ac parameter assumes tT = 5 ns.
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'124FBK32F - 60 '248GBK32F - 60 MIN tRWL tWCS tCAH tDH tRAH tRCH tRRH tWCH tRHCP tCHS tCHR tCRP tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF Setup time, W low before RAS high Setup time, W low before CAS low Hold time, column address after CAS low Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, RAS high from CAS precharge Hold time, CAS low after RAS high (self refresh) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Refresh time interval 2 10 0 10 10 10 0 0 10 35 - 50 10 5 5 15 30 20 20 0 10 16 30 2 45 30 MAX '124FBK32F - 70 '248GBK32F - 70 MIN 12 0 15 15 10 0 0 15 40 - 50 10 5 5 15 35 25 20 0 12 16 30 2 52 35 MAX '124FBK32F - 80 '248GBK32F - 80 MIN 15 0 15 15 10 0 0 15 45 - 50 10 5 5 15 40 30 20 0 15 16 30 60 40 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns UNIT
tT Transition time NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time.
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TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS660 - MARCH 1996
MECHANICAL DATA
BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE
4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP
0.054 (1,37) 0.047 (1,19)
1.005 (25,53) 0.995 (25,27)
0.050 (1,27) 0.040 (1,02) TYP
0.128 (3,25) 0.120 (3,05)
0.010 (0,25) MAX 0.400 (10,16) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM)
4040197 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
device symbolization (TM124FBK32F illustrated)
TM124FBK32F
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
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Copyright (c) 1998, Texas Instruments Incorporated

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