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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
D D D D D D D
Organization - TM2SR72EPU . . . 2 097 152 x 72 Bits - TM4SR72EPU . . . 4 194 304 x 72 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM2SR72EPU -- Uses Nine 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M x 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM4SR72EPU -- Uses 18 16M-Bit SDRAMs (2M x 8-Bit) in Plastic TSOPs Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3) (CL = 2) ACCESS TIME (CLOCK TO OUTPUT) tCK2 tCK3 (CL = 3) (CL = 2) 9 ns 9 ns 9 ns 10 ns REFRESH INTERVAL
D D D D D D D D D D
High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface Byte-Read/Write Capability Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Two Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM
'xSR72EPU-12A 'xSR72EPU-12
12 ns 12 ns
15 ns 18 ns
64 ms 64 ms
CL = CAS latency -12A speed device is supported only at -5% to +10% VDD
description
The TM2SR72EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number SMOS687). The TM4SR72EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number SMOS687).
operation
The TM2SR72EPU operates as nine TMS626812DGE devices that are connected as shown in the TM2SR72EPU functional block diagram. The TM4SR72EPU operates as eighteen TMS626812DGE devices connected as shown in the TM4SR72EPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM2SR72EPU ( SIDE VIEW )
TM4SR72EPU ( SIDE VIEW ) A[0:10] A[0:8] A11/BA0 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S[0:3] SA[0:2] SCL SDA VDD VSS WE
PIN NOMENCLATURE Row-Address Inputs Column-Address Inputs Bank-Select Zero Column-Address Strobe Data In / Data Out Clock Enable System Clock Data In / Data Out Data-In / Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
1
10 11
40
41
84
2
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NO. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN DQMB1 DQMB0 NAME DQ15 VDD DQ14 DQ13 DQ12 DQ10 DQ11 VDD VDD VDD WE VDD DQ4 VSS DQ9 DQ8 DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VSS DQ0 VSS A0 VSS NC CK0 CB1 CB0 A10 NC NC NC A8 A6 A4 A2 S0 NO. 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIN NAME DQMB3 DQMB2
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Pin Assignments
DQ31
DQ30
DQ29
VDD DQ28
DQ27
DQ26
DQ25
VSS DQ24
DQ23
DQ22
VSS DQ21
CKE1
VDD DQ20
DQ19
DQ18
DQ17
VSS DQ16
VDD
VDD NC
SDA
VSS CK2
VSS NC
SCL
CB3
CB2
NC
NC
NC
NC
NC
NC
S2
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NO. 126 125 124 123 122 121 120 109 108 107 106 105 104 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PIN NAME A11/BA0 DQMB5 DQMB4 DQ47 VDD DQ46 DQ45 DQ44 DQ43 DQ42 VSS DQ41 DQ40 DQ39 DQ38 DQ37 VDD DQ36 DQ35 DQ34 DQ33 VSS DQ32 VDD CK1 VDD CAS RAS VSS A1 VSS NC CB5 CB4 NC NC NC A9 A7 A5 A3 S1 NO. 168 167 166 165 164 163 162 161 160 159 158 157 156AAAAAA DQ59 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 VSS 139AAAAAA DQ48 138 137 136 135 134 133 132 131 130AAAAAA DQMB6 129 128 127 PIN NAME DQMB7 DQ63 DQ62 DQ61 VDD DQ60 DQ58 DQ57 VSS DQ56 DQ55 DQ54 VSS DQ53 VDD DQ52 DQ51 DQ50 DQ49 VSS CKE0 VDD VDD NC VSS CK3 CB7 CB6 SA2 SA1 SA0 NC NC NC NC NC NC S3
TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2SR72EPU
S0 CS DQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 DQMB4 R DQ[32:39] 8 CS DQM DQ[0:7] U4 CK1 CK0 RB U0, U4 RB U1, U5, U8 RC U2, U6 RC U3, U7 CS DQMB1 R DQ[8:15] 8 DQM DQ[0:7] U1 DQMB5 R DQ[40:47] 8 CS CK2 DQM DQ[0:7] CK3 CS DQMB1 R CB[0:7] 8 DQM DQ[0:7] U8 R = 10 RB = 5 RC = 10 C = 10 pF C U5 RC C RC
S2 CS DQMB2 R DQ[16:23] 8 DQM DQ[0:7] U2 DQMB6 R DQ[48:55] 8 CS DQM DQ[0:7] U6
VDD
U[0:8] Two 0.1 F (minimum) per SDRAM
VSS
U[0:8]
CS DQMB3 R DQ[24:31] RAS CAS WE CKE0 A[0:11] 8 DQM DQ[0:7] U3 DQMB7 R DQ[56:63] 8
CS DQM DQ[0:7] U7
RAS: SDRAM U[0:8] CAS: SDRAM U[0:8] WE: SDRAM U[0:8] CKE: SDRAM U[0:8] A[0:11]: SDRAM U[0:8] SCL
SPD EEPROM SDA A0 SA0 A1 SA1 A2 SA2
LEGEND: CS = Chip Select SPD = Serial Presence Detect
4
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
functional block diagram for the TM4SR72EPU
S1 S0 CS CS CS CS VSS U0 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] UB0 DQM DQ[0:7] DQMB4 R DQ[32:39] 8 U4 DQM DQ[0:7] UB4 DQM DQ[0:7] R = 10 RC = 10 RB = 5 RB CS CS CS CS CK: U0, U4 CK0 RB CK: U1, U5, U8 U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] UB1 DQM DQ[0:7] DQMB5 R DQ[40:47] 8 U5 DQM DQ[0:7] UB5 DQM DQ[0:7] RC CK: U2, U6 CS CS CK2 RC CK: U3, U7 RC U8 DQMB1 R CB[0:7] 8 DQM DQ[0:7] UB8 DQM DQ[0:7] VDD S3 S2 CS CS CS CS CKE1 CKE0 RAS U2 DQMB2 R DQ[16:23] 8 DQM DQ[0:7] UB2 DQM DQ[0:7] DQMB6 R DQ[48:55] 8 U6 DQM DQ[0:7] UB6 DQM WE DQ[0:7] A[0:11] CS CS CS CS A[0:11]: U[0:8], UB[0:8] WE: U[0:8], UB[0:8] CAS 10 K CKE: UB[0:8] CKE: U[0:8] RAS: U[0:8], UB[0:8] CAS: U[0:8], UB[0:8] CK3 RC CK: UB3, UB7 CK: UB2, UB6 CK1 RB CK: UB0, UB4 RB CK: UB1, UB5, UB8 VDD U[0:8], UB[0:8] Two 0.1 F (minimum) per SDRAM U[0:8], UB[0:8]
U3 DQMB3 R DQ[24:31] 8 DQM DQ[0:7]
UB3 DQM DQ[0:7] DQMB7 R DQ[56:63] 8
U7 DQM DQ[0:7]
UB7 DQM DQ[0:7]
SPD EEPROM SCL A0 A1 A2 SDA
SA0 SA1 SA2
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2SR72EPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W TM4SR72EPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
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MIN 3 2 2 0 NOM MAX 3.6 UNIT V V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH-SPD High-level input voltage VIL TA Ambient temperature VIL MIN = -1.5 V ac (pulse width High-level input voltage for SPD device Low-level input voltage VDD + 0.3 5.5 0.8 70 -0.3
recommended operating conditions
v 5 ns)
C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETERS TM2SR72EPU MIN TM4SR72EPU MIN MAX MAX UNIT pF pF pF pF pF pF pF pF
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Ci(CK) Ci(AC) Co Input capacitance, CK input 27 47 47 10 12 27 9 7 27 92 47 18 17 27 9 7 Input capacitance, address and control inputs: A0 - A11, RAS, CAS, WE Input capacitance, CKE input Output capacitance Ci(CKE) Ci(DQMBx) Ci(Sx) Ci/o(SDA) Input capacitance, DQMBx input Input capacitance, Sx input Input/output capacitor, SDA input Ci(SPD) Input capacitor, SA0, SA1, SA2, SCL inputs NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V. 6
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
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PARAMETER TEST CONDITIONS '2SR72EPU-12A MIN 2.4 '2SR72EPU-12 MIN MAX 2.4 MAX UNIT V V VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) IOH = - 2 mA IOL = 2 mA 0.4 0.4 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, Output disabled
TM2SR72EPU
"10 "10
"10 "10
A A
IO
Output current (leakage)
ICC1
Operating current
Burst length = 1, CAS latency = 2 tRC tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) CKE VIL MAX, tCK = 15 ns (see Note 5) CKE and CK VIL MAX, tCK = (see Note 6)
765 855 18 18
675 855
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC2P ICC2PS
Precharge standby current in g y power-down mode
18 18
ICC2NAAAAAAAAA VIH MIN, tCK = 15 ns (see Note 5) CKE Precharge standby current in CKE VIH MIN, CK VIL MAX, tCK = ICC2NS non-power-down mode (see Note 6) ICC3P ICC3PS ICC3N Active standby current y power-down mode in
270 18 72 72
270
18 72 72
CKE VIL MAX, tCK = 15 ns (see Note 5) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6)
CKE and CK VIL MAX, tCK = (see Note 6)
ICC3NS
Active standby current non-power-down mode
in
315 90
315
90
ICC4
Burst current
Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Note 7) tRC tRC MIN CAS latency = 2 CAS latency = 3
1170
990
1395 675 765
1395 630 765
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 18 18 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state only twice during tRC. 5. Control, DQ, and address inputs change state only once every 30 ns. 6. Control, DQ, and address inputs do not change (stable). 7. Control, DQ, and address inputs change only once every cycle.
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
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PARAMETER TEST CONDITIONS '4SR72EPU-12A MIN 2.4 '4SR72EPU-12 MIN MAX 2.4 MAX UNIT V V VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) IOH = - 2 mA IOL = 2 mA 0.4 0.4 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD + 0.3 V, Output disabled
TM4SR72EPU
"20 "20
"20 "20
A A
IO
Output current (leakage)
ICC1
Operating current
Burst length = 1, CAS latency = 2 tRC tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) CKE VIL MAX, tCK = 15 ns (see Note 5) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6) CKE and CK VIL MAX, tCK = (see Note 6)
783 875 36 36
683 873
mA mA mA mA mA mA mA mA
ICC2P ICC2PS ICC2N
Precharge standby current in g y power-down mode
36 36
ICC2NS ICC3P ICC3PS ICC3N
Precharge standby current in non-power-down mode Active standby current y power-down mode
540 36
540
36
in
CKE VIL MAX, tCK = 15 ns (see Note 5) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6)
144 144 630 180
144 144
CKE and CK VIL MAX, tCK = (see Note 6)
ICC3NS
Active standby current non-power-down mode
in
630AAA mA 180 mA mA mA mA mA
ICC4
Burst current
Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Note 7) tRC tRC MIN CAS latency = 2 CAS latency = 3
1188
1008 1413 648 783
1413 693 783
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 36 36 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state only twice during tRC. 5. Control, DQ, and address inputs change state only once every 30 ns. 6. Control, DQ, and address inputs do not change (stable). 7. Control, DQ, and address inputs change only once every cycle.
8
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
ac timing requirements
'xSR72EPU-12A MIN tAC2 tAC3 tCK2 tCK3 tLZ tHZ tRC tRCD tRP tRRD tRSA tRAS tWR nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 nWCD tOH tIH tCESP tCH tCL tIS tAPR tAPW tREF Access time, CK high to data out, CAS latency = 2 (see Note 8) Access time, CK high to data out, CAS latency = 3 (see Note 8) Cycle time, CK, CAS latency = 2 Cycle time, CK, CAS latency = 3 Delay time, CK high to DQ in low-impedance state (see Note 9) Delay time, CK high to DQ in high-impedance state (see Note 10) Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to DEAC or DCAB command Delay time, final data in of WRT operation to DEAC or DCAB command Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 Delay time, WRT command to first data in Hold time, CK high to data out Hold time, address, control, and data input Power-down/self-refresh exit time Pulse duration, CK high Pulse duration, CK low Setup time, address, control, and data input Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Refresh interval 60 0 3 1 10 4 4 3 90 30 30 24 24 60 15 1 0 1 1 0 2 0 2 2 3 0 0 3 1.5 10 4 4 3 tRP - (CL -1) tCK 60 64 64 0 1 100 000 15 12 3 10 108 30 36 24 24 72 20 1 0 1 1 0 2 0 2 2 3 0 0 1 100 000 MAX 9 9 18 12 3 10 'xSR72EPU-12 MIN MAX 10 9 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle cycle cycle cycle cycle cycle cycle cycle ns ns ns ns ns ns ns ns ms
tT Transition time (see Note 12) 1 5 1 5 ns All references are made to the rising transition of CKx, unless otherwise noted. -12A speed device is supported only at - 5% to + 10% VDD NOTES: 8. tAC is referenced from the rising transition of CK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CKx that is CAS latency - one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CKx that is CAS latency - one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL.
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
serial presence detect
The serial-presence-detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details.Tables in this section list the SPD contents as follows: Tables in this section list the SPD contents as follows: Table 1-TM2SR72EPU Table 2-TM4SR72EPU
Table 1. Serial Presence-Detect Data for the TM2SR72EPU
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency LVTTL tCK = 12 ns tAC = 9 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 TM2SR72EPU-12A ITEM 128 bytes 256 bytes SDRAM 11 9 1 bank 72 bits DATA 80h 08h 04h 0Bh 09h 01h 48h 00h 01h C0h 90h 02h 80h 08h 08h 01h 0Fh 02h 06h 01h 01h LVTTL tCK = 12 ns tAC = 9 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 TM2SR72EPU-12 ITEM 128 bytes 256 bytes SDRAM 11 9 1 bank 72 bits DATA 80h 08h 04h 0Bh 09h 01h 48h 00h 01h C0h 90h 02h 80h 08h 08h 01h 0Fh 02h 06h 01h 01h
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SMMS683A - JUNE 1997 - REVISED AUGUST 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2SR72EPU (Continued)
BYTE NO. 21 DESCRIPTION OF FUNCTION SDRAM module attributes TM2SR72EPU-12A ITEM Non-buffered/ Non-registered VDD tolerance = (+10%) / (- 5%). Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 9.0 ns N/A N/A tRP = 30 ns tRRD = 24 ns tRCD = 30 ns tRAS = 60 ns 16M Bytes Rev. 1 25 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA 00h TM2SR72EPU-12 ITEM Non-buffered/ Non-registered VDD tolerance = (+10%) , Burst read / write, precharge all, auto precharge tCK = 18 ns tAC = 10 ns N/A N/A tRP = 36 ns tRRD = 24 ns tRCD = 30 ns tRAS = 72 ns 16M Bytes Rev. 1 107 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA 00h
22
SDRAM device attributes: general
1Eh
0Eh
23 24 25 26 27 28 29 30 31 32 - 61 62 63 64 - 71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
F0h 90h 00h 00h 1Eh 18h 1Eh 3Ch 04h 01h 19h 9700...00h
30h A0h 00h 00h 24h 18h 1Eh 48h 04h 01h 6Bh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM4SR72EPU
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 12 ns tAC = 9 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%) / (- 5%). Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 9.0 ns N/A N/A tRP = 30 ns tRRD = 24 ns tRCD = 30 ns tRAS = 60 ns 16M Bytes TM4SR72EPU-12A ITEM 128 bytes 256 bytes SDRAM 11 9 2 banks 72 bits DATA 80h 08h 04h 0Bh 09h 02h 48h 00h 01h C0h 90h 02h 80h 08h 08h 01h 0Fh 02h 06h 01h 01h 00h LVTTL tCK = 12 ns tAC = 9 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%) , Burst read / write, precharge all, auto precharge tCK = 18 ns tAC = 10 ns N/A N/A tRP = 36 ns tRRD = 24 ns tRCD = 30 ns tRAS = 72 ns 16M Bytes TM4SR72EPU-12 ITEM 128 bytes 256 bytes SDRAM 11 9 2 banks 72 bits DATA 80h 08h 04h 0Bh 09h 02h 48h 00h 01h C0h 90h 02h 80h 08h 08h 01h 0Fh 02h 06h 01h 01h 00h
22
SDRAM device attributes: general
1Eh
0Eh
23 24 25 26 27 28 29 30 31
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module
F0h 90h 00h 00h 1Eh 18h 1Eh 3Ch 04h
30h A0h 00h 00h 24h 18h 1Eh 48h 04h
12
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SMMS683A - JUNE 1997 - REVISED AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM4SR72EPU (Continued)
BYTE NO. 32 - 61 62 63 64 - 71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 167-255 DESCRIPTION OF FUNCTION Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open Rev. 1 26 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 1Ah 9700...00h Rev. 1 108 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 6Ch 9700...00h TM4SR72EPU-12A ITEM DATA TM4SR72EPU-12 ITEM DATA
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM2SR72EPU 2097152 BY 72-BIT TM4SR72EPU 4194304 BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A - JUNE 1997 - REVISED AUGUST 1997
device symbolization (TM2SR72EPU)
TM2SR72EPU Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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MECHANICAL DATA
BU (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP 0.125 (3,18) 0.118 (3,00) DIA 2 Places
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.255 (31,88) 1.245 (31,62) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088183/A 06/97
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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Copyright (c) 1998, Texas Instruments Incorporated

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