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TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
D D D D D D D D D D D D D D D D
Organization . . . 512K x 16 x 2 Banks 3.3-V Power Supply ( 10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) High Bandwidth - Up to 83-MHz Data Rates CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry Burst Sequence Programmable to Serial or Interleave Burst Length Programmable to 1, 2, 4, 8, or Full Page Chip Select and Clock Enable for Enhanced-System Interfacing Cycle-by-Cycle DQ-Bus Mask Capability With Upper and Lower Byte Control Auto-Refresh and Self-Refresh Capability 4K Refresh (Total for Both Banks) High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface Power-Down Mode Compatible With JEDEC Standards Pipeline Architecture Temperature Ranges: Operating, 0C to 70C Storage, - 55C to 150C
DGE PACKAGE ( TOP VIEW )
VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQML W CAS RAS CS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSS DQ15 DQ14 VSSQ DQ13 DQ12 VCCQ DQ11 DQ10 VSSQ DQ9 DQ8 VCCQ NC DQMU CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
SYNCHRONOUS CLOCK CYLE TIME tCK3 (CL = 3) '626162-12A '626162-12
ACCESS TIME CLOCK TO OUTPUT tAC3 (CL = 3) 9 ns 9 ns tAC2 (CL = 2) 9 ns 10 ns
REFRESH INTERVAL tREF 64 ms 64 ms
PIN NOMENCLATURE A0-A10 Address Inputs A0-A10 Row Addresses A0-A7 Column Addresses A10 Automatic-Precharge Select Bank Select Column-Address Strobe Clock Enable System Clock Chip Select SDRAM Data Input/Output Data/Output Mask Enables No Connect Row-Address Strobe Power Supply (3.3-V Typ) Power Supply for Output Drivers (3.3-V Typ) Ground Ground for Output Drivers Write Enable
tCK2 (CL = 2) 15 ns 18 ns
12 ns 12 ns
CL = CAS latency
-12A speed device is supported only at -5/+10% VCC
description
The TMS626162 device is a high-speed 16 777 216-bit synchronous dynamic randomaccess memory (SDRAM) organized as two banks of 524 288 words with 16 bits per word. All inputs and outputs of the TMS626162 series are compatible with the LVTTL interface.
A11 CAS CKE CLK CS DQ0-DQ15 DQML, DQMU NC RAS VCC VCCQ VSS VSSQ W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches. The TMS626162 SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK CKE CS DQMx RAS CAS W A0 - A11
AND
Array Bank T
Control
DQ Buffer
16
DQ0 - DQ15
Array Bank B 12
Mode Register
operation
All inputs to the '626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs, DQ0- DQ15, also are referenced to the rising edge of CLK. The '626162 has two banks that are accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh both banks alternately. Five basic commands or functions control most operations of the '626162:
D D D D D D
Bank activate/row-address entry Column-address entry/write operation Column-address entry/read operation Bank deactivate Auto-refresh Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or gate) the CLK input. The device contains a mode register that must be programmed for proper operation. Table 1 through Table 3 show the various operations that are available on the '626162. These truth tables identify the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that explains the abbreviated symbols. An access operation refers to any read or write command in progress at cycle n. Access operations include the cycle upon which the read or write command is entered and all subsequent cycles through the completion of the access burst.
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operation (continued)
Table 1. Basic Command Truth Table
COMMAND STATE OF BANK(S) T = deac B = deac X X SB = deac SB = actv SB = actv SB = actv SB = actv SB = actv X X T = deac B = deac CS RAS CAS W A11 A10 A9 - A0 A9 = V A8 - A7 = 0 A6 - A0 = V X X V V V V V X X X X MNEMONIC
Mode register set Bank deactivate (precharge) Deactivate all banks Bank activate/row-address entry Column-address entry / write operation Column-address entry / write operation with auto-deactivate Column-address entry/read operation Column-address entry/read operation with auto-deactivate Burst stop No operation Control-input inhibit / no operation Auto refresh
L L L L L L L L L L H L
L L L L H H H H H H X L
L H H H L L L L H H X L
L L L H L L H H L H X H
X BS X BS BS BS BS BS X X X X
X L H V L H L H X X X X
MRS DEAC DCAB ACTV WRT WRT-P READ READ-P STOP NOOP DESL REFR
For execution of these commands on cycle n: - CKE (n-1) must be high, or - tCESP must be satisfied for power-down exit, or - tCESP and tRC must be satisfied for self-refresh exit, or - tCES and nCLE must be satisfied for clock-suspend exit. DQMx(n) is a don't care. All other unlisted commands are considered vendor-reserved commands or illegal commands. Auto-refresh or self-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry. Legend: n = CLK cycle number L = Logic low H = Logic high X = Don't care, either logic low or logic high V = Valid T = Bank T B = Bank B actv = Activated deac = Deactivated BS = Logic high to select bank T; logic low to select bank B SB = Bank selected by A11 at cycle n
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operation (continued)
Table 2. Clock Enable (CKE) Command Truth Table
COMMAND Self-refresh entry Power-down entry on cycle (n + 1) Self-refresh Self refresh exit Power-down exit# CLK suspend on cycle (n + 1) CLK suspend exit on cycle (n + 1) STATE OF BANK(S) T = deac B = deac T = no access operation B = no access operation T = self refresh B = self refresh T = power down B = power down T = access operation B = access operation T = access operation B = access operation CKE (n - 1) H H L L L H L CKE (n) L L H H H L H CS (n) L X L H X X X RAS (n) L X H X X X X CAS (n) L X H X X X X W (n) H X H X X X X MNEMONIC SLFR PDE -- -- -- HOLD --
For execution of these commands, A0 - A11 (n) and DQMx (n) are don't cares. All other unlisted commands are considered vendor-reserved commands or illegal commands. On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode. A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. # If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise, either DESL or NOOP command must be applied before any other command. Legend: n = CLK cycle number L = Logic low H = Logic high X = Don't care, either logic low or logic high T = Bank T B = Bank B deac = Deactivated
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operation (continued)
Table 3. Data-Mask (DQM) Command Truth Table
COMMAND STATE OF BANK(S) T = deac and B = deac T = actv and B = actv ( no access operation ) T = write or B = write T = write or B = write T = read or B = read T = read or B = read DQML DQMU (n) X DATA IN (n) DATA OUT (n + 2) MNEMONIC
--
N/A
Hi-Z
--
--
X
N/A
Hi-Z
--
Data-in enable
L
V
N/A
ENBL
Data-in mask
H
M
N/A
MASK
Data-out enable
L
N/A
V
ENBL
Data-out mask
H
N/A
Hi-Z
MASK
For execution of these commands on cycle n: - CKE (n) must be high, or - tCESP must be satisfied for power-down exit, or - tCESP and tRC must be satisfied for self-refresh exit, or - tCES and nCLE must be satisfied for clock suspend exit. CS(n), RAS(n), CAS(n), W(n), and A0 - A11 are don't cares. All other unlisted commands are considered vendor-reserved commands or illegal commands. DQML controls D 0 - D 7 and Q 0 - Q 7. DQMU controls D 8 - D 15 and Q 8 - Q15. A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. Legend: n = CLK cycle number L = Logic low H = Logic high X = Don't care, either logic low or logic high V = Valid M = Masked input data N/A = Not applicable T = Bank T B = Bank B actv = Activated deac = Deactivated write = Activated and accepting data inputs on cycle n read = Activated and delivering data outputs on cycle (n + 2)
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burst sequence
All data for the '626162 is written or read in a burst fashion, that is, a single starting address is entered into the device and then the '626162 internally accesses a sequence of locations based on that starting address. After the first access some of the subsequent accesses can be at preceding as well as succeeding column addresses, depending on the starting address entered. This sequence can be programmed to follow either a serial burst or an interleave burst (see Table 4 through Table 6). The length of the burst can be programmed to be 1, 2, 4, 8, or full-page ( 256 ) accesses (see the section on setting the mode register, page 9). After a read burst is complete (as determined by the programmed-burst length), the outputs are in the high-impedance state until the next read access is initiated. Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0 DECIMAL START Serial Interleave 0 1 0 1 2ND 1 0 1 0 0 1 0 1 BINARY START 2ND 1 0 1 0
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1 - A0 DECIMAL START 0 Serial 1 2 3 0 Interleave 1 2 3 2ND 1 2 3 0 1 0 3 2 3RD 2 3 0 1 2 3 0 1 4TH 3 0 1 2 3 2 1 0 START 00 01 10 11 00 01 10 11 BINARY 2ND 01 10 11 00 01 00 11 10 3RD 10 11 00 01 10 11 00 01 4TH 11 00 01 10 11 10 01 00
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burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2 - A0 DECIMAL START 0 1 2 Serial 3 4 5 6 7 0 1 2 Interleave 3 4 5 6 7 2ND 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 3RD 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 4TH 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 5TH 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 6TH 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 7TH 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8TH 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 START 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 2ND 001 010 011 100 101 110 111 000 001 000 011 010 101 100 111 110 3RD 010 011 100 101 110 111 000 001 010 011 000 001 110 111 100 101 BINARY 4TH 011 100 101 110 111 000 001 010 011 010 001 000 111 110 101 100 5TH 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 6TH 101 110 111 000 001 010 011 100 101 100 111 110 001 000 011 010 7TH 110 111 000 001 010 011 100 101 110 111 100 101 010 011 000 001 8TH 111 000 001 010 011 100 101 110 111 110 101 100 011 010 001 000
latency
The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read command (see the section on setting the mode register, page 9). This feature allows adjustment of the device so that it operates using the capability to latch the data output. The delay between the READ command and the beginning of the output burst is known as CAS latency. After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is restricted, based on the maximum frequency rating of the '626162. There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by the mode-register contents.
two-bank operation
The '626162 contains two independent banks that can be accessed individually or in an interleaved fashion. Each bank must be activated with a row address before it can be accessed. Each bank then must be deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry command (ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank (DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the section on bank deactivation, page 8).
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two-bank row-access operation The two-bank feature allows access of information on random rows at a higher rate of operation than is possible with a standard DRAM, by activating one bank with a row address and, while the data stream is being accessed to/from that bank, activating the second bank with another row address. When the data stream to or from the first bank is complete, the data stream to or from the second bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 28 is an example of two-bank row-interleaving read bursts with automatic deactivate for a CAS latency of three and burst length of eight. two-bank column-access operation The availability of two banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 29 is an example of two-bank column-interleaving read bursts for a CAS latency of three and burst length of two.
bank deactivation (precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A11 used to select the bank to be precharged as shown in Table 1. A bank can be deactivated automatically by using A10 during a read or write command. If A10 is held high during the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank remains active following the burst. The read and write commands with automatic deactivation are signified as READ-P and WRT-P.
chip select (CS)
CS can be used to select or deselect the '626162 for command entry, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use of CS does not affect an access burst that is in progress; the DESL command can only restrict RAS, CAS, and W input to the '626162.
data mask
The mask command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. DQML controls DQ0 - DQ7, and DQMU controls DQ8 - DQ15. The application of DQMx to a write burst has no latency (nDID = 0 cycle), but the application of DQMx to a read burst has a latency of nDOD = 2 cycles. During a write burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst, if DQMx is held high on the rising edge of CLK and nDOD cycles after that rising edge of CLK, the data-output is in the high-impedance state. Figure 18 and Figure 32 through Figure 35 show examples of data-mask operation.
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CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution of a READ (READ-P) or WRT (WRT-P) operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known as a CLK-suspend operation, and its execution indicates a HOLD command. The device resumes operation from the point when it was placed in suspension, beginning with the second rising edge of CLK after CKE returns high. If CKE is brought low when no read or write command is in progress, the device enters power-down mode. If both banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum. Power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. After power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that data in the device remains valid during the power-down mode, the self-refresh command ( SLFR) must be executed concurrently with the power-down entry ( PDE) command. When exiting power-down mode, new commands can be entered on the first CLK edge after CKE returns high, provided that the setup time (tCESP) is satisfied. Table 2 shows the command configuration for a CLK-suspend/power-down operation. Figure 19, Figure 20, and Figure 38 show examples of the procedure.
setting the mode register
The '626162 contains a mode register that must be programmed with the CAS latency, the burst type, and the burst length. This is accomplished by executing a mode-register set (MRS) command with the information entered on the address lines A0 - A9. A logic 0 must be entered on A7 and A8, but A10 and A11 are don't-care entries for the '626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined by A0 - A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow the mode register to be changed. If the addresses are not valid, the previous contents of the mode register remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input mode word valid on A0 - A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both banks are deactivated.
A11 A10 A9 A8 0 A7 0 0 = Serial 1 = Interleave (burst type) A6 A5 A4 A3 A2 A1 A0
Reserved
REGISTER BIT A9
Write Burst Length L th
REGISTER BITS A6 A5 A4
CAS latency lt
REGISTER BITS A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1
BURST LENGTH 1 2 4 8 256
0 1
A2 - A0 1
0 0
1 1
0 1
2 3
All other combinations are reserved. See timing requirements for minimum valid read latencies based on maximum frequency rating.
Figure 1. Mode-Register Programming
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refresh
The '626162 must be refreshed at intervals not exceeding tREF (see timing requirements) or data cannot be retained. Refresh can be accomplished by performing a read or write access to every row in both banks, 4 096 auto-refresh (REFR) commands, or by placing the device in self-refresh mode. Regardless of the method used, refresh must be accomplished before tREF has expired. auto refresh (REFR) Before performing a REFR, both banks must be deactivated (placed in precharge). To enter a REFR command, RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The refresh address is generated internally such that, after 4 096 REFR commands, both banks of the '626162 have been refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command automatically deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not necessarily have to be consecutive, but all 4 096 must be completed before tREF expires. self refresh (SLFR) To enter self refresh, both banks of the '626162 must be deactivated and then a self-refresh (SLFR) command must be executed (see Table 2). The SLFR command is identical to the REFR command, except that CKE is low. For proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK that RAS and CAS are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, all refreshing signals are generated internally for both banks with all external signals (except CKE) being ignored. Data is retained by the device automatically for an indefinite period when power is maintained, and power consumption is reduced to a minimum. To exit self-refresh mode, CKE must be brought high. New commands are issued after tRC has expired. If CLK is made inactive during self refresh, it must be returned to an active and stable condition before CKE is brought high to exit self refresh (see Figure 21). Upon exiting self refresh, the device must begin the normal-refresh scheme immediately. If the burst-refresh scheme is used, then 4 096 REFR commands must be executed before continuing with normal device operations. If a distributed-refresh scheme utilizing auto refresh is used (for example, two rows every 32 s), the first set of refreshes must be performed before continuing with normal device operation. This ensures that the SDRAM is fully refreshed.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7 and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only if it is issued to the same bank as the preceding READ or WRT command. The interruption of READ-P or WRT-P operations is not supported.
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interrupted bursts (continued)
Table 7. Read-Burst Interruption
INTERRUPTING COMMAND READ, READ-P EFFECT OR NOTE ON USE DURING READ BURST Current output cycles continue until the programmed latency from the superseding-READ (READ-P) command is met and new output cycles begin (see Figure 2). The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQMx must be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD-1), nCCD, and (nCCD+1), assuming that there is any output on these cycles (see Figure 3). The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes, whichever occurs first (see Figure 4). The DQ bus is in the high-impedance state when nBSD cycles are satisfied or when the read burst completes, whichever occurs first. The bank remains active. A new read or write command cannot be entered for at least two cycles after the STOP command (see Figure 5).
WRT, WRT-P
DEAC, DCAB
STOP
nCCD = One Cycle CLK READ Command at Column Address C0 Interrupting READ Command at Column Address C1 DQ C0 C1 C1 + 1 C1 + 2 Output Burst for the Interrupting READ Command Begins Here
a) INTERRUPTED ON ODD CYCLES
nCCD = Two Cycles CLK READ Command at Column Address C0 Interrupting READ Command at Column Address C1 Output Burst for the Interrupting READ Command Begins Here
DQ
C0
C0 + 1
C1
C1 + 1
b) INTERRUPTED ON EVEN CYCLES NOTE A: For these examples, assume CAS latency = 3, and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
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interrupted bursts (continued)
nCCD = Five Cycles CLK READ Command Interrupting WRT Command
DQ
Q
D
D
DQMx
See Note B
NOTES: A. For the purposes of this example, assume CAS latency = 3, and burst length = 4. B. DQMx must be high to mask output of the read burst on cycles (nCCD - 1), nCCD, and (nCDD + 1).
Figure 3. Read Burst Interrupted by Write Command
nCCD = Two Cycles
nHZP
CLK Interrupting DEAC/DCAB Command
READ Command
DQ
Q
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
nCCD = Two Cycles
nBSD
CLK
READ Command
Interrupting STOP Command Q
NEW Command
DQ NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 5. Read Burst Interrupt by STOP Command
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interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING COMMAND READ, READ-P WRT, WRT-P DEAC, DCAB EFFECT OR NOTE ON USE DURING WRITE BURST Data in on previous cycle is written. No further data in is accepted (see Figure 6). The new WRT (WRT-P) command and data in immediately supersede the write burst in progress (see Figure 7). The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to mask the DQ bus so that an interrupt does not violate the write-recovery specification (tWR ) (see Figure 8). The data on the input pins at the time of the burst-STOP command is not written; no further data is accepted. The bank remains active. A new read or write command cannot be entered for at least nBSD cycles after the STOP command (see Figure 9).
STOP
nCCD = One Cycle CLK WRT Command READ Command
DQ
D a) INTERRUPTED ON ODD CYCLES nCCD = Two Cycles
Q
Q
Q
CLK WRT Command READ Command
DQ
D
D b) INTERRUPTED ON EVEN CYCLES
Q
Q
NOTE A: For these examples, assume CAS latency = 3, burst length = 4.
Figure 6. Write Burst Interrupted by Read Command
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interrupted bursts (continued)
nCCD = Two Cycles
CLK WRT Command at Column Address C0 DQ C0 Interrupting WRT Command at Column Address C1 C0 + 1 C1 C1 + 1 C1 + 2 C1 + 3
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by Write Command
nCCD = Three Cycles CLK WRT Command Interrupting DEAC or DCAB Command D Ignored tWR DQMx Ignored
DQ
D
NOTE A: For this example, assume burst length = 4.
Figure 8. Write Burst Interrupted by DEAC/DCAB Command
nCCD = Two Cycles nBSD CLK WRT Command Interrupting STOP Command New Command
DQ
D
D
Ignored
Ignored
NOTE A: For this example, assume burst length = 4.
Figure 9. Write Burst Interrupted by STOP Command
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SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
power up
Device initialization should be performed after a power up to the full VCC level. After power is established, a 200-s interval is required (with no inputs other than CLK). After this interval, both banks of the device must be deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the device initialization.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VCCQ VSS VSSQ VIH VIL Supply voltage Supply voltage for output drivers Supply voltage Supply voltage for output drivers High-level input voltage Low-level input voltage (see Note 2) 2 - 0.3 0 3 3 NOM 3.3 3.3 0 0 VCC + 0.3 0.8 70 MAX 3.6 3.6 UNIT V V V V V V C
TA Operating free-air temperature NOTE 2: VIL MIN = 1.5 V ac (pulsewidth
v 5 ns)
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TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Note 3)
PARAMETER VOH VOL II IO ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Operating current Precharge standby current in power-down g y mode Precharge standby current in g y non-power-down mode Precharge standby current in power-down g y mode Precharge standby current in g y non-power-down mode Burst current Auto-refresh Auto refresh current IOH = - 2 mA IOL = 2 mA 0 V VI VCC + 0.3 V, 0 V VO VCC + 0.3 V, All other pins = 0 V to VCC Output disabled CAS latency = 2 CAS latency = 3 TEST CONDITIONS '626162-12A MIN 2.4 0.4 10 10 85 105 2 2 30 2 8 8 35 10 140 170 75 85 2 MAX '626162-12 MIN 2.4 0.4 10 10 80 105 2 2 30 2 8 8 35 10 130 170 70 85 2 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA A
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Burst length = 1, tRC g , tRC MIN IOH/IOL = 0 mA, one bank activated (see Note 4) CKE CKE CKE VIL MAX, tCK = 15 ns (see Note 5) CKE & CLK VIL MAX, tCK = (see Note 6)
w
v
w VIH MIN, tCK = 15 ns (see Note 5)
v
v VIL MAX, tCK = 15 ns (see Note 5) CKE & CLK v VIL MAX, tCK = (see Note 6) CKE w VIH MIN, tCK = 15 ns (see Note 5) CKE w VIH MIN, CLK v VIL MAX tCK = (see Note 6)
Page burst, IOH/IOL = 0 mA g , All banks activated, nCCD = one cycle (see Note 7) CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3
ICC6 Self-refresh current -12A-speed device is supported only at -5/+10% VCC. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state only twice during tRC. 5. Control, DQ, and address inputs change state only once every 30 ns. 6. Control, DQ, and address inputs do not change (stable). 7. Control, DQ, and address inputs change state only once every cycle.
w tRC MIN CKE v VIL MAX
tRC
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 8)
MIN Ci(S) Ci(AC) Ci(E) Co Input capacitance, CLK input Input capacitance, address and control inputs: A0 - A11, CS, DQMx, RAS, CAS, W Input capacitance, CKE input Output capacitance MAX 5 5 5 8 UNIT pF pF pF pF
NOTE 8: VCC = 3.3 0.3 V and bias on pins under test is 0 V.
ac timing requirements over recommended ranges of supply voltage and operating free-air temperature
'626162-12A PARAMETER tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tWR Cycle time, CLK Cycle time, CLK Pulse duration, CLK high Pulse duration, CLK low Access time, CLK high to data out (see Note 9) Access time, CLK high to data out (see Note 9) Hold time, CLK high to data out Delay time, CLK high to DQ in low-impedance state (see Note 10) Delay time, CLK high to DQ in high-impedance state (see Note 11) Setup time, address, control, and data input Hold time, address, control, and data input Power down/self-refresh exit time (see Note 12) Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 13) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one banki to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Delay time, final data in of WRT operation to DEAC or DCAB command 60 15 3 1 10 60 90 30 30 24 24 100000 CAS latency = 2 CAS latency = 3 3 3 10 3 1.5 10 72 108 30 36 24 24 tRP - (CL -1) * tCK 60 20 100000 CAS latency = 2 CAS latency = 3 MIN 15 12 4 4 9 9 3 3 10 MAX '626162-12 MIN 18 12 4 4 10 9 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tT Transition time 1 5 1 5 ns See Parameter Measurement Information for load circuits. All references are made to the rising transition of CLK, unless otherwise noted. -12A-speed device is supported only at - 5 / + 10% VCC . NOTES: 9. tAC is referenced from the rising transition of CLK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CLK that is CAS latency - one cycle after the READ command. An access time is measured at output reference level 1.4 V. 10. tLZ is measured from the rising transition of CLK that is CAS latency - one cycle after the READ command. 11. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 12. See Figure 20 and Figure 21. 13. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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ac timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'626162-12A PARAMETER tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 CAS latency = 3 0 1 0 1 1 0 2 0 2 2 3 0 1 0 0 1 MIN MAX 64 1 0 1 1 0 2 0 2 2 3 0 1 0 1 '626162-12 MIN MAX 64 UNIT ms cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
nWCD Delay time, WRT command to first data in nBSD Delay time, STOP command to READ or WRT command See Parameter Measurement Information for load circuits. All references are made to the rising transition of CLK, unless otherwise noted. -12A-speed device is supported only at - 5 / + 10% VCC .
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SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level should be changed to VIH MIN and VIL MAX instead of the midpoint level. All specifications referring to READ commands are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
1.4 V ZO = 50 Output Under Test CL = 50 pF RL = 50
Figure 10. LVTTL-Load Circuit
tCK tCH
CLK tT tCL tiS tT tiH DQ, A0 - A11, CS, RAS, CAS, W, DQMx, CKE tT tiH tiS, tCESP DQ, A0 - A11, CS, RAS, CAS, W, DQMx, CKE tT
Figure 11. Input-Attribute Parameters
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PARAMETER MEASUREMENT INFORMATION
CAS latency
CLK ACTV Command READ Command tAC tLZ tHZ tOH
DQ
Figure 12. Output Parameters
READ, WRT DESL ACTV ACTV, REFR, SELF-REFRESH EXIT ACTV DEAC, DCAB ACTV MRS
nCCD nCDD tRAS tRC tRCD tRP tRRD tRSA
READ, READ-P, WRT, WRT-P, DEAC, DCAB Command Disable DEAC, DCAB ACTV, MRS, REFR, SLFR READ, READ-P, WRT, WRT-P ACTV, MRS, REFR, SLFR ACTV (different bank) ACTV, MRS
Figure 13. Command-to-Command Parameters
nHZP
CLK DEAC or DCAB Command Q Q
READ Command DQ
tHZ Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 14. Read Followed by Deactivate
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PARAMETER MEASUREMENT INFORMATION
tAPR CLK ACTV, MRS, REFR, or SLFR Command
READ-P Command DQ
Final Data Out
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 15. Read With Auto-Deactivate
nCWL tWR CLK DEAC or DCAB Command
WRT Command DQ D
WRT Command D
NOTE A: For this example, assume burst length = 1.
Figure 16. Write Followed By Deactivate
nCWL tAPW CLK ACTV, MRS, REFR, or SLFR Command
WRT Command DQ D
WRT-P Command D
Figure 17. Write With Auto-Deactivate
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PARAMETER MEASUREMENT INFORMATION
nDOD nDOD CLK WRT Command
tRWL
READ Command DQ Q
DEAC or DCAB Command Ignored Ignored Ignored
D
ENBL Command DQMx
MASK Command
MASK Command
MASK Command
ENBL Command
MASK Command
MASK Command
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 18. DQ Masking
nCLE CLK nCLE
DQ
DQ
DQ
DQ
DQ
tiS tiS tiH tiH CKE
Figure 19. CLK-Suspend Operation
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PARAMETER MEASUREMENT INFORMATION
CLK Last Data-In WRT (WRT-P) Operation CLK Is Don't Care, But Must Be Stable Before CKE High
Exit Power-Down Mode If tCESP Is Satisfied (New Command)
Last Data-Out READ (READ-P) Operation CKE tiH tiS
Enter Power-Down Mode
tCESP
CLK DESL or NOOP Command Only If tCESP Is Not Satisfied
Last Data-In WRT (WRT-P) Operation CLK Is Don't Care, But Must Be Stable Before CKE High
Last Data-Out READ (READ-P) Operation CKE tiH tiS
Enter Power-Down Mode
Exit Power-Down Mode (New Command)
tCESP
Figure 20. Power-Down Operation
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PARAMETER MEASUREMENT INFORMATION
CLK Exit SLFR if tCESP Is Satisfied DESL or NOOP Command Only Until tRC Is Satisfied
SLFR Command Both Banks Deactivated
CLK Is Don't Care, But Must Be Stable Before CKE high
ACTV, MRS, or REFR Command
CKE tiH tiS tCESP
tRC
CLK
SLFR Command Both Banks Deactivated
CLK is Don't Care, But Must Be Stable Before CKE High
tCESP NotYet Satisfied
Exit SLFR
ACTV, MRS, or REFR Command DESL or NOOP Only Until tRC Is Satisfied tRC
CKE tiH tiS tCESP
Figure 21. Self-Refresh Operation
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ACTV T CLK
READ T
DEAC T
DQ
a
b
c
d
DQMx
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
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W
A10
R0
A11
A0 - A9
R0
C0
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
CS
CKE
BURST TYPE (D/Q) Q
BANK (B/ T ) T
ROW ADDR R0 a C0
BURST CYCLE b C0 + 1 c C0 + 2 d C0 + 3
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 22. Read Burst (CAS latency = 3, burst length = 4)
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ACTV T CLK
WRT T
DEAC T
26 DQ DQMx RAS CAS
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a
b
c
d
e
f
g
h
PARAMETER MEASUREMENT INFORMATION
W
A10
R0
A11
A0 - A9
R0
C0
CS
CKE
BURST TYPE (D/Q) D
BANK (B/ T ) T
ROW ADDR R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD and tWR for the '626162-12 at 83 MHz.
Figure 23. Write Burst (burst length = 8)
ACTV B CLK
WRT B
READ B
DEAC B
DQ
a
b
c
d
DQMx
RAS
PARAMETER MEASUREMENT INFORMATION
CAS
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W
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
A10
R0
A11
A0 - A9
R0
C0
C1
CS
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
CKE
BURST TYPE (D/Q) D Q
BANK (B/ T ) B B
ROW ADDR R0 R0 a C0
BURST CYCLE b C0 + 1 c d
C1 C1 + 1 Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 24. Write-Read Burst (CAS latency = 3, burst length = 2)
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28 CLK DQ DQMx RAS CAS W A10 A11 A0 - A9 CS CKE
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ACTV T
READ T
WRT-P T
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
R0
PARAMETER MEASUREMENT INFORMATION
R0
C0
C1
BURST TYPE (D/Q) Q D
BANK (B/ T ) T T
ROW ADDR R0 R0 a C0 b C0 + 1 c C0 + 2 d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6
BURST CYCLE h C0 + 7 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7 i j k l m n o p
C1 C1 + 1 C1 + 2 Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 25. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV T CLK DQ DQMx RAS CAS W A10 A11 A0 - A9 CS CKE R0 R0
READ T
WRT-P T
a
b
c
d
e
f
g
h
i
PARAMETER MEASUREMENT INFORMATION
C0
C1
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BURST TYPE (D/Q) Q D
BANK (B/ T ) T T
ROW ADDR R0 R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7 i
C1 Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 26. Read Burst - Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
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30 CLK DQ0 - DQ15 DQMx RAS CAS W A10 A11 A0 - A9 CS CKE
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ACTV B
READ- P B
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+253 n+254 n+255
R0
PARAMETER MEASUREMENT INFORMATION
R0
C0
BURST TYPE (D/Q)
BANK (B/ T )
ROW ADDR b c d e f g h C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7 C0 a i
BURST CYCLE j k l m n o p q r s . 255 .
Q B R0 Column-address sequence depends on programmed burst type and starting column address C0. NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 27. Read Burst - Full Page (CAS latency = 3, burst length = 256)
ACTV T ACTV B CLK DQ DQMx RAS CAS W A10 A11 A0 - A9 CS CKE BURST TYPE (D/Q) Q Q Q
R0 C0 R1 R0 R1 a b c d
READ- P T ACTV B READ- P B
ACTV T
READ- P B
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
R2
R3
PARAMETER MEASUREMENT INFORMATION
C1
R2
C2
R3
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BANK (B/ T ) B T B
ROW ADDR R0 R1 R2 a C0 b c d e f g h i C1
BURST CYCLE j k l m n o p q r s . .
C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7 C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7 C2 C2 + 1 C2 + 2 . .
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 28. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (CAS latency = 3, burst length = 8)
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
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32 ACTV B CLK DQ DQMx RAS CAS
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ACTV T READ B
READ T READ B
READ T READ B
a
b
c
d
e
f
PARAMETER MEASUREMENT INFORMATION
W
A10
R0
R1
A11
A0 - A9
R0
R1
C0
C1
C2
C3
C4
CS
CKE
BURST TYPE (D/Q) Q Q Q .
BANK (B/ T ) B T B ...
ROW ADDR R0 R1 R0 ... a C0 b C0 + 1 C1 c
BURST CYCLE d C1 + 1 C2 C2 + 1 ... ... e f ... ...
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).
Figure 29. Two-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
ACTV T ACTV B CLK DQ DQMx RAS a b c d READ B DEAC B
WRT T
DEAC T
e
f
g
h
PARAMETER MEASUREMENT INFORMATION
CAS W A10 A11 A0 - A9 CS CKE R0 C0 R1 C1 R0 R1
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BURST TYPE (D/Q) Q D
BANK (B/ T ) B T
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
Column-address sequence depends on programmed burst type and starting column address C0 and C1. (Refer to Table 5.) NOTE A: This example illustrates minimum tRCD and tWR for the '626162-12 at 83 MHz.
Figure 30. Read-Burst Bank B, Write-Burst Bank T (CAS latency = 3, burst length = 4)
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TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV T ACTV B CLK DQ
WRT- P T READ- P B
34 DQMx RAS CAS
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a
b
c
d
e
f
g
PARAMETER MEASUREMENT INFORMATION
W
A10
R0
R1
A11
A0 - A9
R0
R1
C0
C1
CS
CKE BURST TYPE (D/Q) D Q BURST CYCLE a C0 b C0 + 1 c C0 + 2 d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
BANK (B/ T ) T B
ROW ADDR R0 R1
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum nCWL for the '626162-12 at 83 MHz.
Figure 31. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (CAS latency = 3, burst length = 4)
ACTV T CLK
READ T
WRT T
DCAB
a DQ DQMx RAS
b
c
d
e
f
g
h
PARAMETER MEASUREMENT INFORMATION
CAS W A10 A11 A0 - A9 CS CKE R0 C0 C1 R0
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TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
BURST TYPE (D/Q) Q D
BANK (B/ T ) T T
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '626162-12 at 83 MHz.
Figure 32. Data Mask (CAS latency = 3, burst length = 4)
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SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV B CLK DQ0 - DQ7
ACTV T
READ B
READ T
READ B
READ T
READ B
36 DQML DQ8 - DQ15 DQMU RAS
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
a
b
c
d
e
f
High Impedance
PARAMETER MEASUREMENT INFORMATION
CAS
W
A10
R0
R1
A11
A0 - A9 CS
R0
R1
C0
C1
C2
C3
C4
CKE BURST TYPE (D/Q) Q Q Q Q
BANK (B/ T ) T B T B
ROW ADDR R0 R1 R0 R1 a C0 b C0 + 1 C1 c
BURST CYCLE d C1+1 C2 C1+1 C3 C3+ 1 e f g h
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
Figure 33. Data Mask With Byte Control (CAS latency = 3, burst length = 2)
ACTV B CLK DQ0 - DQ7 DQML DQ8 - DQ15 DQMU RAS
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
ACTV T READ B
DEAC B
WRT T
DEAC T
e
f
g
h
a
b
c
d
PARAMETER MEASUREMENT INFORMATION
CAS W A10 A11 A0 - A9 CS CKE R0 C0 R1 C1 R0 R1
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
BURST TYPE (D/Q) Q D
BANK (B/ T ) T B
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD read burst, and a minimum tWR write burst for the '626162-12 at 83 MHz
Figure 34. Data Mask With Byte Control (CAS latency = 3, burst length = 4)
37
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
38 CLK DQ0 - DQ7 DQML DQ8 - DQ15 DQMU RAS CAS W A10 A11 A0 - A9 CS CKE
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ACTV T
READ T ACTV B WRT B DCAB
a
b
c
d
f
h
a
b
c
d
e
f
g
h
PARAMETER MEASUREMENT INFORMATION
R0
R1
R0
C0
R1
C1
BURST TYPE (D/Q) Q D
BANK (B/ T ) T B
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD and tWR for the '626162-12 at 83 MHz.
Figure 35. Data Mask With Cycle-by-Cycle Byte Control (CAS latency = 3, burst length = 4)
REFR CLK DQ DQMx RAS CAS
ACTV T
READ T
DEAC T
REFR
a
b
c
d
PARAMETER MEASUREMENT INFORMATION
W A10
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R0
A11 A0 - A9 CS CKE R0 C0
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
BURST TYPE (D/Q) Q
BANK (B/ T ) T
ROW ADDR R0 a C0
BURST CYCLE b C0 + 1 c C0 + 2 d C0 + 3
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTE A: This example illustrates minimuim tRC and tRCD for the '626162-12 at 83 MHz.
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
Figure 36. Refresh Cycles (CAS latency = 3, burst length = 4)
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SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
40 DCAB CLK MRS ACTV B WRT-P B DQ a b c d DQMx RAS
PARAMETER MEASUREMENT INFORMATION
CAS
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
W
A10 See Note B A11 See Note B A0 - A9 See Note B CS
R0
R0
C0
CKE BURST TYPE (D/Q) D BURST CYCLE a C0 b C0 + 1 c C0 + 2 d C0 + 3
BANK (B/ T ) B
ROW ADDR R0
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5). NOTES: A. This example illustrates minimum tRP, tRSA, and tRCD for the '626162-12 at 83 MHz. B. Refer to Figure 1.
Figure 37. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate) (CAS latency = 2, burst length = 4)
ACTV T
READ T HOLD
WRT-P T HOLD
PDE
CLK DQ0 DQMx RAS CAS a b c d e f g h
PARAMETER MEASUREMENT INFORMATION
W A10 A11 A0 - A9 CS CKE R0 C0 C1 R0
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
BURSTBANK TYPE (D/Q) Q D (B/ T ) T T
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 38. CLK Suspend (HOLD) During Read Burst and Write Burst (CAS latency = 3, burst length = 4)
41
TMS626162 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
device symbolization
TI TMS626162 DGE Package Code W B Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code -SS Speed Code (-12A, -12)
42
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS626162 524288-WORD BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E - FEBRUARY 1995 - REVISED APRIL 1997
MECHANICAL DATA
DGE (R-PDSO-G50)
0.018 (0,45) 0.012 (0,30) 26
PLASTIC SMALL-OUTLINE PACKAGE
0.031 (0,80) 50
0.006 (0,16) M
0.471 (11,96) 0.455 (11,56) 0.404 (10,26) 0.396 (10,06)
1 0.829 (21,05) 0.821 (20,85)
25 0.006 (0,15) NOM
Gage Plane 0.010 (0,25) 0- 5 0.024 (0,60) 0.016 (0,40)
Seating Plane 0.047 (1,20) MAX 0.000 (0,00) MIN 0.004 (0,10) 4040070-5 / C 12/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
43
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Copyright (c) 1998, Texas Instruments Incorporated

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