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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
D D D D D D D D D D
Organization: DRAM: 262 144 Words x 16 Bits SAM: 256 Words x 16 Bits Single 5.0-V Power Supply (10%) Dual-Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and Serial-Address-Memory (SAM) Ports Write-per-Bit Function for Selective Write to Each I/O of the DRAM Port Byte-Write Function for Selective Write to Lower Byte (DQ0 - DQ7) or Upper Byte (DQ8- DQ15) of the DRAM Port 4 - Column or 8 - Column Block - Write Function for Fast Area - Fill Operations Enhanced Page Mode for Faster Access With Extended-Data-Output (EDO) Option for Faster System Cycle Time CAS-Before-RAS (CBR) and Hidden Refresh Functions Long Refresh Period - Every 8 ms (Maximum) Full - Register- Transfer Function Transfers Data from the DRAM to the Serial Register
D D D D D D D D D
Split-Register-Transfer Function Transfers Data from the DRAM to One-Half of the Serial Register While the Other Half is Outputing Data to the SAM Port 256 Selectable Serial Register Starting Points Programmable Split-Register Stop Point Up to 55-MHz Uninterrupted Serial-Data Streams 3-State Serial Outputs for Easy Multiplexing of Video Data Streams All Inputs/Outputs and Clocks TTL Compatible Compatible With JEDEC Standards Designed to Work With the Texas Instruments (TITM) Graphics Family Fabricated Using TI's Enhanced Performance Implanted CMOS (EPICTM) Process
performance ranges
ACCESS TIME ROW ENABLE tRAC (MAX) - 60 Speed - 70 Speed 60 ns 70 ns ACCESS TIME SERIAL DATA tSCA (MIN) 15 ns 20 ns DRAM PAGE CYCLE TIME tPC (MIN) 35 ns 40 ns DRAM EDO CYCLE TIME tPC (MIN) 30 ns 30 ns SERIAL CYCLE TIME tSCC (MIN) 18 ns 22 ns OPERATING CURRENT SERIAL PORT STANDBY lCC1 (MAX) 180 mA 165 mA
Table 1. Device Option Table
DEVICE 55160 55161 55170 55171 POWER SUPPLY VOLTAGE 5.0 V 0.5 V 5.0 V 0.5 V 5.0 V 0.5 V 5.0 V 0.5 V BLOCK-WRITE CAPABILITY 4 -column 4 -column 8 - column 8 - column PAGE / EDO OPERATION Page EDO Page EDO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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SMVS464 - MARCH1996
DGH PACKAGE (TOP VIEW)
VCC TRG VSS SQ0 DQ0 SQ1 DQ1 VCC SQ2 DQ2 SQ3 DQ3 VSS SQ4 DQ4 SQ5 DQ5 VCC SQ6 DQ6 SQ7 DQ7 VSS CASL WE RAS A8 A7 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SC SE VSS SQ15 DQ15 SQ14 DQ14 VCC SQ13 DQ13 SQ12 DQ12 VSS SQ11 DQ11 SQ10 DQ10 VCC SQ9 DQ9 SQ8 DQ8 VSS DSF NC / GND CASU QSF A0 A1 A2 A3 VSS
PIN NOMENCLATURE A0 - A8 RAS CASL, CASU DSF TRG WE DQ0 - DQ15 SC SE SQ0 - SQ15 QSF VCC VSS NC/GND Address Inputs Row-Address Strobe Column-Address Strobe, Byte Select Special-Function Select Output Enable, Transfer Select Write Enable, Write Mask Select DRAM Data I / O Serial Clock Serial Enable Serial Data Output Special-Function Output Power Supply Ground No Connect / Ground (Important: not connected internally to VSS)
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description
The TMS551xx multiport video RAMs (VRAMs) are high-speed dual-ported memory devices. Each consists of a dynamic random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a serial-data register [serial-access memory (SAM)] organized as 256 words of 16 bits each. These devices support three basic types of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data from the DRAM to the SAM. Except during transfer operations, these devices can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The TMS551xx multiport VRAMs provide several functions designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports (see Table 2). On the DRAM port, greater pixel draw rates are achieved by the block-write function. The TMS5516x devices' 4-column block-write function allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations, up to a total of 64 bits of data per CASx cycle time. Similarly, the TMS5517x devices' 8-column block-write function allows 16 bits of data to be written to any combination of eight adjacent column-address locations, up to a total of 128 bits of data per CASx cycle time. Also on the DRAM port, the write-per-bit (or write-mask) function allows masking of any combination of the 16 DQs on any write cycle. The persistent write-per-bit function uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. All TMS551xx devices offer byte control. Byte control can be applied in write cycles, read cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The TMS551xx devices offer enhanced-page-mode operation that results in faster access time. The TMS551x1 devices also offer extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and the standard DRAM cycles. The TMS551xx devices offer a split-register-transfer (DRAM to SAM) function. This feature enables real-time register load implementation for continuous serial-data streams without critical timing requirements. The serial register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the DRAM. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register-transfer operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 55 MHz. A separate output, QSF, is included to indicate which half of the serial register is active. Refreshing the SAM is not required because the data register that comprises the SAM is static. All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. All TMS551xx employ TI's state-of-the-art EPIC technology combining very high performance with improved reliability. All TMS551xx are offered in a 64-pin small-outline gull-wing-leaded package (DGH suffix) for direct surface mounting. The TMS551xx VRAMs and other TI multiport VRAMs are supported by a broad line of graphics processors and control devices from Texas Instruments.
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4-column functional block diagram (TMS5516x)
DSF
Input Buffer 1 of 4 Sub-Blocks (see next page) SpecialFunction Logic Refresh Counter
Input Buffer 1 of 4 Sub-Blocks (see next page)
Row Buffer
9
DQ0 - DQ15
16
A0 - A8
Output Buffer
Column Buffer
1 of 4 Sub-Blocks (see next page)
SerialAddress Counter SplitRegister Status
SC
SQ0 - SQ15
16
SerialOutput Buffer
QSF SE RAS CASx TRG WE Timing Generator 1 of 4 Sub-Blocks (see next page) SE
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4-column functional block diagram (TMS5516x) (continued)
SpecialFunction Logic Color Register
DSF Input Buffer
DRAM Input Buffer DQx DQx+1 DQx+2 DQx+3 DRAM Output Buffer
MUX
W/B Unlatch
W/B Latch
Address Mask
WritePer-Bit Control
Refresh Counter
Column Dec. RAS CASx TRG WE Sense AMP Timing Generator 512 x 512 Memory Array
Row Buffer A0 - A8 Row Decoder Column Buffer
Serial-Data Register Serial-Data Pointer SQx SQx+1 SQx+2 SQx+3 SerialOutput Buffer SerialAddress Counter SplitRegister Status SC
SE
1 of 4 Sub-Blocks
QSF SE
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
8-column functional block diagram (TMS5517x)
DSF
Input Buffer
SpecialFunction Logic 1 of 2 Sub-Blocks (see next page) Input Buffer
Refresh Counter
Row Buffer
9
DQ0 - DQ15
16 A0 - A8
Output Buffer
Column Buffer
SerialAddress Counter SplitRegister Status
SC
1 of 2 Sub-Blocks (see next page) SQ0 - SQ15 16
QSF SE SerialOutput Buffer SE
RAS CASx TRG WE Timing Generator
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8-column functional block diagram (TMS5517x) (continued)
DSF Input Buffer SpecialFunction Logic Color Register
DRAM Input Buffer
MUX
W/B Unlatch
W/B Latch
Address Mask
WritePer-Bit Control DQx DQx + 1 DQx + 2 DQx + 3 DQx + 4 DQx + 5 DQx + 6 DQx + 7
Refresh Counter
DRAM Output Buffer
Column DEC Sense AMP 512 x 512 Memory Array
Row Buffer A0 - A8 Column Buffer
Row Decoder
RAS CASx TRG WE
Timing Generator
Serial-Data Register Serial-Data Pointer
SQx SQx + 1 SQx + 2 SQx + 3 SQx + 4 SQx + 5 SQx + 6 SQx + 7
SerialAddress Counter SplitRegister Status
SC
Serial Output Buffer
QSF 1 of 2 Sub-Blocks SE SE
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SMVS464 - MARCH1996
Table 2. Function Table
RAS FALL FUNCTION CASx Reserved (do not use) CBR refresh (no reset) and stop-point set CBR refresh (option reset)|| CBR refresh (no reset)k Full-register transfer Split-register transfer DRAM write (nonmasked) DRAM write (nonpersistent write-per-bit) DRAM write (persistent write-per-bit) DRAM block write (nonmasked)h DRAM block write (nonpersistent write-per-bit)h DRAM block write (persistent write-per-bit)h Load write-mask register Load color register L L L L H H H H H H H H H H TRG L X X X L L H H H H H H H H WE L L H H H H H L L H L L H H DSF L H L H L H L L L L L L H H DSF X X X X X X L L L H H H L H RAS X Stop Point # X X Row Addr Row Addr Row Addr Row Addr Row Addr Row Addr Row Addr Row Addr Refresh Addr Refresh Addr CASx X X X X Tap Point Tap Point Col Addr Col Addr Col Addr Block Addr Block Addr Block Addr X X RAS X X X X X X X Write Mask X X Write Mask X X X CASx FALL ADDRESS DQ0 - DQ15 CASL CASU WE X X X X X X Valid Data Valid Data Valid Data Col Mask Col Mask Col Mask Write Mask Color Data MNEMONIC CODE
-- CBRS CBR CBRN RT SRT RW RWM RWM BW BWM BWM LMR LCR
Legend: X = Don't care Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled DQ0 - DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. Logic L is selected when either or both CASL and CASU are low. The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed. CBRS cycle should be performed immediately after the power-up initialization for stop-point mode. # A0 - A3, A8: don't care; A4 - A7 : stop-point code || CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. kCBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. hFor 4-column block write (TMS5516x), block address is A2 - A8; for 8-column block write (TMS5517x), block address is A3 - A8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle.
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Table 3. Pin Description Versus Operational Mode
PIN A0 - A8 RAS CASL CASU DSF Row, column address Row-address strobe Column-address strobe, DQ output enable Block-write enable Load-write-mask-register enable Load-color-register enable CBR (option reset) DQ output enable Write enable, write-per-bit enable DRAM data I/O, write mask Serial clock SQ output enable, QSF output enable Serial-data output Serial-register status Power supply Ground DRAM TRANSFER Row address, tap point Row-address strobe Tap-address strobe Split-register-transfer enable SAM
TRG WE DQx SC SE SQx QSF VCC VSS
Transfer enable
NC/GND Make no external connection or tie to system GND For proper device operation, all VCC pins must be connected to a 5.0-V supply and all VSS pins must be tied to ground.
pin definitions
address (A0 -A8) Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are set up on pins A0 -A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set up on pins A0 -A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on or before the falling edge of RAS and the first falling edge of CASx. In 4-column block-write operations (TMS5516x), column-address bits A0 - A1 are ignored. Column-address bits A2- A8 become the block address that selects one of the 128 blocks in the active row. In 8-column block write operations (TMS5517x), column-address bits A0 - A2 are ignored. Column address bits A3 - A8 become the block address that selects one of the 64 blocks in the active row. In full-register operations, column-address bit A8 selects which half of the active row in the DRAM is transferred to the SAM. Column address bits A0 -A7 select one of 256 tap points (starting positions) for the serial-data output. In split-register-transfer operations, column address bit A8 selects the DRAM half row. Column-address bit A7 is ignored. The internal serial-address counter identifies which half of the SAM is in use. If the high half of the SAM is in use, the low half of the SAM is loaded with the low half of the DRAM half row, and vice versa. Column-address bits A0 - A6 select one of 127 tap points (starting locations) for the serial output. Locations 127 and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are not valid tap points in split-register-transfer operations. row-address strobe (RAS) The falling edge of RAS latches the states of the row address, CASL, CASU, DSF, TRG, WE, and the DQs onto the chip to initiate DRAM and transfer functions. RAS also functions as a DRAM output enable.
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column-address strobe (CASL, CASU) The first falling edge of CASx latches the states of the column address and DSF onto the chip to control DRAM and transfer functions. CASL and CASU provide byte control in DRAM operations. CASL controls the lower byte (DQ0- DQ7), and CASU controls the upper byte (DQ8 - DQ15). Byte control can be applied in read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. CASx also functions as a DRAM output enable. special-function select (DSF) DSF is latched on the falling edge of RAS and the falling edge of CASx to determine which functions are invoked on a particular cycle (see Table 2). output enable, transfer select (TRG) TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG also functions as DRAM output enable. write enable, write-per-bit select (WE) WE selects either the write mode or the read mode in a CASx cycle. Dropping WE low selects the write mode. Holding WE high selects the read mode. Holding WE low on the falling edge of RAS selects the write-per-bit operation. DRAM data I/O, write mask, column mask (DQ0 - DQ15) DQ0- DQ15 function as the DRAM input / output port in DRAM operations. In normal DRAM write cycles, all 16 bits of write data are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the DQs are latched as the write mask on the falling edge of RAS. Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fan-out of one Series 74 TTL load. The outputs are in the high-impedance (floating) state until RAS, CASx, and TRG have all been brought low in read cycles. For the TMS551x0 devices, the outputs remain valid until CASx is brought high, TRG is brought high, or WE is brought low. For the TMS551x1 devices, the outputs remain valid until both RAS and CASx are brought high, TRG is brought high, or WE is brought low. serial clock (SC) The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM location. serial enable (SE) SE functions as the output enable for SQ0 - SQ15 and QSF. SE low enables the serial-data output. SE high disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC automatically increments the internal serial-address counter regardless of the state of SE. serial data outputs (SQ0 - SQ15) SQ0- SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance state when SE is high.
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functional operation description
random-access operation Table 4. DRAM Function Table
RAS FALL FUNCTION CASx Reserved (do not use) CBR refresh (no reset) and stop-point set CBR refresh (option reset)|| CBR refresh (no reset)k DRAM write (nonmasked) DRAM write (nonpersistent write-per-bit) DRAM write (persistent write-per-bit) DRAM block write (nonmasked)h DRAM block write (nonpersistent write-per-bit)h DRAM block write (persistent write-per-bit)h Load write-mask register Load color register L L L L H H H H H H H H TRG L X X X H H H H H H H H WE L L H H H L L H L L H H DSF L H L H L L L L L L H H DSF X X X X L L L H H H L H RAS X Stop Point # X X Row Addr Row Addr Row Addr Row Addr Row Addr Row Addr Refresh Addr Refresh Addr CASx X X X X Col Addr Col Addr Col Addr Block Addr Block Addr Block Addr X X RAS X X X X X Write Mask X X Write Mask X X X CASx FALL ADDRESS DQ0 - DQ15 CASL CASU WE X X X X Valid Data Valid Data Valid Data Col Mask Col Mask Col Mask Write Mask Color Data MNEMONIC CODE
-- CBRS CBR CBRN RW RWM RWM BW BWM BWM LMR LCR
Legend: X = Don't care Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled DQ0 - DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. Logic L is selected when either or both CASL and CASU are low. The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed. CBRS cycle should be performed immediately after the power-up initialization for stop-point mode. # A0 - A3, A8: don't care; A4 - A7 : stop-point code || CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. kCBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. hFor 4-column block write (TMS5516x), block address is A2 - A8; for 8-column block write (TMS5517x), block address is A3 - A8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle.
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refresh
CAS-before-RAS (CBR) refresh
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN (no reset) and CBRS (no reset and stop point set) refreshes do not end the persistent write-per-bit mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within the required time period, trf(MA). The output buffers remain in the high-impedance state during the CBR type refresh cycles regardless of the state of TRG.
hidden refresh
A hidden refresh is accomplished by holding either or both CASL and CASU low in the DRAM read cycle and cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be refreshed. enhanced page mode (TMS551x0) Enhanced page mode allows faster memory access by keeping the same row address while selecting random column addresses. The maximum RAS low time and minimum CASx page cycle time are used to determine the number of columns that can be accessed. Unlike conventional page mode, the enhanced page mode allows the TMS551x0 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx goes low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CASx. In this case, data is obtained after ta(C) max (access time from CASx low) if ta(CA) max (access time from column address) has been satisfied. extended data output ( TMS551x1) The TMS551x1 features extended data output during DRAM accesses. While RAS and TRG are low, the DRAM output remains valid even when CASx returns high. The output remains valid until WE is low, TRG is high, or both CASx and RAS are high (see Figure 1, Figure 2, and Figure 3). The extended data-output mode functions in all read cycles including DRAM read, page-mode read, and read-modify-write cycles.
RAS
CASx tdis(RH)
DQ0 - DQ15
Valid Output
TRG See "switching characteristics over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x1)
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extended data output (TMS551x1) (continued)
RAS
CASx tdis(CH)
DQ0 - DQ15
Valid Output
TRG See "switching characteristics over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 2. DRAM Read Cycle With CAS-Controlled Output (TMS551x1)
RAS
CASx
A0 - A8
Row
Column
Column ta(CP) ta(C) ta(CA) th(CLQ) Valid Output tdis(RH) Valid Output tdis(G)
ta(C) ta(CA) DQ0 - DQ15
TRG See "switching characteristics over recommended ranges of supply voltage and operating free-air temperature" table. See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 3. DRAM Page-Read Cycle With Extended Data Output (TMS551x1)
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byte operation Byte operation can be applied in DRAM read cycles, write cycles, block-write cycles, load-write-mask-register cycles and load-color-register cycles. In byte operation, the column address (A0 -A8) is latched at the first falling edge of CASx. In read cycles, CASL enables the lower byte (DQ0 -DQ7) and CASU enables the upper byte (DQ8- DQ15) (see Figure 4).
RAS
CASL
CASU
tsu(CA) th(CLCA)
A0 - A8
Row ta(C)
Column
DQ0 - DQ7 ta(C) DQ8 - DQ15 ta(G) TRG
Lower Byte Output
Upper Byte Output
See "switching characteristics over recommended ranges of supply voltage and operating free-air temperature" table. See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 4. Example of a Byte-Read Cycle
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byte operation (continued) In byte-write operation, CASL enables data to be written to the lower byte (DQ0 -DQ7) and CASU enables data to be written to the upper byte (DQ8 - DQ15). In an early-write cycle, WE is brought low prior to both CASx signals. Data setup and hold times for DQ0 - DQ15 are referenced to the first falling edge of CASx (see Figure 5).
RAS
WE
CASL
CASU
tsu(CA) th(CLCA)
A0 - A8
Row tsu(DCL)
Column
th(CLD) DQ0 - DQ15 Valid Input
See "switching characteristics over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 5. Example of an Early-Write Cycle
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byte operation (continued) For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data is strobed in with data setup and hold times for DQ0 - DQ15 referenced to WE (see Figure 6).
RAS
CASL
CASU
WE tsu(DWL) th(WLD) DQ0 - DQ15 Valid Input
See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 6. Example of a Late-Write Cycle
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write-per-bit The write-per-bit function allows the masking of any combination of the 16 DQs on any write cycle. The write-per-bit operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling edge of RAS, the write operation is performed without any masking. There are two write-per-bit modes: the nonpersistent write-per-bit and the persistent write-per-bit.
nonpersistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask selects which of the 16 DQs are to be written and which are not. After RAS has latched the on-chip write-per-bit mask, input data is driven onto the DQ pins and is latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. CASL enables the lower byte (DQ0 - DQ7) to be written through the mask and CASU enables the upper byte (DQ8 - DQ15) to be written through the mask. If a write-mask-low (write mask = 0) is strobed into a particular DQ pin on the falling edge of RAS, data is not written to that DQ. If a write-mask-high (write mask = 1) is strobed into a particular DQ pin on the falling edge of RAS, data is written to that DQ (see Figure 7).
RAS
CASL
CASU
WE tsu(DQR) th(RDQ) tsu(DWL) th(WLD)
DQ0 - DQ15
Write Mask
Valid Input
See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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persistent write-per-bit
The persistent write-per-bit mode is initiated only by performing a load-write-mask-register (LMR) cycle first. In the persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary number of write cycles until another LMR cycle is performed or until power is removed. The LMR cycle is performed using DRAM write-cycle timing except DSF is held high on the falling edge of RAS and held low on the first falling edge of CASx. A binary code is input to the write-mask register through the random I/O pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. Byte-write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and is reset only by a CBR refresh with option reset cycle (see Figure 8).
Load Write-Mask Register RAS
Persistent Write-Per-Bit
CBR Refresh (option reset)
CASx
A0 - A8 Refresh Address DSF Row Column
WE DQ0 - DQ15 Write-Mask Data Mask Data = 1: Write to DQ enabled = 0: Write to DQ disabled Valid Input
Figure 8. Example of a Persistent Write-Per-Bit Operation
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4-column block write (TMS5516x) The 4-column block-write function allows up to 64 bits of data to be written simultaneously to one row of the memory array. This function is implemented as 4 columns x 4 DQs and repeated in four quadrants. In this manner, each of the four one-megabit quadrants can have up to four consecutive columns written at a time with up to four DQs per column (see Figure 9).
DQ15 DQ14 DQ13 DQ12 4th Quadrant
DQ11 DQ10 3rd Quadrant DQ9 DQ8 One Row of 0 - 511 DQ7 DQ6 2nd Quadrant DQ5 DQ4
DQ3 DQ2 1st Quadrant DQ1 DQ0
Four Consecutive Columns of 0 - 511
Figure 9. 4-Column Block-Write Operation Each one-megabit quadrant has a 4-bit column mask to mask off any or all of the four columns from being written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. Write data (color data) is provided by four bits from the on-chip color register. Bits 0 - 3 from the 16-bit write-mask register, bits 0 - 3 from the 16-bit column-mask register, and bits 0 - 3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4 - 7, 8 - 11, and 12 - 15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10).
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4-column block write (continued)
DQ15 DQ14 DQ13 DQ12
DQ11 DQ10 DQ9 DQ8 One Row of 0 - 511 DQ7 DQ6 DQ5 DQ4
12 13 14 15
8 9 10 11
DQ3 DQ2 DQ1 DQ0
4 5 6 7
Column Mask
0 1 2 3 2
3 6 5 4 1 0
7 10 9 8
11 14 13 12
15
Write Mask
0
1
2
3
4
5
6
7
8
9 10 11
12 13 14 15
Color Register
Figure 10. 4-Column Block Write With Masks
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4-column block write (continued) Every four adjacent columns makes a block, which results in 128 blocks along one row. Block 0 comprises columns 0 - 3, block 1 comprises columns 4 - 7, block 2 comprises columns 8 - 11, etc., as shown in Figure 11.
Block 0 Block 1
......................
Block 127
One Row of 0 - 511 0 1 2 3 4 5 6 7
...........................
511
Columns
Figure 11. 4-Column-Block Column-Organization During 4-column block-write cycles, only the seven most significant column addresses (A2 - A8) are latched on the falling edge of CASx to decode one of the 128 blocks. Address bits A0 - A1 are ignored. All one-megabit quadrants have the same block selected. A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on the use of the write-mask capability, allowing additional performance options. Example of block write: block-write column address = 110000000 (A0 - A8 from left to right) bit 0 = 1011 = 1110 = 1111 1st Quad bit 15 0111 1011 1010 4th Quad
color-data register write-mask register column-mask register
1011 1111 0000 2nd Quad
1100 1111 0111 3rd Quad
Column-address bits A0 and A1 are ignored. Block 0 (columns 0 - 3) is selected for all one-megabit quadrants. The first quadrant has DQ0 - DQ2 written with bits 0 - 2 from the color-data register to all four columns of block 0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0. The second quadrant (DQ4 - DQ7) has all four columns masked off due to the column-mask bits 4 - 7 being 0, so that no data is written. The third quadrant (DQ8 - DQ11 ) has its four DQs written with bits 8 - 11 from the color-data register to columns 1 - 3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to the column-mask bit 8 being 0. The fourth quadrant (DQ12 - DQ15) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 12 after the 4-column block-write operation shown in the example.
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4-column block write (continued)
DQ15 1 0 1 0
DQ14 1
0
1
0 4th Quadrant
DQ13 0
0
0
0
DQ12 0
0
0
0
Columns 0
1
2
3
Figure 12. Example of Fourth Quadrant After 4-Column Block-Write Operation
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8-column block write (TMS5517x) The 8-column block-write function allows up to 128 bits of data to be written simultaneously to one row of the memory array. This function is implemented as 8 columns x 8 DQs and repeated in two bytes. In this manner, each of the two bytes can have up to eight consecutive columns written at a time with up to eight DQs per column (see Figure 13).
DQ15 DQ14 DQ13 DQ12 Upper Byte DQ11 DQ10 DQ9 DQ8 One Row of 0 - 511 DQ7 DQ6 DQ5 DQ4 Lower Byte DQ3 DQ2 DQ1 DQ0
Eight Consecutive Columns of 0 - 511
Figure 13. 8-Column Block-Write Operation Each byte has an 8-bit column mask to mask off any or all of the eight columns from being written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. Write data (color data) is provided by eight bits from the on-chip color register. Bits 0 - 7 from the 16-bit write-mask register, bits 0 - 7 from the 16-bit column-mask register, and bits 0 - 7 from the 16-bit color-data register configure the block write for the lower byte, while bits 8 - 15 control the upper byte in a similar fashion (see Figure 14).
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8-column block write (TMS5517x) (continued)
Lower Byte DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Upper Byte DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
One Row of 0-511
Column Mask
0 1 2 3
4 5 6 7
Column Mask
8 9 10 11
12 13 14 15
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15
Color Register
Figure 14. 8-Column Block Write With Masks Every eight adjacent columns makes a block resulting in 64 blocks along one row. Block 0 comprises columns 0 - 7, block 1 comprises columns 8 - 15, block 2 comprises columns 16 - 23, etc., as shown in Figure 15.
Block 0 Block 63
One Row of 0 - 511 0 1 2 3 4 5 6 7
.............
Columns
Write Mask
Write Mask
504
505
506
507 508
509
510
511
Figure 15. 8-Column-Block Column-Organization During 8-column block-write cycles, only the six most significant column addresses (A3 - A8) are latched on the falling edge of CASx to decode one of the 64 blocks. Address bits A0 - A2 are ignored. Both bytes have the same block selected.
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8-column block write (continued) A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the write-mask capability allowing additional performance options. Example of block write: block-write column address = 110000000 (A0 - A8 from left to right) bit 0 color-data register = write-mask register = column-mask register = 10111011 11101111 11110000 Lower Byte bit 15 11000111 11111011 01111010 Upper Byte
Column-address bits A0 - A2 are ignored. Block 0 (columns 0 - 7) is selected for both bytes. The lower byte has DQ0 - DQ2 and DQ4 - DQ7 written with bits 0 - 2 and 4 - 7 from the color-data register to columns 0 - 3. Columns 4 - 7 are not written and retain their previous data due to the column-mask bits 4 - 7 being 0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being 0. The upper byte has DQ8 - DQ12 and DQ14 - DQ15 written with bits 8 - 12 and 14 - 15 from the color-data register to columns 1 - 4 and 6. Columns 0, 5, and 7 are not written and retain their previous data due to the column-mask bits 8, 13, and 15 being 0. DQ13 is not written and retains its previous data due to the write-mask-register bit 13 being 0. If the previous data was all 0s, the upper byte would contain the data pattern in Figure 16 after the 8-column block-write operation shown in the example.
DQ15 0 1 1 1 1 0 1 0 DQ14 0 1 1 1 1 0 1 0 DQ13 0 0 0 0 0 0 0 0 DQ12 0 0 0 0 0 0 0 0 DQ11 0 0 0 0 0 0 0 0 DQ10 DQ9 DQ8 00000000 Upper Byte
01111010
01111010
Columns 0 1 2 3 4 5 6 7
Figure 16. Example of Upper Byte After 8-Column Block-Write Operation
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load color register The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS and on the first falling edge of CASx. The color register is loaded from pins DQ0 - DQ15, which are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. If only one CASx is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until power is lost or until another load-color-register cycle is performed (see Figure 17 and Figure 18).
Load-Color-Register Cycle
Block-Write Cycle (no write mask)
Block-Write Cycle (nonpersistent write-per-bit)
RAS CASx A0 - A8 WE TRG DSF DQ0 - DQ15 4 6 5 6 1 2 3 2 3
Legend: 1. Refresh address: A0 - A8 are latched on the falling edge of RAS. 2. Row address: A0 - A8 are latched on the falling edge of RAS. 3. Block address A2 - A8 (TMS5516x) or A3 - A8 (TMS5517x) are latched on the first falling edge of CASx. 4. Color data: DQ0 - DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first. 5. Write-mask data: DQ0 - DQ15 are latched on the falling edge RAS. 6. Column-mask data: DQ0 - DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first. = don't care
Figure 17. Example of Block Writes
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load color register (continued)
Load-Mask-Register Cycle
Load-Color-Register Cycle
Persistent Write-Per-Bit Block-Write Cycle
RAS CASx A0 - A8 WE TRG DSF DQ0 - DQ15 5 4 6 1 1 2 3
Legend: 1. Refresh address: A0 - A8 are latched on the falling edge of RAS. 2. Row address: A0 - A8 are latched on the falling edge of RAS. 3. Block address A2 - A8 (TMS5516x) or A3 - A8 (TMS5517x) are latched on the first falling edge of CASx. 4. Color data: DQ0 - DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first. 5. Write-mask data: DQ0 - DQ15 are latched on the falling edge RAS. 6. Column-mask data: DQ0 - DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first. = don't care
Figure 18. Example of a Persistent Block Write DRAM-to-SAM transfer operation During the DRAM-to-SAM transfer operation, one-half of a row (256 columns) in the DRAM array is selected to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS, determines whether the full-register-transfer operation or the split-register-transfer operation is performed. Table 5. SAM Function Table
RAS FALL FUNCTION CASx Full-register-transfer read Split-register-transfer read H H TRG L L WE H H DSF L H CASx FALL DSF X X ADDRESS RAS Row Addr Row Addr CASx Tap Point Tap Point DQ0 - DQ15 RAS X X CASx WE X X MNEMONIC CODE
RT SRT
Logic L is selected when either or both CASL and CASU are low. X = don't care
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full-register-transfer read
A full-register-transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is brought low and latched at the falling edge of RAS. Nine row-address bits (A0 - A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0 - A8) are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is transferred. Address bits A0 - A7 select one of the SAM's 256 available tap points from which the serial data is read out (see Figure 19).
A8 = 0 A8 = 1
0
255 256
511 512 x 512 Memory Array
256-Bit Data Register 0 255
Figure 19. Full-Register-Transfer Read A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer cycle (see Figure 20).
Early Load RAS Real-Time Load Late Load
CASx
A0 - A8 Row TRG Tap Point Row Tap Point Row Tap Point
WE
SC
Old Data
Tap Bit
Old Data
Old Data
Tap Bit
Old Data
Old Data
Tap Bit
Figure 20. Example of Full-Register-Transfer Read Operations
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split-register-transfer read
In split-register-transfer operations, the serial-data register is split into halves (see Figure 21). The low half contains bits 0 - 127, and the high half contains bits 128 - 255. While one half is being read out of the SAM port, the other half can be loaded from the memory array.
A8 = 0 A8 = 1
0
255 256
511 512 x 512 Memory Array
256 - Bit Data Register 0 255
Figure 21. Split-Register-Transfer Read To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the falling edge of RAS (see Figure 22). Nine row-address bits (A0 - A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 - A6 and A8) are latched at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be transferred. Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the inactive half. Column-address bits A0 - A6 select one of 127 tap points in the specified half of SAM. Locations 127 and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are not valid tap points in split-register-transfer operations.
RAS
Full XFER
Split XFER
Split XFER
Split XFER
A8 = 0 0 A DRAM B 511 0 A B
A8 = 1 A7 = 0 511 C 0 A B
A8 = 1 A7 = 1 511 C D
A8 = 0 0 A7 = 0 A E B C D 511
0 SAM A B
255
0 C B
255
0 C SQ D
255
0 E SQ D
255
SQ A7 shown is internally controlled.
SQ
Figure 22. Example of a Split-Register-Transfer Read Operation A full-register transfer must precede the first split-register transfer to ensure proper operation. After the full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock requirement.
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split-register-transfer read (continued)
QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low, the serial-address pointer is accessing the lower (least significant) 128 bits of SAM. When QSF is high, the pointer is accessing the higher (most significant) 128 bits of SAM. QSF changes state upon completing a full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached.
Full-Register-Transfer Read With Tap Point N RAS Split-RegisterTransfer Read
CASx
TRG
DSF
SC td(CLQSF) td(GHQSF) QSF
Tap Point N
NOTE A: See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 23. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read
Split-RegisterTransfer Read With Tap Point N RAS
Split-RegisterTransfer Read
CASx
TRG
DSF td(RHMS) SC 127 or 255 td(MSRL) Tap Point N td(SCQSF) QSF NOTE A: See "timing requirements over recommended ranges of supply voltage and operating free-air temperature" table.
Figure 24. Example of Successive Split-Register-Transfer Read Operations
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serial-read operation The serial-read operation can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. Serial data is accessed from the SAM at the rising edge of serial clock SC. SE low enables the outputs. SE high disables the outputs. Holding SE high does not disable SC. The rising edge of SC automatically increments the internal serial-address counter regardless of the state of SE. In full-register-transfer operations, the counter proceeds sequentially to the most significant bit (bit 255), and then wraps around to the least significant bit (bit 0), as shown in Figure 25.
0 1 2 Tap 254 255
Figure 25. Serial-Pointer Direction for Serial Read In split-register-transfer operations, serial data can be read out from the active half of SAM by clocking SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to the inactive half during this period, the serial pointer points next to the tap point location loaded by that split-register-transfer (see Figure 26).
0
Tap
126
127
128
Tap
254
255
Figure 26. Serial Pointer for Split-Register Read - Case I If there is no split-register transfer to the inactive half during this period, the serial pointer points to the next bit, bit 128 or bit 0, respectively (see Figure 27).
0
Tap
126
127
128
Tap
254
255
Figure 27. Serial Pointer for Split-Register Read - Case II split-register programmable stop point The TMS551xx offers programmable stop-point mode for split-register-transfer read operation. This mode can be used to improve 2-D drawing performance in a nonscanline data format. In split-register-transfer read operations, the stop point is defined as a register location at which the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode, the SAM is divided into partitions whose length is programmed on row addresses A4 - A7 in a CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 28).
0 127 128 255
Partition Length Stop Points
Figure 28. Example of SAM With Partitions
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split-register programmable stop point (continued) Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding CASx low, WE low, and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses A4- A7, which are used to define the SAM's partition length. The other row-address inputs are don't cares. Stop-point mode should be initiated immediately after the power-up initialization (see Table 6). Table 6. Programming Code for Stop-Point Mode
MAXIMUM PARTITION LENGTH 16 32 64 128 (default) ADDRESS AT RAS IN CBRS CYCLE A8 X X X X A7 L L L L A6 L L L H A5 L L H H A4 L H H H A0 - A3 X X X X NUMBER OF PARTITIONS 16 8 4 2 STOP-POINT STOP POINT LOCATIONS 15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255 31, 63, 95, 127, 159, 191, 223, 255 63, 127, 191, 255 127, 255
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM partition the serial output begins and at which stop point the serial output stops coming from one half of SAM and switches to the opposite half of SAM (see Figure 29).
RAS Full Read XFER Tap = H1 H1 SC Split Read XFER Tap = L1 191 L1 Split Read XFER Tap = H2 63 H2 Split Read XFER Tap = L2 255 L2
0
L1
SAM Low Half 63
L2
127
128
H1
SAM High Half 191
H2
255
Figure 29. Example of Split-Register Operation With Programmable Stop Points
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256-/512-bit compatibility of split-register programmable stop point The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point mode, the column-address bits AY7 and AY8 are swapped internally to assure compatibility (see Figure 29). This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don't care and AY7 decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR ( option reset ) cycle is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their normal functions. Consistent use of CBR cycles ensures that the TMS551xx remains in nomal mode.
NON STOP-POINT MODE AY8 = 0 AY8 = 1 AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1 512 x 512 Memory Array STOP-POINT MODE AY8 = 0 AY8 = 1 AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1 512 x 512 Memory Array
256 - Bit Data Register 0 255 0 255
256 - Bit Data Register
Figure 30. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately after the power-up initialization cycles are performed. power up To achieve proper device operation, an initial pause of 200 s is required after power up followed by a minimum of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two SC cycles are required to initialize the SAM port. After initialization, the internal state of the TMS551xx is as follows:
STATE AFTER INITIALIZATION QSF Write mode Write-mask register Color register Serial-register tap point SAM port Defined by the transfer cycle during initialization Nonpersistent mode Undefined Undefined Defined by the transfer cycle during initialization Output mode
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SMVS464 - MARCH1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
TMS551xx Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS551xx MIN VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage Low-level input voltage (see Note 2) 2.4 -1.0 4.5 NOM 5.0 0 6.5 0.8 MAX 5.5 UNIT V V V V
TA Operating free-air temperature 0 70 C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A High-level output voltage Low-level output voltage Input current (leakage) TEST CONDITIONS IOH = - 1 mA IOL = 2 mA VCC = 5.5 V, VI = 0 V to 5.8 V, All other pins at 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, See Note 3 See Note 4 tc(SC) = MIN All clocks = VCC tc(SC) = MIN See Note 4 tc(SC) = MIN, tc(P) = MIN, (P) MIN tc(SC) = MIN, (SC) MIN See Note 4 See Note 4 See Note 5 See Note 5 Standby Active Standby Active Standby Active Standby Active Standby '551x0 '551x1 '551x0 '551x1 SAM PORT '551xx-60 MIN 2.4 0.4 10 10 180 225 5 70 180 225 135 140 175 185 180 225 200 250 MAX '551xx-70 MIN 2.4 0.4 10 10 165 205 5 65 165 205 115 140 155 185 165 205 180 225 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA mA mA mA
Output current (leakage) Operating current Operating current Standby current Standby current RAS only refresh current RAS only refresh current Page mode current Page-mode c rrent Page-mode c rrent Page mode current CBR current CBR current
tc(SC) = MIN, See Note 4 Active ICC6 Data-transfer current See Note 4 Standby ICC6A Data-transfer current tc(SC) = MIN Active For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open NOTES: 3. SE is disabled for SQ output leakage tests. 4. Measured with one address change while RAS = VIL; tc(rd ), tc( W ), tc(TRD) = MIN 5. Measured with one address change while CASx = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6)
PARAMETER Ci(A) Ci(RC) Ci(W) Ci(SC) Ci(SE) Ci(DSF) Ci(TRG) Co(O) Co(QSF) Input capacitance, address inputs Input capacitance, address strobe inputs Input capacitance, write enable input Input capacitance, serial clock Input capacitance, serial enable Input capacitance, special function Input capacitance, transfer register input Output capacitance, SQ and DQ Output capacitance, QSF MIN MAX 6 7 7 7 7 7 7 7 9 UNIT pF pF pF pF pF pF pF pF pF
NOTE 6: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7)
PARAMETER ta(C) ta(CA) ta(CP) ta(G) ta(R) ta(SE) ta(SQ) tdis(CH) tdis(G) tdis(RH) tdis(SE) tdis(WL) Access time, DQx from CASx low Access time, DQx from column address Access time, DQx from CASx high Access time, DQx from TRG low Access time, DQx from RAS low Access time, SQx from SE low Access time, SQx from SC high Disable time, random output from CASx high (see Note 8) Disable time, random output from TRG high (see Note 8) Disable time, random output from RAS high (see Note 8) Disable time, serial output from SE high (see Note 8) Disable time, random output from WE low (see Note 8) td(RLCL) = MAX CL = 30 pF CL = 30 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 30 pF CL = 30 pF tSEZ tWEZ TEST CONDITIONS td(RLCL) = MAX td(RLCL) = MAX td(RLCL) = MAX ALT. SYMBOL tCAC tAA tCPA tOEA tRAC tSEA tSCA tOFF tOEZ 3 3 3 3 0 '551xx-60 MIN MAX 17 30 35 15 60 12 15 15 15 15 10 15 3 3 3 3 0 '551xx-70 MIN MAX 20 35 40 20 70 15 20 20 20 20 20 20 UNIT ns ns ns ns ns ns ns ns ns ns ns ns
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data out reference level: VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial-data out reference level: VOH / VOL = 2 V/0.8 V. 8. tdis(CH), tdis(RH), tdis(G), tdis( WL ), and tdis(SE) are specified when the output is no longer driven.
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL tc(P) (P) tc(rd) tc(rdW) tc(RDWP) tc(SC) tc(TRD) tc(W) tw(CH) tw(CL) (CL) tw(GH) tw(RH) tw(RL) tw(RL)P tw(SCH) tw(SCL) tw(TRG) tw(WL) tsu(CA) tsu(DCL) tsu(DQR) tsu(DWL) tsu(RA) tsu(rd) tsu(SFC) tsu(SFR) tsu(TRG) tsu(WCH) tsu(WCL) tsu(WMR) tsu(WRH) th(CHrd) th(CLCA) Cycle time, page-mode read, write time page mode read Cycle time, read Cycle time, read-modify-write Cycle time, page-mode read-modify-write Cycle time, serial clock (see Note 9) Cycle time, transfer read Cycle time, write Pulse duration, CASx high '551x0 Pulse duration, CASx low P lse d ration CAS lo (see Note 10) Pulse duration, TRG high Pulse duration, RAS high Pulse duration, RAS low (see Note 11) Pulse duration, RAS low (page mode) Pulse duration, SC high Pulse duration, SC low Pulse duration, TRG low Pulse duration, WE low Setup time, column address before CASx low Setup time, data valid before CASx low, early write Setup time, write mask valid before RAS low, non-persistent write-per-bit Setup time, data valid before WE low, late write Setup time, row address before RAS low Setup time, WE high before first CASx low, read Setup time, DSF before first CASx low Setup time, DSF before RAS low Setup time, TRG before RAS low Setup time, WE low before both CASx high, write Setup time, WE low before first CASx low, early write Setup time, WE low before RAS low, write-per-bit Setup time, WE low before RAS high, write Hold time, WE high after both CASx high, read (see Note 12) tWP tASC tDSC tMS tDSW tASR tRCS tFSC tFSR tTHS tCWL tWCS tWSR tRWL tRCH '551x1 '551x0 '551x1 tPC tPC tRC tRMW tPRMW tSCC tRC tWC tCPN tCAS tCAS tTP tRP tRAS tRASP tSC tSCP '551xx -60 MIN 35 30 110 150 80 18 110 110 10 10 17 20 40 60 5 5 15 10 0 0 0 0 0 0 0 0 0 15 0 0 15 0 10 000 60 100 000 10 000 10 000 MAX '551xx - 70 MIN 40 30 130 175 90 22 130 130 10 10 20 20 50 70 8 8 20 10 0 0 0 0 0 0 0 0 0 15 0 0 15 0 10 000 70 100 000 10 000 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Hold time, column address after first CASx low tCAH 10 10 ns th(CLD) Hold time, data valid after first CASx low, early write tDH 15 15 ns th(CLQ) Hold time, DQ output after CASx low (TMS551x1) tDHC 4 5 ns Timing measurements are referenced to VIL max and VIH min. NOTES: 9. Cycle time assumes tt = 3 ns. 10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this can require additional CASx low time [tw(CL)]. 11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this can require additional RAS low time [tw(RL)]. 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
ALT. SYMBOL th(CLW) th(RA) th(RDQ) th(RHrd) th(RLCA) th(RLD) th(RLW) th(RSF) th(RWM) th(SFC) th(SFR) th(SHSQ) th(TRG) th(WLD) th(WLG) td(CACH) td(CAGH) td(CARH) td(CASH) td(CAWL) td(CHRL) td(CLGH) td(CLQSF) td(CLRH) td(CLRL) td(CLSH) td(CLTH) td(CLWL) td(CLZ) td(DCL) td(DGL) Hold time, WE low after first CASx low, early write Hold time, row address after RAS low Hold time, write mask valid after RAS low, non-persistent write-per-bit Hold time, WE high after RAS high, read (see Note 12) Hold time, column address valid after RAS low (see Note 13) Hold time, data valid after RAS low (see Note 13) Hold time, WE low after RAS low, write Hold time, DSF after RAS low Hold time, WE low after RAS low, write-per-bit Hold time, DSF after first CASx low Hold time, DSF after RAS low Hold time, SQ after SC high Hold time, TRG after RAS low Hold time, data valid after WE low, late write Hold time, TRG high after WE low (see Note 14) Delay time, column address valid to CASx high Delay time, column address to TRG high in real-time-load and late-load full-register transfer Delay time, column address valid to RAS high Delay time, column address to first SC high after TRG high, early-load full-register transfer Delay time, column address valid to WE low, read-modify-write Delay time, both CASx high to RAS low Delay time, CASx low to TRG high, read Delay time, first CASx low to QSF switching, full-register transfer (see Note 15) Delay time, CASx low to RAS high Delay time, first CASx low to RAS low, CBR refresh Delay time, first CASx low to first SC high after TRG high, early-load full-register transfer Delay time, first CASx low to TRG high, real-time-load and late-load full-register transfer Delay time, CASx low to WE low, read-modify-write (see Note 16) Delay time, first CASx low to DQ in the low-impedance state Delay time, data to CASx low Delay time, data to TRG low tCQD tRSH tCSR tCSD tCTH tCWD tCLZ tDZC tDZO 17 0 20 15 37 3 0 0 tWCH tRAH tMH tRRH tAR tDHR tWCR tFHR tRWH tCFH tRFH tSOH tTHH tDH tOEH tCAL tATH tRAL tASD tAWD tCRP '551xx -60 MIN 10 10 10 0 30 35 30 30 10 10 10 4 10 15 10 30 20 30 25 50 0 17 30 20 0 20 15 45 2 0 0 MAX '551xx - 70 MIN 15 10 10 0 30 35 35 35 10 10 10 5 10 15 10 45 20 35 25 60 0 20 30 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
td(GHD) Delay time, TRG high before data applied at DQ tOED 10 15 ns Timing measurements are referenced to VIL max and VIH min. NOTES: 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle. 13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference. 14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 15. TRG must disable the output buffers prior to applying data to the DQ pins. 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is VOH / VOL = 2 V/0.8 V.
38
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
ALT. SYMBOL td(GHQSF) td(GLRH) td(GLZ) td(MSRL) td(RHCL) td(RHMS) td(RLCA) td(RLCH) ( ) td(RLCL) td(RLQSF) td(RLSH) td(RLTH) td(RLWL) td(SCQSF) td(SCTR) td(THRH) td(THRL) td(THSC) Delay time, TRG high to QSF switching, full-register transfer (see Note 16) Delay time, TRG low to RAS high Delay time, TRG low to DQ in the low-impedance state Delay time, last SC high at boundary (127 or 255) to RAS low, split-register transfer Delay time, RAS high to first CASx low, CBR refresh Delay time, RAS high to last SC high at boundary (127 or 255), split-register-transfer Delay time, RAS low to column address valid '551x0 Delay time, RAS low to CASx high y g Delay time, RAS low to first CASx low (see Note 17) Delay time, RAS low to QSF switching, full-register transfer (see Note 16) Delay time, RAS low to first SC high after TRG high, early-load full-register transfer Delay time, RAS low to TRG high (see Note 18) Delay time, RAS low to WE low, read-modify-write Delay time, last SC high at boundary (127 or 255) to QSF switching, split-register transfer (see Note 16) Delay time, SC high to TRG high, full-register transfer Delay time, TRG high to RAS high (see Note 18) Delay time, TRG high to RAS low (see Note 18) Delay time, TRG high to SC high (see Note 18) '551x1 CBR tRAD tCSH tCSH tCHR tRCD tRQD tRSD tRTH tRWD tSQD tTSL tTRD tTRP tTSD 5 - 10 40 20 65 50 80 20 5 - 10 50 25 tRPC tTQD tROH tOELZ 10 3 15 0 15 15 60 53 10 20 43 65 70 55 95 25 30 '551xx -60 MIN MAX 25 15 3 20 0 20 15 70 60 10 20 50 70 35 '551xx - 70 MIN MAX 30 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
trf(MA) Refresh time interval, memory tREF 8 8 ms tt Transition time tT 3 50 3 50 ns Timing measurements are referenced to VIL max and VIH min. NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is VOH / VOL = 2 V/0.8 V. 17. The maximum value is specified only to assure RAS access time. 18. Real-time-load and late-load full-register transfer
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rd) tw(RL) td(RLCH) RAS tw(RH) tt td(RLCL) td(CHRL) CASx tw(CH) td(RLCA) th(RA) tsu(RA) tsu(CA) A0 - A8 Row th(SFR) Column th(RLCA) th(CLCA) td(CACH) td(CARH) tw(CL) td(CLRH)
tsu(SFR) DSF
td(CLGH) tsu(TRG) th(TRG) TRG tsu(rd) th(RHrd) th(CHrd) WE td(DGL) DQ0 - DQ15 Data In td(GLZ) td(CLZ) ta(C) ta(CA) ta(R) For TMS551x0, CASx high disables the output regardless of the state of RAS. For TMS551x1, both RAS and CASx must be high to disable the output. tdis(CH) ta(G) tdis(G) Data Out tw(TRG) td(GLRH)
Figure 31. Read-Cycle Timing With CASx-Controlled Output
40
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rd) tw(RL) td(RLCH) RAS tw(RH) td(CLRH) td(RLCL) td(CHRL) CASx tw(CH) td(RLCA) th(RA) th(RLCA) tsu(RA) tsu(CA) A0 - A8 Row th(SFR) Column td(CACH) th(CLCA) td(CARH) tw(CL)
tt
tsu(SFR) DSF
td(CLGH) tsu(TRG) th(TRG) TRG tsu(rd) WE tdis(G) td(DGL) DQ0 - DQ15 Data In td(GLZ) td(CLZ) ta(C) ta(CA) ta(R) For TMS551x0, RAS high does not disable the output. For TMS551x1, both RAS and CASx must be high to disable the output. ta(G) Data Out tdis(RH) th(RHrd) tw(TRG) td(GLRH)
th(CHrd)
Figure 32. Read-Cycle Timing With RAS-Controlled Output
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS td(RLCH) tt td(RLCL) td(CHRL) CASx th(RLCA) th(RA) td(RLCA) tsu(RA) A0 - A8 tsu(SFR) th(RSF) th(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WCH) tsu(WMR) th(RLW) th(RWM) WE 1 th(CLW) tsu(WCL) tw(WL) tsu(WRH) th(SFC) Row Column tsu(SFC) td(CACH) tsu(CA) th(CLCA) td(CARH) tw(CL) td(CLRH) tw(RH) tt td(CHRL) tw(CH)
tsu(DQR) th(RDQ) DQ0 - DQ15 2
th(CLD) tsu(DCL) th(RLD) 3
In early-write operations, DQ0 - DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx.
Figure 33. Early-Write-Cycle Timing Table 7. Early-Write-Cycle State Table
CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Valid data Valid data Valid data
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SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) RAS tw(RL) td(RLCH) tt td(CHRL) td(RLCL) CASx td(RLCA) th(RLCA) tsu(CA) th(RA) tsu(RA) A0 - A8 Row th(RSF) tsu(SFR) th(SFR) DSF tsu(rd) TRG tsu(TRG) td(GHD) th(RLW) tsu(WMR) th(RWM) WE tsu(DQR) 1 tsu(DWL) th(RDQ) th(RLD) DQ0 - DQ15 2 3 th(WLD) th(WLG) tw(WL) tsu(WRH) tsu(WCH) th(CLW) tsu(SFC) th(SFC) Column th(CLCA) td(CACH) td(CARH) tw(CH) td(CLRH) td(CHRL) tt tw(CL) tw(RH)
Figure 34. Late-Write-Cycle Timing (Output-Enable-Controlled Write) Table 8. Late-Write-Cycle State Table
CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Valid data Valid data Valid data
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rdW) tw(RL) td(RLCH) RAS td(CHRL) td(RLCL) CASx tsu(RA) th(RA) tsu(CA) th(RLCA) td(RLCA) A0 - A8 Row th(RSF) tsu(SFR) th(SFR) DSF th(TRG) tsu(rd) td(CAWL) tw(TRG) TRG th(RLW) tsu(TRG) tsu(WMR) th(RWM) WE 1 ta(R) tsu(DQR) th(RDQ) DQ0 - DQ15 2 ta(G) th(CLW) td(CLWL) td(DCL) td(CLGH) ta(CA) td(RLWL) td(DGL) ta(C) Valid Out tdis(G) tw(WL)
th(WLD)
td(CLRH) tw(CL) tw(CH) th(CLCA) td(CACH) td(CARH) Column
tw(RH) td(CHRL)
th(SFC) tsu(SFC)
tsu(WCH) tsu(WRH)
th(WLG)
td(GHD) tsu(DWL) 3
Figure 35. Read-Modify-Write-Cycle Timing Table 9. Read-Modify-Write-Cycle State Table
CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Valid data Valid data Valid data
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS td(RLCH) td(RLCL) CASx th(CLCA) th(RLCA) td(RLCA) tsu(RA) th(RA) A0 - A8 Row th(RSF) tsu(SFR) th(SFR) tsu(SFC) th(SFC) Block Address tsu(CA) td(CARH) td(CACH) tw(CH) tt td(CHRL) td(CLRH) tw(CL) tw(RH) tt td(CHRL)
DSF tsu(TRG) TRG th(RWM) tsu(WMR) tsu(WCH) tsu(WRH) tsu(WCL) th(CLW) th(RLW) WE 1 tw(WL) th(RLD) tsu(DCL) th(CLD) 2 3 th(TRG)
tsu(DQR) th(RDQ) DQ0 - DQ15
For 4-column block write (TMS5516x), block address is A2 - A8; for 8-column block write (TMS5517x), block address is A3 - A8. In early-write operations, DQ0 - DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx.
Figure 36. Block-Write-Cycle Timing (Early Write) Table 10. Block-Write-Cycle State Table
CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Column mask Column mask Column mask
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS tt td(CHRL) CASx td(RLCA) th(RLCA) th(RA) tsu(RA) A0 - A8 tsu(SFR) th(SFR) DSF tsu(TRG) TRG td(GHD) th(RLW) tsu(WMR) th(RWM) WE 1 tsu(DQR) th(RDQ) th(RLD) DQ0 - DQ15 2 3 tsu(WRH) th(WLG) tw(WL) tsu(DWL) th(WLD) th(CLW) tsu(WCH) Row th(RSF) tsu(SFC) Block Address th(SFC) td(CARH) tsu(CA) th(CLCA) td(CACH) td(RLCL) td(RLCH) td(CLRH) tw(CL) tw(RH) tt td(CHRL) tw(CH)
For 4-column block write (TMS5516x), block address is A2 - A8; for 8-column block write (TMS5517x), block address is A3 - A8. In late-write operations, DQ0 - DQ15 are all latched on the first falling edge of WE. Thus tsu(DWL) and th(WLD) are referenced only to the first falling edge of WE.
Figure 37. Block-Write-Cycle Timing (Late Write) Table 11. Block-Write-Cycle State Table
CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Column mask Column mask Column mask
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS tt td(RLCL) td(CHRL) tw(CL) CASx th(RA) tsu(RA) A0 - A8 tsu(SFC) Refresh Row tw(CH) td(RLCH) td(CLRH) tt td(CHRL) tw(RH)
tsu(SFR) th(RSF) th(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR)
th(SFC)
tsu(WCH) tsu(WRH) th(RLW)
th(RWM) WE
th(CLW) tsu(WCL) tw(WL) tsu(DCL) th(CLD) th(RLD)
DQ0 - DQ15
Write Mask
In early-write operations, DQ0 - DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx.
Figure 38. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS td(RLCH) tt td(CHRL) td(RLCL) CASx th(RA) tsu(RA) A0 - A8 th(RSF) tsu(SFR) th(SFR) DSF tsu(SFC) th(SFC) Refresh Row td(CLRH) td(CHRL) tt tw(CL) tw(CH) tw(RH)
TRG tsu(TRG) td(GHD) th(RLW) tsu(WMR) th(RWM) WE tsu(DWL)
tsu(WRH) tsu(WCH) th(CLW)
th(WLG) tw(WL)
th(WLD) th(RLD) DQ0 - DQ15 Write Mask
Figure 39. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)
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SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS td(RLCH) tt td(CHRL) CASx th(RA) tw(CH) td(RLCL) tw(CL) td(CLRH) td(CHRL) tw(RH) tt
tsu(RA)
Refresh Row
A0 - A8 th(SFC) th(RSF) tsu(SFR) th(SFR) DSF tsu(TRG) th(TRG) TRG tsu(WCH) tsu(WRH) th(RLW) th(RWM) tsu(WCL) WE tw(WL) tsu(DCL) th(CLD) th(RLD) DQ0 - DQ15 Valid Color Input th(CLW) tsu(SFC)
tsu(WMR)
In early-write operations, DQ0 - DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx.
Figure 40. Load-Color-Register-Cycle Timing (Early-Write Load)
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W) tw(RL) RAS td(RLCH) tt td(RLCL) td(CHRL) CASx th(RSF) th(RA) tsu(RA) A0 - A8 tsu(SFR) th(SFR) DSF tsu(TRG) TRG td(GHD) th(RLW) tsu(WMR) th(WLG) tw(WL) WE tsu(DWL) th(WLD) th(RLD) DQ0 - DQ15 Valid Color Input th(CLW) tsu(WRH) tsu(WCH) tsu(SFC) th(SFC) Refresh Row tw(CL) tw(CH) td(CLRH) td(CHRL) tw(RH) tt
Figure 41. Load-Color-Register-Cycle Timing (Late-Write Load)
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH) tw(RL)P RAS td(RLCL) td(CHRL) CASx td(RLCA) td(RLCH) tsu(RA) th(RA) th(RLCA) A0 - A8 Row th(SFR) tsu(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR) tsu(rd) WE ta(C) ta(CA) td(DGL) ta(R) DQ0 - DQ15 Data In td(DCL) Data Out tdis(CH) ta(G) ta(CP) ta(CA) tdis(G) Data Out th(RHrd) Column tsu(CA) th(CLCA) tc(P) td(CACH) td(CARH) Column td(CLGH) tw(CH) td(CLRH) tt
tw(CL)
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write mode (normal, block write, etc.).
Figure 42. Enhanced-Page-Mode Read-Cycle Timing (TMS551x0)
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH) tw(RL)P RAS td(RLCL) td(CHRL) CASx td(RLCA) td(RLCH) tsu(RA) th(RA) th(RLCA) A0 - A8 Row th(SFR) tsu(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR) tsu(rd) WE ta(C) ta(CA) td(DGL) ta(R) DQ0 - DQ15 Data In ta(G) ta(CP) Data Out th(CLQ) ta(CA) tdis(WL) tdis(RH) tdis(G) Data Out th(RHrd) Column tsu(CA) th(CLCA) tc(P) td(CACH) td(CARH) Column td(CLGH) tw(CH) td(CLRH) tt
tw(CL)
td(DCL) NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write mode (normal, block write, etc.).
Figure 43. Extended-Data-Output Read-Cycle Timing (TMS551x1)
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P RAS td(RLCH) td(RLCL) td(CHRL) CASx tsu(RA) td(RLCA) tsu(CA) th(RA) th(CLCA) th(RLCA) A0 - A8 Row tsu(SFR) th(RSF) th(SFR) tsu(SFC) DSF 1 tsu(TRG) th(TRG) TRG tsu(WMR) th(RWM) WE 3 tsu(DQR) tsu(DCL) th(RDQ) th(RLD) DQ0 - DQ15 4 5 5 tsu(DWL) th(CLD) th(WLD) tsu(WCH) tw(WL) See Note A tsu(WCH) tsu(WRH) 2 th(SFC) tsu(SFC) 2 th(SFC) Column tw(CL) tc(P) tw(CH) tw(RH) td(CLRH) td(CHRL)
td(CACH) td(CARH) Column
DQ0 - DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. In early-write operations, tsu(DWL) and th(WLD) are not applicable; tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx. In late-write operations, tsu(DCL) and th(CLD) are not applicable. NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications are not violated.
Figure 44. Enhanced-Page-Mode Write-Cycle Timing Table 12. Enhanced-Page-Mode Write-Cycle State Table
CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit Load-write-mask register on either the first falling edge of WE or the falling edge of CASx, whichever occurs later. STATE 1 L L L H 2 L L L L 3 H L L H 4 Don't care Write mask Don't care Don't care 5 Valid data Valid data Valid data Write mask
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P RAS td(RLCH) td(CHRL) CASx td(RLCA) tsu(RA) th(RLCA) A0 - A8 Row th(SFR) tsu(SFR) tsu(SFC) DSF 1 2 tsu(rd) tsu(WCH) 2 tsu(WCH) td(DCL) td(CLGH) td(CLGH) tsu(TRG) TRG tsu(WMR) th(RWM) WE 3 tsu(DQR) td(DCL) th(RDQ) DQ0 - DQ15 4 tsu(DWL) Valid Out ta(G) td(DGL) ta(R) td(GHD) ta(C) 5 td(DGL) Valid Out tdis(G) ta(CP) 5 ta(C) ta(CA) th(WLD) th(WLD) td(GHD) tsu(DWL) tw(TRG) tw(WL) tw(TRG) tsu(WRH) Column th(SFC) Column tsu(SFC) th(SFC) th(RA) tsu(CA) td(RLCL) tc(RDWP) tw(CH) td(CLRH) td(CHRL) tw(RH)
tw(CL) td(CARH) th(CLCA) td(CACH)
td(CLWL) td(CAWL) td(RLWL) th(TRG)
NOTE A: A read cycle or a write cycle can be mixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
Figure 45. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing Table 13. Enhanced Page-Mode Read-Modify-Write-Cycle State Table
CYCLE Write operation (nonmasked) Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit Load-write-mask register on either the first falling edge of WE or the falling edge of CASx, whichever occurs later. STATE 1 L L L H 2 L L L L 3 H L L H 4 Don't care Write mask Don't care Don't care 5 Valid data Valid data Valid data Write mask
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH) tw(RL)P RAS td(RLCL) td(CHRL) CASx td(RLCA) td(RLCH) tsu(RA) th(RA) th(RLCA) A0 - A8 Row th(SFR) tsu(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR) tsu(rd) WE ta(CA) td(DGL) ta(R) DQ0 - DQ15 Data In td(DCL) ta(G) tdis(WL) Data Out Data In tsu(DCL) ta(C) tw(WL) th(CLW) tsu(WCL) Column tsu(CA) th(CLCA) tc(P) td(CACH) td(CARH) Column td(CLGH) tw(CH) td(CLRH) tt
tw(CL)
th(CLD)
Figure 46. Extended-Data-Output Read-Followed-by-Write-Cycle Timing (TMS551x1)
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P RAS td(RLCH) td(RLCL) td(CHRL) CASx td(RLCA) tsu(CA) th(RA) tsu(RA) A0 - A8 th(SFR) tsu(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR) th(RWM) WE 1 tsu(DWL) tsu(DQR) th(RDQ) DQ0 - DQ15 th(CLD) th(WLD) tsu(DCL) th(RLD) 2 3 3 See Note A tsu(WCH) tw(WL) tsu(WCH) tsu(WRH) Row th(RLCA) Block Address th(SFC) tsu(SFC) tc(P) tw(CH) tw(CL) td(CLRH) td(CHRL) tw(RH)
th(CLCA) td(CACH) td(CARH) Block Address th(SFC) tsu(SFC)
For 4-column block write (TMS5516x), block address is A2 - A8; for 8-column block write (TMS5517x), block address is A3 - A8. DQ0 - DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. In early-write operations, tsu(DWL) and th(WLD) are not applicable; tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx. In late-write operations, tsu(DCL) and th(CLD) are not applicable. NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications are not violated.
Figure 47. Enhanced-Page-Mode Block-Write-Cycle Timing Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table
CYCLE Block-write operation (nonmasked) Block-write operation with nonpersistent write-per-bit Block-write operation with persistent write-per-bit STATE 1 H L L 2 Don't care Write mask Don't care 3 Column mask Column mask Column mask
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(rd) tw(RL) RAS tt td(CHRL) td(RHCL) tw(RH) td(CHRL)
CASx tsu(RA) A0 - A8 Row th(RA)
DSF th(TRG)
tsu(TRG) TRG
WE
DQ0 - DQ15
Hi-Z
Figure 48. RAS-Only Refresh-Cycle Timing
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(rd) tw(RH) RAS td(RHCL) td(CLRL) CASx td(CHRL) tsu(RA) A0 - A8 tsu(SFR) DSF 2 1 th(SFR) th(RA) td(RLCH) tw(RL) tt
TRG tsu(WMR) WE 3 th(RWM)
DQ0 - DQ15
Hi-Z
Figure 49. CBR-Refresh-Cycle TIming Table 15. CBR-Cycle State Table
CYCLE CBR refresh with option reset CBR refresh with no reset (CBRN) CBR refresh with stop point set and no reset (CBRS) STATE 1 Don't care Don't care Stop address 2 L H H 3 H H L
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Memory Read Cycle tc(rd) tw(RL) RAS td(CARH) td(CHRL) CASx td(RLCA) th(CLCA) tsu(CA) th(RA) tsu(RA) A0 - A8 Row Col 1 tsu(SFR) th(SFR) DSF 2 th(RHrd) tsu(TRG) th(TRG) TRG tsu(rd) WE ta(R) DQ0 - DQ15 Data Out ta(G) ta(C) 3 td(GLRH) tsu(WMR) th(RWM) 3 tsu(WMR) th(RWM) 3 tsu(WMR) th(RWM) 2 tsu(RA) th(RA) 1 tsu(SFR) th(SFR) 2 1 tsu(SFR) th(SFR) th(RA) tw(CL) tt td(RLCH) tw(RH) tw(RL) Refresh Cycle tc(rd) tw(RH) tc(rd) Refresh Cycle
tsu(RA)
tsu(RA) th(RA)
tdis(CH) tdis(G)
Figure 50. Hidden-Refresh-Cycle Timing Table 16. Hidden-Refresh-Cycle State Table
CYCLE CBR refresh with option reset CBR refresh with no reset (CBRN) CBR refresh with stop point set and no option reset (CBRS) STATE 1 Don't care Don't care Stop address 2 L H H 3 H H L
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(TRD) tw(RL) td(RLCL) RAS td(CHRL) CASx td(RLCH) td(CARH) td(RLCA) th(RA) tsu(RA) A0 - A8 tsu(SFR) DSF tsu(TRG) TRG th(RWM) tsu(WMR) WE DQ0 - DQ15 tw(SCH) See Note A tw(SCL) td(CASH) th(TRG) tw(GH) Row th(RLCA) tw(CL) tsu(CA) th(CLCA) See Note C Tap Point A0 - A8 th(SFR) tw(RH)
td(SCTR)
Hi-Z td(CLSH) td(RLSH)
SC ta(SQ) th(SHSQ) SQ Old Data Old Data td(GHQSF) QSF H SE L td(RLQSF) td(CLQSF) th(SHSQ)
tw(SCH) tc(SC) ta(SQ) New Data
Tap Point Bit A7
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The memory-to-data-register-transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written into from the 256 corresponding columns of the selected row. B. Once data is transferred into the data registers, SAM is in the serial-read mode (that is, SQx is enabled), allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition of SC. C. A0 - A7: register tap point; A8: identifies the DRAM half of the row D. Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min.
Figure 51. Full-Register-Transfer Read Timing, Early-Load Operations
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PARAMETER MEASUREMENT INFORMATION
tc(TRD) tw(RL) RAS td(CHRL) CASx td(RLCA) th(RA) tsu(RA) th(RLCA) th(CLCA) A0 - A8 tsu(SFR) DSF tsu(TRG) TRG td(CLTH) td(CAGH) td(RLTH) th(RWM) td(THRL) td(THRH) tw(GH) Row Tap Point A0 - A8 th(SFR) See Note C td(RLCL) td(RLCH) tw(CL) tsu(CA) tw(RH)
See Note D
tsu(WMR) WE
td(SCTR) DQ0 - DQ15 SC th(SHSQ) SQ Old Data See Note A Hi-Z tw(SCH) ta(SQ) tw(SCL) Old Data th(SHSQ) Old Data td(GHQSF) QSF H SE L NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The memory to data register-transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written into from the 256 corresponding columns of the selected row. B. Once data is transferred into the data registers, SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition of SC. C. A0 - A7: register tap point; A8: identifies the DRAM half of the row D. Late-load operation is defined as td(THRH) < 0 ns. td(RLQSF) td(CLQSF) Tap Point Bit A7 New Data ta(SQ) tc(SC) td(THSC) See Note B
Figure 52. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(TRD) tw(RL) RAS td(CHRL) td(RLCH) td(RLCA) CASx th(RA) tsu(RA) A0 - A8 tsu(TRG) th(TRG) TRG th(SFR) tsu(SFR) DSF th(RWM) tsu(WMR) WE DQ0 - DQ15 td(MSRL) tc(SC) tw(SCH) SC Bit 127 or 255 tw(SCL) ta(SQ) th(SHSQ) SQ Bit 126 or Bit 254 Bit 127 or Bit 255 td(SCQSF) td(SCQSF) QSF MSB Old New MSB Tap Point M ta(SQ) ta(SQ) Bit 127 or Bit 255 Bit 255 or 127 Row Tap Point A0 - A8 See Note A th(CLCA) tsu(CA) tw(CL) tw(CH) td(RLCL) tw(RH)
Hi-Z td(RHMS) tc(SC) Tap Point N tw(SCL) Tap Point N ta(SQ)
Tap Point M
SE VIL NOTE A: A0 - A6: tap point of the given half; A7: don't care; A8: identifies the DRAM half of the row
Figure 53. Split-Register-Transfer Read Timing
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PARAMETER MEASUREMENT INFORMATION
RAS tsu(TRG) TRG tc(SC) tc(SC) tw(SCH) tw(SCH) tw(SCL) SC ta(SQ) th(SHSQ) SQ ta(SE) SE NOTE A: While reading data through the serial-data register, TRG is a don't care, except TRG must be held high when RAS goes low. This is to avoid the initiation of a register-data transfer operation. th(SHSQ) Valid Out tw(SCL) tw(SCH) th(TRG)
ta(SQ) th(SHSQ) Valid Out
ta(SQ)
Valid Out
Figure 54. Serial-Read Timing (SE = VIL )
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS tsu(TRG) TRG tc(SC) tc(SC) tw(SCH) tw(SCH) SC ta(SQ) ta(SQ) th(SHSQ) ta(SE) ta(SQ) th(SHSQ) Valid Out Valid Out tw(SCL) tw(SCL) tw(SCH) th(TRG)
SQ
Valid Out
Valid Out
tdis(SE) SE NOTE A: While reading data through the serial-data register, TRG is a don't care except TRG must be held high when RAS goes low. This is to avoid the initiation of a register-data transfer operation.
Figure 55. Serial-Read Timing (SE-Controlled Read)
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SMVS464 - MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS CASx ADDR Row Tap1 (low) TRG DSF Row Tap1 (high) Row Tap2 (low) Row Tap2 (high)
CASE I SC Tap1 (low) QSF Bit Tap1 127 (high) Bit 255 Tap2 (low) Bit 127
CASE II SC Tap1 (low) QSF Bit Tap1 127 (high) Bit 255 Tap2 (low) Bit 127
CASE III SC Tap1 (low) QSF Full-Register-Transfer Read Split Register to the High Half of the Data Register Split Register to the Low Half of the Data Register Split Register to the High Half of the Data Register Bit Tap1 127 (high) Bit 255 Tap2 (low) Bit 127
NOTES: A. In order to achieve proper split-register operation, a full-register-transfer read should be performed before the first split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read cycle and the first split-register cycle. B. A split-register-transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the inactive half. After the td(MSRL) is met, the split-register-transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 56. Split-Register Operating Sequence
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TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 - MARCH 1996
MECHANICAL DATA
DGH (R-PDSO-G64) PLASTIC SMALL-OUTLINE PACKAGE
0,80 64
0,45 0,25
0,12 M 33
12,12 11,96
14,50 14,00
0,15 NOM
Gage Plane 0,25 0- 5 26,42 26,17 0,70 0,40
1
32
Seating Plane 2,38 MAX 0,00 MIN 0,10 4040068 / B 10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold flash or protrusion. Maximum mold protrusion is 0,125.
device symbolization
TI TMS551xx W B Y M DGH Package Code LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code -SS Speed Code (- 60, -70)
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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