 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 HIGH SPEED RAIL TO RAIL OUTPUT VIDEO AMPLIFIERS FEATURES D High Speed - 100 MHz Bandwidth (-3 dB, G= 2) - 900 V/s Slew Rate APPLICATIONS D D D D D Video Line Driver Imaging DVD / CD ROM Active Filtering General Purpose Signal Chain Conditioning D Excellent Video Performance - 25 MHz Bandwidth (0.1 dB, G = 2) - 0.007% Differential Gain - 0.007 Differential Phase D Rail-to-Rail Output Swing D High Output Drive, IO = 100 mA (typ) D Ultralow Distortion D Wide Range of Power Supplies - VS = 3 V to 15 V - HD2 = -78 dBc (f = 5 MHz, RL = 150) - HD3 = -85 dBc (f = 5 MHz, RL = 150) VOUT VS- IN+ - VO = -4.5 / 4.5 (RL = 150 ) SN10501 DBV PACKAGE (TOP VIEW) 1 2 3 4 IN - 5 VS+ DESCRIPTION The SN10501 family is a set of rail-to-rail output single, dual, and triple low-voltage, high-output swing, lowdistortion high-speed amplifiers ideal for driving data converters, video switching, or low distortion applications. This family of voltage feedback amplifiers can operate from a single 15-V power supply down to a single 3-V power supply while consuming only 14 mA of quiescent current per channel. In addition, the family offers excellent ac performance with 100-MHz bandwidth, 900-V/s slew rate and harmonic distortion (THD) at -78 dBc at 5 MHz. VIDEO DRIVE CIRCUIT VS+ DEVICE SN10501 SN10502 SN10503 DESCRIPTION Single Dual Triple DIFFERENTIAL GAIN vs NUMBER OF LOADS 0.20 + Differential Gain - % 0.18 10 F Video In 75 3 4 5 + - 2 VS- 1 k 1 k + SN10501 1 0.1 F 75 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 Gain = 2 Rf = 1.5 k 40 IRE - NTSC Worst Case 100 IRE Ramp VO 75 VS = 5 V VS = 5 V 10 F 0.1 F 1 2 3 4 5 Number of Loads - 150 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage, VS Input voltage, VI Output current, IO (2) Differential input voltage, VID Continuous power dissipation Maximum junction temperature, TJ Operating free-air temperature range, TA Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 16.5 V VS 150 mA 4V See Dissipation Rating Table PACKAGE DISSIPATION RATINGS PACKAGE DBV (5) JC (C/W) 55 38.3 26.9 JA (C/W) 324.1 176 122.6 POWER RATING TA 25C 385 mW 710 mW 1.02 W TA = 85C 201 mW 370 mW 530 mW 150C -40C to 85C -65C to 150C 300C D (8) D (14) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The SN1050x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, (VS+ and VS-) Dual supply Single supply 1.35 2.7 MAX 7.5 15 V UNIT Input common-mode voltage range VS- + 1.1 VS+ - 1.1 V PACKAGE/ORDERING INFORMATION TEMPERATURE PACKAGED DEVICES SINGLE ORDERABLE SN10501D -40C to 85C SN10501DR SN10501DBVR SN10501DBVT DUAL ORDERABLE SN10502D SN10502DR --- --- TRIPLE ORDERABLE SN10503D SN10503DR --- --- PACKAGE TYPE SOIC SOIC SOT23-5 SOT23-5 TRANSPORT MEDIA, QUANTITY Rails, 75 Tape and Reel, 2500 Tape and Reel, 3000 Tape and Reel, 250 PIN ASSIGNMENTS PACKAGE DEVICES SN10501 D PACKAGE (TOP VIEW) SN10502 D PACKAGE (TOP VIEW) SN10503 D PACKAGE (TOP VIEW) NC IN- IN+ VS- 1 2 3 4 8 7 6 5 NC VS+ VOUT NC 1OUT 1IN- 1IN+ VS- 1 2 3 4 8 7 6 5 VS+ 2OUT 2IN- 2IN+ NC - No internal connection NC NC NC VS+ 1IN+ 1IN- 1OUT 1 2 3 4 5 6 7 14 13 12 11 10 9 8 2OUT 2IN- 2IN+ VS- 3IN+ 3IN- 3OUT NC - No internal connection 2 www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 ELECTRICAL CHARACTERISTICS VS = 5 V, RL = 150 , and G = 2 unless otherwise noted TYP PARAMETER AC PERFORMANCE G = 1, VO = 100 mVPP Small signal bandwidth 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth(1) Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion Second harmonic distortion Third harmonic distortion Differential gain (NTSC, PAL) Differential phase (NTSC, PAL) Input voltage noise Input current noise Crosstalk (dual and triple only) G = 2, VO = 100 mVPP, Rf = 1 k G = 10, VO = 100 mVPP, Rf = 1 k G = 2, VO = 100 mVPP, Rf = 1 k G > 10, f = 1 MHz, Rf = 1 k G = 2, VO = 2.5 Vpp G = 2, VO = 2.5 Vpp G = -2, VO = 2 Vpp G = -2, VO = 2 Vpp G = 2, VO = 2 VPP, f = 5 MHz RL = 150 RL = 150 G = 2, R = 150 G = 2, R = 150 f = 1 MHz f = 1 MHz f = 5 MHz Ch-to-Ch -78 -85 0.007 0.007 13 0.8 -90 dBc dBc % nV/Hz pA/Hz dB Typ Typ Typ Typ Typ Typ Typ 170 100 12 25 120 57 900 25 52 MHz MHz MHz MHz MHz MHz V/s ns ns Typ Typ Typ Typ Typ Typ Min Typ Typ TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX (1) Full-power bandwidth = SR / 2Vpp DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Input bias current Input offset current INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Input resistance Input capacitance OUTPUT CHARACTERISTICS Output voltage swing Output current (sourcing) Output current (sinking) Output impedance POWER SUPPLY Specified operating voltage Maximum quiescent current Power supply rejection (PSRR) Per channel 5 14 75 7.5 18 62 7.5 20 60 7.5 22 60 V mA dB Max Max Min RL = 150 RL = 499 RL = 10 RL = 10 f = 1 MHz -4.5 / 4.5 -4.7 / 4.7 100 -100 0.02 -4.5 / 4.5 92 -92 -4.4 / 4.4 88 -88 -4.4 / 4.4 88 -88 V V mA mA Typ Min Min Min Typ Common-mode / differential VCM = 2 V -4 / 4 94 33 1 / 0.5 -3.9 / 3.9 70 65 65 V dB M pF Min Min Typ Max VO = 2 V VCM = 0 V VCM = 0 V VCM = 0 V 100 12 0.9 100 80 25 3 500 75 30 5 700 75 30 5 700 dB mV A nA Min Max Max Max 3 SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V, RL = 150 , and G = 2 unless otherwise noted TYP PARAMETER AC PERFORMANCE G = 1, VO = 100 mVPP Small signal bandwidth 0.1 dB flat bandwidth Gain bandwidth product Full-power bandwidth(1) Slew rate Settling time to 0.1% Settling time to 0.01% Harmonic distortion Second harmonic distortion Third harmonic distortion Differential gain (NTSC, PAL) Differential phase (NTSC, PAL) Input voltage noise Input current noise Crosstalk (dual and triple only) G = 2, VO = 100 mVPP, Rf = 1.5 k G = 10, VO = 100 mVPP, Rf = 1.5 k G = 2, VO = 100 mVPP, Rf = 1.5 k G > 10, f = 1 MHz, Rf = 1.5 k G = 2, VO = 4 V step G = 2, VO = 4 V step G = -2, VO = 2 V step G = -2, VO = 2 Vpp G = 2, VO = 2 VPP, f = 5 MHz RL = 150 RL = 150 G = 2, R = 150 G = 2, R = 150 f = 1 MHz f = 1 MHz f = 5 MHz Ch-to-Ch -82 -88 0.014 0.011 13 0.8 -90 dBc dBc % nV/Hz pA/Hz dB Typ Typ Typ Typ Typ Typ Typ 170 100 12 10 120 60 750 27 48 MHz MHz MHz MHz MHz MHz V/s ns ns Typ Typ Typ Typ Typ Typ Min Typ Typ TEST CONDITIONS 25C 25C OVER TEMPERATURE 0C to 70C -40C to 85C UNITS MIN/ MAX (1) Full-power bandwidth = SR / 2Vpp DC PERFORMANCE Open-loop voltage gain (AOL) Input offset voltage Input bias current Input offset current INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio Input resistance Input capacitance OUTPUT CHARACTERISTICS Output voltage swing Output current (sourcing) Output current (sinking) Output impedance POWER SUPPLY Specified operating voltage Maximum quiescent current Power supply rejection (PSRR) Per channel 5 12 70 15 15 62 15 17 60 15 19 60 V mA dB Max Max Min RL = 150 RL = 499 RL = 10 RL = 10 f = 1 MHz 0.5 / 4.5 0.2 / 4.8 95 -95 0.02 0.3 / 4.7 85 -85 0.4 / 4.6 80 -80 0.4 / 4.6 80 -80 V V mA mA Typ Min Min Min Typ Common-mode / differential VCM = 1.5 V to 3.5 V 1/4 96 33 1 / 0.5 1.1 / 3.9 70 65 65 V dB M pF Min Min Typ Max VO = 1.5 V to 3.5 V VCM = 2.5 V VCM = 2.5 V VCM = 2.5 V 100 12 0.9 100 80 25 3 500 75 30 5 700 75 30 5 700 dB mV A nA Min Max Max Max 4 www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Small signal frequency response Large signal frequency response Slew rate vs Output voltage step Harmonic distortion vs Frequency Voltage and current noise vs Frequency Differential gain vs Number of loads Differential phase vs Number of loads Quiescent current vs Supply voltage Output voltage vs Load resistance Open-loop gain and phase vs Frequency Rejection ratio vs Frequency Rejection ratio vs Case temperature Common-mode rejection ratio vs Input common-mode range Crosstalk vs Frequency Input bias and offset current vs Case temperature 1, 2 3 4, 5 6, 7 8 9, 11 10, 12 13 14 15 16 17 18, 19 20 21, 22 SMALL SIGNAL FREQUENCY RESPONSE 8 7 6 Small Signal Gain - dB Gain = 2 SMALL SIGNAL FREQUENCY RESPONSE LARGE SIGNAL FREQUENCY RESPONSE 8 7 6 Small Signal Gain - dB Gain = 2 Large Signal Gain - dB 8 7 6 5 4 3 2 1 0 1M 10 M 100 M f - Frequency - Hz 1G 100 k 1M 10 M 100 M 1G f - Frequency - Hz Gain = 2 RL = 150 RF = 1 k VO = 2 VPP VS = 5 V VS = 5 V VS = 5 V 5 4 3 2 1 0 -1 -2 RL = 150 RF = 1 k VO = 100 mVPP VS = 5 V 5 4 3 2 1 0 RL = 499 RF = 1.5 k VO = 100 mVPP VS = 5 V Gain = 1 -1 10 M 100 M 1G Gain = 1 100 k 1M -2 100 k f - Frequency - Hz Figure 1 SLEW RATE vs OUTPUT VOLTAGE STEP 1200 1000 SR - Slew Rate - V/ s 800 Fall 600 400 Gain = 2 RL = 150 RF = 1 k VS = 5 V 800 700 Rise SR - Slew Rate - V/ s 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 0 0.5 1 Figure 2 SLEW RATE vs OUTPUT VOLTAGE STEP 0 Gain = 2 RL = 150 RF = 1 k VS = 5 V -10 Harmonic Distortion - dBc Fall Rise -20 -30 -40 -50 Figure 3 HARMONIC DISTORTION vs FREQUENCY Gain = 2 RL = 150 VO = 2 VPP VS = 5 V HD2 -60 -70 -80 -90 -100 HD3 200 0 VO - Output Voltage Step - V 1.5 2 2.5 3 3.5 4 0.1 VO - Output Voltage Step - V 1 10 f - Frequency - MHz 100 Figure 4 Figure 5 Figure 6 5 SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com HARMONIC DISTORTION vs FREQUENCY 0 -10 Harmonic Distortion - dBc -20 -30 -40 -50 -60 -70 -80 -90 -100 0.1 HD2 HD3 1 1 10 f - Frequency - MHz 100 Gain = 2 RL = 150 VO = 2 VPP VS = 5 V 100 Hz VOLTAGE AND CURRENT NOISE vs FREQUENCY 10 Hz 0.20 0.18 0.16 I n - Current Noise - pA/ Differential Gain - % 0.14 0.12 0.10 0.08 0.06 0.04 0.02 1k 10 k 100 k 1M 0.1 10 M 0 0 DIFFERENTIAL GAIN vs NUMBER OF LOADS Gain = 2 Rf = 1.5 k 40 IRE - NTSC Worst Case 100 IRE Ramp Vn - Voltage Noise - nV/ Vn 1 In 10 VS = 5 V VS = 5 V 1 2 3 4 5 f - Frequency - Hz Number of Loads - 150 Figure 7 DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.4 0.35 Differential Phase - 0.3 0.25 0.2 0.15 0.1 0.05 0 0 1 2 3 4 5 Number of Loads - 150 VS = 5 V VS = 5 V Gain = 2 Rf = 1.5 k 40 IRE - NTSC Worst Case 100 IRE Ramp 0.20 0.18 0.16 Differential Gain - % 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 1 Figure 8 DIFFERENTIAL GAIN vs NUMBER OF LOADS Gain = 2 Rf = 1.5 k 40 IRE - PAL Worst Case 100 IRE Ramp Figure 9 DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.4 0.35 Differential Phase - 0.3 0.25 0.2 0.15 0.1 VS = 5 V 0.05 0 VS = 5 V VS = 5 V Gain = 2 Rf = 1.5 k 40 IRE - PAL Worst Case 100 IRE Ramp VS = 5 V 2 3 4 5 0 1 2 3 4 5 Number of Loads - 150 Number of Loads - 150 Figure 10 QUIESCENT CURRENT vs SUPPLY VOLTAGE 22 20 VO - Output Voltage - V Quiescent Current - mA/Ch 18 16 14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 TA = -40C TA = 85C TA = 25C 5 4 3 2 1 0 -1 -2 -3 -4 -5 10 VS - Supply Voltage - V Figure 11 OUTPUT VOLTAGE vs LOAD RESISTANCE 110 100 90 Open-Loop Gain - dB 80 70 60 50 40 30 20 10 0 -10 100 1k RL - Load Resistance - 10 k 100 Figure 12 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 220 VS = 5 V, 5 V, and 3.3 V 200 180 160 140 120 100 80 60 40 20 0 -20 1 k 10 k 100 k 1 M 10 M 100 M 1 G f - Frequency - Hz Phase - TA = -40 to 85C Figure 13 Figure 14 Figure 15 6 www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 REJECTION RATIO vs FREQUENCY 100 90 80 Rejection Ratios - dB Rejection Ratio - dB 70 60 50 40 30 20 10 0 0.1 1 10 f - Frequency - MHz 100 PSRR CMMR VS = 5 V, 5 V, and 3.3 V 90 80 100 REJECTION RATIO vs CASE TEMPERATURE VS = 5 V, 5 V, and 3.3 V CMMR CMRR - Common-Mode Rejection Ratio - dB COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE 100 90 80 70 60 50 40 30 20 10 0 -6 -4 -2 0 2 4 6 VICR - Input Common-Mode Voltage Range - V VS = 5 V TA = 25C PSRR 70 60 50 40 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - C Figure 16 Figure 17 COMMON-MODE REJECTION RATIO vs INPUT COMMON-MODE RANGE CROSSTALK vs FREQUENCY 120 Crosstalk all Channels 100 Crosstalk - dB 80 Figure 18 CMRR - Common-Mode Rejection Ratio - dB 100 90 80 70 60 50 40 30 20 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VICR - Input Common-Mode Voltage Range - V 0 VS = 5 V TA = 25C 60 40 20 VS = 5 V, 5 V, and 3.3 V Gain = 1 RL = 150 VIN= -1 dB TA = 25C 1M 10 M 100 M 1G 0 100 k f - Frequency - Hz Figure 19 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 0.84 VS = 5 V I OS - Input Offset Current - nA I IB - Input Bias Current - A I IB - Input Bias Current - A 0.82 0.8 0.78 0.76 0.74 0.72 IIB- IOS IIB+ -5 -10 -15 -20 5 0 0.88 10 Figure 20 INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 0.9 VS = 5 V IOS 0.86 0.84 0.82 0.8 IIB- 0.78 -25 IIB+ -5 -10 -15 -20 5 0 I OS - Input Offset Current - nA -25 0.7 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C -30 0.76 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 Case Temperature - C Figure 21 Figure 22 7 SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com APPLICATION INFORMATION 5V +VS + 50 Source HIGH-SPEED OPERATIONAL AMPLIFIERS 100 pF + 49.9 0.1 F 6.8 F The SN10501 operational amplifiers are a family of single, dual, and triple rail-to-rail output voltage feedback amplifiers. The SN10501 family combines both a high slew rate and a rail-to-rail output stage. VI _ SN10501 VO 499 Rf 1.3 k Rg 1.3 k Applications Section Contents 0.1 F 6.8 F 100 pF -VS + D D D D D D D D D D D Wideband, Noninverting Operation Wideband, Inverting Gain Operation Video Drive Circuits Single Supply Operation Power Supply Decoupling Techniques and Recommendations Active Filtering With the SN10501 Driving Capacitive Loads Board Layout Thermal Analysis Additional Reference Material Mechanical Package Drawings -5 V Figure 23. Wideband, Noninverting Gain Configuration WIDEBAND, INVERTING OPERATION Since the SN10501 family are general-purpose, wideband voltage-feedback amplifiers, several familiar operational amplifier applications circuits are available to the designer. Figure 24 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 23 are retained in an inverting circuit configuration. Inverting operation is one of the more common requirements and offers several performance benefits. The inverting configuration shows improved slew rates and distortion due to the pseudo-static voltage maintained on the inverting input. 5V +VS WIDEBAND, NONINVERTING OPERATION The SN10501 is a family of unity gain stable rail-to-rail output voltage feedback operational amplifiers designed to operate from a single 3-V to 15-V power supply. + + 100 pF 0.1 F 6.8 F Figure 23 is the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. Voltage feedback amplifiers, unlike current feedback designs, can use a wide range of resistors values to set their gain with minimal impact on their stability and frequency response. Larger-valued resistors decrease the loading effect of the feedback network on the output of the amplifier, but this enhancement comes at the expense of additional noise and potentially lower bandwidth. Feedback resistor values between 1 k and 2 k are recommended for most situations. CT 0.1 F 50 Source VI Rg 1.3 k RM 52.3 RT 649 SN10501 _ VO 499 Rf 1.3 k 0.1 F 100 pF -VS 6.8 F + -5 V Figure 24. Wideband, Inverting Gain Configuration 8 www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 VS+ + Video In 3 75 4 10 F 5 + - 2 75 VS- + 10 F 0.1 F 1 k 1 k SN10501 1 75 VO 0.1 F In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting Rg to 49.9 for input matching eliminates the need for RM but requires a 100- feedback resistor. This has an advantage of the noise gain becoming equal to 2 for a 50- source impedance--the same as the noninverting circuit in Figure 23. However, the amplifier output now sees the 100- feedback resistor in parallel with the external load. To eliminate this excessive loading, it is preferable to increase both Rg and Rf, values, as shown in Figure 24, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of Rg and RM. The last major consideration to discuss in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input. If the resistance is set equal to the total dc resistance looking out of the inverting terminal, the output dc error, due to the input bias currents, is reduced to (input offset current) multiplied by Rf in Figure 24, the dc source impedance looking out of the inverting terminal is 1.3 k || (1.3 k + 25.6 ) = 649 . To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, and power-supply feedback, RT is bypassed with a capacitor to ground. Figure 25. Cable Drive Application Differential gain and phase measure the change in overall small-signal gain and phase for the color subcarrier frequency (3.58 MHz in NTSC systems) vs changes in the large-signal output level (which represents luminance information in a composite video signal). The SN10501, with the typical 150- load of a single matched video cable, shows less than 0.007% / 0.007 differential gain/phase errors over the standard luminance range for a positive video (negative sync) signal. Similar performance is observed for negative video signals. In practice, similar performance is achieved even with three video loads as shown in Figure 26 due to the linear high-frequency output impedance of the SN10501. VS+ 0.1 F + Video In 3 4 10 F 5 + - 2 75 1 k 1 k VS- 0.1 F + 10 F 75 VO 75 SN10501 1 75 VO 75 75 VO VIDEO DRIVE CIRCUITS Most video distribution systems are designed with 75- series resistors to drive a matched 75- cable. In order to deliver a net gain of 1 to the 75- matched load, the amplifier is typically set up for a voltage gain of +2, compensating for the 6-dB attenuation of the voltage divider formed by the series and shunt 75- resistors at either end of the cable. The circuit shown in Figure 25 applies to this requirement. Both the gain flatness and the differential gain / phase performance of the SN10501 provides exceptional results in video distribution applications. 75 Figure 26. Video Distribution The above circuit is suitable for driving video cables, provided that the length does not exceed a few feet. If longer cables are driven, the gain of the SN10501 can be increased to accommodate cable drops. 9 SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com SINGLE SUPPLY OPERATION The SN10501 family is designed to operate from a single 3-V to 15-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure 27 demonstrate methods to configure an amplifier in a manner conducive for single supply operation. 4. Recommended values for power supply decoupling include a bulk decoupling capacitor (6.8 to 22 F), a mid-range decoupling capacitor (0.1 F) and a high frequency decoupling capacitor (1000 pF) for each supply. A 100 pF capacitor can be used across the supplies as well for extremely high frequency return currents, but often is not required. APPLICATION CIRCUITS Active Filtering With the SN10501 High-frequency active filtering with the SN10501 is achievable due to the amplifier's high slew rate, wide bandwidth, and voltage feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. A simple two-pole low pass filter is presented here as an example, with two poles at 25 MHz. 4.7 pF 50 Source +VS 50 Source + VI RT +VS 2 Rg 1.3 k +VS 2 49.9 _ SN10501 VO 499 Rf 1.3 k 1.3 k Rf VS 1.3 k VI 1.3 k 52.3 5V _ SN10501 50 Source VI 52.3 +VS 2 49.9 VO 33 pF Rg 1.3 k RT +VS 2 _ SN10501 + VO 499 -5 V + Figure 28. A Two-Pole Active Filter With Two Poles Between 90 MHz and 100 MHz Driving Capacitive Loads One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the SN10501 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. Figure 27. DC-Coupled Single Supply Operation Power Supply Decoupling Techniques and Recommendations Power supply decoupling is a critical aspect of any high-performance amplifier design process. Careful decoupling provides higher quality ac performance (most notably improved distortion performance). The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power supply inputs as possible, with the goal of minimizing the inductance of the path from ground to the power supply. Placement priority should put the smallest valued capacitors closest to the device. Use of solid power and ground planes is recommended to reduce the inductance along power supply return current paths, with the exception of the areas underneath the input and output pins. 2. 3. 10 www.ti.com SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the SN10501 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1-F decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2-F to 6.8-F) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. Careful selection and placement of external components preserves the high frequency performance of the SN10501. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire wound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 k, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. It has been suggested that a good starting point for design is to set the Rf to 1.3 k for low-gain, noninverting applications. Doing this automatically keeps the resistor noise terms low, and minimizes the effect of their parasitic capacitance. 4. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs Capacitive Load. Low parasitic capacitive loads (<4 pF) may not need an R(ISO), since the SN10501 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R(ISO) are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the SN10501 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of R(ISO) vs Capacitive Load. This setting does not preserve signal integrity or a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. 2. 3. 11 SN10501 SN10502 SN10503 SLOS408 - MARCH 2003 www.ti.com 5. PD - Maximum Power Dissipation - W Socketing a high speed part like the SN10501 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the SN10501 onto the board. 1.5 1.25 1 8-Pin D Package 0.75 5-Pin DBV Package 0.5 0.25 0 -40 THERMAL ANALYSIS The SN10501 family of devices does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150_ C is exceeded. 40 60 -20 0 20 TA - Ambient Temperature - C 80 JA = 170C/W for 8-Pin SOIC (D) JA = 324.1C/W for 5-Pin SOT-23 (DBV) TJ = 150C, No Airflow The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. Tmax-T A P Dmax + q JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (C). TA is the ambient temperature (C). JA = JC + CA JC is the thermal coefficient from the silicon junctions to the case (C/W). CA is the thermal coefficient from the case to ambient air (C/W). Figure 29. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. 12 MECHANICAL DATA MPDS018E - FEBRUARY 1996 - REVISED FEBRUARY 2002 DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,95 5 4 5X 0,50 0,30 0,20 M 1,70 1,50 3,00 2,60 0,15 NOM 1 3,00 2,80 3 Gage Plane 0,25 0-8 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX A MIN 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless |
Price & Availability of SN10501
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |