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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
D D D D D D D D D
Advanced, Integrated Speech Synthesizer for High-Quality Sound. Operates up to 12.32 MHz (Performs up to 12 MIPS) Very Low-Power Operation, Ideal For Hand-Held Devices. Low-Voltage Operation, Sustainable by Three Batteries Reduced Power Stand-By Modes, Less Than 10 A in Deep-Sleep Mode Supports High-Quality Synthesis Algorithms Such as MELP, CELP, LPC and ADPCM Contains 32K Words Onboard ROM (2K Words Reserved) 640-Word RAM 1.83 Mb of Onboard ROM for Up to 35 Minutes of Speech Data
D D D D D D D D
24 General-Purpose, Bit Configurable I/O 8 Inputs With Programmable Pullup Resistors and a Dedicated Interrupt (Key-Scan) Direct Speaker Driver, 32 (PDM) One-bit Comparator With Edge-Detection Interrupt Service Resistor-Trimmed Oscillator or 32.768 kHz Crystal Reference Oscillator Serial Scan Port for In-Circuit Emulation and Diagnostics The MSP50C605 Is Sold in Die Form or 100-Pin PJM Package. An Emulator Device Is Available in a Ceramic Package for Development
description
The MSP50C605 (C605) is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purpose I/O, onboard ROM, and direct speaker drive in a single package. The computational unit utilizes a powerful new DSP which gives the C605 unprecedented speed and computational flexibility compared with previous devices of its type. The C605 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality. The device consists of a micro-DSP core, embedded program, and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 32 bits of partially configurable I/O. The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor gives the C605 break-point capability in emulation. The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured in 32K 17-bit words. The total ROM space is divided into three areas: 1) The lower 2K words are reserved by Texas Instruments for the purposes of a built-in self-test 2) The upper 30K is for user program/data 3) A 1.83 Mb ROM provides data for up to 30 minutes of speech. The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
description (continued)
A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of three 8-bit wide general-purpose I/O ports and one 8-bit wide dedicated input port. The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup option (70-k minimum resistance) and a dedicated service interrupt. These features make the input port especially useful as a key-scan interface. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the C605 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The functional block diagram gives an overview of the C605 functionality.
functional block diagram
VSS 4 Scan Interface Break Point Emulation OTP Program Serial Comm. Power (EP)ROM Test-Area (reserved) User ROM INT vectors 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF VDD 5
SCANIN
224K bytes Data ROM
SCANOUT SCANCLK SYNC TEST
C port I/O Data Control 0x10 0x14
PC0-7 8
Core DACP DACM DAC 0x30 Instr. Decoder PCU RESET Initialization Logic CU TIMER1 OSC Reference Resistor Trimmed 32 kHz nominal OSCIN OSCOUT Crystal Referenced 32.768 kHz PLL PLL Filter or or Prog. Counter Unit Computational Unit PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F 0x3D 0x38 32 Ohm PDM
Comparator 1 bit: PD5 vs PD4 + D port I/O Data Control 0x18 0x1C - PD0-7 8
TIMER2
Clock Control Gen. Control
E port I/O Data Control 0x20 0x24
PE0-7 8
Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
F port INPUT Data 0x28
PF0-7 8
RAM 640 x 17 bit (data)
0x000 to 0x027F
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
pin assignments
PJM PACKAGE (TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VSS3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VDD2 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NC
NC NC NC NC DACM VDD3 DACP VDD PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VSS NC NC NC NC NC NC NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
VDD V DD1 SCANOUT TEST SYNC SYNCLK SCANIN RESET PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PLL OSCIN OSCOUT VSS
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
pin assignments
Table 1. Signal and Pad Descriptions for the C605
SIGNAL PC0 - PC7 PD0 - PD7 PE0 - PE7 PF0 - PF7 PIN NUMBER 89 - 82 99 - 92 46 - 39 16 - 9 PAD NUMBER Input/Output Ports 8-1 18 - 11 48 - 41 31 - 24 I/O I/O I/O I Port C general-purpose I/O Port D general-purpose I/O Port E general-purpose I/O Port F key-scan input (1 Byte) (1 Byte) (1 Byte) (1 Byte) I/O DESCRIPTION
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details. Scan Port Control Signals SCANIN SCANOUT SCANCLK SYNC TEST 37 33 36 35 34 39 35 38 37 36 I O I I I Scan port data input Scan port data output Scan port clock Scan port synchronization C605: test modes
The scan port pins must be bonded out on any C605 production board. Consult the "Important Note regarding Scan Port Bond Out", see Chapter 7 in the MSP50C614 User's Guide (SPSU014). Oscillator Reference Signals OSCOUT OSCIN PLL DACP DACM RESET 49 48 47 7 5 38 51 50 49 DAC Sound Output 22 20 Initialization 40 Power Signals 32, 52, 9, 19 I Initialization O O Digital-to-analog output 1 (+) Digital-to-analog output 2 (-) O I O Resistor/crystal reference out Resistor/crystal reference in Phase-lock-loop filter
VSS 17, 50, 90, 100 Ground , 8, 31, 32, 91 , 23, 33, 34, 10 VDD 6 21 Processor power (+) The VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required.
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 7 V Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD + 0.3 V Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS . 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
recommended operating conditions
PARAMETER VDD VIH Supply voltage (with respect to VSS) High-level input voltage VDD = 3 V VDD = 4.5 V VDD = 5.2 V VDD = 3 V VIL IOH IOL IOH (DAC) IOL (DAC) f(CPU) R(DAC) Low-level input voltage High-level output current per pin of I/O port Low-level output current per pin of I/O port High-level output DAC current Low-level output DAC current CPU clock rate (as programmed) Resistance between DACP and DACM VDD = 4.5 V VDD = 5.2 V VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VOH = 4 V VOL = 0.5 V VOH = 4 V VOL = 0.5 V 64 32 70 TEST CONDITIONS MIN 3 2 3 3.5 0 0 0 MAX 5.2 3 4.5 5.2 1 1.5 1.7 -2 5 - 10 20 12,320 mA mA mA mA kHz C V V UNIT V
TA Operating free-air temperature Device functionality 0 Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
timing requirements
TEST CONDITIONS t(RESET) t1(WIDTH) Reset low pulse width, while VDD is within specified limits Pulse width required prior to a negative transition at pin...PD3, PD5, or PF0...PF7 MIN 100 2 2 MAX UNIT ns 1/FCPU 1/FCPU
t2(WIDTH) Pulse width required prior to a positive transition at pin...PD2 or PD4 While these pins are being used as interrupt inputs.
t(RESET)
t(RESET)
Figure 1. Initialization Timing Diagram
t1(WIDTH (PD3, PD5, or F port))
t1(WIDTH)
t2(WIDTH (PD2, or PD4))
t2(WIDTH)
Figure 2. MSP50P614 External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
dc electrical characteristics, TA = 25C
PARAMETER VDD = 3 V RESET Threshold changes VDD = 5.2 V Input leakage current Standby current Operating current Supply current Input offset voltage F port pullup resistance Trim deviation Voltage deviation Temperature deviation Resistance deviation TEST CONDITIONS Positive going threshold Negative going threshold Hysteresis Positive going threshold Negative going threshold Hysteresis Ilkg I(STANDBY) IDD I(SLEEP-deep) I(SLEEP-mid) I(SLEEP-light) VIO R(PULLUP) f(RTO t i ) (RTO-trim) f(RTO lt) (RTO-volt) f(RTO t (RTO-temp) ) f(RTO ) (RTO-res) Excludes OSCIN RESET is low VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 4.5 V, VDD = 5 V RRTO = 470 k, VDD = 4.5 V, TA = 25C, fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 k, VDD = 3.5 to 5.2 V, fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 k, FCLOCK = 12.32 MHz DAC off, ARM set, DAC off, DAC off, ARM set, ARM clear, OSC disabled OSC enabled OSC enabled 0.05 15 0.05 40 60 25 70 150 2 TA = 25C, 3 1 5 1.5 -0 1 0.1 1 0.1 01 10 60 100 50 mV k % % %/C % A MIN TYP 2.4 1.8 0.6 3.3 2.9 0.4 1 10 A A mA V V MAX UNIT
Vref = 1 to 4.25 V
VDD = 4.5 V, TA = 0 to 70C, fRTO = 8.192 MHz (PLL setting = 7 Ch) VDD = 4.5 V, TA = 25C, ROSC = 470 k @ 1%, fRTO = 8.192 MHz (PLL setting = 7 Ch)
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
external component absolute values
PARAMETER R(RTO) C(PLL) RTO external resistance PLL external capacitance TA = 25C, TA = 25C, TEST CONDITIONS 1% tolerance 10% tolerance MIN MAX 470 3300 UNIT k pF
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MSP50C605 MIXED-SIGNAL PROCESSOR
SPSS025A - FEBRUARY 2000 - REVISED MAY 2000
MECHANICAL DATA
PJM (R-PQFP-G100)
0,38 0,22
PLASTIC QUAD FLATPACK
0,65 80
0,13 M 51
81
50
12,35 TYP
14,20 13,80
17,45 16,95
100
31
1 18,85 TYP 20,20 19,80 23,45 22,95
30 0,16 NOM
Gage Plane 0,25 0,25 MIN 1,03 0,73 Seating Plane 0- 7
2,90 2,50
3,40 MAX
0,10 4040022 / B 03/95
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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