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MSP50C614 Mixed-Signal Processor User's Guide
SPSU014 January 2000
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This user's guide gives information for the MSP50C61 mixed-signal processor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer information, and electrical characteristics (in data sheet). This document also contains information for the MSP50C604 and MSP50C605, which are in the Product Preview stage of development.
How to Use This Manual
This document contains the following chapters:
Notational Conventions
Chapter 1 -Introduction to the MSP50C614 Chapter 2 -MSP50C614 Architecture Chapter 3 -Peripheral Functions Chapter 4 -Assembly Language Instructions Chapter 5 -Code Development Tools Chapter 6 -Applications Chapter 7 -Customer Information Appendix A -MSP50C605 Preliminary Data Appendix B -MSP50C604 Preliminary Data Appendix C -MSP50C605 Data Sheet
This document uses the following conventions.
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Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter's. Examples use a bold
Read This First
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Notational Conventions
version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Here is an example of a system prompt and a command that you might enter:
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C:
csr -a /user/ti/simuboard/utilities
In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: .asect "section name", address .asect is the directive. This directive has two parameters, indicated by section name and address. When you use .asect, the first parameter must be an actual section name, enclosed in double quotes; the second parameter must be an address.
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Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you don't enter the brackets themselves. Here's an example of an instruction that has an optional parameter: LALK 16-bit constant [, shift] The LALK instruction has two parameters. The first parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma. Square brackets are also used as part of the pathname specification for VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
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Braces ( { and } ) indicate a list. The symbol | (read as or) separates items within the list. Here's an example of a list: { * | *+ | *- } This provides three choices: *, *+, or *-.
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Information About Cautions and Warnings
Unless the list is enclosed in square brackets, you must choose one item from the list.
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Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Trademarks
Intel, i486, and Pentium are trademarks of Intel Corporation. Microsoft, Windows, Windows 95, and Windows 98 are registered trademarks of Microsoft Corporation.
Read This First
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Contents
Contents
1 Introduction to the MSP50C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Features of the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Development Device: MSP50P614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 C605 and C604 (Preliminary Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Terminal Assignments and Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 MSP50C614 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Computation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.2 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3 Data Memory Address Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.1 RAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.2 Data Memory Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4 Program Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.5 Bit Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.6 Memory Organization: RAM and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.6.2 Peripheral Communications (Ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.6.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.6.4 ROM Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.6.5 Macro Call Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.7 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.8 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.9 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.9.1 Oscillator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.9.2 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.9.3 Clock Speed Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.9.4 RTO Oscillator Trim Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.10 Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.11 Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Peripheral Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
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3.2
3.3 3.4 3.5 4
3.1.1 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Dedicated Input Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.3 Dedicated Output Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.4 Branch on D Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.5 Internal and External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.1 Pulse-Density Modulation Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.2 DAC Control and Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.3 PDM Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Interrupt/General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Hardware Initialization States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Assembly Language Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 Multiplier Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2 Shift Value Register (SV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.3 Data Pointer Register (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.5 Top of Stack, (TOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.6 Product High Register (PH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.7 Product Low Register (PL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.8 Accumulators (AC0-AC31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.9 Accumulator Pointers (AP0-AP3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.10 Indirect Register (R0-R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.11 String Register (STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.12 Status Register (STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3 Instruction Syntax and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.1 MSP50P614/MSP50C614 Instruction Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.3.3 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.4 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.5 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.3.6 Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.3.7 Flag Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.3.8 Tag/Flag Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4.4 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.4.2 Class 2 Instructions: Accumulator and Constant Reference . . . . . . . . . . . . . . 4-28 4.4.3 Class 3 Instruction: Accumulator Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.4.4 Class 4 Instructions: Address Register and Memory Reference . . . . . . . . . . . 4-34 4.4.5 Class 5 Instructions: Memory Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.4.6 Class 6 Instructions: Port and Memory Reference . . . . . . . . . . . . . . . . . . . . . . 4-38 4.4.7 Class 7 Instructions: Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
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4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 5
4.4.8 Class 8 Instructions: Logic and Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4.4.9 Class 9 Instructions: Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 Bit, Byte, Word and String Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 MSP50P614/MSP50C614 Computational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 Hardware Loop Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 Lookup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Special Filter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Conditionals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69 Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 Instruction Set Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
Code Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 MSP50C6xx Software Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.6 Software Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.6.1 The Open Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.6.2 Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.6.3 Description of Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.6.4 Debugging a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.6.5 Initializing Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.6 Emulator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.6.7 Emulator Online Help System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.6.8 Known Differences, Incompatibilities, Restrictions . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.7 Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.7.1 Assembler DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.7.2 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.8 Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5.9 C-- Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.9.1 Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5.9.2 Variable Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5.9.3 External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5.9.4 C- - Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5.9.5 Include Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5.9.6 Function Prototypes and Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5.9.7 Initializations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5.9.8 RAM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5.9.9 Variable Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
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5.10
5.11 5.12 6
5.9.10 String Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.11 Constant Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.1 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.2 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.3 Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.4 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.5 Programming Example, C - With Assembly Routines . . . . . . . . . . . . . . . . . . . Beware of Stack Corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reported Bugs With Code Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-45 5-47 5-48 5-48 5-50 5-50 5-51 5-53 5-67 5-67
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 MSP50C614/MSP50P614 Initialization Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 File init.asm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3 Texas Instruments C614 Synthesis Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.1 Memory Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.4 ROM Usage With Respect to Various Synthesis Algorithms . . . . . . . . . . . . . . . . . . . . . 6-14 Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Die Bond-Out Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 Customer Information Fields in the ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3 Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4 Device Production Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.6 New Product Release Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 MSP50C605 Preliminary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3.1 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3.2 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50C604 Preliminary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.1 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.2 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.4 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A-2 A-2 A-2 A-3 A-3 A-3 B-1 B-2 B-2 B-2 B-3 B-3 B-3 B-5
7
A
B
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B.4 C
B.3.5 Host Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.6 Host Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-5 B-5 B-7 B-8
MSP50C605 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1 MSP50C605 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
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Figures
Figures
1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8
xii
Functional Block Diagram for the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Oscillator and PLL Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 RESET Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 MSP50C614 100 Pin PJM PLastic Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 120 Pin Grid Array Package for the Development Device, P614 . . . . . . . . . . . . . . . . . . . . 1-13 MSP50C614 Core Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Computational Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Overview of the Multiplier Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Overview of the Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Overview of the Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Data Memory Address Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 C614 Memory Map (not drawn to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Interrupt Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 Instruction Execution and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 PDM Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Relationship Between Comparator/Interrupt Activity and the TIMER1 Control . . . . . . . . 3-15 Top of Stack (TOS) Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Relative Flag Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Data Memory Organization and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 Data Memory Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 FIR Filter Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps . . . . . . 4-67 Filter Instruction and Circular Buffering for N+1 Tap Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set . . . . . . . . . . . . . . . . . 4-131 Level Translator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Pin IDC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . InstallShield Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Information Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Choose Destination Location Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-5 5-6 5-6 5-7 5-8 5-8 5-9
Figures
5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 7-1 7-2 7-3 7-4 A-1 A-2 A-3 B-1 B-2 B-3 B-4
Select Program Folder Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Copying Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Complete Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Open Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50P614/MSP50C614 Code Development Windows . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Breakpoint Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspect Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspect Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Ports Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Programming Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Init Menu Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Options Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windows Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Context Sensitive Help System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-Pin PJM Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120-Pin Grid Array Package for the Development Device, P614 . . . . . . . . . . . . . . . . . . . . . 120 Pin Grid Array (PGA) Package Leads, P614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 5-11 5-12 5-13 5-14 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-21 5-22 5-23 5-25 5-26 5-27 5-29 5-29 5-30 5-31 7-4 7-5 7-6 7-8
MSP50C605 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 MSP50C605 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 MSP50C605 100-Pin PJM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 MSP50C604 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50C604 Memory Organization and I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50C604 Slave Mode Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50C604 64-Pin PJM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B-6 B-9 B-9
Contents
xiii
Tables
Tables
1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24
xiv
Signal and Pad Descriptions for the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 MSP50C614 100-Pin PJM Plastic Package Pinout Description . . . . . . . . . . . . . . . . . . . . . 1-11 Signed and Unsigned Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Summary of C614's Peripheral Communications Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Programmable Bits Needed to Control Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . 2-37 Status of Circuitry When in Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 How to Wake-Up from Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Destination of Program Counter on Wake-Up Under Various Conditions . . . . . . . . . . . . . 2-40 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 State of the Status Register (17 bit) after RESET Low-to-High . . . . . . . . . . . . . . . . . . . . . 3-21 Status Register (STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Addressing Mode Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Rx Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Addressing Mode Bits and {adrs} Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 MSP50P614/MSP50C614 Addressing Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Auto Increment and Auto Decrement Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Flag Addressing Field {flagadrs} for Certain Flag Instructions (Class 8a) . . . . . . . . . . . . . 4-12 Initial Processor State for the Examples Before Execution of Instruction . . . . . . . . . . . . . 4-13 Indirect Addressing Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Symbols and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 Classes and Opcode Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Class 1 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Class 1a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Class 1b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Class 2 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Class 2a Instruction Descritpion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Class 2b Insstruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Class 3 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Class 3 Instsruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Class 4a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 Class 4a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Class 4b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Class 4c Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Tables
4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 5-1 7-1 A-1 B-1
Class 4d Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 5 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 5 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 6a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 6a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 6b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 7 Instruction Encoding and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 8a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 8a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 8b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 9a Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 9a Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 9b Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 9c Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 9d Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory Address and Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSP50P614/MSP50C614 Computational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Loops in MSP50P614/MSP50C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Processor State for String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lookup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Increment and Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Mode Bits and adrs Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Addressing Syntax and BIts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Names for cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-35 4-36 4-36 4-38 4-38 4-39 4-40 4-41 4-42 4-42 4-43 4-43 4-43 4-44 4-44 4-46 4-50 4-54 4-55 4-57 4-73 4-73 4-73 4-87
String Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 MSP50C614 100-Pin PJM Plastic Package Pinout Description . . . . . . . . . . . . . . . . . . . . . . 7-3 MSP50C605 100-Pin PJM Plastic Package Pinout Description . . . . . . . . . . . . . . . . . . . . . . A-7 MSP50C604 64-Pin PJM Plastic Package Pinout Description . . . . . . . . . . . . . . . . . . . . . . . B-8
Contents
xv
Notes, Cautions, and Warnings
Notes, Cautions, and Warnings
MSP50C605 and MSP50C604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 ROM Locations that Hold Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Instructions with References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Block Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Block Protections Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Setting a Bit in the IFR Using the OUT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Interrupt Service Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Writing to the TIM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 ClkSpdCtrl Bits 8 and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Reference Oscillator Stopped by Programmed Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 Register Trim Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 Idle State Clock Control Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 Reading the Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PDM Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 IntGenCtrl Register Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Internal RAM State after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Stack Pointer Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Data Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 Scan Port Bond Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 MSP50C605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 MSP50C604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
xvi
Chapter 1
Introduction to the MSP50C614
The MSP50C614 (C614) is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the C614 unprecedented speed and computational flexibility compared with previous devices of its type. The C614 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality.
Topic
1.1 1.2 1.3 1.4 1.5 1.6
Page
Features of the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Development Version: P614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 C605 and C604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Terminal Assignments and Signal Descriptions . . . . . . . . . . . . . . . 1-10
1-1
Features of the C614
1.1 Features of the C614
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Advanced, integrated speech synthesizer for high quality sound Operates up to 8 MHz (performs up to 8 MIPS) Very low-power operation, ideal for hand-held devices Low voltage operation, sustainable by three batteries Reduced power stand-by modes, less than 10 A in deep-sleep mode Supports high-quality synthesis algorithms such as MELP, CELP, LPC, and ADPCM Contains 32K words onboard ROM (2K words reserved) 640 words RAM 40 general purpose, bit configurable I/O 8 inputs with programmable pullup resistors and a dedicated interrupt (key-scan) 16 dedicated output pins Direct speaker driver, 32 (PDM) One-bit comparator with edge-detection interrupt service (IMPORTANT: Not currently supported) Resistor-trimmed oscillator or 32-kHz crystal reference oscillator Serial scan port for in-circuit emulation and diagnostics The MSP50C614 is sold in die form; an emulator device for the MSP50C614 is sold in a ceramic package for development.
1-2
Applications
1.2 Applications
Due to its low cost, low-power needs, and high programmability, the C614 is suitable for a wide variety of applications incorporating I/O control and highquality speech:
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Talking Toys Electronic Learning Aids Games Talking Clocks
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Talking Books Talking Dictionaries Warning Systems Equipment for the Handicapped
Introduction to the MSP50C614
1-3
Development Device: MSP50P614
1.3 Development Device: MSP50P614
The MSP50P614 is an EPROM based version of the MSP50C614, and is available in 120 pin windowed ceramic pin grid array. This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each person doing software development should have several of these PGA packaged devices. The MSP software development tool supports non-real-time debugging by scanning the code sequence through the MSP50C614/MSP50P614 scanport without programming the EPROM. However, the rate of code execution is limited by the speed of the PC parallel port. Any MSP50C614/MSP50P614 can be used in this debugging mode. The MSP50P614 EPROM must be programmed to debug the code in real time. The MSP software development tool is used to program the EPROM, set a breakpoint, and evaluate the internal registers after the breakpoint is reached. If a change is made to the code, the code will need to be updated and programmed into another device while erasing previous devices. This cycle of programming, debugging, and erasing typically requires 10-15 devices to be in the eraser at any one time, so 15-20 devices may be required to operate efficiently. The windowed PGA version of the MSP50P614 is required for this debugging mode.
1-4
Functional Description
1.4 Functional Description
The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 64 bits of partially configurable I/O. The core processor is a general-purpose 16 bit micro-controller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor, and several system and control registers. The core processor gives the P614 and C614 break-point capability in emulation. The processor is a Harvard type for efficient DSP algorithm execution. It requires separate program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured in 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for a built-in self-test, 2) the upper 30K is for user program/data. The data memory is internal static RAM. The RAM is configured in 640 17-bit words. Both memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. A flexible clock generation system is included that enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and peripheral clock sources are controlled separately to provide different levels of power management (see Figure 1-2). The peripheral consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one 16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup option (100-k minimum resistance) and a dedicated service interrupt. These features make the input port especially useful as a key-scan interface. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the C614 periphery is a
Introduction to the MSP50C614
1-5
C605 and C604 (Preliminary Information)
built in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The block diagram appearing in Figure 1-1 gives an overview of the C614 functionality. IMPORTANT: a one bit comparator is not currently supported. Typical connections to implement reset functionality are shown in Figure 1-3.
1.5 C605 and C604 (Preliminary Information)
Two related products, the MSP50C605 (C605) and MSP50C604(C604) use the C614 core. The C605 has a 224K byte data ROM built into the chip and 32 I/O port pins. The C605 can provide up to 30 minutes of uninterrupted speech. The C604 is designed to support slave operation with an external host microcontroller. In this mode the C604 can be programmed with a code that communicates with the host via a command set. This command set can be designed to support LPC, CELP, MELP, and ADPCM coders by selecting the appropriate command. The C604 can also be used stand-alone in master mode. The C604 and the C605 use the P614 as the development version device. Details on C605 and C604 processors are found in Appendix A and B. Note: MSP50C605 and MSP50C604 MSP50C605 and MSP50C604 are in the Product Preview stage of development. For more information contact your local TI sales office. See Appendices A and B for more information.
1-6
C605 and C604 (Preliminary Information)
Figure 1-1. Functional Block Diagram for the C614
VSS 5 Scan Interface Break Point Emulation OTP Program Serial Comm. Power (EP)ROM Test-Area (reserved) User ROM INT vectors VDD 5 (P614 only) 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF A port I/O Data Control B port I/O Data Control C port I/O Data Control 0x10 0x14 0x08 0x0C 0x00 0x04 VPP
SCANIN SCANOUT SCANCLK SYNC TEST PGMPULSE
PA0-7 8
PB0-7 8
(C614 only) (P614 only)
PC0-7 8
Core DACP DACM RESET DAC 0x30 Instr. Decoder PCU Initialization Logic CU TIMER1 OSC Reference Resistor Trimmed 32 kHz nominal OSCIN OSCOUT Crystal Referenced 32.768 kHz PLL PLL Filter or or Prog. Counter Unit Computational Unit PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F 0x3D 0x38 32 Ohm PDM
Comparator 1 bit: PD5 vs PD4 + D port I/O Data Control 0x18 0x1C - PD0-7 8
TIMER2
Clock Control Gen. Control
E port I/O Data Control 0x20 0x24
PE0-7 8
Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
F port INPUT Data 0x28
PF0-7 8
RAM 640 x 17 bit (data)
G port OUTPUT 0x000 to 0x027F Data 0x2C
PG0-15 16
Introduction to the MSP50C614
1-7
C605 and C604 (Preliminary Information)
Figure 1-2. Oscillator and PLL Connection
a) Crystal Oscillator Operation Connections
MSP50P614 MSP50C614
OSCIN
OSCOUT
PLL
10 M 32.768 kHz
10 M
22 pF
22 pF
C(PLL) = 3300 pF
Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins.
b) Resistor Trim Operation Connections
MSP50C614 MSP50P614
OSCIN
OSCOUT
PLL
R(RTO) = 470 k 1%
C(PLL) = 3300 pF
Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins.
1-8
C605 and C604 (Preliminary Information)
Figure 1-3. RESET Circuit
(MSP50P614 only) VPP VDD 100 k Inside the MSP50P614 MSP50C614 RESET 1 k 1 F (20%) IN914 IN914 5V To Pin 1 of Optional (Scanport) Connector
Reset Switch
To Pin 2 of optional (scan port) connector VSS If it is necessary to use the software development tools to control the MSP50P614 in application board, the 1 k resistor is needed to allow the development tool to over drive the RESET circuit on the application board. This Diode can be omitted (shorted) if the application does not require use of the scanport interface. See Section 7.1.1 regarding scan port bond out.
Introduction to the MSP50C614
1-9
Terminal Assignments and Signal Descriptions
1.6 Terminal Assignments and Signal Descriptions
Table 1-1. Signal and Pad Descriptions for the C614
SIGNAL PAD NUMBER 75 68 85 78 81 18 11 63 56 31 24 49 42 39 32 I/O Input/Output Ports PA0 - PA7 PB0 - PB7 PC0 - PC7 PD0 - PD7 PE0 - PE7 PF0 - PF7 PG0 - PG7 PG8 - PG15 I/O I/O I/O I/O I/O I O Port A general-purpose I/O Port B general-purpose I/O Port C general-purpose I/O Port D general-purpose I/O Port E general-purpose I/O Port F key-scan input Port G dedicated output (1 Byte) (1 Byte) (1 Byte) (1 Byte) (1 Byte) (1 Byte) (2 Bytes) DESCRIPTION
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details. (Currently not supported) Scan Port Control Signals SCANIN SCANOUT SCANCLK SYNC TEST PGMPULSE 54 50 53 52 51 I O I I I Scan port data input Scan port data output Scan port clock Scan port synchronization C614 : test modes P614 : programming pulse
The scan port pins must be bonded out on any C614 production board. Consult the "Important Note regarding Scan Port Bond Out", Section 7.1.1, Scan Port Bond Out. Oscillator Reference Signals OSCIN OSCOUT PLL 65 66 67 I O O DAC Sound Output DACP DACM RESET 22 20 O O Initialization 55 9, 19, 40, 64, 76 10, 21, 23, 41, 77 I Power Signals VSS VDD Ground Processor power (+) Initialization Digital-to-analog output 1 (+) Digital-to-analog output 2 (-) Resistor/crystal reference in Resistor/crystal reference out Phase-lock-loop filter
Pads VSS (19) and VDD (21) service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required. Refer to Section 6.1, Application Circuits, for details.
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Terminal Assignments and Signal Descriptions
The C614 is sold in die form for its volume production. Contact you local TI sales office for mount and bond information. MSP50C614 is also available in 100 pin plastic QFP package. The pinout is shown in Figure 1-4 and Table 1-2.
Table 1-2. MSP50C614 100-Pin PJM Plastic Package Pinout Description
Description GND3/DA NC NC NC DACM VCC3/DA DACP VCC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 NC PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description GND4 VCC4 NC NC PG7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 SCANOUT TEST SYNC SCANCLK SCANIN RESET PE7 PE6 PE5 PE4 PE3 PE2 PE1 Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description PE0 GND NC NC NC X2 X1 PLL PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 GND1 VCC1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Pin # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Description PB0 NC NC NC NC NC NC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 GND2 VCC2 PD7 PD6 PD5 PD7 PD73 PD2 PD1 PD0 Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Introduction to the MSP50C614
1-11
Terminal Assignments and Signal Descriptions
Figure 1-4. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information)
PJM PACKAGE (TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VCC2 GND2 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NC NC
GND3/DA NC NC NC DACM VCC 3/DA DACP VCC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 NC PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 GND4 VCC 4 NC NC PG7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC NC NC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC 1 GND1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PLL X1 X2 NC NC NC GND PE0
1-12
PG6 PG5 PG4 PG3 PG2 PG1 PG0 SCANOUT TEST SYNC SCANCLK SCANIN RESET PE7 PE6 PE5 PE4 PE3 PE2 PE1
Terminal Assignments and Signal Descriptions
For software development and prototyping, a windowed ceramic 120-pin grid array packaged P614 is available. The P614's PGA package is shown in Figure 1-5 and Table 1-3:
Figure 1-5. 120 Pin Grid Array Package for the Development Device, P614
MSP50P614
N M L K J H G F E D C B A
N M L K J H G F E D C B A
extra pin
13 12 11 10 9 8 7 6 5 4 3 2 1 (top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 (bottom view)
Note: PGA Package The PGA package is only available in limited quantities for development purposes.
Introduction to the MSP50C614
1-13
Terminal Assignments and Signal Descriptions
The pin assignments for the 120-pin PGA package (P614 device only) are outlined in the following table. Refer to Section 1.6 for more information on the signal functions. N M L K J H G F E D C B A
nc nc PD0 PD3 PD5 VDD VSS PC2 PC5 PC7 nc nc nc nc nc nc PD1 PD4 PD7 PC1 PC3 PC6 nc nc nc nc VDD DACM nc nc PD2 PD6 PC0 PC4 nc nc nc nc nc extra nc PB0 PB2 PB1 PB3 PB4 PB5 PB6 PB7 VSS PA0 VDD PA3 PA2 PA1 PA7 PA5 PA4 nc PLL PA6 (bottom view) PF7 DACP VSS PF5 PF6 VDD PF2 PF3 PF4 VPP PF1 PF0 PG15 PG14 PG13 PG12 PG11 PG9 PG10 PG8 nc VSS nc nc PG6 PG2 pgmpuls RESET PE4 PE0 nc nc OSCOUT OSCIN VDD nc PG5 PG3 PG0 SYNC scanin PE5 PE2 VSS nc nc nc nc PG7 PG4 PG1 scanout scanclk PE7 PE6 PE3 PE1 nc nc nc
1
2
3
4
5
6
7
8
9
10
11
12
13
It is important to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are PGA numbers N3 and L4, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. Refer to Section 6.1, TBD, for details.
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Chapter 2
MSP50C614 Architecture
A detailed description of MSP50C614 architecture is included in this chapter. After reading this chapter, the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mechanism, and various low power modes.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Page
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Computation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Data Memory Address Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Program Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Bit Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Memory Organization: RAM and ROM . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.10 Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.11 Reduced Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-1
2.1 Architecture Overview
The core processor in the C614 is a medium performance mixed signal processor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accumulator-register file provides additional scratch pad memory and minimizes memory thrashing for many operations. Five different addressing modes and many short direct references provide enhanced execution and code efficiency. The basic elements of the C614 core are shown in Figure 2-1. In addition to the main computational units, the core's auxiliary functions include two timers, an eight-level interrupt processor, a clock generation circuit, a serial scan-port interface, and a general control register.
2-2
Figure 2-1. MSP50C614 Core Processor Block Diagram
Interrupt Inputs Peripheral Interface
Interrupt Flag Register (IFR) Multiplier (MR) Shift Value (SV) Control Register (CTRL) Interrupt Processor 17 x 17 Multiplier Product High (PH) Serial Interface Register Oscillator Register Timer Period (PRD1 and PRD2) Timer Register (TIM1 and TIM2) MUX
Serial Interface
VCO
16 bit ALU
Frequency Divider Instruction Decoder
AP0-AP3 Accumulator Pointer 32 Accumulators (AC0-AC31) Column Exchange Incrementor Top Of Stack (TOS) Stack (R7) Page (R6) Index (R5) Loop (R4) R3 R2 R1 R0 MUX Program Counter (PC) Protection Register (PR) Data Pointer (DP) +1
MUX String Register Test Code 2k x 17 bit Program Memory 30k x 17 bit Macro Calls Vectors Flag Register
Arithmetic Unit
MUX Repeat Counter Status Register (STAT)
MUX Data Memory 640 x 17 bit
Indicates internal programmable registers.
MSP50C614 Architecture
2-3
Figure 2-2. Computational Unit Block Diagram (The shaded boxes represent internal programmable registers.)
16 Shift Value (SV) 16 16 Multiplier Register (MR) 16 16 17 bit x 17 bit Multiplexer 16 MSB 16 16 0 16 Product High (PH) 0 (Product Low, PL) 16 LSB
16 16 A ALU 16 B
16
16
Read/Write Accumulators AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31
5
AP0 AP1 AP2 AP3
5
Internal Databus - 16 bit
2-4
Computation Unit
2.2 Computation Unit
The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth's algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram of the CU is shown in Figure 2-2. The multiplier block is served by 4 system registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand register, a 16-bit high word product register (PH), and a 4-bit shift value register (SV). The output of the ALU is stored in one 16-bit accumulator from among the 32 which compose the accumulator-register block. The accumulator register block can supply either one operand to the ALU (addressed accumulator register or its offset register) or two operands to the ALU (both the addressed register and its offset).
2.2.1
Multiplier
The multiplier executes a 17-bit by 17-bit 2s complement multiply and multiply-accumulate in a single instruction cycle. The sign bit within each operand is bit 16, and its value extends from bit 0 (LSB) to bit 15 (MSB). The sign bit for either operand (multiplier or multiplicand) can assume a positive value (zero) or a value equal to the MSB (bit 15). In assuming zero, the extra bit supports unsigned multiplication. In assuming the value of bit 15, the extra bit supports signed multiplication. Table 2-1 shows the greater magnitude achievable when using unsigned multiplication (65535 as opposed to 32767).
Table 2-1. Signed and Unsigned Integer Representation
Unsigned Decimal 65535 32768 32767 0 Hex 0xFFFF 0x8000 0x7FFF 0x0000 Decimal -1 -32768 32767 0 Signed Hex 0xFFFF 0x8000 0x7FFF 0x0000
During multiplication, the lower word (LSB) of the resulting product, product low, is multiplexed to the ALU. Product low is either loaded to or arithmetically combined with an accumulator register. These steps are performed within the same instruction cycle. Refer to Figure 2-3. At the end of the current execution cycle, the upper word (MSB) of the product is latched into the product high register (PH).
MSP50C614 Architecture
2-5
Computation Unit
The multiplicand source can be either data memory, an accumulator, or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register. For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift value register (SV). Refer to Figure 2-4. As an example of a barrel shift operation, a coded value of 0x7 in the SV register results in a multiplier operand of 0000000010000000 (1 at bit 7). This causes a left-shift 7-times on the 16 bit multiplicand. The output result is 32-bit. On the other hand, if the status bit FM (multiplier shift mode) is SET, then the multiplier operand (0000000010000000) is left-shifted once to form a 17 significant-bit operand (00000000100000000). This mode is included to avoid a divide-by-2 of the product, when interpreting the input operands as signed binary fractions. The multiplier shift mode status bit is located in the status register (STAT). All three multiplier registers (PH, SV, and MR) can be loaded from data memory and stored to data memory. In addition, data can be transferred from an accumulator register to the PH, or vice versa. Both long and short constants can be directly loaded to the MR from program memory. The multiplicand is latched in a write-only register from the internal data bus. The value is not accessible by memory or other system registers.
2-6
Computation Unit
Figure 2-3. Overview of the Multiplier Unit Operation
MULTIPLIER UNIT INPUTS Multiplicand 16-bit - latched in a write-only register from one of the following sources ... Data Memory Accumulator Offset Accumulator MULTIPLYING: SHIFTING: X Multiplier - writeable and readable by Data Memory as one of the following ... (MR) (SV) Multiplier Register or Shift Value Register 16-bit 4-bit
MULTIPLIER UNIT performs multiplication and barrel shifting
MULTIPLIER UNIT INPUTS MSB 16-bit (PH) Product High - readable and writeable by Data Memory - readable and writeable by ALU-A Also write-able by Program Memory (PL) Product Low - a simulated register: PL is realized in ALU-A LSB 16-bit
2.2.2
Arithmetic Logic Unit
The arithmetic logic unit is the focal point of the computational unit, where data can be added, subtracted, and compared. Logical operations can also be performed by the ALU. The basic hardware word-length of the ALU is 16 bits; however, most ALU instructions can also operate on strings of 16-bit words (i.e., a series or array of values). The ALU operates in conjunction with a flexible, 16-bit accumulator register block. The accumulator register block is composed of 32, 16-bit registers which further enhances execution and promotes compact code. The ALU has two distinct input paths, denoted ALU-A and ALU-B (see Figure-2-4). The ALU-A input selects between all zeros, the internal databus, the product high register (PH), the product low (PL), or the offset output of the accumulator register block. The ALU-B input selects between all zeros and the output from the accumulator register block.
MSP50C614 Architecture
2-7
Computation Unit
The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are useful for supporting multiply-accumulate operations (refer to Section 2.2.1, Multiplier). The operations supported by the ALU include arithmetic, logic, and comparison. The arithmetic operations are addition, subtraction, and load (add to zero). The logical operations are AND, OR, XOR, and NOT. Comparison includes equal-to and not-equal-to. The compare operations may be used with constant, memory, or string values without destroying any accumulator values.
2.2.2.1
Accumulator Block
The output of the ALU is the accumulator block. The accumulator block is composed of 32, 16-bit registers. These registers are organized into two terminals, denoted accumulator and OFFSET accumulator. The terminals provide references for all of the data which is to be held in the accumulator block. The accumulator incorporates one-half of the 32 accumulator registers: AC0..AC15. The OFFSET accumulator incorporates the other half: AC16..AC31.
2-8
Computation Unit
Figure 2-4. Overview of the Arithmetic Logic Unit
ALU INPUTS ALU-A 16-bit - selects between ... all 0's Offset Accumulator Register Data Memory Program Memory Product High Product Low ALU-B 16-bit - selects between ... all 0's Accumulator Register
(PH) (PL)
ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic
ALU OUTPUTS THE ACCUMULATOR BLOCK Accumulator Register 16, 16-bit registers ... AC0, AC1, AC2, AC3, AC4, AC5, AC6, AC7, AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15 OFFSET Accumulator Register 16, 16-bit registers ... AC16, AC17, AC18, AC19, AC20, AC21, AC22, AC23, AC24, AC25, AC26, AC27, AC28, AC29, AC30, AC31
For multiply-accumulate operations.
2.2.2.2
Accumulator Pointer Block
There are four 5-bit registers which are used to store pointers to members of the accumulator block. The accumulator pointers (AP0, AP1, AP2, AP3) are used in two modes: 1) as a direct reference to one of 32, or 2) as an indirect reference. The indirect reference includes a direct reference to one of 16 and an offset (optional) which increments the reference by 16: AC(N+16). For example, AC0 has its offset register located at AC16. AC1 has an offset register located at AC17, and so on. The block is circular: address 31, when incremented, results in address 0. The offsets of AC16 through AC31, therefore, are AC0 through AC15, respectively. See Figure 2-5 Indirect referencing by the AP pointers is supported by most of the C614's accumulator-referenced instructions.
MSP50C614 Architecture
2-9
Computation Unit
When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C614 instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of the actual 16-bit accumulator. Some MOV instructions store the contents of the APn directly to memory or load from memory to the APn register. Other instructions can add or load 5-bit constants to the current APn register contents. A full description of the C614 instruction set is given in Chapter 4, Instructions.
Figure 2-5. Overview of the Arithmetic Logic Unit
Accumulator Block: Accumulator Block Pointers: 32, 16-bit registers 4, 5-bit registers AC(0) . . . AC(31) AP(0) . . . AP(3)
The accumulator block pointers may assume values in one of two forms: 1) DIRECT REFERENCE: 0 . . . 31 AC Register # 2) INDIRECT REFERENCE: 0 . . . 15 0 . . . 15 OFFSET 15 . . . 31 OFFSET points to: points to: points to: 0 . . . 15 16 . . . 31 0 . . . 15
- AP registers are served by a 5-bit processor for sequencing addresses or repetitive operations. - Selection between the 4 AP's is made in the 2-bit An field in all accumulator-referenced instructions
2.2.2.3
String Operations
The AP registers are served by a 5-bit processor that provides efficient sequencing of accumulator addresses. The design automates repetitive operations like long data strings or repeated operations on a list of data. When operating on a multiword data string, the address is copied from the AP register to fetch the least significant word of the string. This copy is then consecutively incremented to fetch the next n words of the string. At the completion of the consecutive operations, the actual address stored in the AP register is left unchanged; its value still points to the least significant location. The AP register, therefore, is loaded and ready for the next repeatable operation.
2-10
Data Memory Address Unit
For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or -1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodification of the address avoids the software pipelining effect that post-modification would cause. Some C614 instructions reference only the accumulator register and cannot use or modify the offset register that is fetched at the same time. Other instructions provide a selection field in the instruction word (A~ or ~A op-code bit). This has the effect of exchanging the column addressing sense and thus the source or order of the two registers. Also, some instructions can direct the ALU output to be written either to the accumulator register or to the offset accumulator register. Refer to Chapter 4, Instructions, for more details. The ALU's accumulator block functions as a small workspace, which eliminates the need for many intermediate transfers to and from memory. This alleviates the memory thrashing which frequently occurs with single accumulator designs.
2.3 Data Memory Address Unit
The data memory address unit (DMAU) provides addressing for data memory (internal RAM). The block diagram of the DMAU is shown in Figure 2-6. The unit consists of a dedicated arithmetic block and eight read/write registers (R0 through R7). Each read/write register is 16-bits in size. The arithmetic block is used to add, subtract, and compare memory-address operands. The register set includes four general-purpose registers (R0 to R3) and four special-purpose registers. The special-purpose registers are: the LOOP control register (R4), the INDEX register (R5), the PAGE register (R6), and the STACK register (R7). The DMAU generates a RAM address as output. The DMAU functions completely in parallel with the computational unit, which helps the C614 maintain a high computational throughput.
MSP50C614 Architecture
2-11
Data Memory Address Unit
Figure 2-6. Data Memory Address Unit
Arithmetic Block
R0 R1 R2 R3 R4 R5 R6 R7 LOOP INDEX PAGE STACK
RAM Address
Register Internal Databus
Addressing Mode
Internal Program Bus
2.3.1
RAM Configuration
The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for op-codes in the instruction set. Specifically, the flag bit directs complex branch conditions associated with certain instructions. The flag bit is also used by the computational unit for signed or unsigned arithmetic operations (see Section 2.2.1, Multiplier). The size of the C614 RAM block is 640 17-bit locations. Each address provided by the DMAU causes 17 bits of data to be addressed. These 17 bits are operated on in different ways, depending on the instructions being executed. For most instructions, the data is interpreted as 16-bit word format. This means that bits 0 through 15 are used, and bit 16 is either ignored or designated as a flag or status bit.
2-12
Data Memory Address Unit
There are two-byte instructions, for example MOVB, which cause the processor to read or write data in a byte (8-bit) format. (The B appearing at the end of MOVB designates it as an instruction, which uses byte-addressable arguments.) The byte-addressable mode causes the hardware to read/write either the upper or lower 8 bits of the 16-bit word based on the LSB of the address. In this case, the address is a byte address, rather than a word address. Bits 0 through 7 within the word are used, so that a single byte is automatically rightjustified within the databus. Bits 8 through 15 may also be accessed as the upper byte at that same address. A third data-addressing mode is the flag data mode, whereby, the instruction operates on only the single flag bit (bit 16) at a given address. All flag mode instructions execute in one instruction cycle. The flags can be referenced in one of two addressing modes: 1) global address, whereby 64 global flags are located at fixed locations in the first 64 RAM addresses, and 2) flag relative address, whereby a reference is made relative to the current PAGE (R6). The relative address supports 64 different flags whose PAGE-offset values are stored in the PAGE register. The flag mode instructions cannot address memory in the INDEX-relative modes. See Chapter 4, Instructions, for more details.
2.3.2
Data Memory Addressing Modes
The DMAU provides a powerful set of addressing modes to enhance the performance and flexibility of the C614 core processor. The addressing modes for RAM fall into three categories:
-
Direct addressing Indirect addressing with post-modification Relative addressing
The relative addressing modes appear in three varieties: Immediate Short, relative to the PAGE (R6) register. The effective RAM address is: [*R6 + (a 7 bit direct offset)]. Relative to the INDEX (R5) register. The effective RAM address is: [*R5 + (an indexed offset)]. Long Immediate, relative to the register base. The effective RAM address is: [*Rx + (a 16 bit direct offset)].
Refer to Chapter 4, Instructions, for a full description of how these modes are used in conjunction with various instructions.
MSP50C614 Architecture
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Program Counter Unit
2.4 Program Counter Unit
The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops). The program counter unit generates a ROM address as output. The program counter value, PC, is automatically saved to the stack on various CALL instructions and interrupt service branches. The stack consists of one hardware-level register (TOS) which points to the top-of-stack. The TOS is followed by a software stack. The software stack resides in RAM and is addressed using the STACK register (R7) in indirect mode (see Section 2.3, Data Memory Address Unit). The hardware loop counter controls the execution of repeated instructions using one of two modes: 1) consecutive iterations of a single instruction following the repeat (RPT) instruction, or 2) a single instruction which operates on a string of data values (string loops). For all types of repeated execution, interrupt service branches are automatically disabled (temporarily). The data pointer (DP) register is loaded at two instances: 1) from the accumulator during lookup-table instructions, and 2) from the databus during the fetch of long string constants. To simplify algorithms which require sequential indices to lookup tables, the DP register may be stored in RAM.
2.5 Bit Logic Unit
The bit logic unit is a 1-bit unit which operates on flag bit data. It is controllable by eleven different instructions, which generate the decision flags for conditional program control. The results of operations performed by the bit logic unit are sent either to the flag bit of RAM memory or to the TF1 and TF2 bits of the status register (STAT).
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Memory Organization: RAM and ROM
2.6 Memory Organization: RAM and ROM
Data memory (RAM) and program memory (ROM) are each restricted to internal blocks on the C614. The program memory is read-only and limited to 32K, 17-bit words. The lower 2048 of these words is reserved for an internal test code and is not available to the user. The data memory is static RAM and is limited to 640, 17-bit words. 16 bits of the 17-bit RAM are used for the data value, while the extra bit is used as a status flag. The C614 does not have the capability to execute instructions directly from external memory. However, additional program memory (external ROM) can be accessed using the general-purpose I/O. The interface for external ROM must be configured in the software.
2.6.1
Memory Map
The memory map for the C614 is shown in Figure 2-7. Refer to Section 2.6.3, Interrupt Vectors, for more detailed information regarding the interrupt vectors, and to Section 2.7.2, Peripheral Communications (Ports), for more information on the I/O communications ports.
MSP50C614 Architecture
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Memory Organization: RAM and ROM
Figure 2-7. C614 Memory Map (not drawn to scale)
Program Memory 0x0000 Internal Test Code 2048 x 17 bit (reserved) Data Memory 0x0000 0x027F 0x08 0x0C User ROM 30704 x 17 bit (C614 : read-only) (P614 : EPROM) 0x7F00 Macro Call Vectors 255 x 17 bit (overlaps interrupt vector locations) 0x7FF0 Usable Interrupt Vectors 8 x 17 bit 0x7FF7 0x7FF8 0x7FFE 0x7FFF Unusable Interrupt Vectors (reserved) RESET vector 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x2F 0x30 0x34 0x38 0x39 0x3A 0x3B 0x3D Shaded boxes highlight dedicated ROM and control registers. 0x3E 0x3F 0x07FF 0x0800 RAM 640 x 17 bit Peripheral Ports 0x00 0x04 PA0-7 data PA0-7 ctrl PB0-7 data PB0-7 ctrl PC0-7 data PC0-7 ctrl PD0-7 data PD0-7 ctrl PE0-7 data PE0-7 ctrl PF0-7 data PG0-15 data RTRIM DAC data DAC ctrl IntGenCtrl IFR PRD1 TIM1 ClkSpdCtrl PRD2 TIM2
2.6.2
Peripheral Communications (Ports)
Peripheral functions in the C614 are controlled using one or more of the I/O address-mapped communications ports. Table 2-2 describes the ports. The width of each mapped location, shown in width of location, is independent of the address spacing. In other words, some registers are smaller in width than the spacing between neighboring addresses. The few unused bits appear to the right of the LSB values within the DAC Data register, address 0x30 (refer to Section 3.2.2, DAC Control and Data Registers).
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Memory Organization: RAM and ROM
When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator, the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction, with the address of the I/O port as an argument. A read from these locations is accomplished using the IN instruction, with the address of the I/O port as an argument. When reading from the I/O port to a 16-bit accumulator, the IN instruction automatically clears any extra bits in excess of width of location. The desired bits in the result will be right-justified within the accumulator. Allowable access indicates whether the port is bidirectional, read-only, or write-only. The last column of the table points to the section in this manual where the functions of each bit have been defined in more detail.
Table 2-2. Summary of C614's Peripheral Communications Ports
I/O Map Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x39 Width of Location 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 16 bits 16 bits 4 bits 16 bits 8 bits Allowable Access read & write read & write read & write read & write read & write read & write read & write read & write read & write read & write READ only read & write WRITE only read & write read & write read & write Control Register Name I/O port A data I/O port A control I/O port B data I/O port B control I/O port C data I/O port C control I/O port D data I/O port D control I/O port E data I/O port E control Input port F data Output port G data DAC data DAC control Interrupt/general Ctrl Interrupt flag Abbreviation PA0..7 Data PA0..7 Ctrl PB0..7 Data PB0..7 Ctrl PC0..7 Data PC0..7 Ctrl PD0..7 Data PD0..7 Ctrl PE0..7 Data PE0..7 Ctrl PF0..7 Data PG0..15 Data DAC Data DAC Ctrl IntGenCtrl IFR State after RESET LOW unknown 0x00 unknown 0x00 unknown 0x00 unknown 0x00 unknown 0x00 unknown 0x0000 0x0000 0x0 0x0000 Same state as before RESET 3.1.2 3.1.3 3.2.2 3.2.2 3.4 2.7 3.1.1 Section for Reference
Input states are provided by the external hardware. A control register value of 0x00 yields a port configuration of all inputs.
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Memory Organization: RAM and ROM
Table 2-2. Summary of C614's Peripheral Communications Ports (Continued)
I/O Map Address 0x3A 0x3B 0x3D 0x3E 0x3F Width of Location 16 bits 16 bits 16 bits 16 bits 16 bits Allowable Access read & write read & write WRITE only read & write read & write Control Register Name TIMER1 period TIMER1 count-down Clock speed control TIMER2 period TIMER2 count-down Abbreviation PRD1 TIM1 ClkSpdCtrl PRD2 TIM2 State after RESET LOW 0x0000 2.8 28 0x0000 0x0000 0x0000 2.8 28 0x0000 2.9.3 Section for Reference
2.6.3
Interrupt Vectors
When its event has triggered and its service has been enabled, an interrupt causes the program counter to branch to a specific location. The destination location is stored (programmed) in the interrupt vector, which resides in an upper address of ROM. The following table lists the ROM address associated with each interrupt vector:
Interrupt Name INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 ROM address of Vector 0x7FF0 0x7FF1 0x7FF2 0x7FF3 0x7FF4 0x7FF5 0x7FF6 0x7FF7 0x7FFE RESET 0x7FFF Event Source DAC Timer TIMER1 TIMER2 port D2 port D3 all port F port D4 port D5 Interrupt Priority Highest 2nd 3rd 4th 5th 6th 7th Lowest
storage for ROM Protection Word storage for initialization vector
Note: ROM Locations that Hold Interrupt Vectors ROM locations that hold interrupt vectors are reserved specifically for this purpose. Additional ROM locations 0x7FF8 - 0x7FFD are reserved for future expansion. Like the interrupt vectors, they should not be used for general program storage. The branch to the program location that is specified in the interrupt vector is, of course, contingent on the occurrence of the trigger event. Refer to Section
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Memory Organization: RAM and ROM
3.1.5, Internal and External Interrupts, for more information regarding the specific conditions for each interrupt-trigger event. The branch operation, however, is also contingent on whether the interrupt service has been enabled. This is done individually for each interrupt, using the interrupt mask bits within the interrupt/general control register. Refer to Section 2.7, Interrupt Logic, for more details. The ROM location 0x7FFF holds the program destination associated with the hardware RESET event (branch happens after RESET LOW-to-HIGH). The location 0x7FFE holds the read/write block-protection word. Refer to Section 2.6.4, ROM Code Security, for an explanation of the ROM security scheme.
2.6.4
ROM Code Security
The C614 provides a mechanism for protecting its internal ROM code from third-party pirating. The protection scheme is composed of two levels, both of which prevent the ROM contents from being read. Protection may be applied to the entire program memory, or it can be applied to a block of memory beginning at address 0x0000 and ending at an arbitrary address. The two levels of ROM protection are designated as follows:
-
Direct read and write protection, via the ROM scan circuit. Indirect read protection, which prohibits the execution of memory-lookup instructions.
For the purposes of direct security, the ROM is divided into two blocks. The first block begins at location 0x0000, and ends, inclusively, at location (m x 512 - 1), where m is some integer. Each address specifies a 17-bit word location. The second block begins at location (m x 512), and ends, inclusively, at 0x7FFF (the end of the ROM). The first block is protected from reads and writes by programming a block protection bit, and the second block is protected from reads and writes by programming a global protection bit. The two-block system is designed in such a way that a secondary developer is prevented from changing the partition address between blocks. Once the block protection has been engaged, then the only security option available to the secondary developer is engaging the global protection. Note: Instructions with References Care must be taken when employing instructions that have either long string constant references or look-up table references. These instructions will execute properly only if the address of the instruction and the address of the data reference are within the same block.
MSP50C614 Architecture
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Memory Organization: RAM and ROM
The protection modes are implemented on the C614 as follows. Within the ROM is a dedicated storage for the block protection word (address 0x7FFE). The block protection word is divided into two 6-bit fields and two single-bit fields. The remainder of the 17-bit word is broken into three single-bit fields which are reserved for future use.
ROM Block Protection Word address 0x7FFE WRITE only (17-bit wide location) 16 R 15 R 14 13 12 11 10 09 08 07 06 R 05 04 03 02 01 00
TM TM 05 04
TM TM TM TM 03 02 01 00
GP BP
FM FM FM FM FM FM 05 04 03 02 01 00
TM : True Protection Marker (NTM) FM : False Protection Marker (NFM) R : Reserved for future use (must be 1)
GP : Global Protection (0 value protects) BP : Block Protection (0 value protects) 1 : Default value of cells on erasure
The two 6-bit fields are designated as the true protection marker, (TM5 through TM0) and the false protection marker, (FM5 through FM0). When setting up a partition for partial ROM protection, the address of the partition must be specified as:
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Memory Organization: RAM and ROM
[(NTM + 1) * 512 - 1] = highest ROM address within the block to be protected (NTM + 1) * 512 = lowest ROM address which is left unprotected NTM = the value programmed at TM5...TM0 (true protection marker) the binary complement of NTM NFM NFM = the value programmed at FM5...FM0 (false protection marker) The purpose of the true and false protection markers is to provide parity. An erased P614 EPROM cell defaults to the value 1. Once programmed from 1 to 0, it cannot be programmed back to 1, unless the cell (and all other cells along with it) are subject to erasure. A multi-pass programming, therefore, can only lower the value stored at an EPROM address and never raise it. Once a valid block-partition address has been properly specified in both TM and FM, it is impossible to change TM to another address and still maintain parity with FM.
Note: Block Protection Mode When applying the block protection mode, bits FM5 through FM0 must be programmed as the logical inverse of bits TM5 through TM0, respectively. Across the span of the 32k word ROM space, there are 64 possible values for NTM (including zero). Hence, the 6-bit-wide locations for TM and FM. The two single-bit fields found within the block protection word are the block protection bit (BP) and the global protection bit (GP). If BP and GP are both SET (erased), then no protection is applied to the ROM. If BP is CLEAR and GP is SET, then the block protection mode is engaged. This means that read and write access is prevented at locations 0x0000 through [(NTM + 1) x 512 - 1]. Read and write access is permitted at locations [(NTM + 1) x 512] through 0x7FFF. If GP is CLEAR, then the global protection mode is engaged. This prevents read and write access to all addresses of the ROM, regardless of the value of BP. Note: Block Protection Word The remaining bits in the block protection word are reserved for future use, but must remain set in order to ensure future compatibility. These bits are numbers 6, 15, and 16.
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Interrupt Logic
When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an internal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended. The same initialization sequence is executed before entry into the special test-modes available on the P614 and C614 (EPROM mode, emulation mode, and trace mode). This insures that the protection scheme is always in force when running the processor in one of these modes. A dedicated circuit ensures that a switch between emulation mode and trace mode cannot occur without going through the initialization (security check). This forces all look-up tables and long constant references to originate from an external program source, when in emulation mode. It is possible to switch from trace mode to emulation mode by lowering VPP, but this transition, by design, does not jeopardize code security.
2.6.5
Macro Call Vectors
Macro call vectors are similar to CALL instructions except they take an 8-bit address. The upper 8 bits is always 7Fh. See Section 4.14.83, VCALL, for more information on the VCALL instruction.
2.7 Interrupt Logic
An eight-level interrupt system is included as part of the C614's core processor. The initialization and control of these interrupts is governed by the following components: the global interrupt enable, the interrupt flag register, the interrupt mask register, and the interrupt service branch. Each of these is described below. Interrupts must be globally enabled using the INTE instruction, and they are globally disabled using the INTD instruction. INTE sets the global interrupt enable bit, and INTD clears the global interrupt enable bit. The state of this bit specifically determines whether any interrupt service branches will be taken. The global interrupt enable appears as bit 4 within the status register (STAT). Each interrupt level waits for the conditions of its trigger event (refer to Figure 2-8). At the time that a trigger event occurs, the respective bit is automatically SET in the interrupt flag register (IFR). The IFR is an 8-bit wide port-addressed register; wherein, each interrupt level is represented. A set bit in the IFR indicates that the interrupt is pending and waiting to be serviced. A clear bit indicates that the interrupt is not currently pending. The address of the IFR is 0x39. After a RESET low, the IFR is left in the same state it was before
2-22
Interrupt Logic
the RESET low, assuming there is no interruption in power. For a full description of the interrupt-trigger events, refer to Section 3.1.5, Internal and External Interrupts.
(8-bit wide location) 07 IFR Interrupt Flag register address 0x39 D5 : port D5 falling-edge D4 : port D4 rising-edge D3 : port D3 falling-edge D2 : port D2 rising-edge D5 D4 low priority PF D3 D2 T2 T1 DA high priority 06 05 04 03 02 01 00 INT number
PF : any port F falling-edge T2 : TIMER2 underflow T1 : TIMER1 underflow DA : DAC timer underflow
1 : A bit value 1 indicates pending interrupt waiting to be serviced. RESET: The IFR is left in the same state it was before RESET low, assuming no interruption in power.
INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set. Refer to Section 3.3, Comparator, for details.
Individual interrupts are enabled or disabled for service by setting or clearing the respective bit in the interrupt mask register (IMR, 8 bits). If an interrupt level has its bit cleared in the IMR, then the interrupt service associated with that interrupt is disabled. Setting the bit in the IMR allows service to occur (pending the trigger-event which is registered in the IFR). The IMR is accessible as part of another (larger) register, namely, the interrupt/general control register (peripheral port 0x38). After a RESET LOW, the default value of each bit in the IMR is zero: no interrupt service enabled. A full description of the bit locations in the interrupt/general control register can be found in Section 3.4, Interrupt/General Control Register. The IMR functions independently of the IFR, in the sense that interrupt-trigger events can be registered in the IFR, even if the respective IMR bit is clear. Both the IFR and IMR are readable and writeable as port addressed registers. To read the register, use the IN instruction in conjunction with the port address (0x38 or 0x39). Use the OUT instruction to write. (Refer to Section 2.6.2, Peripheral Communications (Ports), for more information.)
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Interrupt Logic
Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtaining a software interrupt. An IFR bit may also be cleared, using OUT, at any time. Assuming the global interrupt enable is set and the specific bit within the IMR is set, then, at the time of the interrupt-trigger event, an interrupt service branch is initiated. (The trigger event is marked by a 0-to-1 transition in the IFR bit). At that time, the core processor searches all interrupt levels which have both: 1) pending interrupt flag, and 2) interrupt service enabled. The highest priority interrupt among these is selected. The program then branches to the location which is stored in the associated Interrupt Vector (Section 2.6.3, Interrupt Vectors). This location constitutes the start of the interrupt service routine. Instructions in the interrupt service routine are executed until the IRET (return) instruction is encountered. Afterwards, any other pending interrupts will be similarly serviced, in the order of their priority. Eventually, the program returns to whatever point it was before the first interrupt service branch. When an interrupt service branch is taken, the global interrupt enable is automatically cleared by the core processor. This disables all further interrupt service branches while still in the pending service routine. As a result, the programmer must re-enable the interrupts globally using the INTE instruction. If performed as the second-to-last instruction in the service routine, then no nesting of multiple interrupts will occur. If, on the other hand, a nesting of certain interrupts is desired, then the INTE instruction may be included as the first instruction (or anywhere else) within the service routine. When an interrupt service branch is taken, the processor core also clears another status, namely, the respective bit in the IFR. This action automatically communicates to the IFR that the current pending interrupt is now being serviced. Once cleared, the IFR bit is ready to receive another SET whenever the next trigger event occurs for that interrupt. Note: Interrupt Service Branch If the interrupt service branch is not enabled by the respective bit in the mask register, then neither the global interrupt enable nor the respective flag bit is cleared. No program vectoring occurs.
2-24
Interrupt Logic
Figure 2-8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt.
Figure 2-8. Interrupt Initialization Sequence
INTD instruction CLEAR
Global Interrupt Enable INTE instruction SET CLEAR Interrupt-Trigger Event * Internal Timer Underflow * External Input Falling-Edge * External Input Rising-Edge * Software Write Instruction SET BIT INT Flag bits (IFR) Associated With the Interrupt-Trigger Event Interrupt Flag Register (0x39) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
CLEAR BIT
INT Mask bits (IMR) Specific Enable for Interrupt Service Interrupt / General Control Register (0x38) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
Interrupt Service Routine (1 of 8)
Interrupt Service Branch Highest Priority INT is Selected From Among Those Flagged and Enabled. Program Branches to Location Stored in Interrupt Vector.
Interrupt Vector Storage INTE IRET 0x7FF0 0x7FF1 0x7FF2 0x7FF3 0x7FF4 0x7FF5 0x7FF6 0x7FF7
The port-addressed write instruction (OUT) can be used to SET or CLEAR bits in the IFR and IMR.
MSP50C614 Architecture
2-25
Timer Registers
In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered. After an interrupt service branch, it is the responsibility of the programmer to re-SET the global interrupt enable, using the INTE instruction.
2.8 Timer Registers
The C614 contains two identical timers, TIMER1 and TIMER2. Each includes a period register and a count-down register. The period register (PRD1 or PRD2) defines the initial value for the counter, and the count-down register (TIM1 or TIM2) does the counting. When the count-down register decrements to the value 0x0000, then the value currently stored in the period register is loaded to the count-down register. The count-down register then resumes counting again from that value. For each TIMER, there is an interrupt-trigger event associated with the TIMER's underflow condition (the point of reaching 0x0000 and then re-setting again). When enabled, the interrupt INT1 is triggered by the underflow of TIMER1, and the interrupt INT2 is triggered by the underflow of TIMER2. INT1 and INT2 are the second and third-highest priority interrupts in the C614. Refer to Section 2.7, Interrupt Logic, for a summary of the interrupt logic, and to Section 2.6.3, Interrupt Vectors, for a listing of the interrupt vectors. Both the period and the count-down registers are readable and writeable as port-addressed registers:
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Timer Registers
(16-bit wide location) 15 PRD1 register address 0x3A TIM1 register address 0x3B PRD2 register address 0x3E TIM2 register address 0x3F 14 13 12 11 P 10 P T P T 09 P T P T 08 P T P T 07 P T P T 06 P T P T 05 P T P T 04 P 03 P 02 P 01 P 00 P
P P P P TIMER1 Period
T T T T T TIMER1 Count-Down P P P P TIMER2 Period P
T T T T T Triggers INT1 on underflow P P P P P
T T T T T TIMER2 Count-Down
T T T T T Triggers INT2 on underflow
P : period register (initial counter value) T : count-down register (counts from the value in P) 0x0000 : default state of both registers after RESET LOW
TIMER1 may be associated with the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details.
Reading from either the PRD or the TIM returns the current state of the register. This can be used to monitor the progress of the TIM register at any time. Writing to the PRD register does not change the TIM register until the TIM register has finished decrementing to 0x0000. The new value in the PRD register is then loaded to the TIM register, and counting resumes from the new value. Note: Writing to the TIM Register Writing to the TIM register causes the same value to be written to the PRD register. In this case, the TIM register is immediately updated, and counting continues immediately from the new value. Each TIMER decrements its count-down register at a fixed clock rate. The rate is selectable between two existing clock sources: the reference oscillator or 1/2 Master Clock. The rate of the master clock (MC) is programmable. It is determined by the value loaded to the PLL multiplier (Section 2.9.3, Clock Speed Control Register). The source to the TIMER is therefore one-half the frequency of the programmed master clock (1/2 MC). If, instead, the reference oscillator is selected as the source to the TIMER, then the source is either a resistor-trimmed oscillator (RTO) or a crystal oscillator (CRO). Both reference oscillators are designed to run at a nominal 32 kHz. Refer to Section 2.9, Clock Control, for more information regarding the oscillator configuration and clock programmability.
MSP50C614 Architecture
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Timer Registers
Selection between the timer-source options is made using two control bits in the interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bit port-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the source for TIMER1. Setting bit 8 selects the reference oscillator as the source for TIMER1. Similarly, clearing bit 9 of the IntGenCtrl selects 1/2 MC as the source for TIMER2. Setting bit 9 selects the reference oscillator as the source for TIMER2. The default value after a RESET LOW is zero: select 1/2 MC as the source. Each of the TIMERs counts from the value stored in its period register to 0x0000. These maximum and minimum counts each receive a full clock cycle from the TIMER source. This means that the true period of the TIMER, from one underflow event to the next, is the value stored in the period register plus one: Time duration btwn. underflows = (value in PRD + 1) / (frequency of Timer Source) TIMER1 and TIMER2 must be enabled for use. This is done at the IntGenCtrl register. Bit 10 of the IntGenCtrl is the enable bit for TIMER1, and bit 11 is the enable bit for TIMER2. Setting the enable bit enables the TIMER, i.e., starts count-down running. Clearing the enable bit disables the TIMER, i.e., stops the count-down. The default setting after a RESET LOW is zero: both TIMERs disabled. Refer to Section 3.4, Interrupt/General Control Register, for summary information regarding the IntGenCtrl. The TIMER enable bits may be used to start and stop the TIMERs repeatedly in software. Switching the enable bit from 1 to 0 stops the TIMER, but the current value in the count-down register is retained. When the enable bit is subsequently switched from 0 to 1, count-down then resumes from the held value. The following procedure outlines one (of many) possible ways to start the TIMERs. TIMER2 is given as an example: 1) Select the TIMER2 clock source: 1/2 MC or RTO/CRO (bit 9 of the IntGenCtrl, address 0x38). 2) Clear the TIMER2 enable (bit 11 in the IntGenCtrl). 3) Load the count-down register (TIM2) with the desired period value aheadof-time. This prepares TIM2 for counting, and also loads the period register (PRD2) with its value. 4) Be sure the TIMER2 interrupt (INT2) has been enabled for service (set bit 2 of IntGenCtrl). 5) Flip the TIMER2 enable bit from 0 to 1, at the precise time you want counting to begin.
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Clock Control
2.9 Clock Control
2.9.1 Oscillator Options
The C614 has two oscillator options available. Either option may be enabled using the appropriate control bits in the clock speed control register (ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Speed Control Register. The first oscillator option, called the resistor-trimmed oscillator (RTO), is useful in low-cost applications where accuracy is less critical. This option utilizes a single external resistor to reference and stabilize the frequency of an internal oscillator. The oscillator is designed to run nominally at 32 kHz. It has a low VDD coefficient and a low temperature coefficient (refer to Appendix C). The reference resistor is mounted externally across pins OSCIN and OSCOUT. The RTO oscillator is insensitive to variations in the lead capacitance at these pins. The required value of the reference resistor is 470 k (1%). The second oscillator option, CRO for crystal referenced, is a real time clock utilizing a 32.768 kHz crystal. The crystal is mounted externally across pins OSCIN and OSCOUT.
2.9.2
PLL Performance
A software controlled PLL multiplies the reference frequency (generated from either RTO or CRO) by integer multiples. This higher frequency drives the master clock which, in turn, drives the CPU clock. The master clock (MC) drives the circuitry in the periphery sections of the C614. The CPU Clock drives the core processor; its rate determines the overall processor speed. The multiplier in the PLL circuit, therefore, allows the master clock and the CPU clock to be adjusted between their minimum and maximum values. For either oscillator option, the reference frequency (32.768 kHz) is multiplied by four before it is accessed by the PLL circuit. The base frequency for the PLL, therefore, is 131.07 kHz, and the multiplier operates in increments of this base frequency. The minimum multiplication of the base frequency is 1, and the maximum multiplication is 256. The resulting master clock frequency, therefore, can be varied from a minimum of 131.07 kHz to a maximum of 33.554 MHz, in 131.07 kHz steps. From the master clock to the CPU clock, there is a divide-by-two in frequency. The CPU clock, therefore, can be set to run between 65.536 kHz and the maximum achievable (see Appendix C), in 65.536 kHz steps.
MSP50C614 Architecture
2-29
Clock Control
The maximum required CPU clock frequency for the C614 is 8 MHz over the entire VDD range. This rate applies to the speed of the core processor. Higher CPU clock frequencies may be achieved, but these are not qualified over the complete range of supply voltages in the guaranteed specification.
Figure 2-9. PLL Performance
Oscillator Reference 32 kHz Resistor Trimmed RTO or CRO crystal referenced
Timer Source Option Selected in IntGenCtrl 1 0 1 0
Selection Made in ClkSpdCtrl
TIMER2
TIMER2
x4 /2
PLL Phase-Locked-Loop circuit Multiplier Adjusted in ClkSpdCtrl x 1 ... x 256
MC Master Clock : Runs Periphery 131.07 kHz ... 33.554 MHz
/2
CPU Clock Core-Processor Speed 65.536 kHz ... FMAX (FMAX = 8 MHz)
2.9.3
Clock Speed Control Register
The ClkSpdCtrl is a 16-bit memory mapped register located at address 0x3D. The reference oscillator (RTO or CRO) is selected by setting one of the two control bits located at bits 8 and 9. Setting bit 8 configures the C614 for the RTO reference option and simultaneously starts that oscillator. Setting bit 9 configures the C614 for the CRO reference option and simultaneously pulses the crystal, which starts that oscillator.
2-30
Clock Control
Note: ClkSpdCtrl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) becomes the least significant bit of the 6-bit resistor trim value. Thus, bits 15-11 and 9 make up the 6-bit resistor trim value. For example, if the ClkSpdCtrl register is 00010X11XXXXXXXX (X means don't care, bold numbers are resistor trim bits), then the resistor trim value is equal to five. The default value of the ClkSpdCtrl is 0x0000, which means that neither option is enabled by default. Immediately after a RESET LOW-to-HIGH, and regardless of whether a resistor or a crystal is installed across OSCIN/ OSCOUT, the C614 does not have a reference oscillator running. In the absence of a reference, however, the PLL still oscillates; it bottoms-out at a minimum frequency. The master clock, in turn, runs at a very slow frequency (less than 100 kHz) in the absence of a reference oscillator. Under this condition, program execution is supported at a slow rate until one of the two references (RTO or CRO) is enabled in software. (Refer to Chapter 8, MSP50C614 Electrical Specifications, for a more precise characterization of the master clock rate under these conditions.) Once a reference oscillator has been enabled, the speed of the master clock (MC) can be set and adjusted, as desired. Bits 7 through 0 in the ClkSpdCtrl constitute the PLL multiplier (PLLM). The value written to the PLLM controls the effective scaling of the MC, relative to the 131.07 kHz base frequency. A 0 value in PLLM yields the minimum multiplication of 1, and a 255 value in PLLM yields the maximum multiplication of 256. The resulting MC frequency, therefore, is controlled as follows: MC CPU Master clock frequency kHz = (PLLM register value + 1) x 131.07 kHz Clock frequency kHz = (PLLM register value + 1) x 65.536 kHz
The configuration of bits in the clock speed control register appears below:
ClkSpdCtrl register address 0x3D WRITE only (16-bit wide location) 15 T5 14 T4 13 T3 12 T2 11 T1 10 09 08 07 M 06 M 05 M 04 M 03 M 02 M 01 M 00 M
I C or T0 R
T : RTO oscillator-Trim adjust I : Idle State clock Control C : enable Crystal oscillator (or T0 if R is set
R : enable Resistor-trimmed oscillator M : PLLM multiplier bits for MC 0x0000 : default state after RESET LOW
MSP50C614 Architecture
2-31
Clock Control
Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleep generated by the IDLE instruction is partially controlled by this bit. When this bit is cleared (default setting), the CPU Clock is stopped during the sleep, but the MC remains running. When the idle state clock control bit is set, both the CPU clock and the MC are stopped during sleep. Refer to section 2.12 for more information regarding the C614's reduced-power modes. Note: Reference Oscillator Stopped by Programmed Disable If the reference oscillator is stopped by a programmed disable, then, on reenable, the oscillator requires some time to restart and resume its correct frequency. This time imposes a delay on the core processor resuming fullspeed operation. The time-delay required for the CRO to start is GREATER than the time-delay required for the RTO to start.
2.9.4
RTO Oscillator Trim Adjustment
Bits 15 through 11 and bit 9 (6 bits total) in the ClkSpdCtrl effect a software control for the RTO oscillator frequency. The purpose of this control is to trim the RTO to its rated (32 kHz) specification. The correct trim value varies from device to device. The user must program bits 15 through 11 and 9, in order to achieve the 32-kHz specification within the rated tolerances. Texas Instruments provides the trim value to the programmer of the P614 part with a sticker on the body of the chip. For the C614 part, the correct trim value is located at I/O location 0x2Fh.
RTRIM Register (Read Only) (Applies to MSP50C614 Device Only) I/O Address 0x2Fh (17-bit wide location) 16 R 15 R 14 R 13 R 12 R 11 R 10 R 09 R 08 R 07 R 06 R 05 04 03 02 01 T1 00 T0
T5 T4
T3 T2
T: RTO oscillator-trim storage (device specific) R: reserved for Texas Instruments use ClkSpdCtrl Value Copied (Shaded) 15 T5 14 T4 13 T3 12 T2 11 T1 10 I 9 T0 8 1 7 6 5 4 3 2 1 0
M7 M6 M5 M4 M3 M2 M1 M0
When selecting and enabling the RTO oscillator,therefore, the bits at positions 05 through 01 should be read from I/O location 0x2F (MSP50C614 device only), then copied to the ClkSpdCtrl trim adjust (bits 15 through 11 of control register 0x3D), and bit 0 of 0x2F I/O port should be copied to bit 9 of ClkSpdCtrl register. The bit ordering is the same; bit 04 of I/O 0x2F copies to bit 15 of register 0x3D. Likewise, bit 00 of I/O 0x2F copies to bit 11 of register 0x3D.
2-32
Execution Timing
However, the general specification of the adjustment can be useful in certain circumstances. For example, the adjustment can be used to obtain a programmatic increase or decrease in the speed of the RTO reference. The default value for the adjustment, after RESET low, is all zeros. The zero value generates the slowest programmable rate for the RTO reference. The maximum value, 0x3F, generates the fastest programmable rate for the RTO reference. The full range from 0x00 to 0x3F, effects an approximate +62% change (based on the RTO resistor value specification). The change is nonlinear and nonlinear it changes from one device to another. On the P614 part, the above method does not cause in the correct trim value to be loaded in ClkSpdCtrl. MSP50P614 is an EPROM device. Any preprogrammed value is erased when the chip goes through a UV erase procedure. The RTO trim value must, therefore, be computed separately for each chip. RTO trim values differ from one chip to another, is identical for the same chip.
Note: Register Trim Value A resistor trim value is only needed when the resistor trimmed oscillator (RTO) is used. The MSP50P614 device must determine the trim value separately and use this value in the ClkSpdCtrl register bits 15-11 and 9, but C614 device needs to copy bit 0 of I/O location 0x2F to bit 9 of the ClkSpdCtrl register and bits 5 through 1 to bits 15 through 11 of ClkSpdCtrl register.
This software-controlled trim for the RTO is not a replacement for the external reference-resistor mounted at pins OSCIN and OSCOUT. Also, note that this adjustment has no effect on the rate of the CRO reference oscillator.
2.10 Execution Timing
For executing program code, the C614's core processor has a three-level pipeline. The pipeline consists of instruction fetch, instruction decode, and instruction execution. A single instruction cycle is limited to one program Fetch plus one data memory read or write. The master clock consists of two phases with non-overlap protection. A fully static implementation eliminates precharge time on busses or in memory blocks. This design also results in a very low power dissipation. Figure 2-9 illustrates the basic timing relationship between the master clock and the execution pipeline.
MSP50C614 Architecture
2-33
Reduced Power Modes
Figure 2-10. Instruction Execution and Timing
CLOCK
FETCH
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
DECODE
N-1
N
N+1
N+2
N+3
N+4
N+5
EXEC
N-2
N-1
N
N+1
N+2
N+3
N+4
N+5
DATA ADD
N-1
N
N+1
N+2
N+3
N+4
N+5
PC ADD
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
2.11 Reduced Power Modes
The power consumption of the C614 is greatest when the DAC circuitry is called into operation, i.e., when the synthesizer speaks. There are, however, a number of reduced power modes (sleep states) on the C614 which may be engaged during quiet intervals. The performance and flexibility of the reduced power modes make the C614 ideal for battery powered operation. Refer to Chapter 8, MSP50C614 Electrical Specifications, for a full description of the electrical characteristics, including the acceptable power-supply ranges. The reduced power state on the C614 is achieved by a call to the IDLE instruction. The idle state is released by some interrupt event. Different modes (or levels) of reduced-power are brought about by controlling a number of different core and periphery components on the device. These components are independently enabled/disabled before engaging the IDLE instruction. The number of subsystems left running during sleep directly impacts the overall power consumption during that state. The various subsystems that determine (or are affected by) the depth of sleep include the:
-
Processor core, which is driven by the CPU clock PLL clock circuitry PLL reference oscillator C614 periphery, which is driven by the master clock TIMER1 and TIMER2 PDM pulsing
2-34
Reduced Power Modes
The deepest sleep achievable on the C614, for example, is a mode where all of the previously listed subsytems are stopped. In this state, the device draws less than 10 A of current and obtains the greatest power savings. It may be awakened from this state using an external interrupt (input port). A number of control parameters determine which of the internal components are left running after the IDLE instruction. In most cases, the states of these controls may be mixed in any combination. There are three combinations, however, which are primarily useful. The three modes (light, mid, and deep sleep) are executed through the independent control of two bits: 1) the idle state clock control, and 2) the reference oscillator enable. The other pertinent controls simply enhance the performance of the modes dictated by these two. Table 2-3 gives a listing of all of the controls which should be maintained by the programmer before engaging the IDLE instruction. In some cases, it will be impossible to wake from sleep unless certain controls are set appropriately before going to sleep. (In those cases, only the hardware RESET low-to-high will bring the device back into its normal operating state.) The top row in Table 2-3 lists the first of the two primary controls, namely, the idle state clock control. The idle state clock control determines the status of the master clock (MC) during sleep. Setting the idle state control causes the CPU clock, the PLL clock circuitry, and the MC to stop after the next IDLE instruction. Clearing the idle state control causes only the CPU clock to stop after IDLE. The PLL clock circuitry governs the MC and determines its rate. Whenever the PLL circuitry is suspended, therefore, the MC stops. The idle state clock control is accessed at bit 10 in the ClkSpdCtrl register. (Refer to Section 2.9.3, Clock Speed Control Register, for more information.) The reference oscillator enable is the other control which selects between the three reduced power modes listed in Table 2-3. This control may be one of two bits, depending on which oscillator reference is implemented in circuitry. Refer to Section 2.9.3, Clock Speed Control Register. When using the resistor-trimmed oscillator (RTO), the reference oscillator enable appears as bit 8 in the ClkSpdCtrl register. When using the crystal-referenced oscillator (CRO), the reference oscillator enable appears as bit 9 in the ClkSpdCtrl register. If both bits 8 and 9 are clear, then no reference oscillator is enabled. If either of bits 8 or 9 are set, then the reference oscillator enable is considered set. This enables the PLL circuitry to regulate to the reference frequency, 32 kHz (assuming the idle state clock control is clear). Whichever state the reference oscillator is in before idle, it remains in that state (running or stopped) after idle. If the reference oscillator is left running during sleep, however, it comes at a cost to power consumption. (This may be a necessary cost if, in your application, elapsed time needs to be monitored during sleep.)
MSP50C614 Architecture
2-35
Reduced Power Modes
The power consumed during sleep when the RTO oscillator is left running is greater than the power consumed during sleep when the CRO oscillator is left running. If the idle state clock control is clear, then the PLL circuitry, active during sleep, will attempt to regulate the MC to whatever frequency is programmed in the PLL multiplier (see Section 2.9.3, Clock Speed Control Register). The MC continues to run at this frequency, even during sleep, provided that the reference oscillator is enabled. If the idle state clock control is set, then neither the MC, CPU clock, nor the TIMER clocks run during sleep, unless the TIMER source is linked to the reference oscillator (Section 2.8, Time Registers). These relationships are shown explicitly, as a function of the reduced power mode, in Table 2-4. Because the DAC circuitry is the single most source of power consumed on the C614, it is important to disable the DAC entirely before engaging any IDLE instruction. This is accomplished at the DAC control register, address 0x34. Refer to Section 3.2.2, DAC Control and Data Registers. The ARM bit is another important control to consider before engaging the reduced power mode. It is recommended that the ARM bit be cleared whenever the idle state clock control is clear, and set whenever the idle state clock control is set Table 2-3. The set ARM bit causes an asynchronous response to all programmable interrupts when in the sleep state. (The cleared ARM bit yields the standard synchronous response at all times.) Affected interrupts include those tied to TIMER1 and TIMER2, as well as those tied to the inputs at Ports F, D2, D3, D4, and D5. The advantage to having the ARM bit set is that the device may be awakened by one of these interrupts, even when the PLL clock circuitry is stopped in sleep (by virtue of the idle state control). The disadvantage of the asynchronous response, however, is that it can render irregularities in the timing of response to these same inputs. Note: Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bit is clear, the only event that can wake the C614 after an IDLE instruction is a hardware RESET lowto-high. When at sleep, the device will not respond to the input ports, nor to the internal timers.
2-36
Reduced Power Modes
Table 2-3. Programmable Bits Needed to Control Reduced Power Modes
deeper sleep ... relatively less power Control Bit Idle state clock control bit 10 ClkSpdCtrl register (0x3D) Enable reference oscillator bit 09 : CRO or bit 08 : RTO ClkSpdCtrl register (0x3D) ARM bit 14 IntGenCtrl register (0x38) Enable PDM pulsing bit 02 DAC Control register (0x34) IDLE instruction (executes the mode) PLL multiplier bits 07 through 00 ClkSpdCtrl register (0x3D) Label for Control Bit A LIGHT MID DEEP
0
1
1
B
1
1
0
C
0
1
1
D
Should be cleared before any IDLE instruction.
E
Same instruction is used to engage any of the modes.
F
Programmed value is 0 ... 255 .
MSP50C614 Architecture
2-37
Reduced Power Modes
Table 2-4. Status of Circuitry When in Reduced Power Modes (Refer to Table 2-3)
deeper sleep ... relatively less power Component CPU clock (processor core) PLL clock circuitry Master clock (MC) status (C614 periphery) MC rate Synchrony of external interrupts PDM pulsing TIMER1 or TIMER2 status * Assuming TIMER is enabled 1) TIMER source = 1/2 MC 2) TIMER source = RTO or CRO Determined by Controls E A, E A, E B, F C, E D LIGHT stopped running running 131 kHz ... 34 MHz Synchronous stopped 1) running 2) running MID stopped stopped stopped -- Asynchronous stopped 1) stopped 2) running DEEP stopped stopped stopped -- Asynchronous stopped 1) stopped 2) stopped
A, B, E
If the reference oscillator is stopped by a programmed disable or by an IDLE instruction, then, on re-enable or wake-up, the oscillator requires some time to restart and resume its correct frequency. This time imposes a delay on the core processor resuming full-speed operation. The time-delay required for the CRO to start is greater than the time-delay required for the RTO to start. There are a number of ways to wake the C614 from the IDLE-induced sleep state. The various options are summarized, as a function of the reduced power mode, in Table 2-5. Naturally, the RESET event (happens after the RESET pin has gone low-to-high) causes an immediate escape from sleep; whereby, the program counter assumes the location stored in the RESET interrupt vector. The RESET escape from sleep is always enabled, regardless of the depth of sleep or the state of programmable controls. The more functional methods available for waking the device are: 1) the Internal TIMER interrupt, and 2) the external input-port interrupt. For either of these options to work, the respective bit in the interrupt mask register (address 0x38) must be set to enable the associated interrupt service. If the appropriate IMR bit is not set before the IDLE instruction, then the interrupt-trigger event will not be capable of waking the device from sleep. Note also the state of the idle state clock control bit and the ARM bit, if you expect to wake-up using either type of interrupt (internal or external). In most cases, the state of these bits should coincide Table 2-3.
2-38
Reduced Power Modes
The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however, the act of going to sleep can bring a TIMER to stop, thereby preventing a TIMER-induced wake-up. The bottom row of Table 2-4 illustrates the various conditions under which the TIMER will continue to run after the IDLE instruction. Not that the reduced power mode DEEP leaves both TIMERs stopped after IDLE. This mode cannot, therefore, be used for a timed wake-up sequence.
Table 2-5. How to Wake-Up from Reduced Power Modes (Refer to Table 2-3 and Table 2-4)
deeper sleep ... relatively less power Event Timer interrupts TIMER1 and TIMER2 * Assuming respective IMR bit is set * Assuming ARM bit is set as in C External interrupts Port F and D2,3,4,5 (if input) * Assuming respective IMR bit is set * Assuming ARM bit is set as in C RESET DAC Timer * Assuming PDM bit is clear as in D Determined by Controls LIGHT MID DEEP
A, B, C
If TIMER is running, then Underflow wakes device.
No wake-up from TIMER.
C
Rising-Edge, or Falling-Edge, as appropriate, wakes device. RESET LOW-to-HIGH always wakes device.
none
D
No wake-up from DAC Timer.
The external interrupt is the other programmable option for waking the C614 from sleep. The associated interrupt-trigger event is, in some cases, a risingedge at the input port; in some cases it is a falling-edge. Refer to Section 3.1.5, Internal and External Interrupts, for a full description of these events. Consider also the comparator driven interrupts described in Section 3.3, Comparator. The input ports which are supported by external interrupt include the entire F Port, and, when programmed as inputs, Ports D2, D3, D4, and D5. Refer to Section 3.1, I/O, for a description of the various I/O configurations. Under normal operation the DAC timer, when IMR enabled, triggers an interrupt on underflow. Before any IDLE instruction, however, the entire DAC circuitry should be disabled. This ensures the effectiveness of the reduced power mode and prevents any wake-up from the DAC timer.
MSP50C614 Architecture
2-39
Reduced Power Modes
In order to wake the device using a programmable interrupt, the interrupt mask register must have the respective bit set to enable interrupt service (see Section 2.7, Interrupt Logic). In some cases, the ARM bit must also be set, in order for the interrupts to be visible during sleep Table 2-3. After the C614 wakes from sleep, the program counter assumes a specific location, resuming normal operation of the device. Normally, the destination of the program on wake-up is the interrupt service routine associated with the interrupt which initiated the wake-up. The start of the interrupt service routine is defined by the program location stored in the respective interrupt vector (see Section 2.6.3, Interrupt Vectors). This wake-up response requires that the global interrupt enable is set before going to sleep (use the INTE instruction). If the global interrupt enable is CLEAR before going to sleep, then the programmed interrupt can still wake the device, provided that the respective IMR and ARM bits are set as in Table 2-5 Instead of waking to the interrupt service routine, however, the program counter assumes the location immediately following the IDLE instruction which initiated the sleep. This type of wake-up response may be useful for putting the C614 into a hold sleep; whereby, any number of programmable interrupts can wake the device, yet they all return the program to the very same location. In order to accomplish this, each of the necessary interrupts should be enabled in the IMR. The global interrupt enable, however, is cleared using the INTD instruction. Table 2-6 lists the various possible destinations of the program counter on wake-up, provided that the wake-up is bound to occur under the given conditions.
Table 2-6. Destination of Program Counter on Wake-Up Under Various Conditions
State of Interrupt Controls before IDLE Instruction * Global interrupt enable is SET * Respective IMR bit is SET * Global interrupt enable is CLEAR * Respective IMR bit is SET * Global interrupt enable is SET * Respective IMR bit is CLEAR Assuming Wake-Up can occur... Destination of Program Counter after Wake-Up Program counter goes to the location stored in the interrupt vector associated with the waking Interrupt. Program counter goes to the next instruction immediately following the IDLE which initiated sleep. Wake-up cannot occur from the programmed Interrupt under these conditions. If RESET low-to-high occurs, then program goes to the location stored in the RESET interrupt vector.
2-40
Chapter 3
Peripheral Functions
This chapter describes in detail the MSP50C614 peripheral function, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, comparator and digital-to-analog (DAC) control mechanisms.
Topic
3.1 3.2 3.3 3.4 3.5
Page
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Interrupt/General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Hardware Initialization States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3-1
I/O
3.1 I/O
The C614 has 64 input-output pins. Forty of these are software configurable as either inputs or outputs. Eight are dedicated inputs, and the remaining sixteen are dedicated outputs.
3.1.1
General-Purpose I/O Ports
The forty configurable input/output pins are organized in 5 ports, A,B,C,D, and E. Each port is one byte wide. The pins within these ports can be individually programmed as input or output, in any combination. The selection is made by clearing or setting the appropriate bit in the associated control register (Control A, B, C, D, or E). Clearing the bit in the control register renders the pin as a high-impedance input. Setting the control bit renders the pin as a totem-poleoutput. When configured as an input, the data presented to the input pin can be read by referring to the appropriate bit in the associated data register (Data A, B, C, D, or E). This is done using the IN instruction, with the address of the data register as an argument. When configured as an output, the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the associated data register. This is done using the OUT instruction, with the address of the data register as an argument.
Port A Control register address Possible control values Value after RESET low Data register address Possible input data values Possible output data values 0x00h 0x04h Port B 0x0Ch Port C 0x14h Port D 0x1Ch Port E 0x24h
0 = High-Z INPUT
1 = TOTEM-POLE OUTPUT
0 = High-Z INPUT 0x08h 0x10h 0x18h 0x20h
Low = 0
High = 1 0 = Low
(don't care on write) 1 = High
Each of these I/O ports is only 8 bits wide. The reason for the 4-byte address spacing is so that instructions with limited addressability (such as memory transfers) can still access
these registers.
Note: Reading the Data Register Whether configured as input or as output, reading the data register reads the actual state of the pin. The programmable I/O are initialized to a known state by cycling the RESET pin low-to-high. The state of the control registers during and after RESET low
3-2
I/O
is 0x00 (all inputs). The state of the data registers after RESET low is unknown (input state provided by external hardware). The 8-bit width is the true size of the mapped location. This is independent of the address spacing, which is greater than 8-bits. When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend across 8 bits. Within a 16-bit accumulator, the desired bits should be right-justified. When reading from these locations to a 16-bit accumulator, the IN instruction automatically clears the extra bits in excess of 8. The desired bits in the result will be right-justified within the accumulator. The following table shows the bit locations of the I/O port mapping:
(8-bit wide location) 07 06 05 04 03 02 A port data register . . . . . address 0x00 A port control register . . . address 0x04 B port data register . . . . . address 0x08 B port control register . . . address 0x0C C port data register . . . . . address 0x10 C port control register . . . address 0x14 D port data register . . . . . address 0x18 D port control register . . address 0x1C E port data register . . . . . address 0x20 E port control register . . . address 0x24
01 00
A7 A6 A5 A4 A3 A2 A1 A0 C C C C C C C C
B7 B6 B5 B4 B3 B2 B1 B0 C C C C C C C C
C7 C6 C5 C4 C3 C2 C1 C0 C C C C C C C C
D7 D6 D5 D4 D3 D2 D1 D0 C C C C C C C C
E7 E6 E5 E4 E3 E2 E1 E0 C C C C C C C C
A7, B7, C7, D7, E7 : data register C : control register (0 = IN, 1 = OUT) 0x00 : state of control register after RESET low
Ports D4 and D5 may be dedicated to the Comparator function, if the Comparator Enable bit is set. If so, then bits 4 and 5 of the D port Control register must be CLEAR. Please refer to Section 3.3, Comparator, for details.
Port D0 is connected to the branch condition COND1. Port D1 is connected to the branch condition COND2, assuming the comparator is disabled. Please refer to Section 3.1.4, Branch on D Port, (and to Section 3.3, Comparator) for more information. External interrupts can be caused by transitions on ports D2, D3, D4, and D5. The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs.
Peripheral Functions
3-3
I/O
3.1.2
Dedicated Input Port F
Port F is an 8-bit wide input-only port. The data presented to the input pin can be read by referring to the appropriate bit in the F port data register, address 0x28. This is done using the IN instruction, with the 0x28 address as an argument. The state of the F port data registers after RESET low is unknown (input state provided by external hardware) Each of the pins at port F has a programmable pull-up resistor. The resistance of these pullups is at least 100 k. All eight pullup resistors can be enabled by setting the enable pullup (EP) in the interrupt/general control register (IntGenCtrl). The address of the IntGenCtrl is 0x38, and the location of the EP bit is 12. Clearing the EP bit disables the eight pullups, and setting the EP bit enables the eight pullups. After RESET low, the default setting for the EP bit is 0 (F-port pullups disabled).
Input Port F Data register address Possible input data values Possible output data values Value after RESET low 0x28h Low = 0 High = 1
N/A Pullup resistors DISABLED
When reading from the 8-bit F-port data register to a 16-bit accumulator, the IN instruction automatically clears the extra bits in excess of 8. The desired bits in the result will be right-justified within the accumulator. The following table shows the bit locations of the port F address mapping:
F port Input Data register address 0x28h READ only
(8-bit wide location) 07 06 05 04 03 02 01 00 F7 F6 F5 F4 F3 F2 F1 F0
The external interrupt INT5 is triggered by a falling-edge event on any of the eight port-F input pins (see Section 3.1.5, Internal and External Interrupts). Specifically, INT5 is triggered if all eight port-F pins are held high, and then one or more of these pins is taken low. Port F, therefore, is especially useful as a key-scan interface.
3-4
I/O
3.1.3
Dedicated Output Port G
Port G is a 16-bit wide output-only port. The output drivers have a Totem-Pole configuration. The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port Data register, address 0x2C. This is done using the OUT instruction, with the 0x2C address as an argument. After RESET low, the default settings for the G port outputs are 0 (logical low).
Totem-Pole Output Port G Data register address Possible input data values Possible output data values Value after RESET low 0x2Ch N/A 0 = Low 1 = High
0 = Low
The following table shows the bit locations of the port G address mapping:
G port Data address 0x2C read and write
(16-bit wide location) 15 14 13 12 11
10
09
08 07 06 05 04 03 02 01 00
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 0x0000 : default state of data register after RESET low
Peripheral Functions
3-5
I/O
3.1.4
Branch on D Port
Instructions exist to branch conditionally depending upon the state of ports D0 and D1. These conditionals are COND1 and COND2, respectively. The conditionals are supported whether the D0 and D1 ports are configured as inputs or as outputs. The following table lists the four possible logical states for D0 and D1, along with the software instructions affected by them.
D0 = 1 COND1 = TRUE. . . CIN1 CNIN1 JIN1 JNIN1 CIN1 CNIN1 JIN1 JNIN1 CIN2 CNIN2 JIN2 JNIN2 CIN2 CNIN2 JIN2 JNIN2 has its conditional call taken. has its conditional call ignored. has its conditional jump taken. has its conditional jump ignored. has its conditional call ignored. has its conditional call taken. has its conditional jump ignored. has its conditional jump taken. has its conditional call taken. has its conditional call ignored. has its conditional jump taken. has its conditional jump ignored. has its conditional call ignored. has its conditional call taken. has its conditional jump ignored. has its conditional jump taken.
D0 = 0
COND1 = FALSE. . .
D1 = 1
COND2 = TRUE. . .
D1 = 0
COND2 = FALSE. . .
COND2 may be associated instead with the comparator function, if the comparator Enable bit is set. Please refer to Section 3.3, Comparator, for details.
3.1.5
Internal and External Interrupts
INT3, INT4, INT6, and INT7 are external interrupts which may be triggered by events on the PD2, PD3, PD4, and PD5 pins. These interrupts are supported whether the D-port pins are programmed as inputs or outputs. (When programmed as an output, the pin effectively triggers a software interrupt.) INT5 is an external interrupt triggered by a falling-edge event on any of the F-port inputs. It is triggered if all eight port-F pins are held high, and then one or more of these pins is taken low. Only the transition from 0xFFh (all high) to (one or more pins) low will trigger the INT5 event. If any F-port pin is continuously held low and another is toggled high-to-low, no interrupt is detected at the toggling pin. After all F-port pins have been brought high again, then it is possible for a new INT5 trigger to occur. INT0 is an internal interrupt (highest priority) which is triggered by an underflow condition on the DAC Timer (see Section 3.2.2, DAC Control and Data
3-6
I/O
Registers). INT1 and INT2 are high-priority, internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2, respectively. Please refer to Section 2.8, Timer Registers, for a full description of the TIMER controls and their underflow conditions.
When properly enabled, any of these interrupts may be used to wake the device up from a reduced-power state. In a deep-sleep state, they can also be used to wake the device when used in conjunction with the ARM bit. Please refer to Section 2.11, Reduced Power Modes, for information regarding the C614's reduced power modes. A summary of the interrupts is given in Table 3-1.
Table 3-1. Interrupts
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Vector 0x7FF0 0x7FF1 0x7FF2 0x7FF3 0x7FF4 0x7FF5 0x7FF6 0x7FF7 Source DAC Timer TIMER1 TIMER2 PD2 PD3 All port F PD4 PD5 Trigger Event Timer underflow Timer underflow Timer underflow Rising edge Falling edge Any falling edge Rising edge Falling edge Priority Highest 2nd 3rd 4th 5th 6th 7th Lowest Port D2 goes high Port D3 goes low Any F port pin goes from all-high to low Port D4 goes high Port D5 goes low Comment Used to synch. speech data
INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set.
Note: Interrupts in Reduced Power Mode An interrupt may be lost if its event occurs during power-up or wake-up from a reduced power mode. Also, note that interrupts are generated as a divided signal from the master clock. The frequency of the various timer interrupts will therefore vary, depending upon the operating master clock frequency.
Peripheral Functions
3-7
Digital-to-Analog Converter (DAC)
3.2 Digital-to-Analog Converter (DAC)
The C614 incorporates a two-pin pulse-density-modulated DAC which is capable of driving a 32 loudspeaker directly. To drive loud speakers other than 32 , an external impedance-matching circuit is required.
3.2.1
Pulse-Density Modulation Rate
The rate of the master clock (MC) determines the pulse-density-modulation (PDM) rate, and this governs the output sampling-rate and the achievable DAC resolution. In particular, the sampling rate is determined by dividing the PDM rate by the required resolution: Output sampling rate = PDM Rate / 2 (# DAC resolution bits) PDM Rate Set in ClkSpdCtrl register Address 0x3D #DAC resolution bits Set in DAC control register Address 0x34
For example, a 9 bit PDM DAC at 8 kHz sampling rate requires a PDM rate of 4.096 MHz. There are four sampling rates which may be used effectively within the constraints of the C614 and the various software vocoders provided by Texas Instruments. These are: 7.2 kHz, 8 kHz, 10 kHz, and 11.025 kHz. Other sampling rates, however, may also be possible. From the MC to the PDM clock, there is an optional divide-by-two in frequency. This option is controlled by the PDM clock divider in the interrupt/general control register. This means that the PDM rate can be set to run between 131.07 kHz and 33.554 MHz in 131.07 kHz steps (the same as the MC). Or, the PDM rate can be set to run between 65.536 kHz and the maximum achievable CPU frequency (see Chapter 8, MSP50C614 Electrical Specifications) in 65.536 kHz steps. The PDM clock divider determines which of these two ranges apply. Within these ranges, it is the PLLM which sets the rate: ClkSpdCtrl, 0x3D. Refer to Section 3.2.3, PDM Clock Divider, for more information regarding the PDM clock divider and the available combinations of CPU clock rates vs sampling rates. (Section 2.9.3, Clock Speed Control Register, has more details regarding the PLLM.)
3.2.2
DAC Control and Data Registers
The resolution of the PDM-DAC is selected using the control bits in the DAC control register (address 0x34). The available options are 8, 9, or 10 bits of resolution. Bits 0 and 1 in the DAC control register control this option:
3-8
Digital-to-Analog Converter (DAC)
DAC Control register Address 0x34 Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits:
(4-bit wide location) 03 02 01 00 DM DM DM E E E 0 0 1 0 1 0
DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DAC enable) 0x0 : default state of register after RESET low
Bit 2 in the DAC control register is used to enable/disable the pulse-density modulation. This bit must be set in order to enable the overall functionality of the DAC. After RESET is held low, the default state of bit 2 is clear. In this state, the output at the DAC pins is guaranteed to be zero (no PDM pulsing). During DAC activity, the PDM enable bit may also be toggled at any time to achieve the zero state. In other words, toggling the PDM enable bit from high-to-low-tohigh brings the DAC output to the known state of zero. Note: PDM Enable Bit By default, the PDM enable bit is cleared: DAC function is off. Data values are output to the DAC by writing to the DAC data register, address 0x30. The highest-priority interrupt, INT0, is generated at the sampling rate governed by the ClkSpdCtrl and the DAC control register. The program in software is responsible for writing a correctly-scaled DAC value to the DAC data register, in response to each INT0 interrupt. The register at 0x30 is 16-bits wide. The data is written in sign-magnitude format. Bit 15 of the register is the sign bit. Bits 14 and 13 are the overflow bits. Bits 12 through 3 are the data-value bits: The MSB is bit 12, and the LSB is bit 5, 4, or 3, depending on the resolution.
DAC Data register Address 0x30 Write Only 10 bit DAC resolution: 9 bit DAC resolution: 8 bit DAC resolution: S : Sign bit O : Overflow bits (16-bit wide location) 15 S S S 14 O O O 13 O O O 12 M M M 11 D D D 10 D D D 09 D D D 08 D D D 07 D D D 06 D D D 05 D D L 04 D L X 03 L X X 02 X X X 01 X X X 00 X X X
M : Most-significant data value L : Least-significant data value
D ; Data (magnitude) X : ignored bits
The overflow bits function in different ways, depending on the drive mode selected. The two DAC drive modes are informally named C3x style and C5x
Peripheral Functions
3-9
Digital-to-Analog Converter (DAC)
style. Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style.
The overflow bits appear in the DAC data register (14 and 13) to the left of the MSB data bit (12). In the C3x style mode, the overflow bits serve as a 2-bit buffer to handle overflow in the value field (bits 12...3). Any magnitude written to the value field which is greater than 1023 (up to the limit 4095) lands a 1 in the overflow. The overflow state (when a 1 appears in either bit 13 or 14) yields the maximum PDM saturation and delivers the maximum possible current drive to the loudspeaker. The overflow bits thus help to ensure that the audible artifacts of wrap-around do not occur.
3.2.3
PDM Clock Divider
The pulse-density-modulation rate is determined by the master clock. The PDM rate may be set equal to the rate of the MC, or it may be set at one-half the rate of the MC. This option is controlled by the PDM clock divider (PDMCD) in the interrupt/general control register (IntGenCtrl). The PDMCD is located at bit 13 in IntGenCtrl (address 0x38). Clearing the PDMCD bit results in a PDM rate equal to 1/2 MC (i.e., the CPU Clock rate). Setting the PDMCD bit results in a PDM rate equal to the MC. After RESET is held low, the default setting for the PDMCD bit is zero (PDM rate = 1/2 MC).
Figure 3-1. PDM Clock Divider
PDMCD PDM Clock Divider Bit 13 in IntGenCtrl MC Master Clock : 131.07 kHz ... 33.554 MHz (rate adjusted in ClkSpdCtrl) 0 /2 PDM Rate Pulse-Density-Modulation Rate Governs DAC Capacity 65.536 kHz ... FMAX or 131.07 ... 33.554 MHz
1
x1 (frequency)
/2
CPU Clock Core-Processor Speed 65.536 kHz ... FMAX (8 MHz is max assured : see Chapter 9)
3-10
Digital-to-Analog Converter (DAC)
For a given sampling rate and DAC resolution, the CPU clock rate may be increased, if necessary, through the use of over-sampling. In the previous example, an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used. A 2-times over-sampling, therefore, would require the PDM rate to be 8 MHz. This can be accomplished in two ways: PDM rate = 8 MHz : Set the master clock to 8 MHz also (ClkSpdCtrl). Set the PDMCD bit to 1: 1x master clock (IntGenCtrl). CPU clock rate will be 4 MHz. PDM rate = 8 MHz : Set the master clock to 16 MHz. Set the PDMCD bit to 0: 1/2 master clock. CPU clock rate will be 8 MHz. In the case of over-sampling, the same number of instructions are achievable between each INT0 interrupt. Not every INT0, however, requires an independently computed synthesis value, hence, the advantage in increased instruction capacity. A 2-times over-sampling means that every 2nd INT0 requires a computed update from the synthesis algorithm. The other INT0 may be satisfied with an interpolating filter computation, then a return to the main program. As stated previously, the maximum ensured CPU clock frequency for the C614 operates over the entire VDD range. This rate applies to the speed of the core processor. Operating the processor higher than the listed specification is not recommended by Texas Instruments. The following tables illustrate a number of possible combinations with respect to sampling rate, PDM rate, DAC resolution, master clock rate, and CPU clock rate. The first table applies to the 8 kHz sampling rate and N-times-8 kHz over-sampling. The second applies to the 10 kHz sampling rate and N-times-10 kHz over-sampling. Note: The value programmed to the PLLM register is not exactly the multiplicative factor between the 32-kHz reference and the master clock. Refer to Section 2.9.3, Clock Speed Control Register, for more information on the relationship between the PLLM and the resulting MC rate. The column in these tables output sampling rate reports the true audio sampling rate achievable by the C614, using the 32.768-kHz CRO. The values reported are not always exact multiples of the 8-kHz and 10-kHz options; however, they are the closest obtainable (using the PLLM multiplier) under the given set of constraints.
Peripheral Functions
3-11
Digital-to-Analog Converter (DAC)
8 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference ClkSpdCtrl PLLM Register Value (hex) 0x 0F 0x 1E 0x 3E 0x 7C 0x 1E 0x 3E 0x 7C 0x 1E 0x 3E 0x 7C 0x 3E 0x 7C 0x 3E 0x 7C 0x 7C Master Clock Rate (MHz) 2.10 4.06 8.26 16.38 4.06 8.26 16.38 4.06 8.26 16.38 8.26 16.38 8.26 16.38 16.38 CPU Clock Rate (MHz) 1.05 2.03 4.13 8.19 2.03 4.13 8.19 2.03 4.13 8.19 4.13 8.19 4.13 8.19 8.19 Output Sampling Rate (kHz) 8.19 15.87 32.26 64.00 7.94 16.13 32.00 7.94 16.13 32.00 8.06 16.00 8.06 16.00 8.00 Number of Instructs Between DAC Interrupts 128 128 128 128 256 256 256 256 256 256 512 512 512 512 1024 Number of Instructs Between 8 kHz Interrupts 128 256 512 1024 256 512 1024 256 512 1024 512 1024 512 1024 1024
DAC Precision 8 bits
IntGenCtrl PDMCD Bit 1
OverSampling Factor 1x 2x 4x 8x
PDM Rate (MHz) 2.10 4.06 8.26 16.38 2.03 4.13 8.19 4.06 8.26 16.38 4.13 8.19 8.26 16.38 8.19
0
1x 2x 4x
9 bits
1
1x 2x 4x
0
1x 2x
10 bits
1
1x 2x
0
1x
3-12
Digital-to-Analog Converter (DAC)
10 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference ClkSpdCtrl PLLM Register Value (hex) 0x 13 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 0x 4D 0x 9B 0x 4D 0x 9B 0x 9B Master Clock Rate (MHz) 2.62 5.11 10.22 20.45 5.11 10.22 20.45 5.11 10.22 20.45 10.22 20.45 10.22 20.45 20.45 CPU Clock Rate (MHz) 1.31 2.56 5.11 10.22 2.56 5.11 10.22 2.56 5.11 10.22 5.11 10.22 5.11 10.22 10.22 Output Sampling Rate (kHz) 10.24 19.97 39.94 79.87 9.98 19.97 39.94 9.98 19.97 39.94 9.98 19.97 9.98 19.97 9.98 Number of Instructs Between DAC Interrupts 128 128 128 128 256 256 256 256 256 256 512 512 512 512 1024 Number of Instructs Between 10 kHz Interrupts 128 256 512 1024 256 512 1024 256 512 1024 512 1024 512 1024 1024
DAC Precision 8 bits
IntGenCtrl PDMCD Bit 1
OverSampling Factor 1x 2x 4x 8x
PDM RATE (MHZ) 2.62 5.11 10.22 20.45 2.56 5.11 10.22 5.11 10.22 20.45 5.11 10.22 10.22 20.45 10.22
0
1x 2x 4x
9 bits
1
1x 2x 4x
0
1x 2x
10 bits
"1"
1x 2x
"0"
1x
Peripheral Functions
3-13
Comparator
3.3 Comparator
The C614 provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD4 and PD5. PD5 is the noninverting input to the comparator, and PD4 is the inverting input. When the comparator is enabled, the conditional operation COND2 (normally associated with PD1) becomes associated with the comparator result. In addition, the interrupts associated with PD4 and PD5 (namely, INT6 and INT7), become interrupts based on a transition in the comparator result. Finally, the start/stop function of TIMER1 may be controlled, indirectly, by a comparator transition. When enabled, therefore, the comparator controls the following four events: (1) Steady-State Comparator TRUE CIN2 CNIN2 VPD5 > VPD4 JIN2 JNIN2 COND2 = TRUE . . . has its conditional jump taken. has its conditional jump ignored. COND2 = FALSE . . . JIN2 JNIN2 has its conditional jump ignored. has its conditional jump taken.
has its conditional call taken. has its conditional call ignored. VPD5 < VPD4
(2) Steady-State Comparator FALSE CIN2 CNIN2
has its conditional call ignored. has its conditional call taken.
(3) Comparator transition FALSE-to-TRUE INT6 trigger event
VPD5 rises above VPD4 . . .
IF: [(INT6 Flag is SET) OR (INT7 Flag is CLEAR)] AND (TIMER1 Enable is CLEAR) THEN: TIMER1 stops counting (4) Comparator transition TRUE-to-FALSE INT7 trigger event IF: [(INT6 Flag is CLEAR) AND (INT7 Flag is SET)] OR (TIMER1 Enable is SET)] THEN: TIMER1 starts counting With regards to the transition events, the rising-edge in the comparator is a trigger for INT6. This happens independently of any activity associated with TIMER1. TIMER1, on the other hand, comes to a stop anytime the following conditional is true: IF: [(INT6 Flag is SET) OR (INT7 Flag is CLEAR)] AND (TIMER1 Enable is CLEAR)] THEN: TIMER1 stops counting INT6 flag refers to bit 6 within the interrupt flag register (IFR, peripheral port 0x39). This bit is automatically SET anytime that an INT6 event occurs. The
3-14
VPD5 falls below VPD4 . . .
Comparator
bit is automatically CLEARed again if an INT6 event occurs at the same time that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latter indicates that the program vectoring associated with INT6 is enabled. (The flag bit is SET when the INT event occurs. Only if the mask bit is set, does the interrupt service occur: vectoring takes place and the flag bit is once again cleared. Refer to Section 2.7, Interrupt Logic, for more details) The INT6 Flag may also be SET or CLEARed deliberately, at any time, in software. Use the OUT instruction with the associated I/O port address (IFR, address 0x39). INT7 flag refers to bit 7 within the interrupt flag register. This bit is automatically SET anytime that an INT7 event occurs. The bit is automatically CLEARed again if an INT7 event occurs at the same time that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 7). The latter indicates that the service for INT7 is enabled. The INT7 Flag may also be SET or CLEARed at any time, in software. Use the OUT instruction with the associated I/O port address (IFR, address 0x39). The TIMER1 enable bit is set or cleared in software: bit 10 of the IntGenCtrl. Similarly, the falling-edge event in the comparator is a trigger for INT7. This happens independently of any activity associated with TIMER1. TIMER1 starts counting anytime the following conditional is true: IF: [(INT6 Flag is CLEAR) AND (INT7 Flag is SET)] OR (TIMER1 Enable is SET)] THEN: TIMER1 starts counting
Figure 3-2. Relationship Between Comparator/Interrupt Activity and the TIMER1 Control
INT-Trigger Event INT Service Branch port-addressed write instruction TIMER1 ENABLE Bit 10, IntGenCtrl (0x38) INT Flag bits (IFR) Associated With the Interrupt-Trigger Event Interrupt Flag Register (0x39) 01 2 3 4 5 INT6 INT7
Comparator ENABLE Bit 15, IntGenCtrl (0x38)
TIMER1 Control 0 = TIM1 stopped 1 = TIM1 running
Peripheral Functions
3-15
Comparator
The comparator, along with all of its associated functions, is enabled by setting bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The default value of the register is zero: comparator disabled. Note: IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set, PD4 and PD5 become the comparator inputs. At any time during which bit 15 is set, PD4 and PD5 MUST be set to INPUT (I/O Port D Control, address 0x1C, bits 4 and 5 CLEARed). Failure to do so may result in a bus contention. The function of pins PD4 and PD5, and the behavior of events COND2, INT6, INT7, and TIMER1 are very different, depending on whether the comparator has been enabled or disabled. A summary of the various states appears in the following table: Comparator ENABLED SET bit 15 in the IntGenCtrl, address 0x38 . . . (port D Control, 0x1C, bit 4 MUST be 0) (port D Control, 0x1C, bit 5 MUST be 0) (PD5 relative to PD4) (relative to PD4) (assuming TIMER1 Enable is 0)
PD4 functions as comparator negative input PD5 functions as comparator positive input COND2 maps to the state of the comparator INT6 is triggered by a rising edge at PD5 INT7 is triggered by a falling edge at PD5 TIMER1 may be started by a falling edge at PD5 TIMER1 will be stopped by a rising edge at PD5 Comparator DISABLED PD4 functions as a general I/O pin PD5 functions as a general I/O pin COND2 maps to the state of the I/O pin PD1 INT6 is triggered by a rising edge at PD4 INT7 is triggered by a falling edge at PD5
CLEAR bit 15 in the IntGenCtrl, address 0x38 . . . (port D Control 0x1C, bit 4 = 0 or 1) (port D Control 0x1C, bit 5 = 0 or 1) (0 or 1 logical) (0 to 1 logical) (1 to 0 logical)
TIMER1 is started/stopped in software by setting/clearing TIMER1 enable (IntGenCtrl)
3-16
Interrupt/General Control Register
3.4 Interrupt/General Control Register
The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The service branch enable status for each of the eight interrupts is registered in the IMR. A SET bit in the IMR enables that interrupt to assume the service branch (at the time that the associated trigger event occurs). A CLEAR bit disables the service branch for that interrupt. The IMR is located at bits 0 through 7 in the IntGenCtrl. Bit 0 is associated with INT0, which is the highest priority interrupt. Bit 7 is associated with INT7. Refer to Section 2.7, Interrupt Logic, for more information regarding the interrupt-system logic and initialization sequence.
IntGenCtrl register address 0x38 (16-bit wide location) 15 CE 14 13 12 EP 11 E2 10 E1 09 S2 08 S1 07 D5 06 D4 05 04 03 D2 02 T2 01 T1 00 DA
AR PD
PF D3
low priority 0x0000 : State after RESET low Interrupt mask register CE : Comparator enable AR : ARM bit PD : Pulse-density clock: PDMCD EP : Enable pullup resistors on port F E2 : Enable TIMER2 (1 value starts timer) E1 : Enable TIMER 1 (1 value starts timer) S2 : Clock source for TIMER2 (0 chooses 1/2 MC) S1 : Clock source for TIMER1 (0 chooses 1/2 MC) D5 D4 D3 D2 PF T2 T1 DA : : : : port D5 falling-edge port D4 rising-edge port D3 falling-edge port D2 rising-edge
high priority
: any port F falling-edge : TIMER2 underflow : TIMER1 underflow : DAC timer underflow
(1 value enables interrupt service)
The remaining bits in the IntGenCtrl have various control functions which are not directly related to the interrupt system. Four of these are related to the timer functions. Bits 8 and 9 are used to select the clock sources which govern the rates of TIMER1 and TIMER2. Clearing bit 8 chooses 1/2 MC as the source for TIMER1 (i.e., the TIMER runs at one-half the frequency of the Master Clock). Setting bit 8 chooses the oscillator reference (RTO or CRO) as the source for TIMER1. (The same applies for bit 9 and TIMER2.) Bits 10 and 11 in the IntGenCtrl are used to enable TIMER1 and TIMER2, respectively. Setting bit 10 starts TIMER1, and clearing bit 10 stops TIMER1. (The same applies for bit 11 and TIMER2).
Peripheral Functions
3-17
Interrupt/General Control Register
The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on input port F. Setting this bit engages all 8 F-port pins with at least 100-k pull-ups (see Section 3.1.2, Dedicated Input Port F) Bit 13 is the PDMCD bit for the pulse-density modulation clock. Clearing this bit yields a PDM clock rate equal to one-half the frequency of the master clock (i.e., the CPU clock rate). Setting bit 13 yields a PDM rate equal to the rate of the master clock (see Section 3.2.3, PDM Clock Divider) Bit 14 is the ARM bit. The set ARM bit causes an asynchronous response to the internal and external interrupts during the sleep state. If the master clock has been suspended during sleep, then the ARM bit must be set (before the IDLE instruction), in order to allow a programmable interrupt to wake the C614. Refer to Section 2.11, Reduced Power Modes, for more information. Finally, the top-most bit in the IntGenCtrl is the comparator enable bit. Setting bit 15 enables the comparator and all of its associated functions. Some of the C614's conditions, interrupts, and timers behave differently, depending on whether the comparator is enabled or disabled by this bit. Refer to Section 3.3, Comparator, for a full description.
3-18
Hardware Initialization States
3.5 Hardware Initialization States
The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the C614. When the RESET pin is held low, the device assumes a deep sleep state and various control registers are initialized. After the RESET pin is taken high once again, the Program Counter is loaded with the value stored in the RESET Interrupt Vector. Note: Internal Power Reset Function There is no power-on reset function internal to the C614. After the initial power-up or after an interruption in power, the RESET pin must be cycled low-tohigh. The application circuitry must therefore provide a mechanism for accomplishing this during a power-up transition or after a power fluctuation. The application circuits shown in Section 6.1, Application Circuits, illustrate one implementation of a reset-on-power-up circuit. The circuit consists of an RC network (100 k, 1 F). When powering VDD from 0 V to 4.5 V, the circuit provides some delay on the RESET pin's low-to-high transition. This delay helps to ensure that the C614 initialization occurs after the power supply has had time to stabilize between VDD MIN and VDD MAX. VDD MIN and VDD MAX are the minimum and maximum supply voltages as rated for the device. The circuit shown, however, may not shield the RESET pin from every kind of rapid fluctuation in the power supply. At any time that the power supply falls below VDD MIN, even momentarily, then the RESET pin must be held low and then high once again, either by the user of the device or by some other external circuitry. Refer to Chapter 8, MSP50C614 Electrical Specifications, for a characterization of the values VDD MIN, VDD MAX, VIL, and VOL. (VIL and VOL are the low-level and high-level input voltages, respectively, which dictate the precise levels of transition for RESET.) When the RESET pin is held low, the C614 is considered reset and has the following internal states: RESET low . . .
-
I/O ports are be placed in a high impedance Input condition: Ports A, B, C, D, and E. All outputs on Port G is are set to low (0x0000). Device is placed in a deep sleep state (refer to reduced power mode IV in Table 2-7). PLL circuitry, master clock, CPU clock, and TIMERs are stopped. Current draw from the VDD is less than 10 A in this condition. Interrupt flag register (IFR at address 0x39) is not automatically cleared. Internal RAM is not automatically cleared.
Peripheral Functions
3-19
Hardware Initialization States
Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power. This applies also to the interrupt flag register. The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, many of the programmable controls and registers are left in their default states: RESET high, just after low . . .
-
No reference oscillator is enabled. PLL runs at its minimum achievable rate. Master clock runs at a very slow frequency (less than 100 kHz). PLL multiplier is set to 0x00 (renders slowest speed for MC, once reference is enabled). RTO oscillator trim bits are set to zero (renders slowest speed for RTO, once enabled). Interrupt mask register is 0x00. Global interrupt enable is clear. All Interrupts are disabled. I/O Ports A through E and output Port G have the same state as in RESET low. All pull-up resistors on input Port F are disabled. DAC circuitry is disabled (no PDM pulsing). Both TIMER1 and TIMER2 are disabled. Count-down and period registers are 0x0000. The status register is partially initialized, as specified in Table 3-1. Idle state clock control and ARM bit are both set to zero.
When in this state, the processor runs, albeit slowly. It executes the following initialization routine, then resumes execution of the program: 1) ROM block protection word is read from address 0x7FFE. 2) ROM block protection word is loaded to an internal register. 3) RESET interrupt vector is read from address 0x7FFF. 4) Program counter is loaded with the value read from (3); execution resumes there.
3-20
Hardware Initialization States
Note: Stack Pointer Initialization The software stack pointer (R7) must be initialized by the programmer, so that it points to some legitimate address in data memory (RAM). This must be done prior to any CALL or CCC instruction. If this is not done, then the first push/pop operation performed on the STACK will render the Program Counter to an unknown state.
Table 3-2. State of the Status Register (17 bit) after RESET Low-to-High (Bits 5 through 16 are left uninitialized)
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bit Name XM UM OM FM IM (reserved) XZF XSF RCF RZF OF SF ZF CF TF1 TF2 TAG Same state as before RESET Initialized Value 0 0 0 0 0 Description Extended sign mode disabled Unsigned multiplier mode disabled (allows signed multiplier mode) Overflow mode disabled (allows ALU normal mode) Shift mode for fractional multiplication disabled (allows unsigned fractional/integer arithmetic) Global interrupt enable bit Reserved for future use Transfer equal-to-zero status bit Transfer sign status bit Auxiliary register carry-out status bit Auxiliary register equal-to-zero status bit Accumulator overflow status bit Accumulator sign status bit (extended 17th bit) Accumulator equal-to-zero status bit (16 bits) Accumulator carry-out status bit (16th ALU bit) Test flag 1 Test flag 2 Memory tag
Peripheral Functions
3-21
3-22
Chapter 4
Assembly Language Instructions
This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described.
Topic
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Instruction Syntax and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . 4-8 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Bit, Byte, Word and String Addressing . . . . . . . . . . . . . . . . . . . . . . . . 4-44 MSP50P614/MSP50C614 Computational Modes . . . . . . . . . . . . . . . . 4-49 Hardware Loop Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 String Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 Lookup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4.10 Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 4.11 Special Filter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59 4.12 Conditionals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69 4.13 Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 4.14 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 4.15 Instruction Set Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 4.16 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-196
4-1
Introduction
4.1 Introduction
In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding. The execution of programs can only be executed from internal program memory. Usable program memory starts from location 800h. The data memory is 640 by 17-bits of static RAM, 16 bits of which are an arithmetic value. The 17th bit is used for flags or tags.
4.2 System Registers
A functional description of each system register is described below.
4.2.1
Multiplier Register (MR)
The multiplier uses this 16-bit register to multiply with the multiplicand. MOV instructions are used to load the MR register. The multiplicand is usually the operand of the multiply instructions. All multiply, multiply-accumulate instructions, and filter instructions (FIR, FIRK, COR and CORK) use the MR register (see Section 4.11 for detail).
4.2.2
Shift Value Register (SV)
The shift value register is 4-bits wide. For barrel shift instructions, the multiplier operand decodes a 4 bit value in the shift value register (SV) to a 16 bit value. For example, a value of 7H in the SV register is decoded to a multiplier operand of 0000000010000000 binary. In effect, this causes a left shift of 7 bits to in the final 32 bit product. In other words, a nonzero value, say k (0 k 15), in the SV register means padding k number of zeros to the right of the final result.
4.2.3
Data Pointer Register (DP)
The data pointer register (DP) is a 16-bit register that is used to point to a program memory location for various look up table instructions. DP is not directly loaded by the user, It is loaded during the execution of lookup instructions overwriting the previous content of the DP register. Lookup instructions are described in detail in section 4.9. The DP register autoincrements the next logical program memory location after the execution of a lookup instruction. In addition to lookup instructions, the filter instructions FIRK and CORK (see Section 4.11 for detail) use the DP pointer to look up filter coefficients. It may be required to context save and restore the DP in interrupt service routines.
4.2.4
Program Counter (PC)
The program counter (PC) holds the program memory location to be used for the next instruction's execution. It increments (by 1 for single word instructions
4-2
System Registers
or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction. Call and jump instructions also store the next instruction address by adding PC+2 and then storing the result in the TOS register. Upon encountering a RET instruction, the TOS value is reloaded to the PC. Call instructions may not precede RET instructions. Similarly, a RET instruction may not immediately follow another RET instruction. In these conditions, pipeline operations breaks down and the PC never recovers its return address from the TOS register. The processor stalls, and the only solution is to reset the device. On the other hand, RET can be safely replaced by IRET eliminating processor stalls in all conditions. However, IRET takes one more cycle than RET.
4.2.5
Top of Stack, (TOS)
The top of stack (TOS) register holds the value of the stack pointed by the stack register (R7). The MSP50P614/MSP50C614 hardware uses TOS register for very efficient returns from CALL instructions. Figure 4-1 shows the operation of the TOS register. When call instructions are executed, the old TOS register value is pushed into the stack by pre-incrementing R7. The current PC value is incremented by 2 to compute the final return address and is then stored in the TOS register. Thus, the TOS register holds the next PC value pointing to the next instruction. When the subroutine reaches the RET instruction, the program counter (PC) is loaded with the TOS register. Next, the TOS is loaded with the value pointed to by R7. Finally, the stack register (R7) is decremented.
Figure 4-1. Top of Stack (TOS) Register Operation
Program counter (PC) +2 Top of stack register (TOS) Read before incrementing R7 Data memory stack area Increment R7 then store TOS value Stack register (R7) Preincrement during write (+2) Postdecrement during read (+2)
The MSP50P614/MSP50C614 development tools use the TOS register for parameter passing. The TOS register must be used with caution inside user programs. If the TOS register and stack register (R7) are not restored to their previous values after using the TOS register in an application, the program can hang the processor or cause the program to behave in an unpredictable way.
Assembly Language Instructions
4-3
System Registers
It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only.
4.2.6
Product High Register (PH)
This register holds the upper 16 bits of the 32 bit result of a multiplication, multiply-accumulate, or shift operation. The lower 16 bits of the result are stored in the PL register. The PH register can be loaded directly by MOV instructions. Special move accumulate instructions MOVAPH, MOVAPHS, MOVSPH, MOVSPHS also use the PH register.
4.2.7
Product Low Register (PL)
This register holds the lower 16 bits of the 32 bit result of a multiplication, multiply-accumulate, or shift operation. The upper 16 bits of the result are stored in the PH register. There are no instructions that load or save the PL register directly, but multiply-accumulate instructions allow the contents of the PL register to be added, subtracted or transferred to the accumulator.
4.2.8
Accumulators (AC0-AC31)
There are 32 accumulators on the MSP50P614/MSP50C614. Each is 16 bits wide. The first sixteen accumulators, AC0-AC15, have offset accumulators, AC16-AC31, and vice versa. At any one time, four accumulators can be selected through accumulator pointer registers, AP0-AP3 (see section 4.2.9). Some instructions can specify offset accumulators which are the accumulators pointed to by APn +16 or APn -16 (whichever is in the range 0 to 31). The offset accumulators are indicated by an offset bit (A~) in some instructions. When this bit is 0, An points to the accumulator directly. If it is 1, then An~ points to the offset (for some instructions this scheme changes). The selected accumulator pointer register should contain the index to the corresponding accumulator. For example, if AP0 has a value of 25, then it is pointing to accumulator AC25. If the offset bit is 1, A0~, then it is pointing to accumulator AC9 (25-16=9). Because, accumulators can only be addressed through accumulator pointers, special symbols are used in MSP50P614/ MSP50C614 instructions. Accumulators are indicated by the symbol An, where n ranges from 0 to 3. The symbol indicates that the accumulator pointed to by APn is the referring accumulator. If APn has a value of k, it is pointing to accumulator ACk. Similarly, An~ points to the offset accumulator pointed by APn. For example, if AP3 = 22, then A3 is accumulator AC22 and A3~ is accumulator AC6.
4-4
System Registers
During accumulator read operations, both An and offset An~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumulator (An or An~) is the least significant word (LSW) of the string and is restored at the end of the operation. String instructions are described in detail in section 4.8.
4.2.9
Accumulator Pointers (AP0-AP3)
The accumulator pointer (AP) registers are 5 bit registers which point to one of the 32 available accumulators. The APs contain the index of accumulators. Many instructions allow preincrement or predecrement accumulator pointers. Such instructions have a suffix of ++A for preincrement or - -A for predecrement. Accumulator pointers can be stored or loaded from memory using various addressing modes. Limited arithmetic operations can be performed on accumulator pointers.
Bit AP0-AP3 Bits 16 - 5 Not used 4 3 2 1 0
Points to An n = val (b0-b4)
4.2.10 Indirect Register (R0-R7)
Indirect registers, R0-R7, are 16-bit registers that are used in various addressing modes or as general-purpose registers. R0, R1, R2 and R3 can be used solely as general-purpose registers. These registers can also be used as indirect registers with relative addressing. The R4 or LOOP register is used with instructions BEGLOOP and ENDLOOP to define a hardware controlled loop. If R4 is loaded with a value, n (0 n 32767), the BEGLOOP and ENDLOOP block will be executed n+2 times. The loop stops when R4 becomes negative. The R5 or INDEX register is used with indirect addressing and relative addressing modes of certain instructions. The R6 or PAGE register is used with page relative addressing and relative flag addressing. The R7 or STACK register holds the pointer to the stack. It can be used as a general-purpose register as long as no CALL/RET instructions are used before restoring it with its old value. However, this register can only be used as a general-purpose register when maskable interrupts are disabled. The old
Assembly Language Instructions
4-5
System Registers
value of the STACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used. CALL instructions increment R7 by 2., RET instructions decrement R7 by 2. The stack in MSP50P614/MSP50C614 is positively incremented.
4.2.11 String Register (STR)
The string register (STR) holds the length of the string used by all string instructions. MOV instructions are used to load this register to define the length of a string. The value in this register is not altered after the execution of a string instruction. A value of zero in this register defines a string length of 2. Thus, a numerical value, ns, in the STR register, defines a string length of ns+2. The maximum string length is 32. Therefore, 0 nS 30 corresponds to actual string lengths from 2 to 32.
4.2.12 Status Register (STAT)
The status register (STAT) provides the storage of various single bit mode conditions and condition bits. As shown in Table 4-1, mode bits reside in the first 5 LSBs of the status register and can be independently set or reset with specific instructions. See section 4.6 for detail about these computational modes. Condition bits and flags are used for conditional branches, calls, and flag instructions. Flags and status condition bits are stored in the upper 10 bits of the 17 bit status register. MOV instructions provide the means for context saves and restores of the status register. The STAT should be initialized to 0000h after the processor resets. The XSF and XZF flags are related to data flow to or from the internal data bus. If the destination of the transfer is an accumulator, then the SF, ZF, CF and OF flags are affected. If the destination of the transfer is Rx, the RCF and RZF flags are affected. If the destination of the transfer is through the internal databus, the XSF and XZF flags are affected. The SF flag is the sign flag and it is equal to the most significant bit of an accumulator when an accumulator instruction is executed. ZF is the zero flag and is set when the instruction causes the accumulator value to become zero. CF is the carry flag and is set when the instruction causes a carry. A carry is generated by addition, subtraction, multiplication, multiply-accumulate, compare, shifting and some MOV instructions (that have accumulation features). CF is reset if no carry occurs after execution of an instruction. OF is set when a computation causes overflow in the result. It is reset if no overflow occurs during an accumulator based instruction. Overflow saturation mode is set by the OM bit as explained in section 4.6.
4-6
System Registers
Table 4-1. Status Register (STAT)
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XM UM OM FM IM Function Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Overflow mode. This bit is one if overflow (saturation) mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Fractional multiplication shift mode. This bit is set if fractional mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Maskable interrupt enable mode. If this bit is zero, all maskable interrupts are disabled.
Reserved Reserved for future use. XZF XSF RCF RZF OF SF ZF CF TF1 TF2 TAG Transfer(x) equal to zero status (flag) bit. In transfer instructions, this bit is set if the operation cause the destination result to become zero (excluding accumulator and Rx registers). Transfer(x) sign status (flag) bit. In transfer instructions, the sign bit of the value is copied to this bit if the destination is not accumulator or Rx registers. Indirect register carry out status (flag) bit. This bit is set if an addition to the value of Rx register caused a carry. Indirect register equal to zero status (flag) bit. This bit is set if the Rx register content used by the instruction is zero. Accumulator overflow status (flag) bit. This bit is set if an overflow occurs during computation in ALU. Accumulator sign status (flag) bit (extended 17th bit). This bit is set if the 16th bit (the sign bit) of the destination accumulator is 1. Accumulator equal to zero status (flag) bit (16 bits). This bit is set to 1 if the result of previous instruction cause the destination accumulator to become zero. Accumulator carry out status (flag) bit ( 16th ALU bit). Test Flag 1. Test flags are related with Class 8 instructions discussed later. Test Flag 2. Test flags are related with Class 8 instructions discussed later. Memory tag. Holds the 17th bit whenever a memory value is read.
Assembly Language Instructions
4-7
Instruction Syntax and Addressing Modes
4.3 Instruction Syntax and Addressing Modes
MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destination arguments. In the following subsection, a detail of the MSP50P614/MSP50C614 instruction syntax is explained followed by the subsection which describes addressing modes.
4.3.1
MSP50P614/MSP50C614 Instruction Syntax
All MSP50P614/MSP50C614 instructions with multiple arguments have the following syntax: name [dest] [, src] [, src1] [, mod] where the symbols are described as follows:
name
name of the instruction. Instruction names are shown in bold letters. If the instruction name is followed by a B, the arguments are all byte types. If name is followed by an S, all arguments are word string (strings of words) types. If name is followed by BS, all arguments are byte string types. destination of data to be stored after the execution of an instruction. Optional or not used for some instructions. Destination is also used as both a source and a destination for some instructions. If a destination is specified, it must always be the first argument. Destinations can be system registers or data memory locations referred by addressing modes. This is instruction specific. source of first data. Optional or not used for some instruction. Source can be a system register, a data memory location referred by addressing modes, or a program memory location. This is instruction specific. source of second data. Some instructions use a second data source. Optional or not used for some instructions. Source 1 can be a system register, a data memory location referred by addressing modes, or a program memory location. This is instruction specific.
pre or post modification of a register. The meaning of mod is instruction specific. Square brackets represent optional arguments. Some instructions have many combinations of source and destination registers and addressing modes. The combination is instruction class specific.
dest
src
src1
mod
[]
The possible combinations of sources, destinations and modifications are dependent on the instruction class. Instruction classes are discussed in detail in section 4.4.
4-8
Instruction Syntax and Addressing Modes
4.3.2
Addressing Modes
The addressing modes on the MSP50P614/MSP50C614 are immediate, direct, indirect with post modification, and three relative modes. The relative modes are:
-
Relative to the INDEX or R5 register. The effective address is (indirect register + INDEX). Short relative to the PAGE or R6 register. The effective address is (PAGE+7 bit positive offset). Long relative to Rx. The effective address is (indirect register Rx + 16 bit positive offset).
When string instructions are executed, the operation of the addressing mode used is modified. For all addressing modes except indirect with post modification, a temporary copy of the memory address is used to fetch the least significant data word of the string. Over the next n instruction cycles, the temporary copy of the address is auto-incremented to fetch the next n words of the string. Since the modification of the address is temporary, all Rx registers are unchanged and still have reference to the least significant data word in memory. String data fetches using the indirect with post modification addressing mode and writes the modified address back to the indirect register at each cycle of the string. This will leave the address in the Rx register pointing to the data word whose address is one beyond the most significant word of the string. All addressing modes except immediate addressing are encoded in bits 0 to 7 of the instruction's op-code. Table 4-2 through Table 4-6 show the encoding of various addressing modes. Addressing mode bits (except immediate and flag addressing) come with an am, Rx and pm field. These are combined into a single field called {adrs}. The appropriate decoding and syntax for each addressing mode with the {adrs} field is described in Table 4-4. The pm field only applies to indirect addressing. For other addressing modes, it is coded as zero.
Table 4-2. Addressing Mode Encoding
Bit Opcode 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Rx 2 1 0
next A
am
pm
am contains addressing mode bits 5 - 7. See Table 4-4 for details. Rx is the register being used. See for Table 4-3 for details. pm is the post modification flag. See Table 4-3 for details. next A is the accumulator pointer premodification field. See Table 4-5 for details.
Assembly Language Instructions
4-9
Instruction Syntax and Addressing Modes
Table 4-3. Rx Bit Description
Rx 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 R0 R1 R2 R3 R4 or LOOP R5 or INDEX R6 or PAGE R7 or STACK Operation
Table 4-4. Addressing Mode Bits and {adrs} Field Description
addressing mode encoding, adrs Relative Addressing Modes Direct Short relative Relative to R5 Long relative Indirect Clocks Words clk w Repeat Operation clk nR+4 nR+2 nR+2 nR+4 nR+2 {adrs} 7 6 5 4 3 2 1 0
am
*dma16 *R6 + offset7 *Rx + R5 *Rx + offset16 *Rx *Rx++ 0 *Rx- - *Rx++R5 1 1 0 1 0 0 1 0 0 1 0 0
Rx (x = 0 ... 7) Rx offset7 Rx Rx 0 0 0 0 Rx 1 1 0
pm
0
2 1 1 2 1
2 1 1 2 1
0 0 0 1 0 1
= dma16 and offset16 is the second word nR is RPT instruction argument
4-10
Instruction Syntax and Addressing Modes
Table 4-5. MSP50P614/MSP50C614 Addressing Modes Summary
ADDRESSING Direct Long Relative SYNTAX OPERATION Second word operand (dma16) used directly as memory address. Selects one of 8 address registers as base value and adds the value in the second word operand. Does not modify the base address register. Selects one of 8 address registers as base value and adds the value in R5. Does not modify the base address register. Selects one of 8 address registers to be used as the address, post modifications of increment, decrement, and + INDEX(R5) are possible.
name [dest,] [src,] *dma16 [*2] [, next A] name *dma16 [*2] [,src] [, next A] name [dest] [,src] ,*Rx+offset16 [, next A] name *Rx+offset16 [,src] [, next A] name [dest] [,src] ,*Rx+R5 [, next A] name *Rx+R5 [,src] [, next A] name [dest] [, src] ,*Rx++R5 [, next A] name [dest] [, src] ,*Rx [, next A] name [dest] [, src] ,*Rx++ [, next A] name [dest] [, src] ,*Rx-- [, next A] name *Rx++R5 [, src] [, next A] name *Rx [, src] [, next A] name *Rx++ [, src] [, next A] name *Rx-- [, src] [, next A] name [dest] [, src] ,*R6+offset7 [, next A] name *R6+offset7 [, src] [, next A]
Relative to R5 (INDEX) Indirect
Short Relative
Selects PAGE(R6) register as the base address and adds a 7 bit positive address offset from operand field (b6-b0). This permits the relative addressing of 128 bytes or 64 words. Does not modify the PAGE address register. k is shown as constant. For use with flag instructions only. Adds lower 7 bits of instruction to a fixed address base reference of zero. 64 fixed flags are addressed by this mode beginning at address 0000h. For use with flag instructions only. Adds lower 7 bits of instruction(lsb set to zero) to a address base reference stored in the PAGE register (R6). 64 flags relative to PAGE may be addressed with this mode.
Global Flag
name TFn, dma6 name dma6, TFn
Relative Flag
name TFn, *R6+offset6 name *R6+offset6, TFn
Table 4-6. Auto Increment and Auto Decrement Modes
Operation No modification Aufto increment Auto decrement String mode ++A - -A Syntax 0 0 1 1
next A
0 1 0 1
Table 4-6 describes the accumulator pointer auto preincrement or predecrement syntax. Not all instructions can premodify accumulator pointers. The next A field is a two bit field using bits 10 and 11 of only certain classes of instructions. Instructions with a [next A] have either a --A or a ++A in the instruction. See Table 4-6.
Assembly Language Instructions
4-11
Instruction Syntax and Addressing Modes
For any particular addressing mode, replace the {adrs} with the syntax shown in Table 4-4. To encode the instruction, replace the am, Rx and pm bits with the bits required by the addressing mode (Table 4-4). For example, the instruction MOV An[~], {adrs} [, next A] indicates all of the following (only partial combinations are shown): MOV A0, *0xab12 ; n = 0, {adrs} = dma16 = 0xab12
MOV A1, *R6+0x2f, ++A ; n = 1, {adrs} = *R6+0x2f, offset7 = 0x2f, [next A] = ++A MOV A2~, *R0+R5, - -A ; n = 2, {adrs} = *R0+R5, x = 0, [next A] = - -A MOV A3, *R1+0x12ef MOV A0, *R2 MOV A1, *R3++, - -A MOV A2~, *R4- - ; n = 3, {adrs} = *R1+0x12ef, x = 1, offset16 = 0x12ef ; n = 0, {adrs} = *R2, x = 2 ; n = 1, {adrs} = *R3++, x = 3, [next A] = --A ; n = 2, {adrs} = *R4--, x = 4
MOV A3, *R7++R5, ++A ; n = 3, {adrs} = *R7++R5, x = 7, [next A] = ++A Flag instructions apply to certain classes of instructions (Class 8a). They address only the flag bit by either a 6 bit global address or a 6 bit relative address from the indirect register R6. If bit 0 of these instructions is 0, then bits 1 to 6 of the opcode are taken as the bit address starting from data memory location 0000h. If bit 0 is 1, then bits 1 to 6 are used as an offset from the page register R6 to compute the relative address. Bits 0 to 6 of flag instructions are written as {flagadrs} throughout this manual. When this symbol appears, it should be replaced by the syntax and bits shown in Table 4-7 For example, AND TFn, {flagadrs} can be written as follows (not all possible combinations are shown): AND TF1, *0x21 AND TF2, *R6+0x21 ; global flag addressing, flag address is 0x21 absolute ; relative flag addressing, flag address is R6+0x21 absolute
Table 4-7. Flag Addressing Field {flagadrs} for Certain Flag Instructions (Class 8a)
{flagadrs} Flag Addressing Modes Global Relative
nR is RPT argument
flag addressing mode encoding, flagadrs 6 5 4 3 2 1 0 g/r 0 1
Clocks Words clk w
Repeat Operation, clk nR+2 nR+2
Syntax
flag address bits *dma6 *R6+offset6 dma6 offset6
1 1
1 1
4-12
Instruction Syntax and Addressing Modes
4.3.3
Immediate Addressing
The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax:
name dest, [src,] imm [, next A]
Where: imm is the immediate value of a 16 bit number. Example 4.3.1 ADD AP0, 0x1A Assume the initial processor state in Table 4-8 before execution of this instruction. This instruction adds the immediate value 0x1A to AP0. Final result AP0 = 0x1A + 2 = 0x1C.
Table 4-8. Initial Processor State for the Examples Before Execution of Instruction
Registers (register# = value) AP0 = 2 R0 = 0x0454 R4 = 0x0000 AC2 = 0x13F0 AC3 = 0xFEED MR = 0x1A15 data memory (*address = data) [word address; to convert to byte, address multiply by 2] *0x022A = 0x0400 *0x0100 = 0x0ABC *0x01F2 = 0x12AC *0x0080 = 0x0000 *0x02A1 = 0x1001 *0x0001 = 0x499A *0x012F = 0x0000 *0x01FA = 0x0112 AP1 = 21 (0x15) R1 = 0x0200 R5 = 2 AC1 = 0x0007 AC28 = 0x11A2 AP2 = 11 (0x0B) R2 = 0x0540 R6 = 0x03E4 AC17 = 0x0112 AC29 = 0xAB AP3 = 29 (0x1D) R3 = 0x03E2 R7 = 0x0100 AC20 = 0x3321 AC19 = 0x1200
program memory (*address = data) *0x13F0 = 0x1B12
Example 4.3.2 MOV R5, 0xF000 Loads the immediate value 0xF000 to R5 register. Final result, R5 = 0xF000. Example 4.3.3 MOVB MR, 0xF2 Loads the immediate byte 0xf2 to MR register. Final result, MR = 0xf2. Example 4.3.4 AND A0, A0~, 0xFF20, - -A Assume the initial processor state in Table 4-8 before execution of this instruction. The source accumulator pointer AP0 is predecremented. After predecrement, A0 points to AC1, and A0~ points to AC17. AC17 is anded with the immediate 16 bit value (0xFF20) and the result is stored in AC1. Final result, AP0 = 1, AC1 = 0xFF20 AND AC17 = 0xFF20 AND 0x0112 = 0x0100.
Assembly Language Instructions
4-13
Instruction Syntax and Addressing Modes
4.3.4
Direct Addressing
Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax:
name [dest,] [src,] *dma16 [* 2] [, next A] name *dma16 [* 2] [, src] [, next A]
Memory Operand Operand
Note the multiplication by 2 with the data memory address. This only needs to be done for word addresses, i.e., the address that points to 16-bit words. This is not required for byte addresses. This is explained in detail in section 4.5. Example 4.3.5 MOV A2, *0x022A * 2 Refer to the initial processor state in Table 4-8 before execution of this instruction. Loads the contents of data memory location 0x022A (=0x0400) to A2 or AC11. The MSP50P614/MSP50C614 always accesses data memory as byte addresses. To read a word address, multiply the address by 2. Final result, A2 = AC11 = 0x0400. Example 4.3.6 MOV A1~, *0x01F2 * 2, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement AP1. After preincrement A1 is AC22 and A1~ is AC6. The content of data memory location 0x01F2 (=0x12AC) is then loaded to accumulator AC22 (offset of AC6). Final result, AP1=22, AC6 = 0x12AC. Example 4.3.7 SUB A1~, A1, *0x02A1 * 2, - -A Refer to the initial processor state in Table 4-8 before execution of this instruction. Predecrement AP1. After predecrement A1 is AC20 and A1~ is AC4. Subtract the content of 0x02A1 (=0x1001) in data memory from AC20 and store result to AC4. Final result, AP1 = 20, AC4 = AC20 - 0x1001 = 0x3321 - 0x1001 = 0x2320. Example 4.3.8 MOV *0x012F * 2, *A0 Refer to the initial processor state in Table 4-8 before execution of this instruction. This is a table lookup instruction. This instruction reads the program memory address stored in A0 or AC2 and stores the data in data memory location 0x012F. Final result, *0x012F = 0x1B12. Example 4.3.9 MULR *0x02A1 * 2 Refer to the initial processor state in Table 4-8 before execution of this instruction. Multiply MR with the contents of 0x02A1. The MSB of the result is stored in PH register and rounded. The LSB is ignored. Final result, multiply MR * *0x02A1 = 0x1A15 * 0x1001 = 0x1A16A15, PH = 0x01A1.
4-14
Instruction Syntax and Addressing Modes
4.3.5
Indirect Addressing
Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications, the register increments or decrements itself by 2 for word operands and by 1 for byte operands. Syntaxes are shown in Table 4-9.
Table 4-9. Indirect Addressing Syntax
Syntax Operation Premodify accumulator pointer if next A is included. Add Rx with R5. Premodify accumulator pointer if next A is included. Use address pointed by Rx, Rx content unchanged Premodify accumulator pointer if next A is included. Use address pointed by Rx, post increment Rx after use Premodify accumulator pointer if next A is included. Use address pointed by Rx, post decrement Rx after use Address Memory Operand
name [dest,] [src,] ,*Rx++R5 [, next A] name *Rx++R5 [, src] [, next A] name [dest,] [src,] ,*Rx [, next A] name *Rx [, src] [, next A] name [dest,] [src,] ,*Rx++ [, next A] name *Rx++ [, src] [, next A] name [dest,] [src,] ,*Rx- - [, next A] name *Rx- - [, src] [, next A]
Rx (x = 0 - 7)
++ - - ++R5
Note that the Rx registers treats data memory as a series of bytes. Therefore, when a word is loaded, Rx++ increments by 2 (Rx- - decrements by 2). When loading a word address into Rx, the address must be converted into a byte address (by multiplying by 2). For example, if we want Rx to point to the word address, 0x100, Rx should be loaded with 0x100*2=0x200. Example 4.3.10 MOV A1~, *R1++R5, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement AP1. After preincrement A1 is AC22 and A1~ is AC6. The contents of the data memory location stored in R1 are loaded into accumulator AC6. R1 is then incremented by R5. Final result, AP1=22, AC6 = 0xacb, R1 = R1 + R5 = 0x0202. Note that the addressing of the Rx registers is byte addressing. Example 4.3.11 ADD A3~, A3, R6++R5, --A Refer to the initial processor state in Table 4-8 before execution of this instruction. Predecrement AP3. After predecrement, A3 is AC28 and A3~ is AC12. The contents of the data memory location stored in R6 are added to AC28. The result is stored in accumulator AC12. R6 is then incremented by R5. Final result, AP3=28, AC12 = AC28 + *R6 = 0x11A2 + 0x12AC = 0x244E, R6 = R6+R5 = 0x3E6. Note that the Rx registers use byte addresses.
Assembly Language Instructions
4-15
Instruction Syntax and Addressing Modes
Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5. Final result, AP0=3, R5 = 0x0004, *0x0002 = 0xFEED. Example 4.3.13 MOV A2, *R0 Refer to the initial processor state in Table 4-8 before execution of this instruction. The contents of the data memory address in R0 are loaded into A2 (AC11). Final result, AC11 = 0x0400. Note the addressing is byte addressing. Thus, *R0 = 0x0454 indicates the word memory location 0x454/2 = 0x022A. Example 4.3.14 IN *R4++, 0x00 The contents of the I/O port location 0x00 (port PPA) are stored in the location pointed to by R4. R4 is incremented by 2 after this operation. Example 4.3.15 MOVB *R7++, A3 Refer to the initial processor state in Table 4-8 before execution of this instruction. Store the lower 8 bits of A3 (AC29) in the data memory byte address pointed to by R7. R7 is then incremented by one. Notice that to find the word address, divide the address in R7 by 2. Final result, R7=0x0101, *0x0100 = 0xAB (byte address) or *0x80 = 0xAB00 (word address). Example 4.3.16 OUT 0x08, *R1- - Refer to the initial processor state in Table 4-8 before execution of this instruction. The contents of the data memory byte location stored in R1 are placed on port 0x08 (port PPB). R1 is then decremented by 2. Final result, R1 = 0x01FE, *0x08 = 0xCB. Port PPB is 8-bits wide, so the upper 8-bits of *R1 (0x0A) are ignored.
4.3.6
Relative Addressing
There are three types of relative addressing on the MSP50P614/MSP50C614: short relative, long relative, and relative to the index register, R5. These addressing modes are described below.
4.3.6.1
Relative to Index Register R5
This relative addressing mode uses one of the 8 address registers (R0-R7) as a base value. The index register, R5, is added to the base address value in Rx. The base address register is not modified. Thus, the effective address is Rx + R5. Syntax:
name [dest,] [src,] *Rx+R5 [, next A] name *Rx+R5 [, src] [, next A]
4-16
Instruction Syntax and Addressing Modes
Rx (x = 0 - 7) Index Register (R5)
Address
+
Operand
Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4-8 before execution of this instruction. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDed with AC2. The result is stored in AC2. The values in R3 and R5 are unchanged. Final result, AC2 = AC2 AND *0x01F2 = 0x13F0 AND 0x12AC = 0x12A0. Example 4.3.18 MOV *R2+R5, A2~, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement AP2. After preincrement, A2 is AC12 and A2~ is AC28. Store AC28 in the data memory byte location R2+R5. The values in R2 and R5 are unchanged. Final result, *0x02A1 = 0x11A2. Example 4.3.19 ADD A0~, A0, *R4+R5, --A Refer to the initial processor state in Table 4-8 before execution of this instruction. Predecrement AP0. After predecrement, A0 is AC1 and A0~ is AC17. Add AC1 to the contents of byte location R4+R5 and put the result in AC17. The values in R4 and R5 are unchanged. Final result, AC17 = AC1 + *(R4+R5) = 0x0007 + *0x0002 = 0x0007 + 0x499A = 0x49A1.
4.3.6.2
Short Relative
Short relative (also called PAGE Relative) addressing selects the Page register (R6) as a base value and adds a 7-bit positive offset from the operand. The page register is not modified. Syntax:
name [dest,] [src,] *R6+offset7 [, next A] name *R6+offset7 [, src] [, next A]
R6 PAGE register 7-Bit positive offset Address
+
Operand
Assembly Language Instructions
4-17
Instruction Syntax and Addressing Modes
Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4-8 before execution of this instruction. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD A0~, A0, *R6+0x10, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. Add AC3 to the contents of byte address R6+0x10 and store the result in AC19. The value in R6 is unchanged. Final result, AC19 = AC3 + *(R6+0x10) = 0xFEED + *0x01FA = 0xFEED + 0x0112 = 0xFFFF.
4.3.6.3
Long Relative
Long relative addressing selects one of the 8 address registers (Rx) as a base value and adds the value of the second word operand. The base address register is not modified. Syntax:
name [dest,] [src,] *Rx+offset16 [, next A] name *Rx+offset16 [, src] [, next A]
Rx (x = 0 - 7) Memory Operand
Address
+
Operand
Example 4.3.22 MOV A0~, *R1+0x0254, ++A Refer to the initial processor state in Table 4-8 before execution of this instruction. Preincrement A0. After preincrement, A0 is AC3 and A0~ is AC19. Load the contents of the data memory byte location R1+0x0254 into AC19. R1 remains unchanged. Final result, AP0=3, AC19=*(R1+0x0254) = *0x022A = 0x0400. Example 4.3.23 MOV *R7+0x0442, MR Refer to the initial processor state in Table 4-8 before execution of this instruction. Store the value in MR to data memory byte location, R7+0x0442. R7 remains unchanged. Final result, *0x02A1 = 0x1A15.
4-18
Instruction Syntax and Addressing Modes
4.3.7
Flag Addressing
This addressing mode addresses only the 17th bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various logical operations can be performed without affecting the remaining 16 bits of the selected word. Two addressing modes are provided. The first addressing mode, global flag addressing, has bit 0 set to zero and a six bit field (b1-b6) that defines the flag word address. The second mode, relative flag addressing, has bit 0 set to one and a six bit field (b1-b6) that defines the flag address relative to R6 (see Figure 4-2). In other words, the, i.e., effective address = (contents of R6) + (6 bit offset). In flag addressing, R6 contains the address that points to the 17th bit. This should not be confused with byte addresses and word addresses.
Figure 4-2. Relative Flag Addressing
R6 PAGE register 6-Bit positive offset Address
+
Operand
Syntax: Global Flag: Relative Flag:
name {dest}, {src} name TFn, dma6 name dma6, TFn name TFn, *R6+offset6 name *R6+offset6, TFn
Example 4.3.24 MOV *0x02, TF2 Take the test flag 2 bit (TF2 in the status register) and place it into the 17th bit of the data memory location 0x02. Example 4.3.25 AND TF1, *0x20 AND the test flag 1 bit (TF1 in status register) with the 17th bit of the data memory location 0x20 and store the result in the TF1 bit of the STAT. Example 4.3.26 OR TF2, *R6+0x02 OR the test flag 2 bit (TF2 in status register) with the 17th bit of the data memory location *(R6+0x02) and store the result in the TF2 bit in of the status register. So, if R6=0x0100, then relative flag address is 0x0102. Example 4.3.27 XOR TF1, *R6+0x20 XOR the test flag 1 bit (TF1 in status register) with the 17th bit of the data memory location *(R6+0x20) and store the result in TF1 bit of the status register. So, if R6=0x0100, then relative flag address is 0x0120.
Assembly Language Instructions
4-19
Instruction Syntax and Addressing Modes
4.3.8
Tag/Flag Bits
The words TAG and flag may be used interchangeably in this manual. The TAG bit is the 17th bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614. When an instruction of the format, MOV accumulator, RAM is performed, the STAT register is affected by various properties of this transfer. The TAG bit of the RAM location is copied into the TAG bit of the STAT register during such transfers. The TAG bit can be modified using several instructions: STAG, RTAG, SFLAG, RFLAG. There are subtle differences between these instructions that the user must understand before using them. The first difference between the xTAG and xFLAG instructions is the addressing.
STAG *0x0000 RTAG *0x0002 STAG *0x0002 * 2 ;sets the TAG bit of RAM word zero ;clears the TAG bit of RAM word one ;sets the TAG bit of RAM word two
STAG and RTAG use RAM byte addresses to specify which TAG to set or clear. This immediately causes confusion since there are 1280 bytes and only 640 TAGs. What happens when an odd byte is used to set a tag with STAG?
STAG *0x0001 STAG *0x0003 STAG *0x0005 * 2 ;sets the TAG bit of RAM word zero ;sets the TAG bit of RAM word one ;sets the TAG bit of RAM word five
All word boundaries in RAM start at even numbers, RAMeven. If an odd byte, RAMeven + 1 is used to set a TAG, then the TAG for RAMeven is set. Thus,
STAG *0x0000 STAG *0x0001
are functionally equivalent. As a sharp contrast, the SFLAG and RFLAG instructions use RAM word addresses to specify which TAG to set or clear.
SFLAG *0x0000 SFLAG *0x0001 ;sets the TAG bit of RAM word zero ;sets the TAG bit of RAM word one
Another difference between the xTAG and xFLAG instructions is the addressing modes. STAG and RTAG can use {adrs} addressing modes. This includes, direct, short relative, relative to R5, long relative, and indirect addressing modes. This affects the number of clock cycles it takes to execute xTAG instructions.
4-20
Instruction Syntax and Addressing Modes
However, xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6-bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code,
ram0 ram1 ram2 STAG MOV RTAG equ0x0000 *2 ;RAM word zero equ0x0001 *2 ;RAM word one equ0x0002 *2 ;RAM word two *ram1 A0,*ram1 *ram1 ;This sets the TAG bit of ram2! ;TAG bit is not set in STAT register! ;TF1 bit in STAT is set!? ;TAG bit is set in STAT register
SFLAG *ram1 MOV MOV A0,*ram1 TF1,*ram1
Explanation: The first three instructions perform as you would expect. The TAG bit is set at the RAM variable, ram1. The TAG bit is set in the STAT register when the MOV instruction executes. Finally, ram1's TAG bit is cleared. The next two instructions are problematic. When SFLAG sets the tag bit, it will set the tag bit for the second word location, ram2. This does not set the TAG bit for ram1. What is worse is that the value in ram1 must be less than 64 (dma6) since this is global addressing for SFLAG. To access TAG bits for higher RAM, the R6 (PAGE) register is needed. The last instruction is also confusing. Why is TF1 set in the STAT even though ram1's TAG bit is not set? The answer is that this MOV instruction considers the {src} argument to be a word value instead of the usual byte value. Thus, this MOV instruction operates on ram2 rather than on ram1.
Assembly Language Instructions
4-21
Instruction Classification
4.4 Instruction Classification
The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory, hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within the class, and the abbreviated field descriptions. Some of the following symbols will be used repeatedly throughout this chapter as shown in Table 4-10 (for additional information see section 4.13).
Table 4-10. Symbols and Explanation
Symbol ! {adrs}n {cc} {flagadrs} ~A ~A~ A~ adrs An Explanation Invert the bit of the source. Used with flag addressing only. The contents of the effective data memory address referred to by the addressing mode syntax. If n is specified, n bits are involved. If unspecified, data is 16 bits. See Table 4-4. Condition code mnemonic used with conditional branch/calls and test flag/bit instructions. Curly braces indicate this field is not optional. Flag addressing syntax as shown in Table 4-7. Select offset accumulator as the destination accumulator if this bit is 1. Can be either ~A or A~ based on the opcode (or instruction). Select offset accumulator as source if this bit is 1. Addressing mode bits am, Rx, pm. See Table 4-4. Accumulator pointed to by APn. Accumulators cannot be referenced directly. For example, A22 is not valid since accumulators are only addressible though the accumulator pointers AP0-AP3. Therefore, to access accumulators, use A0, A1, A2 and A3. This should not be confused with APn where AP is an accumulator pointer, not an accumulator. Indicates the offset of the accumulator pointed to by accumulator pointer An. This is also an accumulator, not an accumulator pointer. Accumulator pointer APn where n = 0, 1, 2 or 3. The difference between An and APn is that An is the accumulator pointed to by APn. In both cases, n ranges from 0 to 3. Condition code bits used with conditional branch/calls and test flag/bit instructions. Clock cycles to execute the instruction n bit data memory address. For example, dma8 means 8-bit location data memory address. If n is not specified, defaults to dma16. Flag addressing bits as shown in Table 4-7. Test flag bit. Global/relative flag bit for flag addressing. n bit immediate value Constant field bits.
An~ Apn cc clk dma[n] flagadrs flg g/r imm[n] k0...kn
4-22
Instruction Classification
Table 4-11. Symbols and Explanation (Continued)
Symbol next A [next A] Not nR ns offset[n] pma[n] port[n] R Rx s x Explanation Accumulator control bits as described in Table 4-6. The preincrement (++A) or predecrement (- -A) operation on accumulator pointers An or An~. NOT condition on conditional jumps, conditional calls or test flag instructions. Value in the repeat counter loaded by repeat instruction. Value in string register STR. n bit offset from a reference register. n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16. n bit I/O port address. Rx registers are treated as general purpose registers. These bits are not related to any addressing modes. Indirect register bits as described in Table 4-3. Represents string mode if 1, otherwise normal mode. Don't care
Instructions on the MSP50P614/MSP50C614 are classified based on the operations the instruction group performs (see Table 4-11). Each instruction group is referred to as a class. There are 9 instruction classes. Classes are subdivided into subclasses. Classes and opcode definitions are shown in Table 4-11.
Table 4-11. Instruction Classification
Class Sub- Description Class 1 A B 2 A B 3 Accumulator and memory reference instructions Accumulator and memory references with or without string operations and accumulator preincrementing Accumulator and memory references with or without string operations Accumulator constant reference Short constant to accumulator Long constant to accumulator Accumulator reference instructions with no addressing modes
Assembly Language Instructions
4-23
Instruction Classification
Table 4-11. Instruction Classification (Continued)
Class 4 A B C D 5 6 A B 7 A B C 8 A B 9 A B C D SubClass Description Register and memory reference Memory references that use Rx; all addressing modes available Memory references with short constant fields operating on Rx Memory references with long constant fields operating on Rx and others Memory references with long constant fields operating on Rx and others General mMemory reference instructions I/O port and memory reference instructions Port/memory reference Port/accumulator reference Program control instructions Macro call instructions Conditional and unconditional jump instructions Conditional and unconditional call instructions Logical bit instructions Logical flag instructions Test status instructions Miscellaneous instructions Filter instructions Miscellaneous short constant instructions Accumulator address instructions Other instructions
4-24
Instruction Classification
Table 4-12. Classes and Opcode Definition
Bit Class 1a Class 1b Class 2a Class 2b Class 3 Class 4a Class 4b Class 4c Class 4d Class 5 Class 6a Class 6b Class 7a Class 7b JMP *An Class 7c CALL *An Class 8a Class 8b Class 9a Class 9b Class 9c Class 9d ENDLOOP n 16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 1 1 C6a 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 flg flg 0 1 0 1 1 s 1 Not x Not x n Not 0 0 1 1 1 1 1 An C9a An 0 0 1 0 1 0 C9c C9d 0 1 0 1 1 1 x 0 0 1 An C8a cc C9a 0 k imm5 0 0 1 0 0 1 0 n 1 An 0 1 1 0 0 0 14 C1a 13 12 ~A~ C1b C2a next A next A C4a C4b 1 1 k4 1 1 C5 port4 An 1 cc x cc x x x x x x x x R k3 0 0 k2 0 0 k7 0 1 11 10 9 An An An An An am k6 C4c C4d am am port6 vector8 rx x x x x x x x x x pm x x x g/r C8b 1 C8b 1 k5 C2b C3 Rx R R R Rx Rx k1 x x pm pm C6b ~A~ 8 7 6 am am 5 4 3 Rx Rx imm8 0 0 1 0 A~ A~ pm k0 x x ~A ~A 2 1 pm pm 0 next A s
flagadrs Rx Rx
NOP 1 1 1 1 1 1 1 1 Meaning of this bit depends on what class 3 instruction is used.
4.4.1
Class 1 Instructions: Memory and Accumulator Reference
This class of instructions controls execution between data memory and the accumulator block. In addition to the explicit opcode field that specifies an arithmetic operation, an eight bit data memory addressing mode reference field (am, Rx, pm i.e., adrs field) controls the addressing of one input operand, and a 4 bit field (An and next A in class 1a) or 2 bit field (An in class 1b) selects an accumulator location as the other input operand. The results are written to the addressed accumulator location (or to the offset accumulator in class 1a if ~A bit = 1). In addition, each instruction can be treated as a single word length operation or as a string, depending on the string control encoded in the op code (s = 1 in class 1b and An = 11 binary in class 1a).
Assembly Language Instructions
4-25
Instruction Classification
Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory. Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A bit. The ADD or SUB instructions add or subtract memory from an accumulator register and save the results in the accumulator register (~A=0) or its offset (~A=1). Two of the four codes provided by the next A field will cause a pre-increment or a predecrement of the accumulator register pointer (AP) prior to execution. This preincrement is a permanent change to the referenced AP and further expands the use of the accumulator block as an efficient workspace. Preincrements and predecrements are not available in string mode One of the four codes of the An field (An = 11 binary) will cause the instruction to be treated as a multicycle string instruction. This will not result in any permanent modification to the referenced AP. Since there is no reference to offset accumulators in Class 1b instructions, the execution operates on memory and accumulators. All other modes of control (string, preincrement/predecrement AP, data memory addressing modes, etc.) are provided for logical, byte, multiply-accumulate, and barrel shift instructions.
Table 4-13. Class 1 Instruction Encoding
Bit Class 1a Class 1b 16 0 0 15 0 1 14 13 12 ~A~ C1b 11 10 9 An An 8 7 6 5 4 3 2 1 0
C1a
next A s
adrs adrs
Table 4-14. Class 1a Instruction Description
C1a 0 0 Mnemonic ADD An[~], An, {adrs} [, next A] ADDS An[~], An, {adrs} Description Add contents of data memory location referred by {adrs} to accumulator An and store the results in the same accumulator An (if ~A=0) or offset accumulator An~ (~A=1). ALU status is modified. Subtract contents of data memory location referred by {adrs} from accumulator An and store the results in the same accumulator An (if ~A=0) or offset accumulator An~ (~A=1). ALU status is modified. Load accumulator An (~A=0) or offset accumulator An~ (~A=1) from data memory location referred to {adrs}. ALU status is modified. Store accumulator (A~=0) or offset accumulator (A~=1) to data memory location referred to by addressing mode {adrs}. Transfer status is modified.
0
1
SUB An[~], An, {adrs} [, next A] SUBS An[~], An, {adrs}
1
0
MOV An[~], {adrs} [, next A] MOVS An[~], {adrs} MOV {adrs}, An[~] [, next A] MOVS {adrs}, An[~]
1
1
4-26
Instruction Classification
Table 4-15. Class 1b Instruction Description
C1b 0 0 0 0 Mnemonic OR An, {adrs} ORS An, {adrs} Description Logical OR the contents of the data memory location in {adrs} and the selected accumulator. Result(s) stored in accumulator(s). ALU status is modified Logical AND the contents of the data memory location in {adrs} and the accumulator. Result(s) stored in accumulator(s). ALU status is modified Exclusive OR the contents of the data memory location in {adrs} and the accumulator. Result(s) stored in accumulator(s). ALU status is modified Load the contents of the data memory location in {adrs}and to the lower 8 bits of the accumulator. Zero fill the upper byte in the accumulator ALU status is modified. Store the lower 8 bits of accumulator to the data memory location in {adrs}. The data byte is automatically routed to either the lower byte or upper byte in the 16 bit memory word based on the LSB of the address. Transfer status is modified. N/A Store the arithmetic status of the contents of {adrs} subtracted from accumulator into the ALU status bits. The accumulator is not modified. Look up the value stored in program memory addressed by the accumulator and store in the data memory location in {adrs}. Transfer status is modified . Multiply the MR register by the contents of {adrs} and transfer the lower 16 bits of the result to the accumulator. Latch the upper 16 bits into the PH register. ALU status is modified. Load the MR register in signed mode from the data memory location in {adrs}. In parallel, subtract the PH register from the accumulator. The string bit will string with the previous ALU status (CF, ZF) but it will not load the string counter (executes once). ALU status is modified. Load the MR register in signed mode from the data memory location in {adrs}. In parallel, add the PH register to the accumulator. The string bit will string with the previous ALU status (CF, ZF) but it will not load the string counter (executes once). ALU status is modified.
0
0
0
1
AND An, {adrs} ANDS An, {adrs}
0
0
1
0
XOR An, {adrs} XORS An, {adrs}
0
0
1
1
MOVB An, {adrs}8 MOVBS An, {adrs}8 MOVB {adrs}8, An MOVBS {adrs}8, An
0
1
0
0
0 0
1 1
0 1
1 0
Reserved CMP An, {adrs} CMPS An, {adrs}
0
1
1
1
MOV {adrs} , *An MOVS {adrs} , *An
1
0
0
0
MULTPL An, {adrs} MULTPLS An, {adrs}
1
0
0
1
MOVSPH An, MR, {adrs} MOVSPHS An, MR, {adrs}
1
0
1
0
MOVAPH An, MR, {adrs} MOVAPHS An, MR, {adrs}
Assembly Language Instructions
4-27
Instruction Classification
Table 4-15. Class 1b Instruction Description (Continued)
C1b 1 0 1 1 Mnemonic MULAPL An, {adrs} MULAPLS An, {adrs} SHLTPL An, {adrs} SHLTPLS An, {adrs} Description Multiply the MR register by the addressing mode {adrs} and add the lower 16 bits of the product to the accumulator. Latch the upper 16 bits into the PH register. ALU status is modified. Shift left n bits (SV reg). The 16 bit contents of the data memory location in {adrs} are shifted and placed in accumulator (string) An. Zeros fill from the right and either zeros or ones fill the left depending on the sign (assuming XSGM mode is set). Transfer the lower 16 bits to the accumulator and latch the upper 16 bits in PH. ALU status is modified. Shift left n bits (SV reg ). The contents of the data memory location in {adrs} are placed in a 32 bit result. Zeros fill from the right and either zeros or sign extended ones fill the left (if XSGM mode is set). Subtract the lower 16 bits from the accumulator and latch the upper 16 bits in PH. ALU status is modified. Shift left n bits (SV reg). The contents of the data memory location in {adrs} are placed into a 32 bit result. Zeros fill the right and either zeros or sign extended ones fill the left (in XSGM mode). Add the lower 16 bits to the accumulator and latch the upper 16 bits in PH. ALU status is modified. Multiply the MR register by the contents of {adrs} and subtract the lower 16 bits of the product from the accumulator. Latch the upper 16 bits into the PH register. ALU status is modified.
1
1
0
0
1
1
0
1
SHLSPL An, {adrs} SHLSPLS An, {adrs}
1
1
1
0
SHLAPL An, {adrs} SHLAPLS An, {adrs}
1
1
1
1
MULSPL An, {adrs} MULSPLS An, {adrs}
4.4.2
Class 2 Instructions: Accumulator and Constant Reference
These instructions provide the capability to reference short (8 bits) or long (16 bits or (nS+2) * 16 bit string) constants stored in program memory and to execute arithmetic and logical operations between accumulator contents and these constants. Since the MSP50P614/MSP50C614 is a Harvard type processor, these instructions are necessary and distinct from the general class of memory reference instructions. Subclass 2a, listed belows include references between accumulator and short 8 bit constants. This class has the advantage of requiring only 1 instruction word to code and 1 instruction cycle to execute Thus is particularly useful for control variables such as loop counts, indexes, etc. The short constants also provide full capability for byte operations in a single instruction word. Subclass 2b references accumulator and long constants from program memory (16 bits for non string constants and (nS+2) * 16 bits for string constants). Class 2b instructions take 2 instruction words to code. The execution of these instructions is 2 instruction cycles when the long constant is a single word. The execution is nS+2 execution cycles for nS word string
4-28
Instruction Classification
constants. Long constants (16 bits) and long string constants differ in that references are made to constants in the second word of the two-word instruction word. References made to a single 16 bit integer constant are immediate. That is, the actual constant value follows the first word opcode in memory. For string constants, the second word reference to the constants is immediate-indirect which indicates that the second word is the address of the least significant word of the string constant. This definition allows all long string constants to be located in a table and permits the reference in the machine language listing to be consistent with those of shorter constants.
Table 4-16. Class 2 Instruction Encoding
Bit Class 2a Class 2b 16 1 1 15 0 1 14 1 1 13 0 0 0 12 11 C2a 10 9 An An C2b 8 7 6 5 4 3 2 1 0
imm8
0 0 1 A~ ~A
next A
Table 4-17. Class 2a Instruction Description
C2a 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Mnemonic ADDB An, imm8 MOVB An, imm8 SUBB An, imm8 CMPB An, imm8 ORB An, imm8 ANDB An, imm8 XORB An, imm8 MOVB MR, imm8 Description Add an 8 bit positive constant to the accumulator and store the result in the accumulator. ALU status is modified. Load an 8 bit positive constant into accumulator. ALU status is modified. Subtract 8 bit positive constant from accumulator and store result accumulator. ALU status modified. Modify ALU status with the result of 8 bit positive value subtracted from accumulator. Original accumulator value not modified. Logical OR 8 bit positive constant with accumulator and store result to accumulator. ALU status modified. Logical AND 8 bit positive constant with accumulator. Store result to accumulator. ALU status modified. Logical XOR 8 bit positive constant with accumulator. Store result to accumulator. ALU status modified. Load 8 bit constant to Multiplier register (MR). Does not change UM mode in status register but will zero fill the top 8 bits in MR register. No change in status.
Assembly Language Instructions
4-29
Instruction Classification
Table 4-18. Class 2b Instruction Description
C2b 0 0 0 Mnemonic ADD An[~], An[~], imm16 [, next A] ADDS An[~], An[~], pma16 MOV An[~], imm16 [, next A] MOVS An[~], pma16 SUB An[~], An[~], imm16 [, next A] SUBS An[~], An[~], pma16 CMP An[~], imm16 [, next A] CMPS An[~], pma16 OR An[~], An[~], imm16 [, next A] ORS An[~], An[~], pma16 AND An[~], An[~], imm16 [, next A] ANDS An[~], An[~], pma16 XOR An[~], An[~], imm16 [, next A] XORS An[~], An[~], pma16 MOV MR, imm16 [, next A] Description Add long constant to accumulator (or offset accumulator if A~=1) and store result to accumulator (~A=0) or offset accumulator (~A=1). ALU status modified. Load long constant to accumulator (~A=0 or 1). ALU status is modified. Subtract a long constant from the accumulator (A~=0 or 1). Store the result in accumulator (~A=0) or offset accumulator (~A=1). ALU status is modified. Modify ALU status by subtracting a long constant from accumulator (A~=0) or from offset accumulator (A~=1). Neither accumulator or offset accumulator is modified Logical OR a long constant with accumulator (A~=0 or 1). Store the result in accumulator(~A=0) or offset accumulator (~A=1). ALU status is modified. Logical AND a long constant with accumulator (A~=0 or 1).Store the result to accumulator(~A=0 or 1) . ALU status is modified. Logical exclusive OR a long constant with accumulator (A~=0 or 1) Store the result to accumulator (~A=0 or 1). ALU status is modified. Load a long constant to MR in signed mode. No change in status.
0 0
0 1
1 0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
4.4.3
Class 3 Instruction: Accumulator Reference
These instructions reference the accumulator and, in some instances, specific registers for transfers. Some instructions use a single accumulator operand and others use both the accumulator and the offset accumulator to perform operations between two accumulator values. The A~ bit in the instruction word reverses the sense of the addressed accumulator and the addressed offset accumulator. In general, if A~=1, the instruction uses the offset accumulator as the input operand on single accumulator operand instructions. It interchanges the arithmetic order (subtract, compare, multiply-accumulate, etc.) of the two operands when both are used. Exceptions to the rule are the instructions NEGAC[S], NOTAC[S], MULSPL[S], MULAPL[S], MULTPL[S], SHLSPL[S], SHLTPL[S] and SHLAPL[S], which use the reverse A~ control (A~=1 for accumulator, A~=0 for offset accumulator). The ~A bit in the instruction word controls the destination of the result to be the accumulator (~A=0) or the offset accumulator (~A=1). In addition to basic accumulator arithmetic functions this class also includes an accumulator lookup instruction and several register transfer instructions
4-30
Instruction Classification
between the accumulator and the MR, SV, or PH register. As with all accumulator referenced instructions, string operations are possible as well as premodification of one of 4 indirectly referenced accumulator pointer registers (AP).
Table 4-19. Class 3 Instruction Encoding
Bit Class 3 16 1 15 1 14 1 13 0 12 0 11 10 9 An 8 7 6 5 C3 4 3 2 0 1 A~ 0 ~A
next A
Table 4-20. Class 3 Instruction Description
C3 00 0 0 Mnemonic 0 NEGAC An[~], An[~] [, next A] NEGACS An[~], An[~] 1 NOTAC An[~], An[~] [, next A] NOTACS An[~], An[~] 0 MOV An[~], *An[~] [, next A] MOVS An[~], *An[~] Description Store the 2's complement of the source accumulator (A~=0 or 1) to the destination accumulator (~A=0 or 1). ALU status is modified. Place the 1's complement of the source accumulator (A~=0 or 1) into the destination accumulator (~A=0 or 1). ALU status is modified. Look up a value in program memory addressed by accumulator (A~=0 or 1). Place the lookup value into the accumulator (~A=0 or 1). The lookup address is post-incremented in the DP register. ALU status is modified based on the lookup value. Zero accumulator (~A=0 or 1). ALU status is modified. Subtract offset accumulator from accumulator (A~=0) or subtract accumulator from offset accumulator (A~=1). Store the result in accumulator (~A=0 or 1). ALU status is modified. Add accumulator to offset accumulator and store result to accumulator (~A=0 or 1). ALU status is modified. Shift accumulator left 1 bit and store the result into accumulator(~A=0) or offset accumulator (~A=1). The LSB is set to zero and the MSB is stored in a carryout status bit. ALU status is modified. Copy accumulator (A~=0 or 1) to accumulator (~A=0 or 1). ALU status is modified.
00
0
0
00
0
1
00 00
0 1
1 0
1 ZAC An[~] [, next A] ZACS An[~] 0 SUB An[~], An, An~ [, next A] SUB An[~], An~, An [, next A] SUBS An[~], An, An~ SUBS An[~], An~, An 1 ADD An[~], An~, An [, next A] ADDS An[~], An~, An 0 SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~]
00 00
1 1
0 1
00
1
1
1 MOV An, An~ [, next A] MOVS An, An~
These instructions have a special 1 word string operations when string mode is selected. The instructions ignore the string count, executing only once but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and this instruction execution was a part of a larger string operation.
Assembly Language Instructions
4-31
Instruction Classification
Table 4-20. Class 3 Instruction Description (Continued)
C3 01 0 0 Mnemonic 0 XOR An[~], An~, An [, next A] XORS An[~], An~, An 1 OR An[~], An~, An [, next A] ORS An[~], An~, An 0 AND An[~], An~, An [, next A] ANDS An[~], An~, An 1 SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] Description Logically exclusive OR accumulator with offset accumulator and store the results in accumulator (~A=0 or 1). ALU status is modified. Logically OR accumulator with offset accumulator and store results into accumulator (~A=0 or 1). ALU status is modified. Logically AND accumulator with offset accumulator and store result(s) into accumulator (~A=0 or 1). ALU status is modified. Shift accumulator or offset accumulator right 1 bit and store result in accumulator (~A=0 or 1). MSB will be set to zero or be set equal to the sign bit (XSGM dependent). ALU status is modified. Subtract product high register from accumulator (A~=0) or from offset accumulator (A~=1) and store the result into accumulator (~A=0) or into the offset accumulator (~A=1). ALU status is modified. String bit causes subtract with carry status (CF). Add product high register to accumulator or to offset accumulator and store the result into accumulator (~A=0 or 1). ALU status is modified. The string bit causes an add with carry status (CF). Transfer product high register to accumulator (~A=0) or offset accumulator (~A=1). ALU status is modified. String bit will cause stringing with current ZF status bit. Copy SF bit in status register to all 16 bits of the accumulator or offset accumulator. On strings, the accumulator address is preincremented causing the sign of the addressed accumulator to be extended into the next accumulator address. Subtract offset accumulator from accumulator(A~=0) or subtract accumulator from offset accumulator (A~=1) and store the status of the result into ALU status. Accumulator or offset accumulator original value remains unchanged. N/A N/A N/A
01
0
0
01
0
1
01
0
1
01
1
0
0 SUB An[~], An[~], PH [, next A] SUBS An[~], An[~], PH
01
1
0
1 ADD An[~], An[~], PH [, next A] ADDS An[~], An[~], PH 0 MOV An[~], PH [, next A] MOVS An[~], PH 1 EXTSGN An[~] [, next A] EXTSGNS An[~]
01
1
1
01
1
1
10
0
0
0 CMP An~, An [, next A] CMP An, An~ [, next A] CMPS An~, An CMPS An, An~ 1 reserved 0 reserved 1 reserved
10 10 10
0 0 0
0 1 1
These instructions have a special 1 word string operations when string mode is selected. The instructions ignore the string count, executing only once, but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and current instruction were part of a larger string operation.
4-32
Instruction Classification
Table 4-20. Class 3 Instruction Description (Continued)
C3 10 10 10 1 1 1 0 0 1 Mnemonic 0 MOV SV, An[~] [, next A] MOVS SV, An[~] 1 MOV PH, An[~] [, next A] MOVS PH, An[~] 0 MOV MR, An[~] [, next A] MOVS MR, An[~] 1 MOVU MR, An[~] [, next A] Description Transfer accumulator(A~=0) or offset accumulator (A~=1) to SV register. Transfer status is modified. Transfer accumulator (A~=0) or offset accumulator (A~=1) to PH register. Transfer status is modified. Transfer accumulator (A~=0) or offset accumulator (A~=1) to MR register in the signed multiplier mode (UM bit in status register set to 0). Transfer status is modified. Transfer accumulator (A~=0 or 1) to MR register in the unsigned multiplier mode(UM bit set to 1). Transfer status is modified. Multiply the MR register by accumulator (A~=1) or offset accumulator (A~=0) , subtract lower 16 bits of the product from the offset accumulator (A~=1) or accumulator (A~=0). Store in the accumulator (~A=0) or offset accumulator (~A=1). Latch the upper 16 bits in PH. ALU status is modified. Multiply MR register by accumulator (A~=1) or offset accumulator (A~=0) , add lower 16 bits of product to offset accumulator (A~=1) or accumulator (A~=0) and store to accumulator (~A=0) or offset accumulator (~A=1). Latch upper 16 bits in PH. ALU status is modified. Barrel shift the accumulator (A~=1 or 1) value n bits left (SV reg). Store the upper 16 bits of the 32 bit shift result to PH (msbs extended by XM mode bit). Transfer the lower 16 bits to accumulator (~A=0) or offset(~A=1). ALU status is modified. Multiply MR register by accumulator(A~=1) or offset (A~=0), transfer lower 16 bits of product to accumulator (~A=0) or offset accumulator(~A=1). Latch upper 16 bits of Product to PH register. ALU status is modified. Barrel shift the accumulator(A~=1) or offset accumulator (A~=0) value n bits left (SV reg). Store the upper 16 bits to PH. Subtract the lower 16 bits of value from offset (A~=1) or accumulator (A~=0) and store in accumulator (~A=0) or offset accumulator (~A=1). ALU status is modified. Barrel shift the accumulator(A~=1) or offset accumulator (A~=0) value n bits left (SV reg). Store the upper 16 bits to PH. Add the lower 16 bits of value to offset accumulator (A~=1) or accumulator (A~=0) and store in accumulator (~A=0) or offset accumulator(~A=1). ALU status is modified.
10
1
1
11
0
0
0 MULSPL An[~], An[~] [, next A] MULSPLS An[~], An[~]
11
0
0
1 MULAPL An[~], An[~] [, next A] MULAPLS An[~], An[~]
11
0
1
0 SHLTPL An[~], An[~][, next A] SHLTPLS An[~], An[~]
11
0
1
1 MULTPL An[~], An[~] [, next A] MULTPLS An[~], An[~]
11
1
0
0 SHLSPL An[~], An[~] [, next A] SHLSPLS An[~], An[~]
11
1
0
1 SHLAPL An[~], An[~] [, next A] SHLAPLS An[~], An[~]
Assembly Language Instructions
4-33
Instruction Classification
Table 4-20. Class 3 Instruction Description (Continued)
C3 11 1 1 Mnemonic 0 MUL An[~] [, next A] MULS An[~] 1 SHL An[~] [, next A] SHLS An[~] Description Multiply MR register by accumulator (A~=1) or offset accumulator (A~=0) and latch the rounded upper 16 bits of the resulting product into the PH register. Barrel shift the accumulator (A~=1) or offset accumulator (A~=0) value n bits left (n stored in SV register). Store the upper 16 bits of the 32 bit shift result to PH.
11
1
1
4.4.4
Class 4 Instructions: Address Register and Memory Reference
Class 4 instructions operate on the indirect register, Rx, that exists in the address unit (ADU). Even though the last three registers (R5-R7) are special (INDEX, PAGE, and STACK), class 4 instructions uniformly apply to all registers. Subclass 4a provides transfers to and from memory. In indirect mode, any one auxiliary register can serve as the address for loading and storing the contents of another. Subclass 4b instructions provide some basic arithmetic operations between referenced auxiliary register and short 8 bit constants from program memory. These instructions are included to provide efficient single cycle instructions for loop control and for software addressing routines. Subclass 4c provide basic arithmetic operations between the referenced auxiliary register and 16 bit constants from program memory. These instruction require 2 instruction cycles to execute. Also a compare to R5 (INDEX) is provided for efficient loop control where the final loop counter value is not chosen to be zero.
Table 4-21. Class 4a Instruction Encoding
Bit Class 4a Class 4b Class 4c Class 4d 16 1 1 1 1 15 1 0 1 1 14 1 1 1 1 13 1 1 1 1 1 1 12 0 11 C4a C4b 1 1 10 9 8 7 6 5 4 3 2 1 0
R k4
1 1
adrs k2
0 0
k3
0 0
k7
0 1
k6
C4c C4d
k5
R R R
k1
x x
k0
x x
4-34
Instruction Classification
Table 4-22. Class 4a Instruction Description
C4a 0 1 Mnemonic MOV {adrs}, Rx MOV Rx, {adrs} Description Store Rx register to data memory referred by addressing mode {adrs}. Modify transfer status. Load Rx with the value in data memory referred by addressing mode {adrs}. Modify transfer status.
Table 4-23. Class 4b Instruction Description
C4b 0 0 1 1 0 1 0 1 Mnemonic ADDB Rx, imm8 SUBB Rx, imm8 MOVB Rx, imm8 CMPB Rx, imm8 Description Add 8 bit positive constant to Rx register. Modify RX status. Subtract 8 bit positive constant from Rx register. Modify RX status. Load Rx with the an 8 bit positive constant. Modify RX status. Store the status of the subtraction (Rx - 8 bit positive constant) into RZF and RCF bits of the STAT register. Rx remains unchanged.
Table 4-24. Class 4c Instruction Description
C4c 0 0 1 1 0 1 0 1 Mnemonic ADD Rx, imm16 SUB Rx, imm16 MOV Rx, imm16 CMP Rx, imm16 Description Add 16 bit positive constant to Rx register. Modify RX status. Subtract 16 bit positive constant from Rx register. Modify RX status. Load Rx with the an 16 bit positive constant. Modify RX status. Store the status of the subtraction (Rx - 16 bit positive constant) into RZF and RCF bits of the STAT register. Rx remains unchanged.
Table 4-25. Class 4d Instruction Description
C4d 0 0 1 1 0 1 0 1 Mnemonic ADD Rx, R5 SUB Rx, R5 MOV Rx, R5 CMP Rx, R5 Description Add R5 to Rx register, Modify RX status. Subtract R5 from Rx register. Modify RX status. Load Rx with R5. Modify RX status. Store the status of the subtraction (Rx - R5) into RZF and RCF bits of the STAT register. Rx and R5 remain unchanged.
Assembly Language Instructions
4-35
Instruction Classification
4.4.5
Class 5 Instructions: Memory Reference
Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), the shift value register (SV), the status register (STAT), the top of stack (TOS), the string register (STR), and the four accumulator pointer registers AP0 to AP3. The data pointer register (DP) is read only since its value is established by lookup table instructions. The RPT n (repeat) instruction is write only since repeated instructions cannot be interrupted. IRET and RET instructions are read only operations for popping the stack and are included in this class because the stack is memory mapped. Also included in this class are four flag instructions that modify flag memory and two instructions that multiply memory by MR, storing the results in the PH register.
Table 4-26. Class 5 Instruction Encoding
Bit Class 5 RET IRET 16 1 1 1 15 1 1 1 14 0 0 0 13 1 1 1 1 1 1 1 12 11 10 C5 1 1 0 0 0 1 0 0 1 1 1 1 9 8 7 6 5 4 3 2 1 0
adrs
1 1 1 1 1 1 1 1 0 0
Table 4-27. Class 5 Instruction Description
C5 0000 0000 0001 0 1 0 Mnemonic MOV {adrs}, SV MOV {adrs}, PH MOV {adrs}, STAT Description Store SV in the data memory location referred by addressing mode {adrs}, zero filled on upper 12 bits. Transfer status is modified. Store the PH in the data memory location referred by addressing mode {adrs}. Transfer status is modified. Store the status (STAT) register contents to the data memory location referred by addressing mode {adrs} (17 bits including TAG). No modification of status. Store string (STR) register contents to data memory location referred by addressing mode {adrs}, zero filled on upper 8 bits. Transfer status is modified. Store the accumulator pointer (APn) register to the data memory location in {adrs}. The upper 10 bits are zero filled. Transfer status is modified. Store the contents of the multiplier (MR) register in {adrs}. Transfer status is modified.
0001
1
MOV {adrs}, STR
001 0100 0100 0101
n
0 1 0
MOV {adrs}, APn MOV {adrs}, MR Reserved MOV {adrs}, DP
Store the data pointer (DP) register contents to the location referred by {adrs}. Transfer status is modified.
4-36
Instruction Classification
Table 4-27. Class 5 Instruction Description (Continued)
C5 0101 0110 0110 1 0 1 Mnemonic MOV {adrs}, TOS STAG {adrs} RTAG {adrs} Description Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode {adrs}. Transfer status is modified. Store 1 to the 17th bit of data memory location referred by {adrs}. Set the tag bit. Store 0 to the 17th bit of data memory location referred by {adrs}. Clear the tag bit. Store TF1 bit if n=1, TF2 bit if n=0 status bit to 17th bit of data memory location referred by addressing mode {adrs}. Load shift value (SV) register with contents of the location referred by addressing mode {adrs}. Transfer status is modified. Load Product High (PH) register with content of data memory location value referred by addressing mode {adrs}. Transfer is status modified. Load top of stack (TOS) register with content of data memory location referred by addressing mode {adrs}. Load String (STR) register with content of data memory location referred by addressing mode {adrs}. Only the lower 8 bits are loaded. Transfer status modified. Load lower 5 bits with content of data memory location referred by addressing mode {adrs} to accumulator pointer (AP) register n. Transfer status is modified (16 bit value). Load Multiplier (MR) register with content of data memory location referred by addressing mode {adrs} and set the multiplier signed mode (UM=0 in STAT register). Transfer status is modified. Load Multiplier (MR) register with content of data memory location referred by addressing mode {adrs} and set the multiplier unsigned mode (UM=1 in STAT register). Transfer status is modified. Multiply MR register by content of data memory location referred by addressing mode {adrs}, add 0x00008000 to the 32 bit product to produce a rounding on the upper 16 bits. Store the upper rounded 16 bits to the PH register. No status change. Multiply MR register by content of data memory location referred by addressing mode {adrs} and store the most significant 16 bits of product into the PH register. No status change. Return from subroutine. Load data memory location value addressed by R7 (STACK) to program counter. Return from interrupt routine. Load data memory location value addressed by R7 (STACK) to program counter.
0 1 1 1 n-1 MOVT {adrs}, TFn 1000 1000 1001 1001 0 1 0 1 MOV SV, {adrs}4 MOV PH, {adrs} MOV TOS, {adrs} MOV STR, {adrs}8
101n
n
MOV APn, {adrs}
1100
0
MOV MR, {adrs}
1100
1
MOVU MR, {adrs}
1101
0
MULR {adrs}
1101
1
MUL {adrs}
1110 1110
0 1
RET IRET
The entire 17 bit is encoded. See Table 4-26.
Assembly Language Instructions
4-37
Instruction Classification
Table 4-27. Class 5 Instruction Description (Continued)
C5 1111 1111 0 1 Mnemonic RPT {adrs}8 MOV STAT, {adrs} Description Load repeat counter with lower 8 bits of data memory location referred by addressing mode {adrs}. Interrupts are queued during execution. Load status (STAT) register with effective data memory location referred by addressing mode {adrs} (17 bits with TAG).
4.4.6
Class 6 Instructions: Port and Memory Reference
These instructions provide the basic expansion port of the MSP50P614/ MSP50C614 processor. IN instructions transfer 16-bit data from one of 16 expansion ports. OUT instructions transfer 16-bit data to one of the 16 expansion ports. In a typical system, the expansion ports are divided into those that serve internal peripheral functions and those that serve external pins. For subclass 6b, IN and OUT provide bidirectional transfers between the same port address (16) and accumulator. In addition, IN and OUT instructions in class 6b can communicate with an extra 48 ports (a total of 64 including the shared ports). Class 6b instructions also have reference to the string bit for checking the arithmetic status of a string transfer.
Table 4-28. Class 6a Instruction Encoding
Bit Class 6a Class 6b 16 1 1 15 1 1 14 0 1 13 0 0 12 C6a 1 1 11 10 9 8 7 6 5 4 3 2 1 0
port4
s An
adrs port6
C6b ~A~
Table 4-29. Class 6a Instruction Description
C6a 0 Mnemonic IN {adrs}, port4 Description Transfer a 16 bit value of addressed port to data memory location referred by addressing mode {adrs}. Refer to port address map. Transfer status is modified. Transfer a 16 bit value in the data memory location referred by addressing mode {adrs} to addressed port. Refer to Port address map. Transfer is status modified.
1
OUT port4, {adrs}
4-38
Instruction Classification
Table 4-30. Class 6b Instruction Description
C6b 0 1 Mnemonic IN An[~], port6 INS An[~], port6 OUT port6, An[~] OUTS port6, An[~] Description Transfer the port's 16 bit value to an accumulator. Port addresses 0-63 are valid. ALU status is modified. Transfer a 16 bit accumulator value to the addressed port. Port addresses 0-63 are valid. Transfer status is modified.
4.4.7
Class 7 Instructions: Program Control
This class of instructions provides the logical program control of conditional branches (jumps) and calls (subroutines). Both branch and call instructions require a 32 bit instruction word. The first word contains the opcode and condition fields and the second word contains the destination address. The condition field can specify the true (Not=0) or false (Not=1) condition of 22 different status conditions. The status bits that establish the conditions are latched and remain unchanged until another instruction that affects them is executed. In addition to call, a macro-call instruction is included. This instruction is similar to an unconditional call instruction. When executed it pushes the PC+1 value to the STACK and loads a paged vector (7F loaded in the upper 8 bits of PC and an 8 bit vector number loaded into the lower 8 bits of the PC). This makes the macro-call a single word instruction that take 2 instruction cycles to execute. This instruction is useful for referencing frequently used subroutines. A normal RET instruction is used to return to the main program from macro-calls. Auxiliary register R7 (STACK) is used as the program stack pointer and is automatically incremented on calls and macro-calls. It is automatically decremented on returns. Interrupts are vectored in the same way as macro-calls. The stack pointer is incremented when interrupts fire and decremented when an IRET is executed. One side effect of the program stack's operation is that it is not permissible to return to a RET instruction. Either the compiler inserts a NOP between such occurrences or the programmer must avoid this sequence.
Assembly Language Instructions
4-39
Instruction Classification
Table 4-31. Class 7 Instruction Encoding and Description
Bit VCALL vector8 Jcc JMP *An Ccc CALL *An 16 1 1 1 1 1 15 1 0 0 0 0 14 1 0 0 0 0 13 1 0 0 0 0 12 1 0 1 0 1 11 1 0 0 1 1 10 1 Not x Not x An Description An 9 0 8 1 7 6 5 4 3 2 1 0
vector8 cc
x Rx
pm
cc
x
x
cc names cc
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TF1 TF2 TAG IN1 IN2 NTF1 NTF2 NTAG NIN1 NIN2
cc name
Z S C B A G E O RC RA RE REZI RLZI L
Not cc name
NZ NS NC NB NA NG NE NO RNC RNA RNE Conditional on ZF=1 Conditional on SF=1 Conditional on CF=1 Conditional on ZF=0 and CF=0 Conditional on ZF=0 and CF=1 Conditional on SF=0 and ZF=0 Conditional if ZF=1 and OF=0 Conditional if OF=1 Conditional on RCF=1 Conditional on RZF=0 and RCF=1 Conditional on RZF=1 Conditional on value of Rx=0 (Not available on Calls) Conditional on MSB of Rx=1. Not available on Calls. NL Conditional on ZF=0 and SF=1 Not assigned Not assigned Conditional on TF1 Conditional on TF2 Conditional on TAG Conditional on IN1 status Conditional on IN2 status
4-40
Instruction Classification
Table 4-31. Class 7 Instruction Encoding and Description (Continued)
cc names cc
1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 XZ XS XG XNZ XNS XNG Description
cc name
Not cc name
Unconditional Not assigned Not assigned Conditional on XSF Conditional on XZF Conditional on ! XSF and ! XZF Not assigned Not assigned Not assigned Not assigned Not assigned
4.4.8
Class 8 Instructions: Logic and Bit
This class of instructions provides a flexible and efficient means to make complex logical decisions. Instead of making a sequence of single bit decisions and constructing a logical statement through a branch decision tree, the program can sequentially combine several status conditions to directly construct a final logic value (TF1 or TF2) which can be used to control a subsequent branch or call. This class includes two subclasses. Class 8a instructions update one of the test flags (TF1 or TF2) with a logical combination of the old test flag value and an addressed memory flag value. Subclass 8b provides a flexible means of logically combining the test flag (TF1 or TF2) with a status condition and storing the results back to the test flag.
Table 4-32. Class 8a Instruction Encoding
Bit Class 8a Class 8b RFLAG {flagadrs} SFLAG {flagadrs} 16 1 1 1 1 15 0 0 0 0 14 0 0 0 0 13 1 1 1 1 12 1 0 1 1 11 10 9 8 C8a 7 6 5 4 3 2 1 0
flg flg
0 1
Not Not
0 0 0 1
flagadrs cc
Rx C8b
1 0
1 1
flagadrs flagadrs
Assembly Language Instructions
4-41
Instruction Classification
Table 4-33. Class 8a Instruction Description
C8a 0 0 0 Mnemonic MOV TFn, {flagadrs} Description Load flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs} to either TF1 or TF2 in status register. Load with inverted value if Not =1. Logically OR either TF1 or TF2 with flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs} (or inverted value if N=1) addressed by the instruction and store back to TF1 or TF2 respectively. Logically AND either TF1 or TF2 with flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs} (or inverted value if Not =1) addressed by the instruction and store back to TF1 or TF2 respectively. Logically exclusive OR either TF1 or TF2 with flag bit (17th bit) from data memory in {flagadrs} if Not =1(or inverted value if Not =0) addressed by the instruction and store back to TF1 or TF2 respectively. Store TF1 or TF2 to flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs}. Reset flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs}.to 0 Set flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs}.to 1
0
1
0
OR TFn, {flagadrs}
1
0
0
AND TFn, {flagadrs}
1
1
0
XOR TFn, {flagadrs}
0
0
1
MOV {flagadrs}, TFn RFLAG {flagadrs} SFLAG {flagadrs}
Table 4-32 Table 4-32
Table 4-34. Class 8b Instruction Description
C8b 0 0 1 1 0 1 0 1 Mnemonic MOV TFn, {cc} [, Rx] OR TFn, {cc} [, Rx] AND TFn, {cc} [, Rx] XOR TFn, {cc} [, Rx] Description Load a logic value of the tested condition to one of the test flag bits in status register (TF1 or TF2). Logically modify one of the two test flags in status register (TF1 or TF2) by ORing it with the status condition specified. Logically modify one of the two test flags in status register (TF1 or TF2) by ANDing it with the status condition specified. Logically modify one of the two test flags in status register (TF1 or TF2) by EXCLUSIVE ORing it with the status condition specified. For this instruction the polarity of Not is inverted (Not =1 for XOR, Not=0 for XNOR).
4.4.9
Class 9 Instructions: Miscellaneous
This instruction class includes all the remaining instructions that do not fit in the previous classes. Some instructions have byte wide operand fields and others have no operands. One subclass is a set of instructions that provide specific DSP functions (FIR filters). Another subclass provides some hardware/ software loop capability. Ten instructions provide the means to set or reset five different status mode bits independently.
4-42
Instruction Classification
Table 4-35. Class 9a Instruction Encoding
Bit Class 9a Class 9b Class 9c Class 9d ENDLOOP n NOP 16 1 1 1 1 1 1 15 1 1 1 1 1 1 14 1 1 1 1 1 1 13 0 1 1 1 1 1 12 1 1 1 1 1 1 11 0 1 0 1 1 1 10 0 0 1 1 1 1 1 1 1 9 An C9a APn 0 0 1 0 1 0 C9c C9d 0 1 0 1 1 1 x 0 0 1 8 7 C9a 6 5 0 4 3 Rx 2 1 1 0 1
imm8 imm5
0 0 1 0 0 1 0 n 1
Table 4-36. Class 9a Instruction Description
C9a 0 0 Mnemonic FIRK An, *Rx Description Finite impulse response tap execution. When used with repeat counter will execute a 16 bit x16 bit multiplication between an indirect-addressed data memory buffer and program memory (coefficients). 32 bit accumulation. Circular buffering. Each tap executes in 2 cycles. Rx automatically increments by 2 per tap. Finite impulse response tap execution. When used with the repeat counter, it will execute a 16 bit x16 bit multiplication between two indirect-addressed data memory buffers into a 32 bit accumulator. Circular buffer operation. Executes in 2 instruction cycles. Rx and R(x+1) automatically increments by 2 per tap. Correlation function. When used with repeat will execute 16x16 multiplication between data memory and program memory, 48 bit accumulation, and a circular buffer operation. Each tap takes 3 instruction cycles. Rx automatically increments by 2 per tap. Correlation function. When used with repeat will execute 16x16 multiplication between two indirectly addressed data memory buffers, 48 bit accumulation, and a circular buffer operation. Each tap takes 3 instruction cycles. Rx and R(x+1) automatically increments by 2 per tap.
0
1
FIR An, *Rx
1
0
CORK An, *Rx
1
1
COR An, *Rx
Table 4-37. Class 9b Instruction Description
C9b 0 0 1 0 1 0 Mnemonic RPT imm8 MOV STR, imm8 MOV SV, imm4 Description Load the repeat counter with an 8 bit constant and execute the instruction that follows imm8+2 times. Interrupts are queued during execution. Load the STR register with an 8 bit constant. Load the SV (shift value) register with a 4 bit constant.
Assembly Language Instructions
4-43
Bit, Byte, Word and String Addressing
Table 4-38. Class 9c Instruction Description
C9c 0 1 Mnemonic MOV APn, imm6 ADD APn, imm5 Description Load the accumulator pointer (AP) with a five bit constant. Add a five bit constant imm5 to the referenced accumulator pointer(AP).
Table 4-39. Class 9d Instruction Description
C9d Mnemonic Description Marks the beginning of loop. Queue interrupts and pushes the next PC value onto a temporary stack location.
0 0 0 0 BEGLOOP
0 0 0 1 ENDLOOP n If R4 is not negative, pops the temporary stack value back on the PC and decrements R4 by n. If R4 is negative, the instruction is a NOP and execution will exit the loop. n is either 1 or 2 0 0 1 0 IDLE 1 0 0 0 INTE 1 0 0 1 INTD 1 0 1 0 SXM 1 0 1 1 RXM 1 1 0 0 SFM 1 1 0 1 RFM 1 1 1 0 SOVM 1 1 1 1 ROVM Stops processor clocks. Device enters low power mode waiting on an interrupt to restart the clocks and execution. Sets IM bit in status register to a 1, thus enabling interrupts. Sets IM bit in status register to a 0, thus disabling interrupts. Sets XM in status register to 1 enabling sign extension mode. Sets XM in status register to 0, disabling sign extension mode. Sets FM in status register to 1, enabling multiplier shift mode for signed fractional arithmetic. Sets FM in status register to 0, enabling multiplier shift mode for unsigned fractional or integer arithmetic. Set OM bit in status register to 1, enabling ALU saturation output (DSP mode). Set OM bit in status register to 0, disabling the saturating ALU operation (normal mode).
4.5 Bit, Byte, Word and String Addressing
The MSP50P614/MSP50C614 has instructions which address bits, bytes, words and strings in data memory or program memory. Data memory is always accessed in bytes by the hardware, but is based on the instruction. The data memory location is treated as a byte, word, or flag address. There are five different kinds of addresses: byte addresses, byte-string addresses, word addresses, word-string addresses, and flag addresses. Each type of address is described below. Refer to Figure 4-3 and Table 4-40 for reference. Byte and byte string address: Byte addressing is used to access individual bytes with an instruction in byte mode. Such instructions have a suffix, B, at the end of instruction name (for example, ADDB, MOVB, etc.). A byte string
4-44
Bit, Byte, Word and String Addressing
is a string of bytes. The length of the byte string is stored in the string register (STR). To define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8. A byte string address can be even or odd. Byte string data is fetched from the lower address (starting address) one byte at a time to consecutive addresses. NOTE: Data Memory Access Data memory access (RAM) is always accessed with byte addresses. Program memory (ROM) is accessed with 17-bit words. Rx registers autoincrement (or autodecrement) by 1 for byte addressing, by 2 for word addressing, or by the length of the string in bytes if Rx++ (or Rx- -) is used. Word and Word string addresses: One data memory word is composed of two consecutive bytes. A word address is always an even byte address and the least significant bit of the byte address is assumed to be zero. Instructions that operate on words have internal hardware which increments the byte address appropriately to load the two consecutive bytes in one clock cycle. To use an absolute word address, the address should be multiplied by 2. A wordstring is a string of consecutive words. Like a byte-string, word-strings use the STR register to define the string length. Word-strings always start at an even byte address. When string instructions are used, words are fetched from the first word-string memory location to consecutive addresses. The word address is the data memory address in bytes. This is obtained by multiplying the byte address by two.
Figure 4-3. Data Memory Organization and Addressing
Flag addresses 0000h 0001h Global flags 0002h 17th Bit 17th Bit 17th Bit Data memory address (even) 0000h 0002h 0004h MS Byte MS Byte MS Byte 1 Word Data memory address (odd) LS Byte LS Byte LS Byte 0001h 0003h 0005h
0040h 0041h Relative flags nnnn
17th Bit 17th Bit
nnnn
Note:
MS Byte
LS Byte
nnnn+1
Word address is data memory address (or byte address) divided by 2.
17th Bit
Flag address always accesses the 17th bit of 17 bit wide data word in data memory.
Assembly Language Instructions
4-45
Bit, Byte, Word and String Addressing
Flag address: The flag (or TAG) address uses linear addressing from 0 to the size of data memory in 17 bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17th bit is accessible. When a word memory location is read, the corresponding flag for that location is always loaded into the TAG bit of the status register (STAT). The flag address always corresponds to a 17 bit wide word address. If string instructions are used, then the flag bit of the last memory location of the string is loaded into the TAG bit of the status register. Global flag addressing or relative flag addressing is used to address flags. Flag bits can be set or reset using flag instructions in addition to various logical operations. The flag address does not have a string mode. Rx post modifications: Indirect addressing allows post modification of Rx. For byte and byte-string mode, Rx is post modified by 1 for each byte. For word and word-string mode Rx is post modified by 2 for each word. Post modification of Rx is not available for flag addressing.
Table 4-40. Data Memory Address and Data Relationship
Mode Single byte Byte string Single word Word string Address Used Absolute 16 bit address Beginning of string at lower address Even address, if odd address is used, the LSB bit of address is assumed 0 Even address beginning at a lower address; if odd address is used, the LSB bit of address is assumed 0 Address is considered as holding 17 bit data, but only 17th bit is accessed. Data Order 8 bit data String length times 8 bit data by Incrementing addresses 16 bit data String length times 16 bit data by incrementing addresses 1 bit data Rx Post modify 1 1 per byte in string 2 2 per word in string not available
Flag
Rx post modification is available by various addressing modes (see 4.3, Instruction Syntax and Addressing Modes for detail).
Example 4.5.1 MOVB A0, *0x0003 Refer to Figure 4-4 for this example. This instruction loads the value 0x78 to the accumulator. The upper 8 bits of the accumulator is padded with zeros. Example 4.5.2 MOV A0, *0x0000 MOV A0, *0x0001 Refer to Figure 4-4 for this example. Both instructions will load the value 0x1234 to the accumulator. In word addressing, the LSB bit of the address is assumed to be zero. Thus, in the second instruction, the least significant bit of the address is ignored. Example 4.5.3 MOV A0, *0x0004 * 2 Refer to Figure 4-4 for this example. The word address 0x0004 is referred. Multiplication by 2 is necessary to convert the word address into the equivalent byte address . After multiplication, the byte address is 0x0008. This instruction will load the value 0x1122 to the accumulator.
4-46
Bit, Byte, Word and String Addressing
Figure 4-4. Data Memory Example
Absolute Word Memory Location 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 Data Memory Location (even) = 2 * (Absolute word memory location) 0x0000 0x0002 0x0004 0x0006 0x0008 0x000a MS Byte 0x12 0x56 0x9a 0xde 0x11 0x33 LS Byte 0x34 0x78 0xbc 0xf0 0x22 0x44 Data Memory Location (odd) 0x0001 0x0003 0x0005 0x0007 0x0009 0x000b
Example 4.5.4
MOV STR, 4-2 MOV AP0, 2 MOVBS A0, *0x0003 Refer to Figure 4-4 for this example. The byte-string length is 4. It is loaded to the string register (STR) in the first instruction. AP0 is 2 and it points to AC2. Third instruction loads the value of the string at byte address, 0x0003, and subsequently stores its contents into four consecutive accumulators starting from AC2. The result is, AC2 = 0x0078, AC3 = 0x009A, AC4 = 0x00BC, AC5 = 0x00DE. Example 4.5.5 MOV STR, 4-2 MOV AP0, 2 MOVS A0, *0x0003 Refer to Figure 4-4 for this example. The byte-string length is 4. AP0 is loaded with 2 and points to AC2. The third instruction loads the value of the string at address 0x0002 (LSB bit is assumed 0) and stored into four consecutive accumulators starting from AC2. The result is, AC2 = 0x5678, AC3 = 0x9ABC, AC4 = 0xDEF0, AC5 = 0x1122. Same result can be obtained by replacing the third instruction by, MOVS A0, *0x0001 * 2 which uses the absolute word memory address. Example 4.5.6 MOV STR, 4-2 OV AP0, 2 MOV R0, 0x0005 MOVBS A0, *R0++ Refer to Figure 4-4 for this example. The byte string length is 4. AP0 points to AC2. R0 is loaded with 0x0005. The fourth instruction loads the value of the byte-string at the address in R0 (i.e, 0x0005 in byte mode). R0 auto-increments by 1 after every fetch and stores the RAM contents into four consecutive accumulators starting from AC2. The result is, AC2 = 0x00BC, AC3 = 0x00DE, AC4 = 0x00F0, AC5 = 0x0011. There were four byte fetches and the new value of R0 = 0x0009.
Assembly Language Instructions
4-47
Bit, Byte, Word and String Addressing
Example 4.5.7
MOV STR, 4-2 MOV AP0, 2 MOV R0, 0x0001 * 2 MOVBS A0, *R0++ Refer to Figure 4-4 for this example. The word-string length is 4. AP0 points to AC2 accumulator. R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002. R0 autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2. The result is, AC2 = 0x5678, AC3 = 0x9ABC, AC4 = 0xDEF0, AC5 = 0x1122. There were 4 word fetches and the new value of R0 = 0x000A. SFLAG *0x0003 MOV A0, *0x0003 * 2 RFLAG *0x0003 MOV A0, *0x0003 * 2 Refer to Figure 4-4 for this example. This example illustrates the use of the TAG and flag bits. Notice that SFLAG uses a word address, 0x0003, while the MOV instruction uses a byte address 0x0003 * 2. The first instruction sets the flag/tag bit at flag address 0x0003. Flag address 0x0003 represents the 17th bit of the 3rd word (or 6th byte) of RAM. In the second instruction, this flag bit is placed in the TAG status bit of the STAT and the value in RAM location 0x0003 * 2 is placed in A0. The third instruction resets the flag/tag to 0 at the same flag address. The fourth instruction reads the same word memory location and writes the TAG bit of STAT, which is now 0. Note: SFLAG *0x0003 could have been replaced by STAG *0x0003 * 2 and RFLAG *0x0003 could have been replaced by RTAG *0x0003 * 2. SFLAG *0x0005 MOVB A0, *0x000b RFLAG *0x0005 MOVB A0, *0x000b Refer to Figure 4-4 for this example. The SFLAG instruction sets the 17th bit (tag/flag) of the 5th word of RAM. The MOVB instruction gets the lower byte of the 5th word of RAM and puts it in A0. In addition, the TAG bit of the STAT register is set. If the MOVB instruction addressed *0x000A instead of *0x000B, the STAT register would still be updated with the same tag/flag bit (the 17th bit of the 5th word of RAM). This means that odd byte locations in RAM, RAModd, have the same tag/flag as the preceding byte location RAModd -1. For example, the 7th word of RAM is made up of two bytes: 0x000E, and 0x000F. These two byte locations share the same tag/flag bit. Example 4.5.9 Example 4.5.8
4-48
MSP50P614/MSP50C614 Computational Modes
Example 4.5.10
MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4-4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded with 0 (string length of 2). The second instruction sets the flag bit to 1 at flag address 0x0032. The next instruction reads the word-string at word memory location, 0x0031, into A0 and also sets the TAG bit of STAT to 1 corresponding to the last memory location of the string (which is word address 0x0032 in this case). The next two instructions verify this by setting the flag to zero and reading the memory string again.
4.6 MSP50P614/MSP50C614 Computational Modes
MSP50P614/MSP50C614 has the following computational modes which are the first 4 bits of the status register.
-
Sign extension mode (bit 0 or XM bit of STAT) Unsigned mode (bit 1 or UM bit of STAT) Overflow mode (bit 2 or OM bit of STAT) Fractional mode (bit 3 or FM bit of STAT)
These modes can be set by setting the appropriate status register bits or by special instructions (Class 9) as shown in Table 4-41.
Assembly Language Instructions
4-49
MSP50P614/MSP50C614 Computational Modes
Table 4-41. MSP50P614/MSP50C614 Computational Modes
Computational Mode Sign extension Setting Instruction SXM Resetting Instruction RXM Function STAT.XM = 1 produces sign extension on data as it is passed into accumulators. This mode copies the 16th bit of the data in the multiplier/multiplicand to the 17th bit. This causes signed multiplication of two signed numbers. STAT.XM = 0 suppresses sign extension. STAT.UM = 1 causes unsigned multiplication where the multiplier assumes its arguments as unsigned value. MOVU instruction can be used to enable this mode. STAT.UM = 0 disables unsigned multiplication. STAT.OM = 1 initiates overflow mode. Overflows cause the accumulator to acquired the most positive or most negative value. In the case of string values, only the MSB 16 bits are modified. The remaining bits in the string are unchanged. STAT.OM = 0 normal overflow operation and the accumulator content is unchanged if any overflow occurs. Affects OF bit of STAT in case of overflow. STAT.FM = 1 enables fractional multiplication shift mode. The multiplier is shifted left 1 bit to produce a 17 bit operand. This mode is used on signed binary fractions and does not require the user to left shift as it would have been required if the FM bit was not set. STAT.FM = 1 turns off fractional mode.
Unsigned
none
none
Overflow
SOVM
ROVM
Fractional
SFM
RFM
Sign Extension Mode: Sign extension mode can be enabled/disabled by setting/resetting the XM bit of STAT. When in sign extension mode, a multiply operation will copy the 16th bit of the multiplier/multiplicand to the 17th bit. When multiplied, this will give a 17 x 17 bit multiplication producing 34 bit result where the upper two bits (33rd and 34th bits) are the sign bits and discarded by the processor. Sign extension is also applicable in string mode. Sign extension mode is the recommended mode to use for signed number multiplication. Example 4.6.1 SXM MOV A0, 0x8000 MOV MR, 0x8000 MULTPL A0, A0 This example illustrates the sign extension mode during multiplication. Here, two negative number 0x8000 are multiplied with 0x8000 to obtain a positive number 0x40000000. If the signs were not extended, we would have obtained 0xC0000000, a negative number.
4-50
MSP50P614/MSP50C614 Computational Modes
Example 4.6.2
SXM MOV STR, 2-2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, --A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication. Here, two negative numbers 0x80000000 and 0x8000 are multiplied to obtain a positive number 0x400000000000. If the signs were not extended, we would have obtained 0xC00000000000, a negative number. Unsigned Mode: The multiplier unsigned mode may be enabled/disabled by setting/resetting the UM bit of the STAT. When in unsigned mode, the 17th bit of the multiplier is loaded as zero to indicate an unsigned value. When UM is set to zero, signed multiplication is enabled and the multiplier copies the MSB of the multiplier (16th bit) to the 17th bit of the multiplier. Example 4.6.1 MOV A0, 0x8000 MOVU MR, A0 MOV A0, 0x80 MULTPL A0, A0 In this example, we do an unsigned multiplication between 0x8000 and 0x80. The first two lines set up the MR register with value 0x8000 and switch to unsigned multiplication mode. Line 3 loads A0 with 0x80 and line 4 multiplies the values in unsigned mode. The lower 16 bits of the result is stored in A0 and the upper 16 bits are stored in PH. The final result is 0x400000, where PH holds the value 0x0040 and A0 holds the lower 16 bits. Notice that if the multiplication is not done in unsigned mode, the MR is treated as negative. We would have obtained 0xFFC00000 (PH = 0xFFC0, A0 = 0000), which is the negative value of the previous result. The key to unsigned multiplication is the MOVU instruction in the second line which set the UM bit to 1 in the STAT register and switches the multiplication mode to unsigned. Overflow Mode: The accumulator's overflow mode may be enabled/disabled by setting/resetting the OM bit of STAT. When the computation is in the overflow mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending upon the direction of the overflow. In string mode, instead of representing the most positive or most negative value, only the 16-bit MSB is set to 0x7FFF or 0x8000 depending on direction of overflow. The remaining words of the accumulator string are unchanged. If the OM status register bit is reset and an overflow occurs, the overflowed results are placed in the accumulator without modification. Note that logical operations cannot result in overflow.
Assembly Language Instructions
4-51
MSP50P614/MSP50C614 Computational Modes
Example 4.6.1
SOVM MOV A0, 0x7FFE ADD A0, 5 In this example, we set the overflow mode (OM = 1 of STAT). Adding 0x7FFE with 5 causes an overflow (OF = 1 of STAT). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF. If overflow mode was not set before the ADD instruction, then the accumulator would overflow. Therefore, the result, 0x8003, would be a negative value. SOVM MOV STR, 2-2 ;string length = 2 MOV AP0, 0 MOV A0, 0x1234 MOV A0~, 0x1000 MOV A0, 0x7F00, ++A MOV A0~, 0x1000 MOV AP0,0 ;point to beginning ;of string ADD A0, A0~, A0 In this example, saturation on a string value is illustrated. A 2 word string is loaded into the STR register. The accumulator string, A0, is loaded with 0x7F001234 and accumulator string A0~ is loaded with 0x10001000. When the two values are added together, it causes an overflow. The OF bit of the STAT is set to 1, the 16 bit MSBs of the string become 0x7FFF, and the lower bits of the string become 0x2234. The final result is 0x7FFF2234. Note that if overflow mode was not set, the result would have been 0x8F002234. Fractional Mode: Multiplier fractional mode may be enabled/disabled by setting/resetting the FM bit of STAT. When the multiplier is in fractional mode, the multiplier is shifted left 1 bit to form a 17 significant bit operand. Fractional mode avoids a divide by 2 of the product when interpreting the input operands as signed binary fractions (Q formats). Fractional mode works with string mode as well. Example 4.6.1 SXM MOV A0, 0x7FFF MOV MR, 0x7FFF MULTPL A0, A0 ;0x7FFF * 0x7FFF ;PH = 0x3FFF A0~ = 0001 SFM MULTPL A0~,A0 ;PH = 0x7FFE A0~ = 0002 Example 4.6.2
This example illustrates the differences between a regular multiply and a fractional mode multiply. The first multiply in the above code is nonfractional. The
4-52
Hardware Loop Instructions
high word of the result is stored in the PH register and is 0x3FFF. The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fractional numbers (all bits are to the right of the decimal point), then the result will be a Q30 number. To translate a Q30 number back to a Q15 number, first left shift the number (MOV A0,PH, SHL A0,A0), and then truncate the lower word (ignore A0~). When fractional mode is set, the left shift is done automatically (MOV A0,PH). Thus, the desired Q15 result is already in the PH register.
4.7 Hardware Loop Instructions
These instructions enhance both execution speed and code space requirements for procedures that use short loop sequences. Because of pipeline delays and the software overhead associated with counting, comparing and branching, software controlled structures are very inefficient for short loops. To ease this burden, two basic types of hardware assisted loop structures are included in the MSP50P614/MSP50C614 processor. Hardware loop instructions are summarized in Table 4-42. Repeatable instructions: Most instructions can be repeated N+2 times with zero software overhead. Repeated instructions are functionally identical to coding the same instruction N+2 times in sequence. Repeat loops require a RPT instruction to set a count length, N. This immediately precedes the instruction to be repeated. This next instruction is repeated N+2 times. The RPT instruction is useful for clearing RAM locations, filtering, etc. If the repeating instruction utilizes auto-increments/decrements to either Rx or AC registers (i.e. *R2++ or ++A), then the repeated modification controls will be permanent. If the repeatable instruction is a string instruction, then the string register (STR) will be replaced by N. During the execution of a RPT instruction, interrupts are queued. Queued interrupts are serviced after the RPT operation completes according to their priority. String instructions: String loops are enabled by direct field decodes in classes 1, 2b, 3 and 6b and have no counter overhead. These instructions automatically load the counter using the contents of the STR. String instruction loops are different because they assume the references made to data memory and accumulators are long data strings, causing pointers to auto-increment. Incrementing pointers does not affect the permanent value stored in Rx or APn registers. For arithmetic string operations, carries from one word operation will automatically be linked to the carry in of the next word operation. Additionally, status equal to zero will be detected on the result as a long string. These combinations provide efficient and convenient means to operate between lists or stings or between a fixed location and a list or string. All string instructions have a suffix, S. In this text, string instructions are written as nameS. During
Assembly Language Instructions
4-53
Hardware Loop Instructions
the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to control the hardware repeat count, it is not possible to nest repeats and strings. When a repeat instruction is followed by a string instruction the string register count is replaced by the value in the preceding repeat instruction. This offers greater utility in some programs and avoids load and store operations on the string register. Loop instructions: This is a software loop with an explicit reference to R4. The beginning of the loop is marked with the BEGLOOP instruction which pushes the next sequential address to a temporary register. A second instruction, ENDLOOP, marks the end of the loop. When executed, ENDLOOP loads the temporary register to the program counter if R4 is positive and then post decrements R4. If R4 is negative, the program counter executes a NOP instruction and exits the loop. Since interrupts are queued during the execution of the loop, no provision for saving the contents of the temporary register is made. Interrupts, if enabled before the execution of BEGLOOP, will automatically be re-enabled after exiting the loop. Enabling interrupts inside the loop have no effect. Queued interrupts are processed according to their priority after the loop exits provided the corresponding interrupt is enabled. The loop overhead is 1 instruction cycle per loop cycle, ideal for repeating high priority repeated blocks in DSP routines.
Table 4-42. Hardware Loops in MSP50P614/MSP50C614
Syntax RPT imm8 | {adrs}8 {repeatable instruction} Operation {repeatable instruction} is executed nR+2 times, where nR is the value in repeat counter. If the instruction following RPT is a string instructions, then string length used will be nR, not the value in the STR register. All interrupts are queued during loop execution. Queued interrupts are processed according to priority after the completion of the RPT loop. String length for the {string instruction} is nS+2. All interrupts are queued during loop execution. Queued interrupts are processed according to priority after the completion of the {string instruction}. The maximum accumulator string length is 32, i.e., 0 nS 29. The number of times the {...body of loop...} is executed is NLOOP+2. All interrupts are queued during loop execution. Queued interrupts are processed according to priority after the completion of the BEGLOOP/ENDLOOP block. Limitations 0 nR 255
{STR= nS} {string instruction}
0 nS 255 NOTE: 0 nS 29 for accumulator strings. 0 NLOOP 32767
{R4= NLOOP} BEGLOOP {...body of loop...} ENDLOOP
4-54
String Instructions
4.8 String Instructions
Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators (N is the length of the string). The STR register should be loaded with N-2 to define a string length, N. A value of zero in the STR register defines a string length of 2 (string length 1 means the instruction is not in string mode). Arithmetic string instructions treat the string as an N word arithmetic value. The result is also an arithmetic value of the same length. Conditionals are set as they would be set without string mode. Comparing two strings is equivalent to comparing each bit of the string. The accumulator status is modified representing the outcome of the entire operation. Examine the following examples.
Table 4-43. Initial Processor State for String Instructions
Registers (register# = value) AP0 = 2 AC0 = AC4 = AC8 = AC12 = 0xAAAA AC16 = AC20 = AP1 = 21 (0x15) AC1 = AC5 = AC9 = AC13 = 0xAAAA AC17 = AC21 = 0x1223 AP2 = 11 (0x0B) AC2 = AC6 = AC10 = AC14 = 0xAAAA AC18 = AC22 = 0xFBCA AP3 = 29 (0x1D) AC3 = AC7 = AC11 = 0xAAAA AC15 = 0xAAAA AC19 = AC23 = 0x233E
data memory (*address = data) *0x0200 = 0x12AC *0x0201 = 0xEE34 *0x0202 = 0x9086 *0x0203 = 0xCDE5
program memory (*address = data) *0x1400 = 0x0123 *0x1404 = 0xFEDC *0x1401 = 0x4567 *0x1405 = 0xBA98 *0x1402 = 0x89AB *0x1404 = 0x7654 *0x1403 = 0xCDEF *0x1405 = 0x3210
Example 4.8.1
MOV STR, 4-2; string length = 2 MOVS A0, 0x1400 Refer to initial the processor state in Table 4-43. A0 points to AC2. Consider a program memory location string of length 4 at 0x1400 = 0xCDEF89AB45670123. STR equal to 4-2=2, defines a string length of 4. Final result, AC2=0x0123, AC3=0x4567, AC4=0x89AB, and AC5=0xCDEF, Example 4.8.2 MOV STR, 3-2; string length = 3 ADDS A1~, A1, *0x0200 Refer to the initial processor state in Table 4-43. A1 is AC21, A1~ is AC5, the
Assembly Language Instructions
4-55
String Instructions
A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3-2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF, AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry. Special String Sequences: There are two string instructions that have a special meaning. If any of the following instructions: MULAPL, MULSPL, MULTPL, SHLAPL, SHLSPL, SHLTPL, EXTSGNS, MOVAPH immediately precedes ADDS An[~],An[~],PH and SUBS An[~],An[~],PH, the following things happen: 1) Carry generated by the preceding instruction is used in computation. 2) Interrupts can occur between these instructions. 3) All instructions in the sequence execute as a single string operation. So, An[~] accumulator pointed by the first instruction of the sequence should be used for the remaining instructions in the sequence and changing the value of n on one of the above instructions in the sequence has no effect. 4) Accumulators used by ADDS and SUBS (when used with PH) auto-increment internal registers, not APn. So subsequent ADDS and SUBS (immediately following) instructions write into higher accumulators. 5) The sequence ends with ADDS or SUBS (used with PH). 6) These sequences may not give same result when single step debugging because, single stepping changes the internal state. They should be used either with a hardware breakpoint or with fast run mode. The breakpoint should be set after the sequence ends. For example, MULAPL A0, A0~ ADDS A0, A0, PH The first instruction performs a multiply-accumulate with MR and A0~, and stores PL in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0~. The MULAPL - ADDS sequence is a special sequence. If A0 is AC0=0xFFFF and MR=0xFF, after execution AC0=0xFF01, AC1=0x00FE. If you replace ADDS A0, A0, PH with ADDS A1, A1, PH and A1 points to a different accumulator, the result is still the same. This is because, the state generated by MULAPL (and other similar instructions described above) is used by ADDS instruction. If another ADDS A0, A0, PH instruction follows the previous one, AC2=0x00FE since the ADDS instruction auto-increments an internal register (not APn). The same reason applies for SUBS An[~],An[~],PH instruction. IMPORTANT: Interrupts may occur between these sequences and the result can be incorrect if the interrupt service changes the state of the processor To prevent interrupts from happening, use the INTD instruction before the execution of the sequence and an INTE afterwards.
4-56
Lookup Instructions
4.9 Lookup Instructions
Table lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, characters for an LCD display which can be read for display in the LCD screen, etc. There are four lookup instructions as shown in Table 4-44. Lookup instructions always read the program memory address from the second argument (which is accumulator or its offset). An asterisk (*) always precedes this accumulator to indicate that this is an address.
Table 4-44. Lookup Instructions
Instructions Description Data Transfer MOV {adrs}, *An The program memory address is stored in accumulator An. Store the contents of this address in data memory location referred by addressing mode {adrs}.
MOV An[~], *An[~] [, next A] The program memory address is stored in accumulator An or its offset An~. Store the contents of this address in accumulator An or An~. MOVS {adrs}, *An The program memory string address is stored in accumulator An. Store the contents of this address to the data memory string referred by the addressing mode {adrs}. The string length is defined in STR register. The program memory string address is stored in accumulator An or its offset An~. Store the contents of this address to the accumulator string An or its offset An~. The string length is defined in STR register.
MOVS An[~], *An[~]
Data Manipulation on Strings ADDS An[~], An[~], pma16 ADD the accumulator string An or its offset An~ with the program memory string at location pma16 and store the result to the accumulator string An or its offset An~. The string length is defined in STR register. Bitwise/logical AND the string An (or its offset An~) with the program memory string at location pma16 and store the result in the accumulator string An or its offset An~. The string length is defined in STR register. Compare the accumulator string An (or its offset An~) with the program memory string at location pma16 and store the result in accumulator string An or its offset An~. The string length is defined in STR register. Subtract accumulator string An (or its offset An~) with program memory string at location pma16 and store the result in accumulator string An or its offset An~. The string length is defined in STR register. Bitwise/Logical XOR the accumulator string An or its offset An~ with program memory string at location pma16 and store the result to accumulator string An or its offset An~. The string length is defined in STR register.
ANDS An[~], An[~], pma16
CMPS An[~], pma16
SUBS An[~], An[~], pma16
XORS An[~], An[~], pma16
Assembly Language Instructions
4-57
Lookup Instructions
Lookup instructions make use of the data pointer (DP) internally. The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after the execution of lookup instructions. If filter instructions FIRK and CORK are used, it is required to context save DP in the interrupt service routine. Since these filter instructions use DP to read coefficient data (see section 4.10), any interrupt occurring between loading the first coefficient and the execution of a FIRK/CORK will change the last value of DP (if the interrupt routine uses a lookup instruction). DP can be stored in RAM ( MOV {adrs}, DP ), and a restoration is done as follows, MOV An, {adrs} SUB An, 0x1 MOV An, *An Context save and restore of instructions are not required if filter instructions are not used. Example 4.9.1
MOV A0, 0x100 MOV A0, *A0
Interrupt
; DP = 0x101 after execution
RPT N-2 FIRK A2, R0++ ...
; Beginning of interrupt service routine ; context save MOV *ctx_DP, DP ; ctx_DP stores the present DP = 0x101 ...some lookup instructions... ; context restore MOV *A0, *ctx_DP SUB A0, 0x1 MOV A0, *A0 ... IRET
; DP = 0x101 ; A0 = 0x100 after execution ; DP = 0x101 after execution
4-58
Input/Output Instructions
4.10 Input/Output Instructions
The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and the accumulators. Data input is performed with the IN instruction (Class 6). This instruction uses a memory address and a 4-bit port address. It can also use an accumulator (or offset accumulator) and a 6-bit port address. String transfers are allowed between the accumulators and the input port. Data output is performed with the OUT instruction (Class 6). The OUT instruction can specify a memory address and a 4-bit port address. It can also use an accumulator (or offset accumulator) and a 6-bit port address. String transfers are allowed between the accumulators and the output port.
4.11 Special Filter Instructions
The MSP50P614/MSP50C614 processor can perform some DSP functions. Fundamental to many filtering algorithms is the FIR structure which requires several parallel operations to execute for each tap of the filter as shown in Figure 4-5. Each tap has 1 multiply and 1 accumulation to obtain the output, y, for N+1 taps,
Figure 4-5. FIR Filter Structure
N+1 Tap FIR filter Newest sample x[k] 16 Delay h[0] h[1]
x[k-1]
Delay h[2]
x[k-2]
Delay
Oldest sample x[k-N] Delay h[N]
Samples, x[k]
x
x
x
x
x[k-3] x[k-2] x[k-1] x[k]
t
x[k+2] x[k+1]
+ 32 or 48 y[k] = m =0..N h [m]x[k-m]
y[k]
+ h[0] x[k] ) h[1]x[k-1] ) h[2]x[k-2] )@@@)h[N]
x[k-N]
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Assembly Language Instructions
Special Filter Instructions
N tap filters ideally require 2N multiply-accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instruction. FIR and FIRK instructions perform 16-x-16 bit multiplies and 32-bit accumulation in 2 clock cycles (per tap). The FIR/FIRK instruction takes 2N clock cycles (for N taps) to execute (once inside the RPT loop). FIRK is useful for fixed filters and requires the minimum amount of data memory. However, the DP register may need to be context saved and restored since the filter coefficients are in ROM. FIR is useful for adaptive filtering or applications where coefficients are provided from an external source. FIR does not require a context save and restore for the DP register since both the buffer and the coefficients are in RAM. COR and CORK instructions perform 16-x-16 bit multiplies and 48-bit accumulation in 3 clock cycles (per tap). Once inside the RPT loop, the total number of clock cycles for an N tap filter is 3N. The COR and CORK instructions are identical in operation and arguments to FIR and FIRK. However, an additional 16 bit extended accumulate cycle is added to prevent the arithmetic overflow common in auto correlation filters. FIR (COR) instructions: The execution of the filter instructions is shown in Figure 4-6. To use FIR (COR) instructions, some initial setup is required. Consecutive Rx pair {Rxeven, Rxeven+1} should be chosen with Rxeven pointing to the RAM sample buffer array and Rxeven+1 pointing to the RAM coefficient array. The MR register should be loaded with the first coefficient, h[0]. FIR (COR) can now execute with a repeat instruction for N taps. The value of Rxeven is incremented during execution. After execution, the last value of Rxeven points to the sample buffer location where the next sample can be stored. FIRK (CORK) instructions: FIRK (CORK) instructions work exactly the same was as FIR(COR) instructions, however, the coefficient array is located in program memory (ROM). Instead of loading Rxeven+1 with the pointer to coefficient array in RAM, the data pointer, DP, is loaded with the value of the coefficient array. Circular Buffering:The easiest way to understand circular buffering is by example. Suppose a filter, h[n], has 3 coefficients. Then, theoretically, to calculate one output sample of the filter, the buffer should contain the current sample plus the past 2 samples. Since the output, y[k], for a three tap filter is,
y[k] = h[0]* x[k] + h[1]* x[k-1] + h[2]* x[k-2]
On the C614, the circular buffer must contain N+1 samples. In the above example, the buffer must contain 4 locations (which is one more location than
4-60
Special Filter Instructions
theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circular buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the circular buffer and the filter coefficients. Therefore, the filter coefficient RAM locations must be loaded into RAM and the circular buffer must be cleared before the first FIR or COR instruction is executed.
; Set up for FIR filtering (N = 3) ; First clear circular buffer and set tag of second to last ; sample zac a0 mov r0,circBuff ;point to circular buffer rpt N-2 ;repeat N times mov *r0++,a0 ;clear RAM locations in circular ; buffer mov *r0,a0 ;N+1 sample in buffer mov r5,2 ;now step back one word and set tag sub r0,r5 ;point r0 back to 2nd to last sample ; in buffer stag *r0 ;set tag ; Second initialize filter coeffs to proper values ; ----- NOTE: In this code, N must be less than 33 since ; ----- there are only 32 accumulator registers! mov STR,N-2 ;set string length to N zacs a0 ;zero out N accumulators mov a0,FIR_COEFFS ;point to filter coeffs movs a0,*a0 ;get N filter coeffs mov r0,coeffs ;point to RAM locs. for filter coeffs movs *r0,a0 ;put filter coeffs into RAM locs. mov a0,circBuff ;set up pointer to start of circular ; buffer mov *startOfBuff,a0 ; Initialize filterSTAT_tag (THIS IS IMPORTANT!) rovm ;This line is MANDATORY! sxm ;Sample values are signed mov *filterSTAT_tag,STAT
Three more details in the above example merit an explanation. The first detail is the pointer to the start of the circular buffer (startOfBuff). This keeps track of the location of the newest or current sample in the circular buffer. It moves backwards by one location in the buffer each time the FIR or COR instruction is executed so that the oldest sample in the buffer is overwritten with the next sample. This backwards movement is also circular. For example, suppose that startOfBuff points to the first RAM location of the circular buffer.
Assembly Language Instructions
4-61
Special Filter Instructions
After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so on. The second detail is the STAT register. The STAT register must be saved immediately after every FIR or COR instruction. Consequently, this saved value must be loaded before every FIR or COR instruction. If the tag bit in the STAT register is set before an FIR or COR instruction, this tells the processor two things. First, it knows that it must wrap around to the first RAM location of the circular buffer. Second, it knows that the startOfBuff (and R0) currently points to the last location in the circular buffer. Thus, R0 will increment by R5 after the first multiply. This will become more clear after examining the next example code. The third detail is that the filter coefficients take up only N RAM locations, but the circular buffer takes up N+1 RAM locations. Below is an example of the FIR or COR execution inside a DAC interrupt service routine.
; FIR Filtering routine (N = 3) ------------------------------------------ rovm ;reset overflow mode mov R5, -2 * N ;circular buffer length (3 words) mov R1,coeffs ;R1 points to first of N filter coefficients mov MR,*R1++ ;must increment R1 mov mov mov zacs R0,*startOfBuff ;R0 points to start of circular buffer AP0,0 ;set up room for the STR,0 ; 32 bit output sample (AC0 and AC1) A0 ; STR should be 1 for COR/CORK instructions STAT,*filterSTAT_tag ;load STAT with last filter tag status
mov rpt fir mov
movs
N-2 A0,*R0++ ;Do one sample --> 32 bit result *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last/oldest sample *ySampleOut,A0 ;FIR outputs bits 0-15 in AC0, 16-32 in AC1
4-62
Special Filter Instructions
mov mov mov
;Replace last sample with newest sample *R0,A0 ; and update the start of the *startOfBuff,R0 ; circular buffer to here (R0)
A0,*nextSample
First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer. Wrap around happens automatically. This tells the processor how many words to step back when the end of the circular buffer is reached. This value must be negative and equal to N words even though the buffer is N+1 words long. For example, suppose a four word circular buffer starts at RAM location 0x0100 and ends at 0x0106 (N = 3). In order to wrap around from location 0x0106 back to location 0x0100, the value 0x006 must be subtracted from 0x0106, giving 0x0100.
0x0100 0x0102 0x0104 0x0106 TAGGED LOCATION Go back N words to wrap around
R0 must point to the current starting point of the circular buffer. R1 must point to the filter coefficients. The MR register must contain the first filter coefficient, h[0]. R0 and R1 must be used this way. The filtering operation will not work if the Rx registers are reversed. The following are the only allowable register combinations, R0 points to circular buffer and R1 points to filter coefficients R2 points to circular buffer and R3 points to filter coefficients
Assembly Language Instructions
4-63
Special Filter Instructions
Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction.
tag
0x0106 x[k-3] x[k-2]
0x010
Use R5 to wrap around
x[k]
x[k-1]
R0
0x0100
0x0102
After FIR/COR execution The STAT register is saved in the filterSTAT_tag location. The output of the filtering operation in the example is located in AC0 (lower word) and AC1 (high word). This 32 bit result is stored in the SampleOut RAM location. R0 should be pointing to the oldest sample. The oldest sample, x[k-3], is overwritten by the next sample to be filtered, x[k+1]. R0 is saved in the startOfBuff pointer for the next FIR/COR instruction
Notice that R0 points backwards by one location from its starting point each time an FIR/COR instruction is executed. In the above figure, R0 would end up at successive locations in a clockwise manner.
4-64
Special Filter Instructions
Important note about setting the STAT register It is very important to consider the initial value of the filterSTAT_tag variable. Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit of the STAT register may not be set. For samples or filter coefficients that are signed, the sign extension mode bit must also be set. Use the following set up for the filterSTAT_tag variable,
rovm sxm mov ; Mandatory ; For signed samples, coefficients, filter output *filterSTAT_tag,STAT ; -- Any addition modes can be set hereafter --
The FIRK/CORK instructions are almost identical to the FIR/COR instructions. The main difference is that the filter coefficients are placed in ROM instead of RAM. In other words, the filter coefficients are in a look-up table. As a result, the R1 register is not used. Before a FIRK/CORK instruction executes, the data pointer register, DP, must be set by the following code,
rovm mov mov mov mov R5, -2 * N A0,FIRK_COEFFS A0,*A0 MR,A0 ;reset overflow mode ;circular buffer length (3 words) ; Loads address of lookup table ; Loads first coefficient to A0 and sets DP ; Load first coefficient in to MR register
In the sequence of code above, the DP register points to the first filter coefficient (in program memory located at FIRK_COEFFS). This happens during the mov A0,*A0 instruction. In addition, the DP register automatically increments to the next address. It should be pointing to the second filter coefficient in program memory. If the contents of the DP register are used somewhere else in the program, a context save and restore must be performed on the DP register for each FIRK/CORK instruction. See the chapter 4 section called, Lookup Instructions. During FIRK/CORK execution, the MR register is loaded with the contents of the DP register, the DP register increments, pointing to the next filter coefficient, and the multiply-accumulate is performed. The remaining FIRK/CORK code is almost the same as the FIR/COR code.
mov mov mov zacs R0,*startOfBuff ;R0 points to start of circular buffer AP0,0 ;set up room for the STR,0 ;32 bit output sample (AC0 and AC1) A0 ; STR should be 1 for COR/CORK instructions
Assembly Language Instructions
4-65
Special Filter Instructions
mov rpt firk mov
STAT,*filterSTAT_tag
;load STAT with last filter tag status
movs
N-2 A0,*R0++ ;Do one sample --> 32 bit result *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample *ySampleOut,A0 ;FIR outputs bits 0-15 in AC0, 16-32 in AC1 A0,*nextSample *R0,A0 *startOfBuff,R0 ;Replace last sample with newest sample and update ; the start of the ; circular buffer to here (R0)
mov mov mov
The set up for the FIRK/CORK instruction is the same as the set up for the FIR/ COR instruction with the exception that the filter coefficients do not need to be loaded into RAM locations. Rather, they can be included just before speech data or elsewhere in the program code as follows,
FIRK_COEFFS include "\..\tables\coeffs.dat"
4-66
Special Filter Instructions
Figure 4-6. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps
DP Rxeven+1 {R1,R3,R5,R7} Rxeven {R0,R2,R4,R6}
coeff_array address coeff_array address sample_buf address
FIRK/CORK only
Program memory (FIRK/CORK)
coeff_array
FIR/COR only
Circular buffer operation only R5 Circular buffer length, -2N Accumulators Pointer An = ACn Point to accumulator, ACr
coeff_array
sample_buf
TAG=1 for 2nd to last sample for Circular buffer operation
PH Accumulators ACr 0-15th bits of y + +
Multiplier
ACr+1 16-31st bits of y ACr+2 32-47th bits of y y[k] = m =0..N h[m]x[k-m]
y=
y=
The value of y is stored in ACr and ACr+1 for FIR instruction (32 bit accumulation). COR instruction uses 48 bit accumulation and includes accumulator ACr+2.
Assembly Language Instructions
IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
Coefficients, h[k] k = 0..N Data memory (FIR/COR) Coefficients, h[k] k = 0..N Past N samples, x[k] MR For COR/CORK ACr+2 ACr+1 ACr For FIR/FIRK ACr+1 ACr 4-67
Special Filter Instructions
Figure 4-7. Filter Instruction and Circular Buffering for N+1 Tap Filter
Rxeven DP Rxeven+1
coeff_array coeff_array
16 Bits h[0] h[1] h[2] h[3] h[4]
CORK/FIRK only COR/FIR only Rxeven 17th Bit x x x x x 0 0 0 0 0 0 0 0 STAT TAG 16 Bits
17th Bit
if TAG = 1 16 Bits
+
R5 = -2(N+1)
17th Bit
coeff_array
0 0 0 0 0 0 0 0 0 0 0
x[k] x[k-1] x[k-2] x[k-3] x[k-4]
h[N-1] h[N]
x x
1 0
x[k-N] x[k+1] sample_buf
x[k-N-1] is replaced by x[k+1]
coeff_array is stored in program or data memory based on filter instruction.
program memory (FIRK/CORK) data memory (FIR/COR) + y = k =0..N h[m] x x[k-m] 48-bit accumulation for COR/CORK y AC n+2 AC n+1 AC n
32-bit accumulation for FIR/FIRK
4-68
Conditionals
4.12 Conditionals
The condition bits in the status register (STAT) are used to modify program control through conditional branches and calls. Various combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register.
'NOT' 'NOT' condition condition alternate mnemonic mnemonic NZF NSF NCF NAE NBE NLE NB NA NG NE NOF NGE NL RNCF RNBE RZ RNA RNE NTF1 NTF2 NTAG NIN1 NIN2 XNZF XNSF XNLE XNG XLE RBE RNZ GE AE BE LE
STAT register bit settings ZF = 1 SF = 1 CF = 1 ZF = 0 & CF = 0 ZF = 0 & CF = 1 ZF = 1 & SF = 0 ZF = 1 & OF = 0 OF = 1 ZF = 0 & SF = 1 RCF = 1 RZF = 0 & RCF = 1 RZF = 1 TF1 = 1 TF2 = 1 TAG = 1 IN1 IN2 XZF = 1 XSF = 1 XZF = 0 & XSF = 0
Arithmetic/Logic Condition Zero flag Sign flag Carry flag Below (unsigned) Above (unsigned) Greater (signed) Equal Overflow flag Less (signed) Rx carry flag Rx above (unsigned) Rx equal Test flag 1 Test flag 2 Memory tag Input line 1 Input line 2 Transfer zero flag Transfer sign flag Transfer greater (signed)
Condition Alternate mnemonic mnemonic ZF SF CF B A G E OF L RCF RA RE TF1 TF2 TAG IN1 IN2 XZF XSF XG
Alternate mnemonics are provided to help program readability. They generate the same opcodes as the associated condition. Status Register (STAT) bit settings are inverted for NOT conditions. Hardware lines used for I/O expansion design. These lines are PA0 and PA1.
Assembly Language Instructions
4-69
Legend
4.13 Legend
All instructions of the MSP50P614/MSP50C614 use the following syntax:
name [dest] [, src] [, src1] [, mod]
name Name of the instruction. Instruction names are shown in bold letter through out the text. dest src src1 mod
Destination of the data to be stored after the execution of the instruction. Optional for some instructions or not used. Destination is also used as both source and destination for some instructions. Source of the first data. Optional for some instructions or not used. Source of the second data. Some instructions use a second data source. Optional for some instructions or not used. Post modification of a register. This can be either next A or Rmod and will be specified in the instruction.
The following table describes the meanings of the symbols used in the instruction set descriptions: Bold type means it must be typed exactly as shown. italics type means it is a variable. [ ] square brackets enclose optional arguments. Operands
0 dma6 63 0 dma16 65535 0 imm5 31 0 imm16 65535 0 offset6 63 0 offset7 127 0 offset16 65535 0 pma8 255 0 pma16 65535 0 port4 15 0 port6 63 Symbol ! An An~ Meaning Invert the bit of the source. Used with flag addressing only. Accumulator selector where n = 0...3. An is the accumulator pointed by APn. Offset accumulator selector where n = 0...3. An is the accumulator pointed by APn+16; APn wraps after 31. pma16 32767 for MSP50P614/MSP50C614 dma16 639 for MSP50P614/MSP50C614
4-70
Legend
Symbol A~ ~A A~ ~A~ An[~] APn adrs {adrs}n
Meaning Select offset accumulator as the source if this bit is 1. Used in opcode encoding only. Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encoding only. Select offset accumulator as the source if this bit is 0. Used in opcode encoding only. Can be either ~A or A~ based on opcode (or instruction). Used in Opcode encoding only. Can be either An or An~ where n = 0...3 Accumulator Pointer register where n = 0..3. Low-order 5 bits select one of 32 accumulators. Addressing mode bits am, Rx, pm. See Table 4-46.
Addressing mode which must be provided. It should be of the format shown in Table 4-46. The curly braces { } are not included in the actual instruction. The subscript n represents the data size (in bits) the instruction will use. For example, {adrs}8 means that the instruction will use 8 bit data from the addressed memory and the upper bits may not be used. If n is not provided, data width is 16 bits.
Condition code bits used with conditional branch/calls and test flag/bit instructions. Conditional code mnemonic used with conditional branch/calls and test flag/bit instructions. Curly braces indicates this field is not optional. Carry flag Total clock cycles per instruction
cc
{cc} CF
clk dma[n]
DP flagadrs
n bit data memory address. For example, dma8 means 8-bit location data memory address. If n is not specified, defaults to dma16.
Data pointer register, 16 bits Flag addressing syntax as shown in Table 4-47. Test flag bit. Used in opcode encoding only. Flag addressing syntax as shown in Table 4-48. Fractional mode Global/relative flag bit for flag addressing. Interrupt enable mode
flg
{flagadrs} FM
g/r
IM
imm[n] k0...kn
MR next A
n bit immediate value. If n is not specified, defaults to imm16.
Constant field bits. Multiply register, 16 bits Accumulator pointer premodification. See Table 4-45. Not condition on conditional jumps, conditional calls or test flag instructions. Not repeatable or not recommended
Not
N/R
Assembly Language Instructions
4-71
Legend
Symbol nR ns OF
Meaning Value in repeat counter loaded by RPT instructions Value in string register STR Overflow flag
offset[n]
OM PC
n bit offset from a reference register.
Overflow mode Program counter, 16 bits
pma[n] port[n]
PH PL
n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16. n bit I/O port address. Certain instructions multiply this port address by 4.
Product high register, 16 bits Product low register, 16 bits (cannot be read/written directly) Rx register treated as a general purpose register. This bit is not related to any addressing mode. Register carry flag Indirect register x where x = 0..7 Register zero flag Represents string mode if 1, otherwise normal mode. Sign flag Status register, 17 bits String register, 8 bits Shift value register, 4 bits Memory tag Test flag 1 Test flag 2 Top of stack register, 16 bits Unsigned mode Word(s) taken by instruction Don't care Extended sign mode Transfer (TX) sign flag Transfer (TX) zero flag Zero flag
R
RCF Rx RZF
s
SF STAT STR SV TAG TF1 TF2 TOS UM
w
x XM XSF XZF ZF
4-72
Legend
Table 4-45. Auto Increment and Decrement
Operation No modification Auto increment Auto Decrement ++A - -A
next A
b9 0 0 1
b8 0 1 0
Table 4-46. Addressing Mode Bits and adrs Field Description
String Repeat Operation Clocks nR+4 nR+2 nR+2 nR+4 Addressing Mode Encoding {adrs} 7 6 5 4 3 2 1 0
Relative Addressing Modes Direct Short relative Relative to R5 Long relative
Clocks
Words
clk
2 1 1 2
w
2 1 1 2
am
*dma16 *R6 + offset7 *Rx + R5 *Rx + offset16 *Rx *Rx++ 0 1 0 0 1 0 0 1 0 0
Rx (x = 0 ... 7) x
pm
0 0
offset7
Rx Rx 0 0 0 0 0 0 0 1 0 1
Indirect
1
1
nR+2
*Rx- - *Rx++R5
0
1
1
Rx
1 1
Replace nR with nS for string operation. Note:
dma16 and offset16 is the second word.
Table 4-47. Flag Addressing Syntax and BIts
{flagadrs} Flag Addressing Modes Global Relative Clocks Words Repeat Operation Syntax flag addressing mode encoding, flagadrs 6 5 4 3 2 1 0
clk
1 1
w
1 1
clk
nR+2 nR+2 *dma6 *R6+offset6
flag address bits dma6 offset6
g/r
0 1
nR is RPT instruction argument
Assembly Language Instructions
4-73
Individual Instruction Descriptions
4.14 Individual Instruction Descriptions
In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions. Each instruction is discussed in detail and provides the following information:
-
Assembler syntax Clock cycles required with or without repeat instructions Words required Limitation and restrictions Execution Affected flags Opcode Description Recommendation to other related instructions (See Also field) Examples
4-74
Individual Instruction Descriptions
4.14.1 ADD
Syntax
[label] name ADD ADD ADD ADD ADD ADD ADD
Add word
dest, src [, src1] [,mod]
An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5 APn, imm5
Clock, clk Table 4-46 2 1 1 2 1 1
Words, w Table 4-46 2 1 1 2 1 1
With RPT, clk Table 4-46 N/R nR+3 nR+3 N/R nR+3 N/R
Class 1a 2b 3 3 4c 4d 9c
Does not affect the status flags.
Execution
[premodify AP if mod specified] dest dest + src (for two operands) dest src + src1 (for three operands) PC PC + w
Flags Affected
dest is An: dest is Rx: src1 is {adrs}:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly TAG is set accordingly
Opcode
Instructions ADD An[~], An, {adrs} [, next A] 16 0 x ADD An[~], An[~], imm16 [, next A] 1 x ADD An[~], An[~], PH [, next A] ADD An[~], An~, An [, next A] ADD Rx, imm16 1 1 1 x ADD Rx, R5 ADD APn, imm5 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 15 0 14 0 13 0 12 ~A 11 10 9 An 8 7 6 5 4 3 2 1 0
next A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
0
0
0
0
0
1
A~
~A
imm16 next A next A
1 1 0 An An 0 0 0 0 1 0 0 1 1 0 0 0 1 1 Rx 0 0 A~ A~ 0 ~A ~A 0
imm16
0 1 0 0 1 0 0 Rx 0 0
APn
imm5
Assembly Language Instructions
4-75
Individual Instruction Descriptions
Description
Syntax ADD dest, src ADD dest, src, src1 [,mod] Description ADD src with dest and store the result to dest. ADD src1 with src and store the result to dest. Premodify the mod before execution. (if provided)
See Also
ADDB, ADDS, SUB, SUBB, SUBS
Example 4.14.1.1 ADD A2, A2~, *R2++R5, --A Decrement accumulator pointer AP2. Add word at address in R2 to A2~, put result in A2. Add value in R5 to R2 and store in R2. Example 4.14.1.2 ADD A1, A1, 0x1221 Add immediate value of 0x1221 to A1 and store result in A1. Example 4.14.1.3 ADD A0, A0~, PH Add PH to accumulator A0~ and store result in accumulator A0. Example 4.14.1.4 ADD A1, A1~, A1 Add accumulator A1 to accumulator A1~, put result in accumulator A1. Example 4.14.1.5 ADD R3, 0x1000 Add 0x1000 to register R3 store result in R3. Example 4.14.1.6 ADD R2, R5 Add R2 to R5, store result in R2. Example 4.14.1.7 ADD AP3, 0x10 Add immediate 0x10 to accumulator pointer AP3, store result in accumulator pointer AP3.
4-76
Individual Instruction Descriptions
4.14.2 ADDB
Syntax
[label]
ADD BYTE
name
ADDB ADDB
dest, src
An, imm8 Rx, imm8
Clock, clk 1 1
Words, w 1 1
With RPT, clk N/R N/R
Class 2a 4b
Execution
dest dest + src PC PC + 1 dest is An: dest is Rx:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly
Flags Affected
Opcode
Instructions ADDB An imm5 ADD Rx, imm8 16 1 1 15 0 0 14 1 1 13 0 1 12 0 0 11 0 0 10 0 9 An 8 7 6 5 4 3 2 1 0
imm8 k7 k6 k5
Rx
k4
k3
k2
k1
k0
See Also Description
ADD, ADDS, SUB, SUBB, SUBS Add immediate value of unsigned src byte to value stored in dest register and store result in the same dest register.
Example 4.14.2.1 ADDB A2, 0x45 Add immediate 0x45 to A2. Example 4.14.2.2 ADDB R5, 0xf2 Add immediate 0xf2 to R5.
Assembly Language Instructions
4-77
Individual Instruction Descriptions
4.14.3 ADDS
Syntax
[label]
Add String
name
ADDS ADDS ADDS ADDS
dest, src, src1
An[~], An, {adrs} An[~], An[~], pma16 An[~], An~, An An[~], An[~], PH
Clock, clk Table 4-46 nS+4 nS+2 1
Words, w Table 4-46 2 1 1
With RPT, clk Table 4-46 N/R nR+2 1
Class 1a 2b 3 3
This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string. This instruction should immediately follow one of the following class 1b instructions: MOVAPH, MULAPL, MULSPL, SHLTPL, SHLSPL, and SHLAPL. An interrupt should not occur between one of these instructions and ADDS. An interrupt may cause incorrect results. Interrupts must be explicitly disabled at least one instruction before the class 1b instruction. This special sequence is protected inside a BEGLOOP - ENDLOOP construct. In addition, single stepping is not allowed for this instruction. An in this instruction should be the same as An in one of the listed class 1b instruction. Offsets are allowed. See Section 4.8 for more detail.
Execution Flags Affected Opcode
Instructions
dest string src string + src1 string PC PC + w dest is An: src1 is {adrs}:
OF, SF, ZF, CF are set accordingly TAG is set accordingly
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDS An[~], An, {adrs}
0 x
0
0
0
~A
1
1
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 0 0 0 0 0 1 A~ ~A
ADDS An[~], An[~], pma16
1 x
pma16 1 1 1 1 0 0 0 0 1 1 1 1 An An 0 0 0 1 1 1 0 0 1 1 0 0 A~ A~ ~A ~A
ADDS An[~], An~, An ADDS An[~], An[~], PH
1 1
Description See Also
Add value of src string to the value of src1 string and store resulting string in dest. String length minus two should be stored in STR before execution. ADD, ADDB, SUB, SUBB, SUBS
Example 4.14.3.1 ADDS A0, A0~, *R2 Add data memory string beginning at address in R2 to accumulator string A0~, put result in accumulator string A0. Example 4.14.3.2 ADDS A0, A0~, 0x1400 Add program memory string beginning at address 0x1400 to accumulator string A0~, put result in accumulator string A0.
4-78
Individual Instruction Descriptions
Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1~, put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0. Note that MULAPL and ADDS constitute a special sequence. When this sequence occurs, interrupts are NOT disabled, so interrupts should be disabled for correct operation. In extended sign mode, if A0 is AC0 = 0x0000, A0~ is AC16=0xFFFF and MR=0xFF, after execution AC0=0xFF01, AC1=0xFFFF.
Assembly Language Instructions
4-79
Individual Instruction Descriptions
4.14.4 AND
Syntax
[label]
Bitwise AND
name dest, src [, src1] [, mod]
AND AND AND AND AND An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, [!]{flagadrs} TFn, {cc} [, Rx]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3 8a 8b
Table 4-46 2 1 1 1 2 1 1 1
N/R nR+3 N/R nR+3
Execution
[premodify AP if mod specified] dest dest AND src (for two operands) dest src AND src1 (for three operands) PC PC + w
Flags Affected
dest is An: dest is TFn: src is {adrs}: src is {flagadrs}:
OF, SF, ZF, CF are set accordingly TFn bits in STAT register are set accordingly TAG bit is set accordingly TAG bit is set accordingly
Opcode
Instructions AND An, {adrs} 16 0 x AND An[~], An[~], imm16 [, next A] 1 x AND An[~], An~, An [, next A] AND TFn, {flagadrs} AND TFn, {cc} [, Rx] 1 1 1 1 0 0 1 0 0 0 1 1 0 1 0 1 1 15 1 14 0 13 0 12 0 11 1 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
1
0
1
0
0
1
A~
~A
imm16 next A flg flg Not Not
1 An 0 0 0 1 0 1 0 0 A~ ~A
flagadrs
Rx 1 0
cc
Description
Syntax AND dest, src, src1 [, mod] AND dest, src AND TFn, {flagadrs} AND TFn, {cc} [, Rx] Description Bitwise AND src1 and src and store result in dest. Premodification of accumulator pointers are allowed with some operand types. Bitwise AND dest and src and store result in dest. AND TFn bit with 17th bit of data memory address referred by addressing mode {flagadrs}, store result in TFn bit in STAT register. n is either 1 or 2. AND test condition {cc} with TFn bit in STAT register. Rx must be provided if cc is one of {RZP, RNZP, RLZP, RNLZP} to check if the selected Rx is zero or negative. Rx should not be provided for other conditionals. n is 1 or 2.
4-80
Individual Instruction Descriptions
See Also
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS
Example 4.14.4.1 AND A3, *R4-- - And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation. Example 4.14.4.2 AND A0~, A0, 0xff0f, - -A Predecrement accumulator pointer AP0. And immediate value 0xff0f to register accumulator A0, store result in accumulator A0~. Example 4.14.4.3 AND TF2, *0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT. Store result in the TF2 bit in the STAT register. Note that {flagadrs} cannot exceed values greater than *0x003F. Example 4.14.4.4 AND TF1, TF2 AND TF1 with TF2 bit in the STAT register and store result in TF1.
Assembly Language Instructions
4-81
Individual Instruction Descriptions
4.14.5 ANDB
Syntax
[label] name
ANDB
Bitwise AND Byte
dest, src
An, imm8
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 2a
Execution
dest dest AND src byte PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions ANDB An, imm8
16 1
15 0
14 1
13 0
12 1
11 0
10 1
9 An
8
7
6
5
4
3
2
1
0
imm8
Description See Also
Bitwise AND src byte and byte stored in dest register and store result in dest register.
AND, ANDS, OR, ORB, ORS, XOR, XORB, XORS
Example 4.14.5.1 ANDB A2, 0x45 AND immediate value 0x45 to A2 (byte mode). Store result in A2. Upper 8 bits of A2 will be ANDed with zeros.
4-82
Individual Instruction Descriptions
4.14.6 ANDS
Syntax
[label] name
ANDS ANDS ANDS
Bitwise AND String
dest, src [, src1]
An, {adrs} An[~], An[~], pma16 An[~], An~, An
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3
Table 4-46 nR+4 nR+3 1 1
N/R nR+3
Execution
dest string dest string AND src string dest string src string AND src1 string PC PC + w dest is An: src is {adrs}:
(for two operands) (for three operands)
Flags Affected Opcode
Instructions ANDS An, {adrs}
OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
16 0 x
15 1
14 0
13 0
12 0
11 1
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 1 0 1 0 0 1 A~ ~A
ANDS An[~], An[~], pma16
1 x
pma16
1 1 0 0 1 1 An 0 1 0 1 0 0 A~ ~A
ANDS An[~], An~, An
1
Description
Syntax ANDS dest, src ANDS dest, src, src1 Description Bitwise AND of src string and dest string and store result in dest string. Bitwise AND src1 string src string and store result in dest string.
See Also
AND, ANDB, OR, ORB, ORS, XOR, XORB, XORS
Example 4.14.6.1 ANDS A0, *R2 AND data memory string beginning at address in R2 to A0, put result in A0. Example 4.14.6.2 ANDS A0~, A0, 0x1400 AND program memory string beginning at address in 0x1400 to A0, put result in A0~. Example 4.14.6.3 ANDS A0, A0~, A0 AND accumulator string A0 to accumulator string A0~, put result in accumulator string A0. Example 4.14.6.4 ANDS A0, A0~, *R2 AND memory string beginning at address in R2 to A0~, put result in A0.
Assembly Language Instructions
4-83
Individual Instruction Descriptions
4.14.7 BEGLOOP
Syntax
[label] name
BEGLOOP
Begin Loop
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Loop must end with ENDLOOP.
Execution
Save next instruction address (PC + 1) (mask interrupts) PC PC + 1 none
Flags Affected Opcode
Instructions BEGLOOP
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Description
This instruction saves the next sequential address in a shadow register and masks interrupts. Interrupts occurring during execution of this and following instructions are actually queued until the loop is complete (see ENDLOOP). The loop executes N number of times. Thus, N - 2, should be loaded in R4 in order to loop N times.
See Also Example 4.14.7.1
BEGLOOP and ENDLOOP block has following restrictions: No CALL instructions can be used. All maskable interrupts are queued. BEGLOOP/ENDLOOP block cannot be nested.
ENDLOOP MOV R4, count - 2 ;init R4 with loop count BEGLOOP ADD A0, A0~, A0 ;add A0~ to A0 (count) times ENDLOOP
Initialize R4 with the loop count value minus 2 to repeat the loop for count times. Execute the ADD A0, A0~, A0 instruction until R4 is negative. R4 is decremented each time ENDLOOP is encountered. When R4 is negative, ENDLOOP becomes a NOP and execution continues with the next instruction after ENDLOOP.
4-84
Individual Instruction Descriptions
4.14.8 CALL
Syntax
[label] name
CALL CALL
Unconditional Subroutine Call
address pma16
*An
Clock, clk 2 2
Word, w 2 1
With RPT, clk N/R N/R
Class 7c 7c
Execution
*R7 TOS TOS PC + 2 PC pma16 or *An R7 R7 + 2 None
Flags Affected Opcode
Instructions CALL pma16
16 1 x
15 0
14 0
13 0
12 0
11 1
10 0
9 1
8 0
7 1
6 0
5 1
4 0
3 0
2 0
1 0
0 0
pma16
0 0 0 1 1 0 An 0 0 0 0 0 0 0 0
CALL *An
1
Description
PC + w is pushed onto the top of stack (TOS) and the second word operand or accumulator value is loaded into the PC. Call instructions cannot immediately followed by RET instructions. No restrictions apply if IRET is used instead of RET.
Description Unconditional call to specified program memory address pma16. Call to address referenced by An.
Syntax CALL pma16 CALL *An
See Also
Ccc, VCALL, RET, IRET
Example 4.14.8.1 CALL 0x2010 Call unconditionally program memory address 0x2010. Example 4.14.8.2 CALL *A0 Call unconditionally program memory address stored in accumulator A0.
Assembly Language Instructions
4-85
Individual Instruction Descriptions
4.14.9 Ccc
Syntax
[label]
Conditional Subroutine Call
name
Ccc
address pma16
Clock, clk 2
Word, w 2
With RPT, clk N/R
Class 7c
Cannot immediately follow a CALL instruction with a return instruction.
If true [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] CZ CS CC CG CE CA CB CO CRC CRE CL CTF1 CTF2 CTAG CIN1 CIN2 CXZ CXS CXG CRA
If Not true
pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16
[label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label]
CNZ CNS CNC CNG CNE CNA CNB CNO CRNC CRNE CNL CNTF1 CNTF2 CNTAG CNIN1 CNIN2 CXNZ CXNS CXNG CRNA
pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16
Execution
IF (cc = true) *R7 TOS TOS PC + 2 PC pma16 R7 R7 + 2 ELSE NOP PC PC + 2
Flags Affected Opcode
Instructions Ccc pma16
none
16 1 x
15 0
14 0
13 0
12 0
11 1
10
9
8
7
6
5
4 0
3 0
2 0
1 0
0 0
Not
cc pma16
4-86
Individual Instruction Descriptions
Table 4-48. Names for cc
cc names cc cc name
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 XZ XS XG XNZ XNS XNG TF1 TF2 TAG IN1 IN2 NTF1 NTF2 NTAG NIN1 NIN2 Z S C B A G E O RC RA RE RZP RLZP L Description p True condition (Not true condition) Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF0 or CF0) Conditional on ZF=0 and CF=1 (Not condition ZF0 or CF1) Conditional on SF=0 and ZF=0 (Not condition SF0 or ZF0) Conditional if ZF=1 and OF=0 (Not condition ZF1 or OF0) Conditional if OF=1 (Not condition OF=0) Conditional on RCF=1 (Not condition RCF=0) Conditional on RZF=0 and RCF=1 (Not condition RZF0 or RCF1) Conditional on RZF=1 (Not condition RZF=0) Conditional on value of Rx=0 Not available on Calls. (Not condition Rx0) Conditional on MSB of Rx=1. Not available on Calls. (Not condition MSB of Rx=0) Conditional on ZF=0 and SF=1 (Not condition ZF0 or SF1) Reserved Reserved Conditional on TF1=1 (Not condition TF1=0) Conditional on TF2=1 (Not condition TF2=0) Conditional on TAG=1 (Not condition TAG=0) Conditional on IN1=1 status. (Not condition IN1=0) Conditional on IN2=1 status. (Not condition IN2=0) Unconditional Reserved Reserved Conditional on XZF=1 (Not condition XZF=0) Conditional on XSF=1 (Not condition XSF=0) Conditional on XSF=0 and XZF=0 (Not condition XSF0 or XZF0) Reserved Reserved Reserved Reserved Reserved
Not cc name
NZ NS NC NB NA NG NE NO RNC RNA RNE RNZP RNLZP NL
Assembly Language Instructions
4-87
Individual Instruction Descriptions
Description
If cc condition in Table 4-48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP. A Ccc instruction cannot be followed by a return (RET) instruction. No restriction applies if IRET is used instead of RET.
Alternate Syntax CNBE pma16 CBE pma16 Description Conditional call on above (unsigned) Conditional call on not above (unsigned) Conditional call on below (unsigned) Conditional call on not below (unsigned) Conditional call on CF = 1 Conditional call on CF = 0 Conditional call on equal Conditional call on not equal CNLE pma16 CLE pma16 Conditional call on greater (signed) Conditional call on not greater (signed) Conditional call on IN1 = 1 Conditional call on IN1 = 0 Conditional call on IN2 = 1 Conditional call on IN2 = 0 CNGE pma16 CGE pma16 Conditional call on less (signed) Conditional call on not less (signed) Conditional call on OF = 1 Conditional call on OF = 0 Conditional call on SF = 1 Conditional call on SF = 0 Conditional call on TAG = 1 Conditional call on TAG = 0 Conditional call on TF1 = 1 Conditional call on TF1 = 0 Conditional call on TF2 = 1 Conditional call on TF2 = 0 Conditional call on ZF = 1 Conditional call on ZF = 0 CRNBE pma16 CRBE pma16 Conditional call on Rx above (unsigned) Conditional call on Rx not above (unsigned)
Syntax CA pma16 CNA pma16 CB pma16 CNB pma16 CC pma16 CNC pma16 CE pma16 CNE pma16 CG pma16 CNG pma16 CIN1 pma16 CNIN1 pma16 CIN2 pma16 CNIN2 pma16 CL pma16 CNL pma16 CO pma16 CNO pma16 CS pma16 CNS pma16 CTAG pma16 CNTAG pma16 CTF1 pma16 CNTF1 pma16 CTF2 pma16 CNTF2 pma16 CZ pma16 CNZ pma16 CRA pma16 CRNA pma16
4-88
Individual Instruction Descriptions
Syntax CRC pma16 CRNC pma16 CRE pma16 CRNE pma16 CXG pma16 CXNG pma16 CXS pma16 CXNS pma16
Alternate Syntax
Description Conditional call on RCF = 1 Conditional call on RCF = 0 Conditional call on RZF = 1 (equal) Conditional call on RZF = 0 (not equal) Conditional call on transfer greater (signed) Conditional call on transfer not greater (signed) Conditional call on XSF = 1 Conditional call on XSF = 0
CRZ pma16 CRNZ pma16 CXNLE pma16 CXLE pma16
Alternate mnemonics are provided as a way of improving source code readability. They generate the same opcode as the original mnemonic. For example, CA (call above) tests the same conditions as CNBE (call not below or equal) but may have more meaning in a specific section of code.
See Also
CALL, VCALL, RET, IRET
Example 4.14.9.1 CZ 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the ZF=1 flag in STAT. Example 4.14.9.2 CTF1 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the TF1=1 flag in STAT. Example 4.14.9.3 CRNBE 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the flags RCF=1, RZF=0 in STAT.
Assembly Language Instructions
4-89
Individual Instruction Descriptions
4.14.10 CMP
[label]
Compare Two Words
name src, src1 [, mod]
CMP CMP CMP CMP An, {adrs} An[~], imm16 [, next A] An, An~ [, next A] An~, An [, next A] Clock, clk Word, w With RPT, clk Table 4-46 2 1 2 1 N/R nR+3 N/R nR+3 Class 1b 2b 3 4c 4d
Table 4-46 2 1 2 1
CMP Rx, imm16 CMP Rx, R5
Does not modify An status
Execution
[premodify AP if mod specified] STAT flags set by src - src1 operation PC = PC + w
Flags Affected
src is An: src is Rx: src is {adrs}:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly TAG bit is set accordingly
Opcode
Instructions CMP An, {adrs} 16 0 x CMP An[~], imm16 [, next A] 1 x CMP An, An~ [, next A] CMP An~, An [, next A] CMP Rx, imm16 1 1 1 x CMP Rx, R5 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 15 1 14 0 13 1 12 1 11 0 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
0
1
1
0
0
1
A~
~A
imm16 next A next A
1 1 0 An An 0 1 1 0 0 0 1 0 0 1 0 0 0 0 Rx 0 0 0 1 0 0 0 0
imm16
0 1 1 1 Rx 0 0
Description See Also
Subtract value of src1 from src (i.e., src-src1) and only modify the status flag. Premodification of accumulator pointer is allowed with some operand types. CMPB, CMPS, Jcc, Ccc
Example 4.14.10.1 CMP A0, *R0 Compare value at accumulator A0 and the content of data memory location pointed by R0 and change the STAT flags accordingly. Example 4.14.10.2 CMP A0~, 0x1400, - -A Predecrement accumulator pointer AP0. Compare value at accumulator A0~ to immediate value at 0x1400 and change the STAT flags accordingly.
4-90
Individual Instruction Descriptions
Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly.
Assembly Language Instructions
4-91
Individual Instruction Descriptions
4.14.11 CMPB
Syntax
[label] name
Compare Two Bytes
src, src1
Clock, clk 1 1
Word, w 1 1
With RPT, clk N/R N/R
Class 2a 4b
CMPB An, imm8 CMPB Rx, imm8
Execution
status flags set by src - src1 byte PC PC + 1
Flags Affected
src is An: src is Rx:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly
Opcode
Instructions CMPB An, imm8 CMPB Rx, imm8 16 1 1 15 0 0 14 1 1 13 0 1 12 0 1 11 1 1 10 1 9 An 8 7 6 5 4 3 2 1 0
imm8 k7 k6 k5
Rx
k4
k3
k2
k1
k0
Description
Subtract value of src1 (zero filled in upper 8 bits) from src (i.e., src-src1) and only modify the status flags. Contents of src not changed. CMP, CMPS, Jcc, Ccc
See Also
Example 4.14.11.1 CMPB A0, 0xf3 Compare immediate value 0xf3 to accumulator A0. Example 4.14.11.2 CMPB R3, 0x21 Compare immediate value 0x21 to R3.
4-92
Individual Instruction Descriptions
4.14.12 CMPS
Syntax
[label]
Compare Two Strings
name
src, src1
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3
CMPS An, {adrs} CMPS An[~], pma16 CMPS An, An~ CMPS An~, An
Table 4-46 nS+4 nS+3 2 1
N/R nR+3
Execution
status flags set by (src - src1) string PC PC + w
Flags Affected
src is An: src1 is {adrs}:
OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
Opcode
Instructions CMPB An, {adrs} 16 0 x CMPS An[~], pma16 1 x CMPS An, An~ CMPS An~, An 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 15 1 14 0 13 1 12 1 11 0 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 0 1 1 0 0 1 A~ 0
pma16
An An 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Description
Subtract src1 string from src string and only modify the status flags. Content of accumulators are not changed. CMPB, CMP, Jcc, Ccc
See Also
Example 4.14.12.1 CMPS A0, *R0 Compare string at data memory location pointed by R0 to A0 and change the STAT flags accordingly. Example 4.14.12.2 CMPS A1~, 0x1400 Compare string at program memory location 0x1400 to A1~ and change the STAT flags accordingly. Example 4.14.12.3 CMPS A2, A2~ Compare accumulator string A2 to accumulator string A2~ and change the STAT flags accordingly.
Assembly Language Instructions
4-93
Individual Instruction Descriptions
4.14.13 COR
Syntax
[label]
Correlation Filter Function
name
COR
dest, src
An, *Rx
Clock, clk 3
Word, w 1
With RPT, clk 3(nR+2)
Class 9a
Execution
With RPT N-2: (mask interrupts) RPT counter = N-2 MR = h[0] = first filter coefficient x = sample data pointed by Rxeven h[1] = second filter coefficient pointed by Rxeven+1 y = result stored in three consecutive accumulators (48 bit) pointed by An
{between every accumulation} IF TAG = 1 Rxeven = Rxeven + R5 {for circular buffering} ELSE { if Rx++ is specified in the instruction} Rxeven++ ENDIF PC PC + 1 {final result} y
+
k+0..N-1
h[k] * x[N-1-k]
(Execution is detailed in section 4.11) Flags Affected Opcode
Instructions COR An, *Rx 16 1 15 1 14 1 13 0 12 1 11 0 10 0 9 An 8 7 1 6 1 5 0 4 3 Rx 2 1 1 0 1
none
Description
When used with repeat will execute 16 x 16 multiplication between two indirectly addressed data memory buffers, 48-bit accumulation, and a circular buffer operation. Each tap takes 3 instruction cycles. The selected register Rx must be even. This instruction also uses R(x+1). This instruction must be used with RPT instruction. See section 4.11 for more detail on the setup of coefficents and sample data. During COR execution, interrupts are queued. RPT, CORK, FIR, FIRK
See Also Example 4.14.13.1
RPT 0 COR A0, *R0 Computes the calculation for 2 tap correlation filter with 48 bit accumulation. See section 4.11 for more detail on the setup of coefficents and sample data.
4-94
Individual Instruction Descriptions
4.14.14 CORK
Syntax
[label] name
Correlation Filter Function
dest, src
Clock, clk 3
Word, w 1
With RPT, clk 3(nR+2)
Class 9a
CORK An, *Rx
Execution
With RPT N-2: (mask interrupts) RPT counter = N-2 MR = h[0] = first filter coefficient x = sample data pointed at by Rxeven h[1] = second filter coefficient pointed by DP y = result stored in three consecutive accumulators (48 bit) pointed by An
{between every accumulation} IF TAG = 1 Rxeven = Rxeven + R5 {for circular buffering} ELSE Rxeven++ { if Rx++ is specified in the instruction} ENDIF PC PC + 1 {final result}
y
+
k+0..N-1
h[k] * x[N-1-k]
(Execution is detailed in section 4.11) Flags Affected Opcode
Instructions CORK An, *Rx 16 1 15 1 14 1 13 0 12 1 11 0 10 0 9 An 8 7 1 6 0 5 0 4 3 Rx 2 1 1 0 1
None
Description
When used with repeat will execute 16 * 16 multiplication between data memory and program memory, 48-bit accumulation, and a circular buffer operation. Each tap takes 3 instruction cycles. Selected register Rx must be even. This instruction also uses R(x+1). This instruction must be used with RPT instruction. See section 4.11 for more detail on the setup of coefficents and sample data. During CORK execution, interrupt is queued. RPT, COR, FIR, FIRK
See Also Example 4.14.13.1
RPT 0 CORK A0, *R0 Computes the calculation for 2 tap correlation filter with 48 bit accumulation. See section 4.11 for more detail on the setup of coefficents and sample data.
Assembly Language Instructions
4-95
Individual Instruction Descriptions
4.14.15 ENDLOOP
Syntax
[label] name
ENDLOOP
End Loop
#
[n]
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
If (R4 0) decrement R4 by n (1 or 2) PC first address after BEGLOOP else NOP PC PC + 1 None
Flags Affected Opcode
Instructions ENDLOOP n
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 0
6 0
5 0
4 1
3
2 0
1 0
0
0
n
Description
This instruction marks the end of a loop defined by BEGLOOP. If register R4 is not negative, R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP. If R4 is negative, a NOP instruction is executed and program exits the loop. Interrupts (queued by BEGLOOP) are processed according to their priority. This instruction results in an overhead of one instruction cycle per loop cycle compared to two instruction cycle if branching is used. If ENDLOOP is used without any argument, it assumes n=1. BEGLOOP, INTE See Example 4.14.7.1 in BEGLOOP.
See Also Example 4.14.15.1
4-96
Individual Instruction Descriptions
4.14.16 EXTSGN
Syntax
[label] name
EXTSGN
Sign Extend Word
dest [, mod]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
An[~] [, next A]
Execution
[premodify AP if mod specified] new most significant word of dest STAT.SF PC PC + 1 None
Flags Affected Opcode
Instructions EXTSGN An[~] [, next A]
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 0
6 1
5 1
4 1
3 1
2 0
1 0
0 ~A
next A
Description See Also
Copy accumulator sign flag (SF) to all 16 bits of An[~]. EXTSGNS
Example 4.14.16.1 EXTSGN A0~, ++A Preincrement accumulator pointer AP0. Sign extend the accumulator A0~.
Assembly Language Instructions
4-97
Individual Instruction Descriptions
4.14.17 EXTSGNS
Syntax
[label] name
EXTSGNS
Sign Extend String
dest
Clock, clk nR+3
Word, w 1
With RPT, clk nR+3
Class 3
An[~]
Execution Flags Affected Opcode
Instructions EXTSGNS An[~]
new most significant word of dest STAT.SF PC PC + 1 None
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 0
6 1
5 1
4 1
3 1
2 0
1 0
0 A~
Description
Extend the sign bit (SF) of most significant word an additional 16 bits to the left. The accumulator address is preincremented (internally) causing the sign of the addressed accumulator to be extended into the next accumulator address. This instruction ignores the string count, executing only once, but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string. IMPORTANT: At this stage of documentation, a bug in this instruction causes the processor to stall when an attempt is made to sign extend a string that has all zeros in it. Also, the same interrupt problem on the accumulator pointers exists if the instruction just before is not a string instruction. For customers who need the EXTSGNS function now as it was originally intended for string data, there is a workaround. Unfortunately, it involves the use of two accumulator pointers, the second pointing to the position in the accumulator register file that would correspond to the extended word location. For example, if a string exists in memory with the value Ox943500000000 (3 word string) and the value was to be moved to a accumulator as a 64 bit sign extended value, the following code would have been (without bugs):
MOV AP0, 0 MOVS A0, *R0 EXTSGNS A0 ; R0 POINTS TO VALUE IN MEMORY ; EXTENDS THE SIGN OF ABOVE ADD IN ACC(3)
Since the bug causes the above function to fail, the status of the 2 least significant words is equal to zero. However, the same case will be correctly executed with the desired result with the existing bug:
MOV AP0, 0
4-98
; POINT TO LSW OF ACCUM STRING
Individual Instruction Descriptions
MOV AP1, 3
; Point to loc corresponding to ; extended word in acc
MOVS A0, *R0 EXTSGN A1
; R0 POINTS TO VALUE IN MEMORY ; not string version as above
Alternatively, the following code can do the same thing but requires more code:
MOV AP0, 0 MOV AP1, 3 ; POINT TO LSW OF ACCUM STRING ; Point to loc corresponding to ; extended word in acc ZAC A1 ; INITIALIZE EXTENDED SIGN VALUE as positive
MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY JNS POSITIVE ; branch around negative extension, ; accepting default pos extension NOT A1 ; INVERT EXTENDED SIGN WORD FOR NEG CASE POSITIVE
......
See Also
EXTSGN
Example 4.14.17.1 EXTSGNS A0~ Sign extend accumulator string A0~. See the above IMPORTANT note on the bug in this instruction at the present time.
Assembly Language Instructions
4-99
Individual Instruction Descriptions
4.14.18 FIR
Syntax
[label] name
FIR
FIR Filter Function (Coefficients in RAM)
dest, src
An, *Rx
Clock, clk 2
Word, w 1
With RPT, clk 2(nR+2)
Class 9a
Execution
With RPT N-2: (mask interrupts) RPT counter = N-2 MR = h[0] = first filter coefficient x = sample data pointed at by Rxeven h[1] = second filter coefficient pointed at Rxeven+1 y = result stored in three consecutive accumulators (32 bit) pointed by An
{between every accumulation} IF TAG = 1 Rxeven = Rxeven + R5 {for circular buffering} ELSE { if Rx++ is specified in the instruction} Rxeven++ ENDIF PC PC + 1 {final result}
y
+
k+0..N-1
h[k] * x[N-1-k]
(Execution is detailed in section 4.11) Flags Affected Opcode
Instructions FIR An, *Rx 16 1 15 1 14 1 13 0 12 1 11 0 10 0 9 An 8 7 0 6 1 5 0 4 3 Rx 2 1 1 0 1
None
Description
Finite impulse response (FIR) filter. Execute finite impulse response filter taps using coefficients from data memory and samples from data memory. The instruction specifies two registers, Rx and R(x+1) which sequentially address coefficients and the sample buffer in the two instruction FIR tap sequence. This instruction must be used with RPT instruction. When used with the repeat counter it will execute a 16 x 16 multiplication between two indirect addressed data memory buffers, 32-bit accumulation, and circular buffer operation. Executes in 2 instruction cycles. Selected register Rx must be even. This instruction also uses R(x+1). See section 4.11 for more detail on the setup of coefficients and sample data. During FIR execution, interrupt is queued.
4-100
Individual Instruction Descriptions
See Also Example 4.14.18.1
RPT, FIRK, COR, CORK
RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data.
Assembly Language Instructions
4-101
Individual Instruction Descriptions
4.14.19 FIRK
Syntax
[label] name
FIRK
FIR Filter Function (Coefficients in ROM)
dest, src
An, *Rx
Clock, clk 2
Word, w 1
With RPT, clk 2(nR+2)
Class 9a
Execution
With RPT N-2: (mask interrupts) RPT counter = N-2 MR = h[0] = first filter coefficient x = sample data pointed by Rxeven h[1] = second filter coefficient pointed by DP y = result stored in three consecutive accumulators (32 bit) pointed by An [between every accumulation} IF TAG = 1 Rxeven = Rxeven + R5 {for circular buffering} ELSE Rxeven++ { if Rx++ is specified in the instruction} ENDIF PC PC + 1 {final result} y
+
k+0..N-1
h[k] * x[N-1-k]
(Execution is detailed in section 4.11) Flags Affected Opcode
Instructions FIRK An, *Rx 16 1 15 1 14 1 13 0 12 1 11 0 10 0 9 An 8 7 0 6 0 5 0 4 3 Rx 2 1 1 0 1
None
Description
Finite impluse response (FIR) filter. Execute finite impulse response filter taps using coefficients from program memory and samples from data memory. Address reference for data memory is indirect using specified Rx and address reference for program memory is contained in DP register.
This instruction must be used with RPT instruction. When used with the repeat counter it will execute 16 x 16 multiplication between indirect addressed data memory buffer and program memory (coef), 32-bit accumulation, and circular buffer operation. Each tap executes in 2 cycles. See section 4.11 for more detail on the setup of coefficents and sample data. Selected register Rx must be even. During FIRK execution, interrupts are queued. See Also RPT, FIR, COR, CORK Example 4.14.19.1 RPT 0 FIRK A0, *R0 Computes the calculation for 2 tap FIR filter with 32 bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data.
4-102
Individual Instruction Descriptions
4.14.20 IDLE
Syntax
[label] name
IDLE
Halt Processor
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution Flags Affected Opcode
Instructions IDLE
Stop processor clocks PC PC + 1 None
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 0
6 0
5 1
4 0
3 0
2 0
1 0
0 0
Description
Halts execution of processor. An external interrupt wakes the processor. This instruction is the only instruction to enter one of the three low power modes defined in section 2.11. Low power modes depend on the state of ClkSpdCtrl register bit 8 through bit 10 and the ARM bit in IntGenCtrl register. MOV A0, 0 OUT 0x34, A0 MOV A0, 0x0400 OUT 0x3d, A0 IN A0, 0x38 OR A0, A0, 0x4000 OUT 0x38, A0 IDLE
Example 4.14.20.1
; ; ; ; ; ; ;
Turn off DAC Turn off clock, idle bit = 1 Write in ClkSpdCtrl (write only) Read IntGenCtrl register value Set ARM = 1 Write to IntGenCtrl Go to deep sleep mode
To understand this routine, refer to the Reduced Power Modes table in section 2.11. The bits to be set up to switch to deep sleep mode are as follows: set bits 10 of ClkSpdCtrl (IO address 0x3d) register to 1 and reset bits 8 and 9 of ClkSpdCtrl register to 0 (The PLLM bits are reset to zero in this example which is not a necessary operation). Note that the ClkSpdCtrl register is write only. Set the ARM bit in the IntGenCtrl (I/O address 0x38) register to 1 (program line 2 and 3 above). The last line executes the IDLE instruction which switches the processor to deep sleep mode.
Assembly Language Instructions
4-103
Individual Instruction Descriptions
4.14.21 IN
Syntax
[label] name
IN IN
Input From Port Into Word
dest, src1
{adrs}, port4 An[~], port6
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 6a 6b
Table 4-46 1 1
nR+3
Execution
dest content of port6 or port4 PC PC + w dest is An: dest is {adrs}
OF, SF, ZF, CF are set accordingly XZF, XSF are set accordingly
Flags Affected
Opcode
Instructions IN {adrs}, port4 16 1 x IN An[~], port6 1 1 1 15 1 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0
port4
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 1 1 0 An
port6
~A
Description
Input from I/O port. Words can be input to memory from one of 16 port addresses or one of 48 port addresses. The port4 address is multiplied by 4 to get the actual port address. INS, OUT, OUTS
See Also
Example 4.14.21.1 IN *R0, 0x0c Input data from port address 0x0c * 4 = 0x30 to data memory location pointed by R0. Example 4.14.21.2 IN A2~, 0x3d Input data from port address 0x3d to accumulator A2~.
4-104
Individual Instruction Descriptions
4.14.22 INS
Syntax
[label] name
INS
Input From Port Into String
src, src1
An[~], port6
Clock, clk nS+2
Word, w 1
With RPT, clk nR+2
Class 6b
Execution
dest content of port6 PC PC + 1 dest is An:
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions INS An[~], port6
16 1
15 1
14 1
13 0
12 1
11 1
10 1
9 An
8
7
6
5
4
3
2
1 0
0 ~A
port6
Description
Input string from same port, port6, to accumulator string. Strings can be input to accumulators from one of 64 port addresses. In this instruction, port6 is sampled nS+2 times. The first sample is stored in the lowest order accumulator of the string and the last sample is stored in the highest order accumulator of the string. IN, OUT, OUTS
See Also
Example 4.14.22.1 INS A2, 0 Input string starting from port 0 to accumulator string.
Assembly Language Instructions
4-105
Individual Instruction Descriptions
4.14.23 INTD
Syntax
[label] name
INTD
Interrupt Disable
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.IM 0 PC PC + 1 None
(IM is STAT bit 4)
Flags Affected Opcode
Instructions INTD
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 0
5 0
4 1
3 0
2 0
1 0
0 0
Description See Also
Disables interrupts. Resets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 0. INTE, IRET
Example 4.14.23.1 INTD Disable interrupts. INTD must be always be immediately followed by a NOP. Any maskable interrupt occurring after the INTD - NOP sequence will not be serviced.
4-106
Individual Instruction Descriptions
4.14.24 INTE
Syntax
[label] name
INTE
Interrupt Enable
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution Flags Affected Opcode
Instructions INTE
STAT.IM 1 PC PC + 1 None
(IM is STAT bit 4)
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Description See Also
Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 1. INTD, IRET
Example 4.1 INTE Enables interrupts. Any maskable interrupts occurring after this instruction is serviced.
Assembly Language Instructions
4-107
Individual Instruction Descriptions
4.14.25 IRET
Syntax
[label] name
IRET
Return From Interrupt
Clock, clk 2
Word, w 1
With RPT, clk N/R
Class 5
Execution
PC TOS R7 R7 - 2 TOS *R7 None
Flags Affected Opcode
Instructions IRET
16 1
15 1
14 0
13 1
12 1
11 1
10 1
9 0
8 1
7 0
6 1
5 1
4 1
3 1
2 1
1 1
0 0
See Also Description
RET, CALL, Ccc, INTE, INTD Return from interrupt. Pop top of stack to program counter.
Example 4.1 IRET Return from interrupt service routine. If used in a called subroutine, return from subroutine.
4-108
Individual Instruction Descriptions
4.14.26 Jcc
Syntax
[label] name
Jcc
Conditional Jumps
pma16 [, Rmod] pma16 [, Rmod]
Clock, clk 2 Word, w 2 With RPT, clk N/R Class 7b
If true [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] Rmod
JZ JS JC JG JE JA JB JO JRC JRE JL JTF1 JTF2 JTAG JIN1 JIN2 JXZ JXS JXG JRA JRZP JRLZP Rx++ Rx-- Rx++R5
If Not true pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label]
JNZ JNS JC JNG JNE JNA JNB JNO JRNC JRNE JNL JNTF1 JNTF2 JNTAG JNIN1 JNIN2 JXNZ JXNS JXNG JRNA JRNZP JRNLZP
pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod] pma16 [, Rmod]
Execution
IF (condition = true OR unconditional) PC pma16 ELSE NOP PC PC + 2 [if post modification specified] IF (Rmod = Rx++) Rx = Rx + 2 ELSE IF (Rmod = Rx--) Rx = Rx - 2 ELSE IF (Rmod = Rx++R5) Rx = Rx +R5 RCF and RZF affected by post-modification of Rx.
Flags Affected
Assembly Language Instructions
4-109
Individual Instruction Descriptions
Opcode
Instructions Jcc pma16 Jcc pma16, Rx++ Jcc pma16, Rx-- Jcc pma16, Rx++R5 16 1 x 1 x 1 x 1 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 0 11 0 10 9 8 7 6 5 4 0 3 0 Rx Rx Rx 2 0 1 0 0 1 1 0 0 1 0 1
Not Not Not Not
cc pma16 cc pma16 cc pma16 cc pma16
cc names cc
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XZ XS XG XNZ XNS XNG TF1 TF2 TAG IN1 IN2 NTF1 NTF2 NTAG NIN1 NIN2 cc name Z S C B A G E O RC RA RE RZP RLZP L Not cc name NZ NS NC NB NA NG NE NO RNC RNA RNE RNZP RNLZP NL
Description True condition (Not true condition) Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF0 or CF0) Conditional on ZF=0 and CF=1 (Not condition ZF0 or CF1) Conditional on SF=0 and ZF=0 (Not condition SF0 or ZF0) Conditional if ZF=1 and OF=0 (Not condition ZF1 or OF0) Conditional if OF=1 (Not condition OF=0) Conditional on RCF=1 (Not condition RCF=0) Conditional on RZF=0 and RCF=1 (Not condition RZF0 or RCF1) Conditional on RZF=1 (Not condition RZF=0) Conditional on value of Rx=0 (Not condition Rx0) Conditional on MSB of Rx=1. (Not condition MSB of Rx=0) Conditional on ZF=0 and SF=1 (Not condition ZF0 or SF1) reserved reserved Conditional on TF1=1 (Not condition TF1=0) Conditional on TF2=1 (Not condition TF2=0) Conditional on TAG=1 (Not condition TAG=0) Conditional on IN1=1 status. (Not condition IN1=0) Conditional on IN2=1 status. (Not condition IN2=0) Unconditional reserved reserved Conditional on XZF=1 (Not condition XZF=0) Conditional on XSF=1 (Not condition XSF=0) Conditional on XSF=0 and XZF=0 (Not condition XSF0 or XZF0) reserved
4-110
Individual Instruction Descriptions
cc names cc
1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 cc name Not cc name reserved reserved reserved reserved
Description True condition (Not true condition)
Description
PC is replaced with second word operand if condition is true (or unconditional). If test condition is false, a NOP is executed.
Alternate Instruction JNBE JBE JNAE JAE Description Conditional jump on above (unsigned) Conditional jump on not above (unsigned) Conditional jump on below (unsigned) Conditional jump on not below (unsigned) Conditional jump on CF = 1 Conditional jump on CF = 0 Conditional jump on equal Conditional jump on not equal JNLE JLE Conditional jump on greater (signed) Conditional jump on not greater (signed) Conditional jump on port D pin PD0=1 Conditional jump on port D pin PD0=0 Conditional jump on port D pin PD1=1 Conditional jump on port D pin PD1=0 JNGE JGE Conditional jump on less than(signed) Conditional jump on not less than (signed) Conditional jump on OF = 1 Conditional jump on OF = 0 Conditional jump on Rx above (unsigned) JRBE Conditional jump on Rx not above (unsigned) Conditional jump on XCF = 1 Conditional jump on XCF = 0 JRZ JRNZ Conditional jump on XZF = 1 (equal) Conditional jump on XZF = 0 (not equal) Conditional jump on Rx not below or equal (unsigned) Conditional jump on Rx < 0 after post-mod
Syntax JA pma16 [, Rmod] JNA pma16 [, Rmod] JB pma16 [, Rmod] JNB pma16 [, Rmod] JC pma16 [, Rmod] JNC pma16 [, Rmod] JE pma16 [, Rmod] JNE pma16 [, Rmod] JG pma16 [, Rmod] JNG pma16 [, Rmod] JIN1 pma16 [, Rmod] JNIN1 pma16 [, Rmod] JIN2 pma16 [, Rmod] JNIN2 pma16 [, Rmod] JL pma16 [, Rmod] JNL pma16 [, Rmod] JO pma16 [, Rmod] JNO pma16 [, Rmod] JRA pma16 [, Rmod] JRNA pma16 [, Rmod] JRC pma16 [, Rmod] JRNC pma16 [, Rmod] JRE pma16 [, Rmod] JRNE pma16 [, Rmod] JRNBE pma16 [, Rmod] JRLZP pma16 [, Rmod]
Assembly Language Instructions
4-111
Individual Instruction Descriptions
Syntax JRNLZP pma16 [, Rmod] JRZP pma16 [, Rmod] JRNZP pma16 [, Rmod] JS pma16 [, Rmod] JNS pma16 [, Rmod] JTAG pma16 [, Rmod] JNTAG pma16 [, Rmod] JTF1 pma16 [, Rmod] JNTF1 pma16 [, Rmod] JTF2 pma16 [, Rmod] JNTF2 pma16 [, Rmod] JXG pma16 [, Rmod] JXNG pma16 [, Rmod] JXS pma16 [, Rmod] JXNS pma16 [, Rmod] JXZ pma16 [, Rmod] JXNZ pma16 [, Rmod] JZ pma16 [, Rmod] JNZ pma16 [, Rmod]
Alternate Instruction
Description Conditional jump on Rx 0 after post-mod Conditional jump on Rx = 0 after post-mod Conditional jump on Rx 0 after post-mod Conditional jump on SF = 1 Conditional jump on SF = 0 Conditional jump on TAG = 1 Conditional jump on TAG = 0 Conditional jump on TF1 = 1 Conditional jump on TF1 = 0 Conditional jump on TF2 = 1 Conditional jump on TF2 = 0 Conditional jump on transfer greater (signed) Conditional jump on transfer not greater (signed) Conditional jump on transfer SF = 1 Conditional jump on transfer SF = 0 Conditional jump on transfer ZF = 1 (zero) Conditional jump on transfer ZF = 0 (not equal) Conditional jump on ZF = 1 Conditional jump on ZF = 0
JXNLE JXLE
Alternate mnemonics are provided as a way of improving source code readability. They generate the same opcode as the original mnemonic. For example, JA (jump above) tests the same conditions as JNBE (jump not below or equal) but may have more meaning in a specific section of code.
See Also
JMP, CALL, Ccc
Example 4.14.27.1 JNZ 0x2010 Jump to program memory location 0x2010 if the result is not zero. Example 4.14.27.2 JE 0x2010, R3++R5 Jump to program memory location 0x2010 if flag RZF = 1. Increment R3 by R5. Since this jump instruction does not have a P at the end, post-modification is NOT reflected in the STAT register. Thus, if R3 becomes zero, RZF is not updated. Example 4.14.27.3 JIN1 0x2010, R1-- Jump to program memory location 0x2010 if I/O port address PD0 pin has a value of 1. Decrement R1 by 2. Example 4.14.27.4 JTAG 0x2010, R2++ Jump to program memory location 0x2010 if TAG bit of STAT is zero. Increment R2 by 2.
4-112
Individual Instruction Descriptions
4.14.27 JMP
Syntax
[label] name
JMP JMP JMP JMP JMP
Unconditional Jump
dest [, mod] pma16 pma16, Rx++ pma16, Rx- - pma16, Rx++R5
*An
Clock, clk 2 2 2 2 2
Word, w 2 2 2 2 1
With RPT, clk N/R N/R N/R N/R N/R
Class 7b 7b 7b 7b 7b
Execution Flags Affected Opcode
Instructions JMP pma16
PC dest [Post-modify Rx if specified] RCF and RZF affected by post-modification of Rx
16 1 x
15 0
14 0
13 0
12 0
11 1
10 0
9 1
8 0
7 1
6 0
5 1
4 0
3 0
2 0
1 0
0 0
pma16
0 0 0 0 0 0 1 0 1 0 1 Rx 0 1
JMP pma16, Rx++
1 x
pma16
0 0 0 0 0 0 1 0 1 0 1 Rx 1 0
JMP pma16, Rx--
1 x
pma16
0 0 0 0 0 0 1 0 1 0 1 Rx 1 1
JMP pma16, Rx++R5
1 x
pma16
0 0 0 1 0 0 An 0 0 0 0 0 0 0 0
JMP *An
1
Description
Instruction JMP pma16[, mod] JMP *An Operation PC is replaced with second word operand. Post modification of Rx register is done if specified. PC is replaced with content of accumulator An.
See Also
Jcc, CALL, Ccc
Example 4.14.26.1 JMP 0x2010, R2-- Jump unconditionally to program memory location 0x2010. Decrement R2 by 2. Example 4.14.26.2 JMP *A3 Jump unconditionally to program memory location stored in accumulator A3.
Assembly Language Instructions
4-113
Individual Instruction Descriptions
4.14.28 MOV
Syntax
[label]
Move Data Word From Source to Destination
name dest, src, [, next A]
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV {adrs}, An[~] [, next A] An[~], {adrs} [, next A] {adrs}, *An An[~], imm16 [, next A] MR, imm16 [, next A] An, An~ [, next A] An[~], PH [, next A] SV, An[~] [, next A] PH, An[~] [, next A] An[~], *An[~] [, next A] MR, An[~] [, next A] {adrs}, Rx Rx, {adrs} Rx, imm16 Rx, R5 SV, {adrs}4 PH, {adrs} MR, {adrs} APn, {adrs} STAT, {adrs} TOS, {adrs} {adrs}, PH {adrs}, MR {adrs}, STAT {adrs}, STR {adrs}, DP {adrs}, SV {adrs}, APn {adrs}, TOS STR, {adrs}8 {flagadrs}, TFn TFn, {flagadrs}
Clock, clk
Word, w
With RPT, clk Table 4-46 Table 4-46 Table 4-46
Class 1a 1a 1b 2b 2b 3 3 3 3 3 3 4a 4a 4c 4d 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 8a 8a
Table 4-46 Table 4-46 Table 4-46 2 2 1 1 1 1 1 1 Table 4-46 Table 4-46 2 1 1 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 1 1 1 1 2 1 1 2 2 1 1 1 1 1 1
N/R N/R nR+3 nR+3 nR+3 nR+3 nR+3 nR+3 Table 4-46 Table 4-46 N/R nR+3 nR+3 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 nR+3 nR+3
4-114
Individual Instruction Descriptions
[label]
name dest, src, [, next A]
MOV MOV MOV MOV TFn, {cc} [, Rx] STR, imm8 SV, imm4 APn, imm5
Clock, clk 1 1 1 1
Word, w 1 1 1 1
With RPT, clk N/R N/R N/R N/R
Class 8b 9b 9b 9c
Execution
[premodify AP if mod specified] dest src PC PC + w
Flags Affected
dest is An: dest is Rx: dest is {adrs}: src is {adrs} src is {flagadrs}
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly XSF, XZF are set accordingly TAG bit is set accordingly TAG bit is set accordingly
Opcode
Instructions MOV {adrs}, An[~] [, next A] 16 0 x MOV An[~], {adrs} [, next A] 0 x MOV {adrs}, *An 0 x MOV An[~], imm16 [, next A] 1 x MOV MR, imm16 [, next A] 1 x MOV An, An~ [, next A] MOV An[~], PH [, next A] MOV SV, An[~] [, next A] MOV PH, An[~] [, next A] MOV An[~], *An[~] [, next A] MOV MR, An[~] [, next A] MOV {adrs}, Rx 1 1 1 1 1 1 1 x MOV Rx, {adrs} 1 x MOV Rx, imm16 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 next A next A next A An An An An An An Rx 1 1 0 0 next A An 1 1 1 0 0 1 15 0 14 1 13 1 12 A~ 11 10 9 An 8 7 6 5 4 3 2 1 0
next A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 A~ next A An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 0 An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 next A An 0 0 1 0 0 1 0 ~A
imm16
1 1 1 0 0 1 0 0
imm16
0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 A~ A~ A~ A~ A~ A~ ~A ~A 0 0 ~A 0
next A next A next A
0
{adrs}
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 Rx {adrs}
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 1 0 Rx 0 0
imm16
Assembly Language Instructions
4-115
Individual Instruction Descriptions
Instructions MOV Rx, R5 MOV SV, imm4 MOV SV, {adrs}4 MOV PH, {adrs}
16 1 1 1 x 1 x
15 1 1 1
14 1 1 0
13 1 1 1
12 1 1 1
11 1 1 0
10 1 0 0
9 0 1 0
8 0 0 0
7 1 0
6 1 0
5 0 0
4
3 Rx
2
1 0
0 0
0
imm4 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 0 0 1
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 0 0 0
MOV MR, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 1 APn
MOV APn, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 1 1 1
MOV STAT, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 0 1 0
MOV TOS, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 0 1
MOV {adrs}, PH
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 0 0
MOV {adrs}, MR
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 1 0
MOV {adrs}, STAT
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 1 1
MOV {adrs}, STR
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 1 0
MOV {adrs}, DP
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 0 0
MOV {adrs}, SV
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 1 An
MOV {adrs}, APn
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 1 1
MOV {adrs}, TOS
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 0 1 1
MOV STR, {adrs}8 MOV {flagadrs}, TFn MOV TFn, {flagadrs} MOV TFn, {cc} [, Rx] MOV STR, imm8 MOV APn, imm5
1 x 1 1 1 1 1
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1
flg flg flg
1 0
Not Not Not
0 1
0 0
0 0
1 0
flagadrs flagadrs
Rx 0 0
cc
0 An 1 0 0 0
imm8 imm5
4-116
Individual Instruction Descriptions
Description
Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types.
Description Move data memory word to An[~] Move An[~] word to data memory Move immediate word to An[~] Move immediate word to multiply register Move An~ word to An Move An word to An~ Move product high reg to An[~] Move lower 4 bits of An[~] to SV register Move An[~] to PH register Move An[~] to MR register in signed multiplier mode Move program memory word at *An[~] to An[~] Move Rx word to data memory Move data memory word to Rx Move immediate word to Rx Move R5 to Rx Move data memory word to product high (PH) register Move data memory word to MR, set multiplier signed mode Move ROM word at *An to data memory Move data memory word (lower 6 bits)to APn register Move data memory word to status register (STAT) Move data memory value (lower 4 bits) to shift value (SV) register Move data memory word to top of stack (TOS) Move product high (PH) register to data memory Move Multiplier register (MR) to data memory Move status register (STAT) to data memory Move string register (STR) byte to data memory Move data pointer (DP) to data memory Move shift value (SV) (4 bits) to data memory Move APn register to data memory Move data memory byte to string register (STR) Move top of stack (TOS) to data memory word Move data flag to TFn in STAT register Move TFn from STAT register to memory flag Load logic value of test condition to TFn bit in STAT register Move immediate value to shift value (SV) register
Syntax MOV An[~], {adrs} [, next A] MOV {adrs}, An[~] [, next A] MOV An[~], imm16 [, next A] MOV MR, imm16 [, next A] MOV An, An~ [, next A] MOV An~, An [, next A] MOV An[~], PH [, next A] MOV SV, An[~] [, next A] MOV PH, An[~] [, next A] MOV MR, An[~] [, next A] MOV An[~], *An[~] [, next A] MOV {adrs}, Rx MOV Rx, {adrs} MOV Rx, imm16 MOV Rx, R5 MOV PH, {adrs} MOV MR, {adrs} MOV {adrs}, *An MOV APn, {adrs} MOV STAT, {adrs} MOV SV, {adrs} MOV TOS, {adrs} MOV {adrs}, PH MOV {adrs}, MR MOV {adrs}, STAT MOV {adrs}, STR MOV {adrs}, DP MOV {adrs}, SV MOV {adrs}, APn MOV STR, {adrs} MOV {adrs}, TOS MOV TFn, {flagadrs} MOV {flagadrs}, TFn MOV TFn, {cc} [, Rx] MOV SV, imm4
Assembly Language Instructions
4-117
Individual Instruction Descriptions
Syntax MOV STR, imm8 MOV APn, imm5
Description Move immediate byte to String Register (STR) Move immediate 5-bit value to APn register
Accumulator condition flags are modified to reflect the value loaded into either An or An~. Signed multiplier mode resets UM (bit 1 in status register) to 0 Load the logic value of the test condition to the TFn bit in the status register (STAT). If the condition is true, TFn=1, else TFn=0.
See Also
MOVU, MOVT, MOVB, MOVBS, MOVS
Example 4.14.28.1 MOV A0, *0x0200 * 2, ++A Preincrement accumulator pointer AP0. Copy content of word memory location 0x0200 to accumulator A0. Example 4.14.28.2 MOV *0x0200 * 2, A0, ++A Preincrement accumulator pointer AP0. Copy content of accumulator A0 to word memory location 0x0200. Example 4.14.28.3 MOV *0x0200 * 2, *A1 Transfer content of program memory location pointed by A1 to word data memory location 0x0200. Example 4.14.28.4 MOV A2, 0xf200, --A Predecrement accumulator pointer AP2. Load accumulator A2 with immediate value 0xf200. Example 4.14.28.5 MOV A0, A0~ Copy content of accumulator A0~ to accumulator A0. Example 4.14.28.6 MOV A0~, A0 Copy content of accumulator A0 to accumulator A0~. Example 4.14.28.7 MOV A0~, PH Copy content of PH to accumulator A0~. Example 4.14.28.8 MOV SV, A3, --A Predecrement accumulator pointer AP3. Copy content of accumulator A3 to SV. Example 4.14.28.9 MOV PH, A3 Copy content of accumulator A3 to PH. Example 4.14.28.10 MOV MR, A3, --A Predecrement accumulator pointer AP3. Copy content of accumulator A3 to MR. Example 4.14.28.11 MOV A1~, *A1 Transfer program memory value pointed by accumulator A1 to accumulator A1~. This is a table lookup instruction. Example 4.14.28.12 MOV *0x0200 * 2, R0 Store content of R0 to data memory word location 0x0200.
4-118
Individual Instruction Descriptions
Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 - 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word location 0x0200. Example 4.14.28.16 Transfer R5 to R0. MOV R0, R5
Example 4.14.28.17 MOV AP2, *R3 Copy content of data memory location stored in R3 to accumulator pointer AP2. Example 4.14.28.18 MOV *R6 + 8 * 2, DP Copy data pointer (DP) to data memory word location pointed by R6 offset by 8 location (short relative addressing). Example 4.14.28.19 MOV STR, *0x0200 * 2 Copy the STR register with the content of word memory location 0x0200. Example 4.14.28.20 MOV *R6+0x20, TF2 Copy TF2 flag to the flag bit in relative flag location R6 offset by 0x20. Example 4.14.28.21 MOV TF1, ZF Copy status of ZF flag in STAT register to TF1. Example 4.14.28.22 MOV SV, 4 - 2 Load SV register with a constant value 2. Example 4.14.28.23 MOV AP3, 23 - 16 Load accumulator pointer AP3 with value 7.
Assembly Language Instructions
4-119
Individual Instruction Descriptions
4.14.29 MOVAPH
Syntax
[label] name
Move With Adding PH
dest, src, src1
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b
MOVAPH An, MR, {adrs}
Table 4-46
Execution
An An + PH MR contents of {adrs} PC PC + w TAG, OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions MOVAPH An, MR, {adrs}
16 0 x
15 1
14 1
13 0
12 1
11 0
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description See Also
Move RAM word to MR register, add PH to An in parallel. MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, MOVSPHS
Example 4.14.34.1 MOVAPH A0, MR, *R3+R5 Load the contents of the byte address created by adding R3 and R5 to the MR register. At the same time, add accumulator A0 to the PH register and store the result in A0.
4-120
Individual Instruction Descriptions
4.14.30 MOVAPHS
Syntax
[label] name
Move With Adding PH
dest, src, src1
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b
MOVAPHS An, MR, {adrs}
Table 4-46
Execution
An An + PH MR contents of {adrs} PC PC + w TAG, OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions MOVAPHS An, MR, {adrs}
16 0 x
15 1
14 1
13 0
12 1
11 0
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Move RAM word to MR, add PH to second word in An string. Certain restriction applies to the use of this instruction when interrupts are occuring on the background. See section 4.8 for more details. MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MOVSPHS
See Also
Example 4.14.35.1 MOVAPHS A0, MR, *R3+R5 Load the content of byte address created by adding R3 and R5 to MR register. At the same time, add second word in accumulator string A0 to PH register, store result in A0 string.
Assembly Language Instructions
4-121
Individual Instruction Descriptions
4.14.31 MOVB
Syntax
[label] name
Move Byte From Source to Destination
dest, src
Clock, clk
Word, w
With RPT, clk Table 4-46 Table 4-46
Class 1b 1b 2a 2a 2b
MOVB An, {adrs} MOVB {adrs}, An MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8
Table 4-46 Table 4-46 1 1 1 1 1 1
N/R N/R N/R
Execution Flags Affected
dest src PC PC + w dest is An: dest is Rx: dest is {adrs}: src is {adrs}
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly XSF, XZF are set accordingly TAG bit is set accordingly
Opcode
Instructions MOVB An, {adrs} 16 0 x MOVB {adrs}, An 0 x MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8 1 1 1 0 0 0 1 1 1 1 0 15 1 14 0 13 0 12 1 11 1 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 0 0 An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 0 1 1 0 1 0 1 1 An An
imm8 imm8 k7 k6 k5
Rx
k4
k3
k2
k1
k0
Description
Syntax MOVB An, {adrs} MOVB {adrs}, An MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8
Copy value of unsigned src byte to dest byte.
Description Move data memory byte to An Move An byte to data memory Move immediate byte to An Move immediate byte to multiply register (MR) Move immediate byte to Rx
Zeros loaded to upper 8 bits of An. Status flags are not modified
See Also
MOVU, MOV, MOVT, MOVBS, MOVS
Example 4.14.29.1 MOVB A0, *R2 Copy data memory byte pointed by R2 to accumulator A0.
4-122
Individual Instruction Descriptions
Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal). Example 4.14.29.5 MOVB R2, 255 Load R2 with immidiate value of 255 (decimal).
Assembly Language Instructions
4-123
Individual Instruction Descriptions
4.14.32 MOVBS
Syntax
[label] name
MOVBS MOVBS
Move Byte String from Source to Destination
dest, src
An, {adrs}8 {adrs}, An
Clock, clk
Word, w
With RPT, clk Table 4-46 Table 4-46
Class 1b 1b
Table 4-46 Table 4-46
Execution
dest src PC PC + w dest is An: dest is {adrs}: src is {adrs}
OF, SF, ZF, CF are set accordingly XSF, XZF are set accordingly TAG bit is set to bit 17th value
Flags Affected
Opcode
Instructions MOVBS An, {adrs}8 MOVBS {adrs}8, An 16 0 x 0 x 1 0 15 1 14 0 13 0 12 1 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 0 0 An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Syntax MOVBS An, {adrs} MOVB {adrs}, An
Copy value of src byte to dest.
Description Move data memory byte string to An word string Move An byte string to data memory
See Also
MOVU, MOV, MOVT, MOVB, MOVS
Example 4.14.30.1 MOVBS A2, *0x0200 Transfer the byte string at data memory location 0x0200 to accumulator string A2. Example 4.14.30.2 MOVBS *0x0200, A2 Transfer accumulator string A2 to data memory byte string location 0x0200.
4-124
Individual Instruction Descriptions
4.14.33 MOVS
Syntax
[label] name
MOVS MOVS MOVS MOVS MOVS MOVS
Move String from Source to Destination
dest, src
An[~], {adrs} {adrs}, An[~] {adrs}, *An An[~], pma16 An[~], PH An, An~
Clock, clk
Word, w
With RPT, clk Table 4-46 Table 4-46 Table 4-46
Class 1a 1a 1b 2b 3 3
Table 4-46 Table 4-46 Table 4-46 nS+4 1 nS+2 2 1 1
N/R 1 nR+2
MOVS An[~], *An[~] nS+4 1 nR+4 3 Certain restriction applies to the use of this instruction when interrupts are occuring on the background. See Section 4.8 for more detail.
Execution
dest src PC PC + w dest is An: dest is {adrs}: src is {adrs}
OF, SF, ZF, CF are set accordingly XSF, XZF are set accordingly TAG bit is set accordingly
Flags Affected
Opcode
Instructions MOVS An[~], {adrs} 16 0 x MOVS {adrs}, An[~] 0 x MOVS {adrs}, *An 0 x MOVS An[~], pma16 1 x MOVS PH, An[~] MOVS SV, An[~] MOVS An[~], PH MOVS An, An~ MOVS MR, An[~] MOVS An[~], *An[~] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 An An An An An An 1 1 1 0 0 0 15 0 14 1 13 0 12 A~ 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 A~ 1 1 An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 0 0 1 0 0 1 A~ ~A
pma16
1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 A~ A~ A~ A~ A~ A~ 0 0 ~A ~A 0 ~A
Assembly Language Instructions
4-125
Individual Instruction Descriptions
Description
Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types.
Description Move data memory word string to An[~] string Move An[~] string to data memory Move program memory string at *An to data memory Move program memory string to An[~] string Move An~ string to An Move An string to An~ string Move product high reg to An[~], string mode. This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string. Move program memory string at *An[~] to An[~]
Syntax MOVS An[~], {adrs} MOVS {adrs}, An[~] MOVS {adrs}, *An MOVS An[~], pma16 MOVS An, An~ MOVS An~, An MOVS An[~], PH
MOVS An[~], *An[~]
See Also
MOVU, MOV, MOVT, MOVB, MOVBS
Example 4.14.31.1 MOVS A2~, *R6 Load the string pointed by R6 to accumulator string A2~. Example 4.14.31.2 MOVS *R4, A2~ Copy the accumulator string A2~ to data memory location pointed by R4. Example 4.14.31.3 MOVS *0x0100 * 2, *A0 Transfer the program memory word string pointed by content of A0 to the data memory word location 0x0100. This is a lookup instruction. Example 4.14.31.4 MOVS A2~, 0x1400 Transfer program memory string at 0x1400 to accumulator string A2~. Example 4.14.31.5 MOVS A1, A1~ Transfer accumulator string A1~ to accumulator string A1. Example 4.14.31.6 MOVS A1~, A1 Transfer accumulator string A1 to accumulator string A1~. Example 4.14.31.7 MOVS A2, PH Transfer value in PH to accumulator string A2. PH is copied to the second word of the string.
4-126
Individual Instruction Descriptions
4.14.34 MOVSPH
Syntax
[label] name
MOVSPH
Move With Subtract from PH
dest, src, src1
An, MR, {adrs}
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b
Table 4-46
Execution
An An - PH MR contents of {adrs} PC PC + w TAG, OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions MOVSPH An, MR, {adrs}
16 0 x
15 1
14 1
13 0
12 0
11 1
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description See Also
Move data memory to MR, subtract PH from An, store result in An. MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, MOVTPHS
Example 4.14.36.1 MOVSPH A0, MR, *R3+R5 Load the content of byte address created by adding R3 and R5 to MR register. At the same time, subtract PH register from accumulator A0, store result in A0.
Assembly Language Instructions
4-127
Individual Instruction Descriptions
4.14.35 MOVSPHS
Syntax
[label] name
Move String With Subtract From PH
dest, src, src1
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b
MOVSPHS An, MR, {adrs}
Table 4-46
Execution
An An (second word) - PH MR contents of {adrs} PC PC + w TAG, OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions MOVSPHS An, MR, {adrs}
16 0 x
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Move data memory word string to MR, subtract PH from second word An string. Store result in An. Certain restrictions apply to the use of this instruction when interrupts are occuring on the background. See Section 4.8 for more details. MOVSPH, MOVAPH, MOVAPHS, MOVTPH, MOVTPHS
See Also
Example 4.14.37.1 MOVSPHS A0, MR, *R3+R5 Load the content of byte address created by adding R3 and R5 to MR register. At the same time, subtract PH register from second word of A0 string, store result in A0 string.
4-128
Individual Instruction Descriptions
4.14.36 MOVT
Syntax
[label] name
MOVT
Move Tag From Source to Destination
dest, src
{adrs}, TFn
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 5
Table 4-46
Execution
dest src PC PC + w
None
Flags Affected Opcode
Instructions MOVT {adrs}, TFn
16 1 x
15 1
14 0
13 1
12 0
11 1
10 1
9 1
8
7
6
5
4
3
2
1
0
fig
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Move TFn from STAT register to memory tag. All addressing modes are available. MOVU, MOV, MOVT, MOVB, MOVBS, MOVS
See Also
Example 4.14.32.1 MOVT *R3++, TF2 Copy the TF2 flag bit to the 17th bit of the word pointed by R3. Increment R3 by 2.
Assembly Language Instructions
4-129
Individual Instruction Descriptions
4.14.37 MOVU
Syntax
[label] name
MOVU MOVU
Move Data Unsigned
dest, src [, mod]
MR, An[~] [, next A] MR, {adrs}
Clock, clk 1
Word, w 1
With RPT, clk nR+3 Table 4-46
Class 3 5
Table 4-46
Execution
[premodify AP if mod specified] dest src PC PC + w
Flags Affected
src is {adrs} UM is set to 1
TAG bit is set accordingly
Opcode
Instructions MOVU MR, An[~] [, next A] MOVU MR, {adrs} 16 1 1 x 15 1 1 14 1 0 13 0 1 12 0 1 11 10 9 8 7 1 1 6 0 5 1 4 1 3 1 2 0 1 A~ 0 0
next A
1 0 0
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types.
Description Move An[~] to MR register in unsigned multiplier mode Move data memory word to MR, reset multiplier signed mode
Syntax MOVU MR, An[~] [, next A] MOVU MR, {adrs}
See Also
MOV, MOVB, MOVT, MOVBS, MOVS
Example 4.14.33.1 MOVU MR, A0~, ++A Preincrement accumulator pointer AP0. Copy the content of accumulator A0~ to MR register. Example 4.14.33.2 MOVU MR, *R3 Copy the value pointed by R3 to MR.
4-130
Individual Instruction Descriptions
Figure 4-8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set
B MR/SV I/O xxxxxx PH Immediate B An SB S SB ROM S xxxx00
B
Rx RAM APn STR
B Flag Bit STAT TOS
NOTE: B = Byte move possible. S = String move possible. R5 can be moved to Rx, An[-] to An[-]
Assembly Language Instructions
4-131
Individual Instruction Descriptions
4.14.38 MUL
Syntax
[label] name
MUL MUL
Multiply (Rounded)
src [, mod]
An[~] [, next A] {adrs}
Clock, clk 1
Word, w 1
With RPT, clk nR+3 Table 4-46
Class 3 5
Table 4-46
Execution
[premodify AP if mod specified] PH,PL MR * src PC PC + w
Flags Affected
src is An : src is {adrs}:
OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
Opcode
Instructions MUL An[~] [, next A] MUL {adrs} 16 1 1 x 15 1 1 14 1 0 13 0 1 12 0 1 11 10 9 8 7 1 1 6 1 5 1 4 1 3 0 2 0 1 A~ 0 0
next A
1 0 1
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Multiply MR and src. The 16 MSBs of the 32-bit product are stored in the the PH register. The contents of the accumulator are not changed. The upper 16 bits of the result are rounded for MUL An, but not for MUL {adrs}. Pre-modify the accumulator pointer if specified.
Description Multiply MR by An[~] word, store result in An[~] Multiply MR by data memory word
Syntax MUL An[~] [, next A] MUL {adrs}
Round upper 16 bits No status change
See Also
MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MULAPL
Example 4.14.38.1 MUL A0~, --A Predecrement accumulator pointer AP0. Multiply MR with accumulator A0~ and store upper 16 bits of the result (rounded) PH. Accumulator A0~ is left unchanged. Example 4.14.38.2 MUL *R3-- Multiply MR with the value pointed at by R3 and store the upper 16 bits of the result (rounded) into PH. Decrement R3 by 2.
4-132
Individual Instruction Descriptions
4.14.39 MULS
Syntax
[label] name
MULS
Multiply String With No Data Transfer
src
An [~]
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
Execution
PH,PL MR * src string PC PC + 1 None
Flags Affected Opcode
Instructions MULS An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 1
6 1
5 1
4 1
3 0
2 0
1 A~
0 0
Description
Multiply MR and the value in src. The 16 MSBs of the ( (ns+3) x 16 ) -bit product are stored in the PH register. The value in src is unchanged and the value in PL is ignored. This instruction rounds the upper 16 bits. Note that An is a string of length nS+2, where nS is the value in STR register. MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MULAPL
See Also
Example 4.14.39.1 MULS A0 Multiply MR with A0 and store the upper 16 bits (with rounding) to PH register.
Assembly Language Instructions
4-133
Individual Instruction Descriptions
4.14.40 MULAPL
Syntax
[label] name
MULAPL MULAPL
Multiply and Accumulate Result
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 1 1
nR+3
Execution
[premodify AP if mod specified] PH,PL MR * src dest dest + PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULAPL An, {adrs} 16 0 x MULAPL An[~], An[~], [next A] 1 1 1 15 1 14 1 13 0 12 1 11 1 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
1
1
0
0
1
0
A~
~A
Description
Perform multiplication of multiply register (MR) and value of src. The 16 MSBs of the 32-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) added to dest. Certain restriction applies to the use of this instruction when interrupts are occuring in the background. See Section 4.8 for more detail.
Description Multiply MR by RAM word, add PL to An Multiply MR by An[~] word, add PL to An[~]
Syntax MULAPL {adrs} MULAPL An[~], An[~] [, next A]
See Also
MULAPLS, MULSPL, MULSPLS, MULTPL, MULTPLS
Example 4.14.40.1 MULAPL A0, *R3++ Multiply MR with the content of data memory word stored at byte location pointed by R3, add PL to accumulator A0, and store result in accumulator A0. Increment R3 by 2. Example 4.14.40.2 MULAPL A2, A2~, --A Multiply MR register to accumulator A2~, add PL to accumulator A2, and store result to accumulator A2.
4-134
Individual Instruction Descriptions
4.14.41 MULAPLS
Syntax
[label] name
MULAPLS MULAPLS
Multiply String and Accumulate Result
dest, src [, mod]
An, {adrs} An[~], An[~]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 nS+3 1
nR+3
Execution
PH,PL MR * src dest dest + PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs} : TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULAPLS An, {adrs} 16 0 x MULAPL S An[~], An[~], [next A] 1 1 1 15 1 14 1 13 0 12 1 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 1 1 0 0 1 0 A~ ~A
Description
Perform multiplication of multiply register (MR) and value of src. The 16 MSBs of the ((ns + 3) x 16)-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) added to dest string.
Description Multiply MR by RAM string, add PL to An Multiply MR by An[~] string, add PL to An[~]
Syntax MULAPLS {adrs} MULAPLS An[~], An[~] [, next A]
See Also
MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS
Example 4.14.41.1 MULAPLS A0, *R3++ Multiply MR with the content of data memory word string store at byte location pointed by R3, add accumulator string A0 to PL, and store result in accumulator A0 string. Increment R3 by 2. Example 4.14.41.2 MULAPLS A2, A2~, --A Multiply MR register to accumulator A2~, add accumulator string A2 to PL and store result to accumulator A2.
Assembly Language Instructions
4-135
Individual Instruction Descriptions
4.14.42 MULSPL
Syntax
[label] name
MULSPL MULSPL
Multiply and Subtract PL From Accumulator
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 1 1
nR+3
Execution
[premodify AP if mod specified] PH,PL MR * src dest dest - PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULSPL An, {adrs} 16 0 x MULSPL An[~], An[~], [next A] 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
1
1
0
0
0
0
A~
~A
Description
Perform multiplication of multiply register (MR) and value of src. The 16 MSBs of the 32-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) are subtracted from dest. Certain restrictions apply to the use of this instruction when interrupts are occuring in the background. See Section 4.8 for more details.
Description Multiply MR by RAM word, substract PL to An Multiply MR by An[~] word, substract PL to An[~]
Syntax MULSPL {adrs} MULSPL An[~], An[~] [, next A]
See Also
MULSPLS, MULTPL, MULTPLS, MULAPL, MULAPLS
Example 4.14.42.1 MULSPL A0, *R3++ Multiply MR with the contents of R3, subtract PL from accumulator A0. and store result in accumulator A0 post-increment. Post-increment R3 by 2. Example 4.14.42.2 MULSPL A2, A2~, --A Predecrement accumulator pointer AP2. Multiply MR register to accumulator A2~, subtract PL from accumulator A2, and store result to accumulator A2.
4-136
Individual Instruction Descriptions
4.14.43 MULSPLS
Syntax
[label] name
MULSPLS MULSPLS
Multiply String and Subtract PL From Accumulator
dest, src
An, {adrs} An[~], An[~]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 nS+3 1
nR+3
Execution
PH,PL MR * src dest dest - PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULSPLS An, {adrs} 16 0 x MULSPL S An[~], An[~] 1 1 1 15 1 14 1 13 1 12 1 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 1 1 0 0 0 0 A~ ~A
Description
Perform multiplication of multiply register (MR) and value of src. The 16 MSBs of the ((ns + 3) x 16)-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) subtracted from dest string.
Description Multiply MR by data memory string, subtract PL from An Multiply MR by An[~] string, subtract PL from An[~]
Syntax MULSPLS {adrs} MULSPLS An[~], An[~]
See Also
MULSPL, MULTPL, MULTPLS, MULAPL, MULAPLS
Example 4.14.43.1 MULSPLS A0, *R3++ Multiply MR with the contents of R3, subtract PL from accumulator string A0, and store result in accumulator string A0. Increment R3 by 2. Example 4.14.43.2 MULSPLS A2, A2~ Multiply MR register to accumulator string A2~, subtract PL from accumulator string A2, and store result to accumulator string A2.
Assembly Language Instructions
4-137
Individual Instruction Descriptions
4.14.44 MULTPL
Syntax
[label] name
MULTPL MULTPL
Multiply and Transfer PL to Accumulator
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 1 1
nR+3
Execution
[premodify AP if mod specified] PH,PL MR * src An PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULTPL An, {adrs} 16 0 x MULTPL An[~], An[~], [next A] 1 1 1 15 1 14 1 13 0 12 0 11 0 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
1
1
0
1
1
0
A~
~A
Description
Perform multiplication of multiply register (MR) and value of src. The 16 MSBs of the 32-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) are stored in An. Certain restrictions apply to the use of this instruction when interrupts are occuring in the background. See Section 4.8 for more detail.
Description Multiply MR by data memory word, move PL to An Multiply MR by An[~] word, move PL to An[~]
Syntax MULTPL {adrs} MULTPL An[~], An[~] [, next A]
See Also
MULTPLS, MULAPL, MULAPLS, MULSPL, MULSPLS
Example 4.14.44.1 MULTPL A0, *R3++ Multiply the contents of R3 with MR register and store PL in accumulator A0. Increment R3 by 2. Example 4.14.44.2 MULTPL A2, A2~, --A Multiply MR register to accumulator A2~ and store PL to accumulator A2.
4-138
Individual Instruction Descriptions
4.14.45 MULTPLS
Syntax
[label] name
MULTPLS MULTPLS
Multiply String and Transfer PL to Acumulator
dest, src
An, {adrs} An[~], An[~]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 nS+3 1
nR+3
Execution
PH, PL MR * src An PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions MULSPLS An, {adrs} 16 0 x MULSPL S An[~], An[~] 1 1 1 15 1 14 1 13 0 12 0 11 0 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 1 1 0 1 1 0 A~ ~A
Description
Perform multiplication of multiply register (MR) and value of src string. The 16 MSBs of the ((ns + 3) x 16)-bit product are stored in the product high (PH) register. The 16 LSBs of the product (contained in product low (PL) register) stored in An string.
Description Multiply MR by effective data memory string, move PL to An Multiply MR by An[~] string, move PL to An[~]
Syntax MULTPLS An, {adrs} MULTPLS An[~], An[~]
See Also
MULTPL, MULAPL, MULAPLS, MULSPL, MULSPLS
Example 4.14.45.1 MULTPLS A0, *R3++ Multiply the contents of R3 with MR register and store PL in accumulator string A0. Increment R3 by 2. Example 4.14.45.2 MULTPLS A2, A2~ Multiply MR register to accumulator string A2~ and store PL to accumulator string A2.
Assembly Language Instructions
4-139
Individual Instruction Descriptions
4.14.46 NEGAC
Syntax
[label] name
NEGAC
Two's Complement Negation of Accumulator
dest, src [,mod]
An[~], An[~] [, next A]
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
Execution
[premodify AP if mod specified] dest -src PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 0
6 0
5 0
4 0
3 0
2 0
1 A~
0 ~A
NEGAC An[~], An[~] [, next A]
next A
Description
Perform two's complement negation of src accumulator and store result in dest accumulator. NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NOTACS
See Also
Example 4.14.46.1 NEGAC A3~, A3, --A Predecrement accumulator pointer AP3. Negate accumulator A3 and store result in accumulator A3~.
4-140
Individual Instruction Descriptions
4.14.47 NEGACS
Syntax
[label] name
NEGACS
Two's Complement Negation of Accumulator String
dest, src
An[~], An[~]
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
Execution
dest -src PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions MULSPL S An[~], An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 0
6 0
5 0
4 0
3 0
2 0
1 A~
0 ~A
Description
Perform two's complement negation of src accumulator string and store result in dest accumulator string. NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NOTACS
See Also
Example 4.14.47.1 NEGACS A3~, A3 Negate accumulator string A3 and store result in accumulator string A3~.
Assembly Language Instructions
4-141
Individual Instruction Descriptions
4.14.48 NOP
Syntax
[label] name
NOP
No Operation
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 9d
Execution Flags Affected Opcode
Instructions NOP
PC PC + 1 None
(No operation)
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Description
This instruction performs no operation. It consumes 1 clock of execution time and 1 word of program memory. RPT
See Also
Example 4.14.48.1 NOP Consumes 1 clock cycle.
4-142
Individual Instruction Descriptions
4.14.49 NOTAC
Syntax
[label] name
NOTAC
One's Complement Negation of Accumulator
dest, src [, mod]
An[~], An[~] [, next A]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
Execution
[premodify AP if mod specified] dest NOT src PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 0
6 0
5 0
4 0
3 1
2 0
1 A~
0 ~A
NOTAC An[~], An[~] [, next A]
next A
Description
Premodify accumulator pointer if specified. Perform one's complement of src accumulator and store result in dest accumulator. NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, XORS, NEGAC, NEGACS
See Also
Example 4.14.49.1 NOTAC A3~, A3, --A Predecrement accumulator pointer AP3. One's complement (invert bits) accumulator A3 and put result in accumulator A3~.
Assembly Language Instructions
4-143
Individual Instruction Descriptions
4.14.50 NOTACS
Syntax
[label] name
NOTACS
One's Complement Negation of Accumulator String
dest, src
An[~], An[~]
Clock, clk nS+2
Word, w 1
With RPT, clk nR+2
Class 3
Execution
dest NOT src PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions NOTACS An[~], An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 0
6 0
5 0
4 0
3 1
2 0
1 A~
0 ~A
Description
Perform one's complement of src accumulator string and store result in dest accumulator string. NOTAC, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, XORS, NEGAC, NEGACS
See Also
Example 4.14.50.1 NOTACS A3~, A3 Take the one's complement (invert bits) of the accumulator string A3 and put result in accumulator string A3~.
4-144
Individual Instruction Descriptions
4.14.51 OR
Syntax
[label] name
OR OR OR OR OR
Bitwise Logical OR
dest, src [, src1] [, mod]
An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3 8a 8b
Table 4-46 2 1 1 1 2 1 1 1
N/R nR+3 N/R nR+3
Execution
[premodify AP if mod specified] dest dest OR src1 (for two operands) dest src OR src1 (for three operands) PC PC + w
Flags Affected
dest is An: dest is TFn: src is {adrs}: src is {flagadrs}:
OF, SF, ZF, CF are set accordingly TFn bits in STAT register are set accordingly TAG bit is set accordingly TAG bit is set accordingly
Opcode
Instructions OR An, {adrs} 16 0 x OR An[~], An[~], imm16 [, next A] OR An[~], An~, An [, next A] OR TFn, {flagadrs} OR TFn, {cc} [, Rx] 1 1 1 1 1 1 0 0 1 1 0 0 15 1 14 0 13 0 12 0 11 0 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 0 0 1 0
next A next A fig fig
Not Not 0
An An 1
1 0 0
0 1
0 0
0 0
0 1
1 0
A~ A~
~A ~A
flagadrs
Rx 0 1
cc
Description
Bitwise OR of src and dest. Result is stored in dest. If three operands are specified then logical OR src and src1, store result in dest. Premodification of accumulator pointers are allowed with some operand types.
Description OR RAM word to An OR immediate word to An[~], store result in An[~] OR An word to An~ word, store result in An[~] OR TFn with memory tag, store result in TFn bit in STAT OR test condition with TFn bit in STAT register. Rx must be provided if cc is one of {RZP, RNZP, RLZP, RNLZP} to check if the selected Rx is zero or negative. Rx should not be provided for other conditionals.
Syntax OR An, {adrs} OR An[~], An[~], imm16 [, next A] OR An[~], An~, An [, next A] OR TFn, {flagadrs} OR TFn, {cc} [, Rx]
Assembly Language Instructions
4-145
Individual Instruction Descriptions
See Also
ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS
Example 4.14.51.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0, Add R5 to R0 after execution. Example 4.14.51.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1. OR immediate 0xF0FF to accumulator A1. Store result in accumulator A1. Example 4.14.51.3 OR A1, A1~, A1, --A Pre-decrement accumulator pointer AP1. OR accumulator A1 to accumulator A1~, put result in A1. Example 4.14.51.4 OR TF1, *R6+0x22 OR TF1 bit in STAT with tag bit (17th bit) at relative flag address 0x22 relative to R6 (i.e., R6+0x22), store result in TF1 flag in STAT. Example 4.14.51.5 OR TF1, ZF OR ZF flag in STAT register with to TF1, put result in TF1 bit in STAT. Example 4.14.51.6 OR TF2, RZP, R2 OR TF2 with the condition code RZP (Rx=0 flag) for R2, and store result in TF2. If the content of R2 is zero then RZP condition becomes true, otherwise false. TF2 bit in STAT is modified based on this result.
4-146
Individual Instruction Descriptions
4.14.52 ORB
Syntax
[label] name
ORB
Bitwise OR Byte
dest, src
An, imm8
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 2a
Execution
dest dest OR src PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions ORB An, imm8
16 1
15 0
14 1
13 0
12 1
11 0
10 0
9 An
8
7
6
5
4
3
2
1
0
imm8
Description
Bitwise OR byte of src and dest. Result is stored in dest. Only lower 8 bits of accumulator is affected. OR, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS
See Also
Example 4.14.52.1 ORB A2, 0x45 OR 0x45 immediate to accumulator A2 lower 8 bits.
Assembly Language Instructions
4-147
Individual Instruction Descriptions
4.14.53 ORS
Syntax
[label] name
ORS ORS ORS
Bitwise OR String
dest, src [, src1]
An, {adrs} An[~], An[~], pma16 An[~], An~, An
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3
Table 4-46 nS+4 nS+2 2 1
N/R nR+2
Execution
dest dest OR src (for two operands) dest src1 OR src (for three operands) C PC + w dest is An: src is {adrs}:
OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
Flags Affected
Opcode
Instructions ORS An, {adrs} 16 0 x ORS An[~], An[~], pma16 ORS An[~], An~, An 1 1 1 1 1 1 15 1 14 0 13 0 12 0 11 0 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 0 1 1 1 1 An An 1 0 0 1 0 0 0 0 0 1 1 0 A~ A~ ~A ~A
Description
Bitwise OR of src and dest. Result is stored in dest. If three operands are specified then logical OR src1 and src, store result in dest.
Description OR RAM string to An string OR ROM string to An[~] string, store result in An[~] string OR An string to An~ string, store result in An[~] string
Syntax ORS An, {adrs} ORS An[~], An[~], pma16 ORS An[~], An~, An
See Also
OR, ORB, AND, ANDS, XOR, XORS, NOTAC, NOTACS
Example 4.14.53.1 ORS A0, *R2 OR data memory string beginning at address in R2 to accumulator string A0. Result stored in accumulator string A0. Example 4.14.53.2 ORS A0, A0~, 0x13F0 OR program memory string beginning at address in 0x13F0 to accumulator string A0~, put result in accumulator string A0. Note that the address 0x13F2 is a program memory address. Example 4.14.53.3 ORS A0, A0~, A0 OR accumulator string A0 to accumulator string A0~, put result in accumulator string A0.
4-148
Individual Instruction Descriptions
4.14.54 OUT
Syntax
[label] name
OUT OUT
Output to Port
dest, src port4, {adrs} port6, An[~]
Clock, clk
Word, w
With RPT, clk nR+3 nR+3
Class 6a 6a
Table 4-46 Table 4-46
Execution
port4 or port6 src PC PC + w
XSF, XZF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected
Opcode
Instructions OUT port4, {adrs} 16 1 x OUT port6, An[~] 1 1 1 15 1 14 0 13 0 12 1 11 10 9 8 7 6 5 4 3 2 1 0
port4
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 1 1 0 An
port6
1
~A
Description
Output to I/O port. Words (16 bits) in memory can be output to one of 16 port addresses. Words (16 bits) in the accumulators can be output to these same 16 port addresses or to an additional 48 port addresses. Note that, port4 address is multipled by 4 to get the actual port address. OUTS, IN, INS
See Also
Example 4.14.54.1 OUT 3, * 0x0200 * 2 Outputs the content of word memory location value stored in 0x0200 to I/O port at location 0x0C (PBDIR port). Note that, address 3 converts to 3 * 4 = 0xc.
Assembly Language Instructions
4-149
Individual Instruction Descriptions
4.14.55 OUTS
Syntax
[label] name
OUTS
Output String to Port
dest, src port6, An[~]
Clock, clk nR+2
Word, w 1
With RPT, clk nR+2
Class 6b
Execution
port6 src PC PC + 1
XSF, XZF are set accordingly
Flags Affected Opcode
Instructions OUTS port6, An[~]
16 1
15 1
14 1
13 0
12 1
11 1
10 1
9 An
8
7
6
5
4
3
2
1 1
0 ~A
port6
Description
Output to I/O port. Word in the accumulator string can be output to one of 64 port addresses. String operation writes several consecutive ports starting from port6 specified in the instruction. OUT, IN, INS
See Also
Example 4.14.55.1 OUTS 0x04, A3 Put the content of acccumulator string A3 to I/O port string address 0x04 (PADIR port). Note that, based on string length, other consecutive ports may also be written.
4-150
Individual Instruction Descriptions
4.14.56 RET
Syntax
[label]
Return From Subroutine (CALL, Ccc)
name
RET
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 5
Execution
PC TOS R7 R7 - 2 TOS *R7 None
Flags Affected Opcode
Instructions RET
16 1
15 1
14 0
13 1
12 1
11 1
10 1
9 0
8 0
7 0
6 1
5 1
4 1
3 1
2 1
1 1
0 0
Description
Return from call or vectored call. Pop stack to program counter, continue execution. Returns from subroutine calls (CALL, Ccc instructions) and interrupts are different because of the way each process is handled. In order to prevent execution pipeline problems the interrupt return (IRET) instruction uses two cycles and the Return (RET) instruction cannot immediately follow a CALL, i.e., RET followed by a RET should not be allowed. CALL, Ccc, IRET
See Also
Example 4.14.56.1 RET Returns from subroutine. A CALL or Ccc instruction must have executed before.
Assembly Language Instructions
4-151
Individual Instruction Descriptions
4.14.57 RFLAG
Syntax
[label] name
RFLAG
Reset Memory Flag
src
{flagadrs}
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 8a
Execution
memory flag bit at {flagadrs} data memory location 0 PC PC + 1 None
Flags Affected Opcode
Instructions RFLAG {flagadrs}
16 1
15 0
14 0
13 1
12 0
11 0
10 0
9 0
8 1
7 1
6
5
4
3
2
1
0
flagadrs
Description
Reset flag at addressed memory location to 0.{flagadrs} includes two groups of memory flag addresses: global flags, which are the first 64 word locations in RAM; and relative flags, which are 64 locations relative to the page register (R6). Flag address {flagadrs} only addresses the 17th bit. (See section 4.3.7 for more information) SFLAG, STAG, RTAG
See Also
Example 4.14.57.1 RFLAG *0x21 Resets the flag bit at RAM byte location 0x0042 to zero. Example 4.14.57.2 RFLAG *R6 + 0x0002 Resets the flag bit at RAM byte location 0x0084 to zero. Assume R6 = 0x0080. The R6 register is represented in bytes, but the 0x0002 is represented in words. Thus, 0x0080 bytes plus 0x0002 words (or 0x0004 bytes) equals 0x0084 (bytes).
4-152
Individual Instruction Descriptions
4.14.58 RFM
Syntax
[label] name
RFM
Reset Fractional Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.FM 0 PC PC + 1 None
Flags Affected Opcode
Instructions RFM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 1
5 0
4 1
3 0
2 0
1 0
0 0
Description
Resets fractional mode. Clears bit 3 in status register (STAT). Disable multiplier shift mode for unsigned fractional or integer arithmetic. SFM
See Also
Example 4.14.58.1 RFM Resets the fractional mode. Clears FM bit of STAT.
Assembly Language Instructions
4-153
Individual Instruction Descriptions
4.14.59 ROVM
Syntax
[label] name
ROVM
Reset Overflow Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.OM 0 PC PC + 1 None
Flags Affected Opcode
Instructions RFM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 1
5 0
4 1
3 0
2 0
1 0
0 0
Description
Resets overflow mode in status register bit 2 (the OM bit). Disable ALU saturation output (normal mode). SOVM
See Also
Example 4.14.59.1 ROVM Resets the overflow mode to zero.
4-154
Individual Instruction Descriptions
4.14.60 RPT
Syntax
[label]
Repeat Next Instruction
name
RPT RPT
src
{adrs}8
Clock, clk
Word, w
With RPT, clk N/R
Class 5 9b
Table 4-46 1 1
imm8
N/R
Execution
IF RPT {adrs}8 load src to repeat counter. ELSE load imm8 to repeat counter. (mask interrupt) repeat next instruction (repeat counter value + 2) times. PC PC + w (next instruction)+1 None
Flags Affected Opcode
Instructions RPT {adrs}8 RPT imm8
16 1 1
15 1 1
14 0 1
13 1 1
12 1 1
11 1 1
10 1 0
9 1 0
8 0 0
7
6
5
4
3
2
1
0
adrs imm8
Description
Loads src value to repeat counter. Execute next instruction src value + 2 times. Interrupts are queued during RPT instruction. Queued interrupts are serviced after execution completes.
Description Load data memory byte to repeat counter, repeat next instruction Load immediate byte to repeat counter, repeat next instruction
Syntax RPT {adrs}8 RPT imm8
See Also Example 4.14.60.1
BEGLOOP, ENDLOOP
RPT *0x0100 * 2 MOV *R1++, A0, ++A Loads the repeat counter with value stored in word data memory location 0x0100. Only 8 bits of data from this location are used. The next instruction stores content of A0 to data memory address pointed by R1. Since R1 post increments and A0 preincrements in this instruction, the overall effect of executing this instruction with RPT is to store accumulator contents to consecutive data memory locations. See MOV instruction for detail of various syntax of MOV instruction. Example 4.14.60.2 RPT 200 NOP Repeat the NOP instruction 202 times (provided the next instruction is repeatable). This causes 203 instruction cycle delay (including 1 cycle for the RPT instruction).
Assembly Language Instructions
4-155
Individual Instruction Descriptions
4.14.61 RTAG
Syntax
[label] name
RTAG
Reset Tag
dest
{adrs}
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 5
Table 4-46
Execution
memory tag bit at {adrs} data memory location 0 PC PC + 1 None
Flags Affected Opcode
Instructions RTAG {adrs}
16 1 x
15 1
14 0
13 1
12 0
11 1
10 1
9 0
8 1
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Resets tag bit at addressed memory location. All addressing modes are available. Note that this instruction accesses only the 17th bit of the RAM location. For odd RAM byte addresses, the least significant bit is ignored. STAG, RFLAG, SFLAG
See Also
Example 4.14.61.1 RTAG * 0x0200 * 2 Reset the tag bit of data memory word location to 0. Note that this operation can also be done with RFLAG by loading the R6 register with * 0200 * 2. Example 4.14.61.2 RTAG *R6+0x0002 Reset the tag bit of RAM location 0x0082. Assume R6 = 0x0080. Unlike the SFLAG and RFLAG instructions, the argument of the STAG/RTAG instruction is interpreted as bytes. Example 4.14.61.3 RTAG *R6+0x0003 Reset the tag bit of RAM location 0x0082. Assume R6 = 0x0080.
4-156
Individual Instruction Descriptions
4.14.62 RXM
Syntax
[label] name
RXM
Reset Extended Sign Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.XM 0 PC PC + 1 None
Flags Affected Opcode
Instructions RXM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 0
5 1
4 1
3 0
2 0
1 0
0 0
Description See Also
Reset extended sign mode status register bit 0 (the XM bit) to 0. SXM
Example 4.14.62.1 RXM Resets the sign extension mode to normal mode. Sets XM bit of STAT to 0.
Assembly Language Instructions
4-157
Individual Instruction Descriptions
4.14.63 SFLAG
Syntax
[label] name
SFLAG
Set Memory Flag
dest
{flagadrs}
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 8a
Execution
memory flag bit at {flagadrs} data memory location 1 PC PC + 1 None
Flags Affected Opcode
Instructions SFLAG {flagadrs}
16 1
15 0
14 0
13 1
12 1
11 1
10 0
9 1
8 0
7 1
6
5
4
3
2
1
0
flagadrs
Description
Set flag at addressed memory location. {flagadrs} includes two groups of memory flag adrresses: global flags, which are the first 64 words in RAM; and relative flags, which are 64 locations relative to the page register (R6). Flag address {flagadrs} only accesses the 17th bit. RFLAG, STAG, RTAG
See Also
Example 4.14.63.1 SFLAG *R6+0x12 Sets the flag bit of the RAM word addressed by R6 plus 0x0002. Note that R6 contains a byte address and 0x0002 is interpreted as a word offset.
4-158
Individual Instruction Descriptions
4.14.64 SFM
Syntax
[label] name
SFM
Set Fractional Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.FM 1 PC PC + 1 None
Flags Affected Opcode
Instructions RXM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 1
5 0
4 0
3 0
2 0
1 0
0 0
Description
Sets bit 3 (the FM bit) in status register (STAT) to 1. Enable multiplier shift mode for signed fractional arithmetic.
Example 4.14.64.1 SFM Set fractional mode. Set FM bit of STAT to 1.
Assembly Language Instructions
4-159
Individual Instruction Descriptions
4.14.65 SHL
Syntax
[label]
Shift Left
name
SHL
dest [, mod]
An[~] [, next A]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
Execution
[premodify AP if mod specified] PH, PL src << SV PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions SHL An[~] [, next A]
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 1
6 1
5 1
4 1
3 1
2 0
1 A~
0 0
next A
Description
Premodify the accumulator pointer if specified. Shift accumulator word left nSV bits (as specified by the SV register) into a 32-bit result. This result is zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the PH register. Accumulator content is not changed. The lower 16-bit value, PL, is discarded. The SHL instruction can be used with a RPT instruction, but without much advantage since the instruction does not write back into the accumulator. Use SHLAC for this purpose. SHLS
See Also
Example 4.14.65.1 SHL A0, ++A Preincrement accumulator pointer AP0. Shift accumulator word A0 to the left by SV bits. Accumulator content is not changed. PH contains the upper 16 bits of the shifted result.
4-160
Individual Instruction Descriptions
4.14.66 SHLAC
Syntax
[label] name
SHLAC
Shift Left Accumulator
dest, src [, mod]
An[~], An[~] [, next A]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
Execution
[premodify AP if mod specified] dest src << 1 PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 0
6 0
5 1
4 1
3 0
2 0
1 A~
0 ~A
SHLAC An[~], An[~] [, next A]
next A
Description
Premodify accumulator pointer if specified. Shift source accumulator src (or its offset) left by one bit and store the result in the destination accumulator (or its offset). LSB of result is set to zero.
Example 4.14.66.1 SHLAC A1, A1 Shift accumulator A1 by one bit to the left. Example 4.14.66.2 SHLAC A1~, A1, --A Predecrement accumulator pointer AP1 by 1. Shift the newly pointed accumulator A1 by one bit to the left, store the result in accumulator A1~.
Assembly Language Instructions
4-161
Individual Instruction Descriptions
4.14.67 SHLACS
Syntax
[label] name
SHLACS
Shift Left Accumulator String Individually
dest, src
An[~], An[~]
Clock, clk nS+2
Word, w 1
With RPT, clk nR+2
Class 3
Execution
dest src << 1 PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions SHLACS An[~], An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 0
6 0
5 1
4 1
3 0
2 0
1 A~
0 ~A
Description
Shift the source accumulator string src (or its offset) left one bit and store the result in destination accumulator string (or its offset). Each accumulator is shifted individually. The shifted bit is propagated through consecutive accumulators in the string.
Example 4.14.67.1 SHLACS A1~, A1 Shift accumulator string A1 one bit to the left, store the result in accumulator string A1~. Note that this instruction alters the content of all accumulators in the string.
4-162
Individual Instruction Descriptions
4.14.68 SHLAPL
Syntax
[label] name
SHLAPL SHLAPL
Shift Left with Accumulate
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A] Clock, clk Word, w With RPT, clk Table 4-46 1 nR+3 Class 1b 3
Table 4-46 1
Execution
[premodify AP if mod specified] PH, PL src << SV dest dest + PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLAPL An, {adrs}
16 0 x
15 1
14 1
13 1
12 1
11 0
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0
SHLAPL An[~], An[~] [, next A]
1
next A
An
1
1
1
0
1
0
A~
~A
Description
Premodify the accumulator pointer if specified. Shift accumulator word or data memory word pointed by {adrs} to left nSV bits (as specified by the SV register) into a 32-bit result. This result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the product high (PH) register. The lower 16 bits of the result [product low (PL) register] is added to the destination accumulator (or its offset). This instruction propagates the shifted bits to the next accumulator.
Description Shift data memory word left, add PL to An Shift An[~] left, add PL to An[~]
Syntax SHLAPL An, {adrs} SHLAPL An[~], An[~] [, next A]
See Also
SHLAPLS, SHLTPL , SHLTPLS, SHLSPL, SHLSPLS
Example 4.14.68.1 SHLAPL A0, *R4++R5 Shift the word pointed by the byte address stored in R4 by nSV bits to the left, add the shifted value (PL) with accumulator A0, store the result in accumulator A0. Add R5 to R4 and store result in R4. PH holds the upper 16 bits of the shift. Example 4.14.68.2 SHLAPL A2, *R1++ Shift the word pointed by the byte address stored in R1 by nSV bits to the left, add the shifted value (PL) with the accumulator (A2), and store the result in accumulator A2. Increment R1 (by 2) . PH holds the upper 16 bits of the shift. Example 4.14.68.3 SHLAPL A1, A1, ++A Preincrement accumulator pointer AP1. Shift the accumulator A1 by nSV bits to the left, add the shifted value (PL) to the accumulator and store the result in accumulator (A1). After execution PH contains the upper 16 bits of the 32 bit shift.
Assembly Language Instructions
4-163
Individual Instruction Descriptions
4.14.69 SHLAPLS
Syntax
[label] name
SHLAPLS SHLAPLS
Shift Left String With Accumulate
dest, src
An, {adrs} An[~], An[~] Clock, clk Word, w With RPT, clk Table 4-46 1 nR+3 Class 1b 3
Table 4-46 nS+3
Execution
PH, PL src << SV dest dest + PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLAPLS An, {adrs}
16 0 x
15 1
14 1
13 1
12 1
11 0
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 1 1 1 0 1 0 A~ ~A
SHLAPLS An[~], An[~]
1
Description
Shift accumulator string or data memory string pointed by {adrs} to left nSV bits (as specified by the SV register). The result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the product high (PH) register. The lower 16 bits of the result [product low (PL) register]) are added to the destination accumulator (or its offset). This instruction propagates the shifted bits to the next accumulators in the string.
Description Shift data memory string left, add PL to An Shift An[~] string left, addb PL to An[~]
Syntax SHLAPLS An, {adrs} SHLAPLS An[~], An[~]
See Also
SHLAPL , SHLTPL , SHLTPLS, SHLSPL, SHLSPLS
Example 4.14.69.1 SHLAPLS A0, *R4++R5 Shift the string pointed by the byte address stored in R4 by nSV bits to the left, add the shifted value (PL) with accumulator string, and store the result in accumulator string A0. Add R5 to R4 and store result in R4. PH holds the upper 16 bits of the shift. Example 4.14.69.2 SHLAPLS A2, *R1++ Shift the string pointed by the byte address stored in R1 by nSV bits to the left, add the shifted value (PL) with accumulator string, the accumulator, and store the result in accumulator string A2. Increment R1 (by 2). PH holds the upper 16 bits of the shift. Example 4.14.69.3 SHLAPLS A1, A1 Shift the accumulator string A1 by nSV bits to the left, add the shifted value (PL) to the accumulator and store the result in accumulator string A1. After execution PH contains the upper 16 bits of the 32 bit shift.
4-164
Individual Instruction Descriptions
4.14.70 SHLS
Syntax
[label] name
SHLS
Shift Left Accumulator String to Product
dest
An[~]
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
Execution
PH, PL src << SV PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions SHLS An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 1
6 1
5 1
4 1
3 1
2 0
1 A~
0 0
Description
Shift accumulator string value left nSV bits (as specified by the SV register) into a ((nS + 2) x 16) -bit result. The result is zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the PH register. Accumulator content is not changed. The lower 16-bit value is discarded. SHLS instruction can be used with RPT instructions, but the string length used will be nS + 2. SHLS
See Also
Example 4.14.70.1 SHLS A0 Shift accumulator string A0 to the left. Accumulator content is not changed. PH contains the upper 16 bits of the shifted result.
Assembly Language Instructions
4-165
Individual Instruction Descriptions
4.14.71 SHLSPL
Syntax
[label] name
SHLSPL SHLSPL
Shift Left With Subtract PL
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A] Clock, clk Word, w With RPT, clk Table 4-46 1 nR+3 Class 1b 3
Table 4-46 1
Execution
[premodify AP if mod specified] PH, PL src << SV dest dest - PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLSPL An, {adrs}
16 0 x
15 1
14 1
13 1
12 0
11 1
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0
SHLSPL An[~], An[~] [, next A]
1
next A
An
1
1
1
0
0
0
A~
~A
Description
Premodify the accumulator pointer if specified. Shift accumulator or data memory value pointed by {adrs} to left nSV bits (as specified by the SV register) into a 32-bit result. This result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the product high (PH) register. The lower 16 bits of the result [product low (PL) register] is subtracted from the destination accumulator (or its offset). This instruction propagates the shifted bit to the next accumulator.
Description Shift data memory word left, substract PL from An Shift An[~] left, substract PL to An[~]
Syntax SHLSPL An, {adrs} SHLSPL An[~], An[~] [, next A]
See Also
SHLSPLS, SHLTPL, SHLTPLS, SHLAPL, SHLAPLS
Example 4.14.71.1 SHLSPL A0, *R4++R5 Shift the word pointed by the byte address stored in R4 by nSV bits to the left, subtract the shifted (PL) from Accummulator A0, and store the result in accumulator A0. Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift. Example 4.14.71.2 SHLSPL A2, *R1++ Shift the word pointed by the byte address stored in R1 by nSV bits to the left, subtract the shifted value (PL) from the accumulator A2, and store the result in accumulator A2. Increment R1 (by 2). PH holds the upper 16 bits of the shift. Example 4.14.71.3 SHLSPL A1, A1, ++A Preincrement accumulator pointer AP1. Shift the accumulator A1 by nSV bits to the left, subtract PL from A1, and store result in accululator A1. After execution PH contains the upper 16 bits of the 32 bit shift.
4-166
Individual Instruction Descriptions
4.14.72 SHLSPLS
Syntax
[label] name
SHLSPLS SHLSPLS
Shift Left String With Subtract PL
dest, src
An, {adrs} An[~], An[~] Clock, clk Word, w With RPT, clk Table 4-46 1 nR+3 Class 1b 3
Table 4-46 nS+3
Execution
PH, PL src << SV dest dest - PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLSPLS An, {adrs}
16 0 x
15 1
14 1
13 1
12 0
11 1
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 1 1 1 0 0 0 A~ ~A
SHLSPLS An[~], An[~]
1
Description
Shift accumulator string or data memory string pointed by {adrs} to left nSV bits (as specified by the SV register). This result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the PH register. The lower 16 bits of the result PL are subtracted from the destination accumulator (or its offset). This instruction propagates the shifted bit to the next accumulator.
Description Shift RAM string left, subtract PL from An Shift An[~] string left, subtract PL from An[~]
Syntax SHLSPLS An, {adrs} SHLSPLS An[~], An[~]
See Also SHLSPL , SHLTPL , SHLTPLS, SHLAPL, SHLAPLS Example 4.14.72.1 SHLSPLS A0, *R4++R5 Shift the string pointed by the byte address stored in R4 by nSV bits to the left, subtract the shifted value (PL) from the value in the accumulator string in A0, and store the result in accumulator string A0. Add R5 to R4 and store result in R4. After execution of the instruction, PH is copied to the next to the last accumulator of the string. Example 4.14.72.2 SHLSPLS A2, *R1++ Shift the string pointed by the byte address stored in R1 by nSV bits to the left, subtract the shifted value (PL) from the value in the accumulator string in A2, and store the result in accumulator string A2. Increment R1 (by 2). After execution of the instruction, PH is copied to the next to the last accumulator of the string. Example 4.14.72.3 SHLSPLS A1, A1 Shift the accumulator string A1 by nSV bits to the left, subtract the lower 16-bits of shifted value (PL) from A1, and store the result in A1. After execution PH contains the upper 16 bits of the 32 bit shift.
Assembly Language Instructions
4-167
Individual Instruction Descriptions
4.14.73 SHLTPL
Syntax
[label] name
SHLTPL SHLTPL
Shift Left and Transfer PL to Accumulator
dest, src [, mod]
An, {adrs} An[~], An[~] [, next A]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 1 1
nR+3
Execution
[premodify AP if mod specified] PH, PL src << SV dest PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLTPL An, {adrs}
16 0 x
15 1
14 1
13 1
12 0
11 0
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0
SHLTPL An[~], An[~] [, next A]
1
next A
An
1
1
0
1
0
0
A~
~A
Description
Premodify the accumulator pointer if specified. Shift accumulator or data memory value pointed by {adrs} to left nSV bits (as specified by the SV register) into a 32-bit result. The result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the extended sign mode (XM) bit in the status register). The upper 16 bits are latched into the PH register. The lower 16 bits of the result PL are transferred to the destination accumulator (or its offset). This instruction propagates the shifted bit into PH.
Description Shift data memory word left, transfer PL to An Premodify APn if next A specified. Shift An[~] left, transfer PL to An[~]
Syntax SHLTPL An, {adrs} SHLTPL An[~], An[~] [, next A]
See Also
SHLTPLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS
Example 4.14.73.1 SHLTPL A0, *R4++R5 Shift the word pointed by the byte address stored in R4 by nSV bits to the left, and store the result in accumulator A0. Add R5 to R4 and store result in R4 at each execution to get the next memory value. After execution PH contains the upper 16 bits of the 32 bit shift. Example 4.14.73.2 SHLTPL A2, *R1++ Shift the value pointed by the byte address stored in R1 by nSV bits to the left, and store the result in accumulator A0. Increment R1 (by 2) at each execution to get the next memory value. After execution PH contains the upper 16 bits of the 32 bit shift. Example 4.14.73.3 SHLTPL A1, A1, ++A Preincrement accumulator pointer AP1. Shift the accumulator A1 by nSV bits to the left. After execution PH contains the upper 16 bits of the 32 bit shift.
4-168
Individual Instruction Descriptions
4.14.74 SHLTPLS
Syntax
[label] name
SHLTPLS SHLTPLS
Shift Left String and Transfer PL to Accumulator
dest, src
An, {adrs} An[~], An[~]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 3
Table 4-46 nS+3 1
nR+3
Execution
PH, PL src << SV dest PL PC PC + 1 OF, SF, ZF, CF are set accordingly src is {adrs}: TAG bit is set accordingly
Flags Affected Opcode
Instructions SHLTPLS An, {adrs}
16 0 x
15 1
14 1
13 1
12 0
11 0
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 1 1 0 1 0 0 A~ ~A
SHLTPLS An[~], An[~]
1
Description
Shift left accumulator string or data memory string pointed at by {adrs} by nSV bits (as specified by the SV register). The result is zero-filled on the right and either zero-filled or sign-extended on the left (based on the setting of the Extended Sign Mode (XM) bit in the status register). The upper 16 bits are latched into the PH register. The result is transferred to the destination accumulator (or its offset). This instruction propagates the shifted bits to the next accumulator, including one accumulator past the string length (which receives the same data as PH).
Description Shift data memory string left, transfer result to An Shift An[~] string left, transfer result to An[~]
Syntax SHLTPLS An, {adrs} SHLTPLS An[~], An[~]
See Also
SHLTPL, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS
Example 4.14.74.1 SHLTPLS A0, *R4++R5 Shift the string pointed by the byte address stored in R4 by nSV bits to the left, and store the result in accumulator string A0. Add R5 to R4 and store result in R4. After execution of the instruction, PH is copied to the next to the last accumulator of the string. Example 4.14.74.2 SHLTPLS A2, *R1++ Shift the string pointed by the byte address stored in R1 by nSV bits to the left, and store the result in accumulator string A0. Increment R1 (by 2) at each execution to get the next memory value. Example 4.14.74.3 SHLTPLS A1, A1 Shift the accumulator string A1 by nSV bits to the left.
Assembly Language Instructions
4-169
Individual Instruction Descriptions
4.14.75 SHRAC
Syntax
[label] name
SHRAC
Shift Accumulator Right
dest, src, [, mod]
An[~], An[~] [, next A]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
Execution
[premodify AP if mod specified] dest src >> 1 PC PC + 1 OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions
16 1
15 1
14 1
13 0
12 0
11
10
9 An
8
7 0
6 1
5 0
4 1
3 1
2 0
1 A~
0 ~A
SHRAC An[~], An[~] [, next a]
next A
Description
Premodify accumulator pointer if specified. Shift source accumulator src or its offset to right one bit and store the result into dest accumulator or its offset. MSB of result will be set according to extended sign mode (XM) bit in the status register.
Example 4.14.75.1 SHRAC A1, A1 Shift right one bit the accumulator A1. Example 4.14.75.2 SHRAC A1~, A1, ++A Preincrement by one accumulator pointer AP1. Shift right one bit the newly pointed accumulator A1, and store result to offset accumulator A1~.
4-170
Individual Instruction Descriptions
4.14.76 SHRACS
Syntax
[label] name
SHRACS
Shift Accumulator String Right
dest, src
An[~], An[~]
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
Execution
dest src >> 1 PC PC + 1
OF, SF, ZF, CF are set accordingly
Flags Affected Opcode
Instructions SHRACS An[~], An[~]
16 1
15 1
14 1
13 0
12 0
11 1
10 1
9 An
8
7 0
6 1
5 0
4 1
3 1
2 0
1 A~
0 ~A
Description
Shift accumulator string right one bit and store the result into An[~] string. MSB of each accumulator in the result will be set according to extended sign mode (XM) bit in the status register. This instruction shifts each accumulator individually 1 bit to the right, so, shifts from one accumulator are not propagated to the next consecutive accumulator in the string. SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, SHLTPL, SHLTPLS.
See Also
Example 4.14.76.1 SHRACS A0, A0 Shift accumulator string A0 1 bit right individually. Example 4.14.76.2 SHRACS A1, A1~ Shift accumulator string A1~ individually, put result in accumulator string A1.
Assembly Language Instructions
4-171
Individual Instruction Descriptions
4.14.77 SOVM
Syntax
[label] name
SOVM
Set Overflow Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.OM 1 PC PC + 1 None
Flags Affected Opcode
Instructions SOVM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 1
5 0
4 1
3 0
2 0
1 0
0 0
Description
Sets overflow mode in status register (STAT) bit 2 to 1. Enable ALU saturation output (DSP mode). ROVM
See Also
Example 4.14.77.1 SOVM Set OM bit of STAT to 1. This is the mode DSP algorithms should use.
4-172
Individual Instruction Descriptions
4.14.78 STAG
Syntax
[label] name
STAG
Set Tag
dest
{adrs}
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 5
Table 4-46
Execution
memory tag bit at address adrs 1 PC PC + w None
Flags Affected Opcode
Instructions STAG {adrs}
16 1 x
15 1
14 0
13 1
12 0
11 1
10 1
9 0
8 0
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Description
Sets the tag bit at the addressed memory location. All addressing modes are available. Note that this instruction accesses only the 17th bit of the RAM location. The argument, {adrs}, is interpreted as bytes. For odd RAM byte addresses, the least significant bit is ignored. RTAG, RFLAG, SFLAG
See Also
Example 4.14.78.1 STAG *R2+R5 Set TAG bit of the word in RAM byte address, R2 + R5. R2 and R5 remain unchanged. Example 4.14.78.2 STAG *0x200 * 2 Set TAG bit of RAM word 0x200 (RAM byte address 0x400). Example 4.14.78.3 STAG *0x401 Set TAG bit of RAM word 0x200 (RAM byte address 0x400).
Assembly Language Instructions
4-173
Individual Instruction Descriptions
4.14.79 SUB
Syntax
[label] name
SUB SUB SUB SUB SUB SUB SUB
Subtract
dest, src, src1, [next A]]
An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An, An~ [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1a 2b 3 3 3 4c 4d
Table 4-46 2 1 1 1 2 1 2 1 1 1 2 1
N/R nR+3 nR+3 nR+3 N/R N/R
Execution
[premodify AP if mod specified] dest dest - src1 (for two operands) dest src - src1 (for three operands) PC PC + w
Flags Affected
dest is An: dest is Rx: src1 is {adrs}:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly TAG bit is set accordingly
Opcode
Instructions SUB An[~], An, {adrs} [, next A] 16 0 x SUB An[~], An[~], imm16 [, next A] SUB An[~], An[~], PH [, next A] SUB An[~], An, An~ [, next A] SUB An[~], An~, An [, next A] SUB Rx, imm16 SUB Rx, R5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 0 14 0 13 0 12 ~A 11 10 9 An 8 7 6 5 4 3 2 1 0
next A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 0 1 1 0 0 0 0 1 1
next A next A next A next A
1 1 1 1 0 0
An An An An 0 0
0 0 0 0 0 1
1 1 0 0 0 0
0 1 1 1 1 1
0 0 0 0
0 0 0 0 Rx Rx
1 0 0 0
A~ A~ 0 1 0 0
~A ~A ~A ~A 0 0
Description
Subtract value of src from value of dest and store result in dest. If three operands are specified, then subtract value of src1 from value of src (i.e., src-src1) and store result in dest string. Premodification of accumulator pointers is allowed with some operand types. Note that subtraction is performed in 2's complement and therefore the CF (carry flag) may get set even when subtracting a smaller value from a larger value.
4-174
Individual Instruction Descriptions
Syntax SUB An[~], An, {adrs} [, next A] SUB An[~], An[~], imm16 [, next A] SUB An[~], An[~], PH [, next A] SUB An[~], An, An~ [, next A] SUB An[~], An~, An [, next A] SUB Rx, imm16 SUB Rx, R5
Description Subtract effective data memory word from An[~], store result in An Subtract immediate word from An[~], store result in An[~] Subtract Product High (PH) register from An[~], store result in An[~] Subtract An~ word from An word, store result in An[~] Subtract An word from An~ word, store result in An[~] Subtract immediate word from Rx Subtract R5 from Rx
See Also
SUBB, SUBS, ADD, ADDB, ADDS
Example 4.14.79.1 SUB A1, A1, 74 Subtract 74 (decimal) immediate from accumulator A1, put result in accumulator A1. Example 4.14.79.2 SUB A0, A0, 2, ++A Pre-increment pointer AP0, subtract 2 from new accumulator A0, put result in accumulator A0. Example 4.14.79.3 SUB A1, A1~, A1 Subtract accumulator A1 from accumulator A1~, put result in accumulator A1. Example 4.14.79.4 SUB A1, A1, A1~, --A Pre-decrement AP1. Subtract accumulator A1~ from accumulator A1, put result in accumulator A1. Example 4.14.79.5 SUB A3~, A3, *R4-- Subtract word at address in R4 from A3, store result in A3~, decrement value in R4 by 2 (word mode) after the subtraction. Example 4.14.79.6 SUB R3, R5 Subtract R5 from R3, put result in R3.
Assembly Language Instructions
4-175
Individual Instruction Descriptions
4.14.80 SUBB
Syntax
[label] name
SUBB SUBB
Subtract Byte
dest, src
An, imm8 Rx, imm8
Clock, clk 1 1
Word, w 1 1
With RPT, clk N/R N/R
Class 2a 4b
Execution
dest dest - imm8 PC PC + 1 dest is An: dest is Rx:
OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly
Flags Affected
Opcode
Instructions SUBB An imm8 SUBB Rx, imm8 16 1 1 15 0 0 14 1 1 13 0 1 12 0 0 11 1 1 10 0 9 An 8 7 6 5 4 3 2 1 0
imm8 k7 k6 k5
Rx
k4
k3
k2
k1
k0
Description
Subtract value of src byte from value of dest byte and store result in dest. Note that subtraction is performed in 2's complement and therefore the CF (carry flag) may get set even when subtracting a smaller value from a larger value.
Description Subtract immediate byte from An Subtract immediate byte from Rx
Syntax SUBB An, imm8 SUBB Rx, imm8
Example 4.14.80.1 SUBB A2, 0x45 Subtract 0x45 from accumulator A2 byte. Example 4.14.80.2 SUBB R3, 0xF2 Subtract 0xF2 from register R3 byte.
4-176
Individual Instruction Descriptions
4.14.81 SUBS
Syntax
[label] name
SUBS SUBS SUBS SUBS SUBS
Subtract Accumulataor String
dest, src, src1
An[~], An, {adrs} An[~], An[~], pma16 An[~], An, An~ An[~], An~, An An[~], An[~], PH
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1a 32b 3 3 3
Table 4-46 ns+4 ns+2 ns+2 1 2 1 1 1
N/R nR+2 nR+2 1
This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string. This instruction should immediately follow one of the following class 1b instructions: MOVAPH, MULAPL, MULSPL, SHLTPL, SHLSPL, and SHLAPL. An interrupt can occur between one of these instructions and this instruction. An interrupt may cause an incorrect result. Also, single stepping is not allowed for this instruction. An in this instruction should be the same as An in one of the listed class 1b instruction. Offsets are allowed. See Section 4.8 for detail.
Execution
[premodify AP if mod specified] dest dest - src (for two operands) dest src - src1 (for three operands) PC PC + w
Flags Affected
dest is An: src1 is {adrs}:
OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
Opcode
Instructions SUBS An[~], An, {adrs} 16 0 x SUBS An[~], An[~], pma16 SUBS An[~], An, An~ SUBS An[~], An~, An SUBS An[~], An[~], PH 1 1 1 1 1 1 1 1 1 1 1 1 15 0 14 0 13 1 12 ~A 11 1 10 1 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 An An An An 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 A~ 0 1 A~ ~A ~A ~A ~A
Description
Subtract the value of the src string from value of the dest string and store the result in the dest string. If three operands are specified, then subtract value of src1 string from value of src string (i.e., src-src1) and store result in dest string. Note that, substraction is performed in 2's complement and therefore the CF (carry flag) may get set even when subtracting a smaller value from a large value.
Assembly Language Instructions
4-177
Individual Instruction Descriptions
Syntax SUBS An[~], An, {adrs} SUBS An[~], An[~], pma16 SUBS An[~], An, An~ SUBS An[~], An~, An SUBS An[~], An[~], PH
Description Subtract data memory string from An string, store result in An[~] string Subtract program memory string from An[~] string, store result in An[~] string Subtract An~ string from An string, store result in An[~] string Subtract An string from An~ string, store result in An[~] string Subtract product high (PH) register from An[~] string mode. This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string. Word alignment with PH is maintained, i.e., PH is subtracted from the second word of the string. Also, only the second word is copied to the destination string.
Example 4.14.81.1 SUBS A0, A0~, *R2++ Subtract data memory string beginning at address in R2 from accumulator string A0~, put result in accumulator string A0 then increment R2 by 2. Example 4.14.81.2 SUBS A1~, A1, 0x1220 Subtract program memory string at address 0x1220 from accumulator string A1, put result in accumulator string A1~. Example 4.14.81.3 SUBS A2, A2, A2~ Subtract accumulator string A2~ from accumulator string A2, put result in accumulator string A2. Example 4.14.81.4 SUBS A2, A2~, A2 Subtract accumulator string A2 from accumulator string A2~, put result in accumulator string A2. Example 4.14.81.5 SUBS A3~, A3~, PH Subtract PH from accumulator string A3~, put result in accumulator string A3. This instruction ignores the string count.
4-178
Individual Instruction Descriptions
4.14.82 SXM
Syntax
[label] name
SXM
Set Extended Sign Mode
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 9d
Execution
STAT.XM 1 PC PC + 1 None
Flags Affected Opcode
Instructions SXM
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 1
8 0
7 1
6 0
5 1
4 0
3 0
2 0
1 0
0 0
Description See Also
Sets extended sign mode status register (STAT) bit 0 to 1. RXM
Example 4.14.82.1 SXM Set XM bit of STAT to 1. Now all arithematic operation will be in sign extention mode.
Assembly Language Instructions
4-179
Individual Instruction Descriptions
4.14.83 VCALL
Syntax
[label] name
VCALL
Vectored Call
dest vector8
Clock, clk 2
Word, w 1
With RPT, clk N/R
Class 7a
Execution
Push PC + 1 PC *(0x7F00 + vector8) R7 R7 + 2 None
Flags Affected Opcode
Instructions VCALL vector8
16 1
15 1
14 1
13 1
12 1
11 1
10 1
9 0
8 1
7
6
5
4
3
2
1
0
vector8
Description
Unconditional vectored call (Macro call). Push next address onto stack, load PC with the content of the address obtained by adding vector8 to 0x7F00. The execution of the instruction continues from the new PC location. RET instruction is used to return from VCALL. RET cannot immediately follow VCALL. IRET can be used instead of RET and IRET can immidiately follow VCALL. VCALL is used to call frequently used routines and takes 1 word. RET, IRET, CALL, Ccc
See Also
Example 4.14.83.1 VCALL 0x7F02 Loads PC value with the program memory address stored in program memory location 0x7F02.
4-180
Individual Instruction Descriptions
4.14.84 XOR
Syntax
[label] name
XOR XOR XOR XOR XOR
Logical XOR
dest, src, src1 [, mod]
An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx]
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1a 2b 3 8a 8b
Table 4-46 2 1 1 1 2 1 1 1
N/R nR+3 N/R nR+3
Execution
[premodify AP if mod specified] dest dest XOR src (for two operands) dest src1 XOR src (for three operands) PC PC + w
Flags Affected
dest is An: dest is TFn: src is {adrs}: src is {flagadrs}:
OF, SF, ZF, CF are set accordingly TFn bits in STAT register are set accordingly TAG bit is set accordingly TAG bit is set accordingly
Opcode
Instructions XOR An, {adrs} 16 0 x XOR An[~], An[~], imm16 [, next A] XOR An[~], An~, An [, next A] XOR TFn, {flagadrs} XOR TFn, {cc} [, Rx] 1 1 1 1 1 1 0 0 1 1 0 0 15 1 14 0 13 0 12 1 11 0 10 0 9 An 8 7 6 5 4 3 2 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 0 0 1 0
next A next A fig fig Not Not
1
An An 1
1 0 0
1 1
0 0
0 0
0 0
1 0
A~ A~
~A ~A
flagadrs
Rx 1 1
cc
Description
Bitwise logical XOR of src and dest. Result is stored in dest. If three operands are specified, then logical XOR src and src1, store the result in dest. Premodification of accumulator pointers is allowed with some operand types.
Description XOR RAM word to An XOR immediate word to An[~], store result in An[~] XOR An word to An~ word, store result in An[~] XOR TFn (either TF1 or TF2) with memory tag, store result in TFn bit in STAT XOR test condition with TFn (either TF1 or TF2) bit in STAT register. Rx must be provided if cc is one of {RZP, RNZP, RLZP, RNLZP} to check if the selected Rx is zero or negative. Rx should not be provided for other conditionals.
Syntax XOR An, {adrs} XOR An[~], An[~], imm16 [, next A] XOR An[~], An~, An [, next A] XOR TFn, {flagadrs} XOR TFn, {cc} [, Rx]
Assembly Language Instructions
4-181
Individual Instruction Descriptions
See Also
XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS
Example 4.14.84.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1. Example 4.14.84.2 XOR A0, A0, 2, ++A Pre-increment pointer AP0, then XOR immediate value 2 to new A0 and store result in A0. Example 4.14.84.3 XOR A1, A1~, A1 XOR accumulator A1 to accumulator A1~, put result in accumulator A1. Example 4.14.84.4 XOR A3, *R4-- XOR word at address in R4 to accumulator A3, decrement value in R4 by 2 (word mode) after the operation. Example 4.14.84.5 XOR A2, A2~, *R2+R5, --A Pre-decrement pointer AP2. XOR word at effective address R2+R5 to new accumulator A2~, put result in accumulator A2. Value of R2 is not modified. Example 4.14.84.6 XOR TF1, *0x21 XOR TF1 with the flag at global address 0x21 and store result in TF1 in STAT. Example 4.14.84.7 XOR TF2, *R6+0x21 XOR TF2 with the flag at effective address R6+0x21 and store result in TF2. Example 4.14.84.8 XOR TF1, CF XOR TF1 with the condition code CF (Carry Flag) and store result in TF1. Example 4.14.84.9 XOR TF1, RZP, R3 XOR TF1 with the condition code RZP (Rx=0 flag) for R3, and store result in TF1. If the content of R3 is zero then RZP condition becomes true, otherwise false.
4-182
Individual Instruction Descriptions
4.14.85 XORB
Syntax
[label] name
XORB
Logical XOR Byte
dest, src
An, imm8
Clock, clk 1
Word, w 1
With RPT, clk N/R
Class 2a
Execution
An An XOR imm8 PC PC + 1
(for two operands)
Flags Affected Opcode
Instructions XORB An, imm8
dest is An:
OF, SF, ZF, CF are set accordingly
16 0
15 0
14 1
13 0
12 1
11 1
10 0
9 An
8
7
6
5
4
3
2
1
0
imm8
Description
Bitwise logical XOR lower 8 bits of An and dest byte. Result is stored in accumulator An. Upper 8 bits of accumulator An is not affected. XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS
See Also
Example 4.14.86.1 XORB A2, 0x45 XOR 0x45 to accumulator A2 (byte mode). Upper 8 bits of A2 is unchanged.
Assembly Language Instructions
4-183
Individual Instruction Descriptions
4.14.86 XORS
Syntax
[label] name
XORS XORS XORS
Logical XOR String
dest, src [, src1]
An, {adrs} An[~], An[~], pma16 An[~], An~, An
Clock, clk
Word, w
With RPT, clk Table 4-46
Class 1b 2b 3
Table 4-46 nS+4 nS+3 2 1
N/R nR+3
Execution
dest dest XOR src dest src1 XOR src PC PC + w dest is An: src is {adrs}:
(for two operands) (for three operands) OF, SF, ZF, CF are set accordingly TAG bit is set accordingly
Flags Affected Opcode
Instructions XORS An, {adrs}
16 0 x
15 1
14 0
13 0
12 1
11 0
10 1
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 0 1 1 1 1 An An 1 0 1 1 0 0 0 0 0 0 1 0 A~ A~ ~A ~A
XORS An[~], An[~], pma16 XORS An[~], An~, An
1 1
Description
Bitwise XOR of src string and dest string. Result is stored in dest string. If three operands are specified, then logical XOR src string and src1 string, store result in dest string.
Description XOR data memory string to An string XOR program memory string to An[~] string, store result in An[~] string XOR An string to An~ string, store result in An[~] string
Syntax XORS An, {adrs} XORS An[~], An[~], pma16 XORS An[~], An~, An
See Also
XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS
Example 4.14.86.1 XORS A0, A0~, *R2 XOR data memory string beginning at address in R2 to accumulator string A0~, put result in accumulator string A0. Example 4.14.86.2 XORS A3~, A3, *R1++R5 XOR data memory string beginning at address in R1 to accumulator string A3, put result in accumulator string A3~. Add value in R5 to the value in R1 and store result in R1. Example 4.14.86.3 XORS A1~, A1, 0x100 * 2 XOR program memory string beginning at word address 0x0100 to accumulator string A1, put result in accumulator string A1~. Example 4.14.86.4 XORS A2, A2~, A2 XOR accumulator string A2 with accumulator string A2~ string, put result in accumulator string A2.
4-184
Individual Instruction Descriptions
4.14.87 ZAC
Syntax
[label] name
ZAC
Zero Accumulator
dest [, mod]
Clock, clk 1
Word, w 1
With RPT, clk nR+3
Class 3
An[~] [, next A]
Execution
[premodify AP if mod specified] dest 0 PC PC + 1 ZF = 1
16 1 15 1 14 1 13 0 12 0 11 10 9 An 8 7 0 6 0 5 0 4 1 3 1 2 0 1 0 0 ~A
Flags Affected
Instructions ZAC An[~] [, next A]
next A
Description
Zero the specified accumulator. Preincrement or predecrement accumulator pointer APn, if specified. ZACS
See Also
Example 4.14.87.1 ZAC A2 Reset the content of accumulator A0 to zero. Example 4.14.87.2 ZAC A1~, ++A Preincrement AP1 by 1. Reset the content of new accumulator A1~ to zero.
Assembly Language Instructions
4-185
Individual Instruction Descriptions
4.14.88 ZACS
Syntax
[label] name
ZAC
Zero Accumulator String
dest
Clock, clk nS+3
Word, w 1
With RPT, clk nR+3
Class 3
An
Execution
dest 0 PC PC + 1
ZF = 1
16 1 15 1 14 1 13 0 12 0 11 1 10 1 9 An 8 7 0 6 0 5 0 4 1 3 1 2 0 1 0 0 ~A
Flags Affected
Instructions ZACS An[~]
Description See Also
Zero the specified accumulator string. ZAC
Example 4.14.88.1 ZACS A1~ Reset the content of offset accumulator string A1~ to zero. Example 4.14.88.2 MOV STR, 32-2 ZACS A0 Reset the content of all accumulators to zero. It does not matter which accumulator AP0 is pointing at since all the accumulators are zeroed.
4-186
Instruction Set Encoding
4.15 Instruction Set Encoding
Instructions ADD An[~], An, {adrs} [, next A] 16 1 x ADD An[~], An[~], imm16 [, next A] 1 x ADD An[~], An[~], PH [, next A] ADD An[~], An~, An [, next A] ADD Rx, imm16 1 1 1 x ADD Rx, R5 ADD APn, imm5 ADDB An, imm5 ADDB Rx, imm8 ADDS An[~], An, {adrs} 1 1 1 1 0 x ADDS An[~], An[~], pma16 1 x ADDS An[~], An~, An ADDS An[~], An[~], PH AND An, {adrs} 1 1 0 x AND An[~], An[~], imm16 [, next A] 1 x AND An[~], An~, An [, next A] AND TFn, {flagadrs} AND TFn, {cc} [, Rx] ANDB An, imm8 ANDS An, {adrs} 1 1 1 1 0 x ANDS An[~], An[~], pma16 ANDS An[~], An~, An BEGLOOP CALL pma16 1 1 1 1 x CALL *An Ccc pma16 1 1 x 0 0 0 0 0 0 1 0 1 1 0 An 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 An An An 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 0 ~A 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 15 1 14 1 13 0 12 ~A 11 10 9 An 8 7 6 5 4 3 2 1 0
next A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
0
0
0
0
0
1
A~ ~A
imm16 next A next A
1 1 0 An An 0 0 0 0 1 0 0 1 1 0 0 0 1 1 Rx 0 0 A~ ~A A~ ~A 0 0
imm16
0 1 0 0 1 0 0 Rx 0 0
APn An
imm5 imm8
k4
1
k3
k2
k7
k6
k5
Rx
k1
k0
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 1 An 0 0 0 0 0 1 A~ ~A
pma16
0 0 0 1 1 1 0 0 1 1 0 0 A~ ~A A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0
next A
An
1
0
1
0
0
1
A~ ~A
imm16 next A flg Not flg Not
0 1 1 1 An An 1 An 0 0 0 1 0 1 0 0 A~ ~A
flagadrs
Rx 1 0
cc
imm8 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 An An 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 A~ ~A A~ ~A 0 0 0 0
pma16
0 0 0 0 0 0 0 0 0 0 0 0 0
Not
cc pma16
Assembly Language Instructions
4-187
Instruction Set Encoding
Instructions CMP An, {adrs}
16 0 x
15 1
14 0
13 1
12 1
11 0
10 0
9 An
8
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0
CMP An[~], imm16 [, next A]
1 x
next A
An
0
1
1
0
0
1
A~ ~A
imm16
1 1 1 1 1 1 0 0 1 0 0 1
CMP An, An~ [, next A] CMP An~, An [, next A] CMP Rx, imm16
1 1 1 x
next A next A
1 1 0
An An 0
1 1 0
0 0 1
0 0 1
0 0
0 0 Rx
0 0
0 1 0
0 0 0
imm16
1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 An 0 1 1 1 Rx 0 0
CMP Rx, R5 CMPB An, imm8 CMPB Rx, imm8 CMPS An, {adrs}
1 1 1 0 x
imm8 k7 k6 k5
Rx
k4
1
k3
k2
k1
k0
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An 0 1 1 0 0 1 A~ 0
CMPS An[~], pma16
1 x
pma16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 1 1 An An An An 1 0 An An An An 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 Rx Rx 0 1 1 Rx Rx 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1
CMPS An, An~ CMPS An~, An COR An, *Rx CORK An, *Rx ENDLOOP n EXTSGN An[~] [, next A] EXTSGNS An[~] FIR An, *Rx FIRK An, *Rx IDLE IN {adrs}, port4
1 1 1 1 1 1 1 1 1 1 1 x
n
~A A~ 1 1 0
next A
1 0 0 1 1 0 0 1
port4
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 1 An An 0 0 1 0 1 1 0 1 0 0 1 0
IN An[~], port6 INS An[~], port6 INTD INTE IRET JMP pma16
1 1 1 1 1 1 x
port6 port6
0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0
~A ~A 0 0 0 0
pma16
0 0 0 0 0 0 1 0 1 0 1 Rx 0 1
JMP pma16, Rx++
1 x
pma16
4-188
Instruction Set Encoding
Instructions JMP pma16, Rx--
16 1 x
15 0
14 0
13 0
12 0
11 0
10 0
9 1
8 0
7 1
6 0
5 1
4
3 Rx
2
1 1
0 0
pma16
0 0 0 0 0 0 1 0 1 0 1 Rx 1 1
JMP pma16, Rx++R5
1 x
pma16
0 0 0 0 0 0 1 0 0 0 0 An 0 0 0 0 0 0 0 0 0 0 0 0 0
JMP *An Jcc pma16
1 1 x
Not
cc pma16
Jcc pma16, Rx++
1 x
0
0
0
0
0
Not
cc pma16
Rx
0
1
Jcc pma16, Rx--
1 x
0
0
0
0
0
Not
cc pma16
Rx
1
0
Jcc pma16, Rx++R5
1 x
0
0
0
0
0
Not
cc pma16
Rx
1
1
MOV {adrs}, An[~] [, next A]
0 x
0
1
1
A~
next A
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 1 0 A~
MOV An[~], {adrs} [, next A]
0 x
next A
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 0 An
MOV {adrs}, *An
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
MOV An[~], imm16 [, next A] MOV MR, imm16 [, next A] MOV An, An~ [, next A] MOV An[~], PH [, next A] MOV SV, An[~] [, next A] MOV PH, An[~] [, next A] MOV An[~], *An[~] [, next A] MOV MR, An[~] [, next A] MOV {adrs}, Rx
1 1 1 1 1 1 1 1 1 x
next A next A next A next A next A next A next A next A
0
An An An An An An An An Rx
0 1 0 0 1 1 0 1
0 1 0 1 0 0 0 0
1 1 1 1 1 1 0 1
0 0 1 1 0 0 1 1
0 0 1 0 0 1 0 0
1 1 0 0 0 0 0 0
0 0
~A 0
A~ ~A A~ ~A A~ A~ 0 0
A~ ~A A~ 0
{adrs}
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 0 1 Rx {adrs}
MOV Rx, {adrs}
1 x
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 Rx Rx 0 0 0 0
MOV Rx, imm16 MOV Rx, R5 MOV SV, imm4 MOV SV, {adrs}
1 1 1 1 x
imm4
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Signed multiplier mode resets UM (bit 1 in status register ) to 0
Assembly Language Instructions
4-189
Instruction Set Encoding
Instructions MOV PH, {adrs}
16 1 x
15 1
14 0
13 1
12 1
11 0
10 0
9 0
8 1
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 0 0 0
MOV MR, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 1 APn
MOV APn, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 1 1 1
MOV STAT, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 0 1 0
MOV TOS, {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 0 1
MOV {adrs}, PH
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 0 0
MOV {adrs}, MR
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 1 0
MOV {adrs}, STAT
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 1 1
MOV {adrs}, STR
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 1 0
MOV {adrs}, DP
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 0 0
MOV {adrs}, SV
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 1 An
MOV {adrs}, APn
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 0 1 1
MOV {adrs}, TOS
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 0 0 1 1
MOV STR, {adrs} MOV {flagadrs}, TFn MOV TFn, {flagadrs} MOV TFn, {cc} [, Rx] MOV STR, imm8 MOV APn, imm6 MOVB An, {adrs}
1 x 1 1 1 1 1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1
flg Not flg Not flg Not
1 0 1 0 1 0
0 0
0 0
1 0
flagadrs flagadrs
Rx 0 0
cc
0 An An 1 0 0 0
imm8 imm5 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 0 An
MOVB {adrs}, An
0
adrs
Flagadrs is 64 locations (global or relative to R6)
4-190
Instruction Set Encoding
Instructions MOVB {adrs}, An MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8 MOVBS An, {adrs}
16 x 1 1 1 0 x
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 An An
imm8 imm8 k7 k6 k5
Rx
k4
1
k3
k2
k1
k0
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 0 1 An
MOVBS {adrs}, An
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 1 0 A~ 1 1 An
MOVS An[~], {adrs}
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
0 1 1 A~ 1 1 An
MOVS {adrs}, An[~]
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 1 An
MOVS {adrs}, *An
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 An An An An An An An 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 A~ ~A A~ A~ 0 0
MOVS An[~], pma16 MOVS PH, An[~] MOVS SV, An[~] MOVS An[~], PH MOVS An, An~ MOVS MR, An[~] MOVS An[~], *An[~] MOVT {adrs}, TFn
1 1 1 1 1 1 1 1 x
A~ ~A A~ ~A A~ 0
A~ ~A
flg
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 0 0 1 0 1
MOVU MR, An[~] [, next A] MOVU MR, {adrs}
1 1 0
next A
1 0 0
An 1
1
0
1
1
1
0
A~
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 1 0 0 An
MOVAPH An, MR, {adrs}
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 1 0 1 An
MOVAPHS An, MR, {adrs}
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 0 An
MOVSPH An, MR, {adrs}
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 1 1 An
MOVSPHS An, MR, {adrs}
0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0
MUL An[~] [, next A]
1
next A
An
1
1
1
1
0
0
A~
0
Assembly Language Instructions
4-191
Instruction Set Encoding
Instructions MUL {adrs}
16 1 x
15 1
14 0
13 1
12 1
11 1
10 0
9 1
8 1
7
6
5
4
3
2
1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 0 1 0
MULR {adrs}
1 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 1 1 1 1 0 An An 1 1 1 1 0 0 A~ 0
MULS An[~] MULAPL An, {adrs}
1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 1
MULAPL An[~], An[~], [next A] MULAPLS An, {adrs}
1 0 x
next A
1 1
An An
1
1
0
0
1
0
A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 1 1 1 1 0 An An 1 1 0 0 1 0 A~ ~A
MULAPLS An[~], An[~] MULSPL An, {adrs}
1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 1
MULSPL An[~], An[~] [, next A] MULSPLS An, {adrs}
1 0 x
next A
1 1
An An
1
1
0
0
0
0
A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 0 1 0 1 0 An An 1 1 0 0 0 0 A~ ~A
MULSPLS An[~], An[~] MULTPL An, {adrs}
1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 0
MULTPL An[~], An[~] [, next A] MUL TPLS An, {adrs}
1 0 x
next A
0 1
An An
1
1
0
1
1
0
A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 An An An An An 1 An 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 A~ ~A A~ ~A A~ ~A A~ ~A A~ ~A 1 1
MULTPLS An[~], An[~] NEGAC An[~], An[~] [, next A] NEGACS An[~], An[~] NOTAC An[~], An[~] [, next A] NOTACS An[~], An[~] NOP OR An, {adrs}
1 1 1 1 1 1 0 x
next A
1 1
next A
1 1 0 1 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 0
OR An[~], An[~], imm16 [, next A] OR An[~], An~, An [, next A] OR TFn, {flagadrs} OR TFn, {cc} [, Rx] ORB An, imm8 ORS An, {adrs}
1 1 1 1 1 0 x
next A next A flg Not flg Not
0 0 0 1 0
An An 1
1 0 0
0 1
0 0
0 0
0 1
1 0
A~ ~A A~ ~A
flagadrs
Rx 0 1
cc
An An
imm8 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
4-192
Instruction Set Encoding
Instructions ORS An[~], An[~], pma16 ORS An[~], An~, An OUT port4, {adrs}
16 1 1 1 x
15 1 1 1
14 1 1 0
13 0 0 0
12 0 0 1
11 1 1
10 1 1
9 An An
8
7 1 0
6 0 1
5 0 0
4 0 0
3 0 1
2 1 0
1
0
A~ ~A A~ ~A
port4
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 0 1 1 1 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 An An 0 0 0 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1
OUT port6, An[~] OUTS port6, An[~] RPT {adrs} RPT imm8 RET RFLAG {flagadrs} RFM ROVM RTAG {adrs}
1 1 1 1 1 1 1 1 1 x
port6 port6
1 1
A~ A~
adrs
imm8
1 1 1 1 0
flagadrs
0 0 0 0 0 0 0 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 An An An 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0
RXM SFLAG {flagadrs} SFM SHL An[~] [, next A] SHLS An[~] SHLAPL An, {adrs}
1 1 1 1 1 0 x
flagadrs
0 1 1 0 0 0 0 A~ A~ 0 0 0
next A
1 0 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 1
SHLAPL An[~], An[~] [, next A] SHLAPLS An, {adrs}
1 0 x
next A
0 1
An An
1
1
1
0
1
0
A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 0 1 1 1 0 An An 1 1 1 0 1 0 A~ ~A
SHLAPLS An[~], An[~] SHLSPL An, {adrs}
1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 0
SHLSPL An[~], An[~] [, next A] SHLSPLS An, {adrs}
1 0 x
next A
1 1
An An
1
1
1
0
0
0
A~ ~A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 1 0 0 1 0 1 0 An An 1 1 1 0 0 0 A~ ~A
SHLSPLS An[~], An[~] SHLTPL An, {adrs}
1 0 x
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 15 1 1 14 1 0 13 1 0 12 0
SHLTPL An[~], An[~] [, next A] Instructions SHLTPLS An, {adrs}
1 16 0 x
next A
11 0 10 1 9
An 8 An
1 7
1 6
0 5
1 4
0 3
0 2
A~ ~A 1 0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
Assembly Language Instructions
4-193
Instruction Set Encoding
Instructions SHLTPLS An[~], An[~] SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~] SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] STAG {adrs}
16 1 1 1 1 1 1 x
15 1 1 1 1 1 1
14 1 1 1 1 1 0
13 0 0 0 0 0 1
12 0 0 0 0 0 0
11 1
10 1
9 An An An An An 0
8
7 1 0 0 0 0
6 1 0 0 1 1
5 0 1 1 0 0
4 1 1 1 1 1
3 0 0 0 1 1
2 0 0 0 0 0
1
0
A~ ~A A~ ~A A~ ~A A~ ~A A~ ~A
next A
1 1
next A
1 1 1 1
0
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 0 1 0 1 1 1 ~A 1 1 1 An 0 1 1 0 1 0 0 0 0
SOVM SUB An[~], An, {adrs} [, next A]
1 0 x
next A
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 ~A
SUB An[~], An[~], imm16 [, next A] SUB An[~], An[~], PH [, next A] SUB An[~], An, An~ [, next A] SUB An[~], An~, An [, next A] SUB Rx, imm16 SUB Rx, R5 SUBB An, imm8 SUBB Rx, imm8 SUBS An[~], An, {adrs}
1 1 1 1 1 1 1 1 0 x
next A next A next A next A
1 1 1 1 1 1 1 0 0 0
An An An An 0 0 An
0 0 0 0 0 1
1 1 0 0 0 0
0 1 1 1 1 1
0 0 0 0
0 0 0 0 Rx Rx
1 0 0 0
A~ ~A A~ ~A 0 1 0 0 ~A ~A 0 0
imm8 k7 k6 k5
Rx
k4
1
k3
k2
k1
k0
An
adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 An An An An An 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 A~ ~A 0 1 ~A ~A
SUBS An[~], An[~], pma16 SUBS An[~], An, An~ SUBS An[~], An~, An SUBS An[~], An[~], PH SXM VCALL vector8 XOR An, {adrs}
1 1 1 1 1 1 0 x
A~ ~A 0 0
vector8 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 1
XOR An[~], An[~], imm16 [, next A] XOR An[~], An~, An [, next A] XOR TFn, {flagadrs} XOR TFn, {cc} [, Rx] XORB An, imm8 XORS An, {adrs}
1 1 1 1 1 0 x
next A next A flg Not flg Not
1 0 0 1 1
An An 1
1 0 0
1 1
0 0
0 0
0 0
1 0
A~ ~A A~ ~A
flagadrs
Rx 1 1
cc
An An
imm8 adrs
dma16 (for direct) or offset16 (long relative) [see section 4.13]
1 1 1 1 0 0 0 0 1 1 1 1 An An 1 0 1 1 0 0 0 0 0 0 1 0 A~ ~A A~ ~A
XORS An[~], An[~], pma16 XORS An[~], An~, An
1 1
4-194
Instruction Set Encoding
Instructions ZAC An[~] [, next A] ZACS An[~]
16 1 1
15 1 1
14 1 1
13 0 0
12 0 0
11
10
9 An An
8
7 0 0
6 0 0
5 0 0
4 1 1
3 1 1
2 0 0
1 0 0
0 ~A ~A
next A
1 1
cc names cc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XZ XS XG XNZ XNS XNG TF1 TF2 TAG IN1 IN2 NTF1 NTF2 NTAG NIN1 NIN2
cc name
Z S C B A G E O RC RA RE RZP RLZP L
Not cc name NZ NS NC NB NA NG NE NO RNC RNA RNE RNZP RNLZP NL
Description True Tr e condition (Not tr e condition) (N t true Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF0 or CF0) Conditional on ZF=0 and CF=1 (Not condition ZF0 or CF1) Conditional on SF=0 and ZF=0 (Not condition SF0 or ZF0) Conditional if ZF=1 and OF=0 (Not condition ZF1 or OF0) Conditional if OF=1 (Not condition OF=0) Conditional on RCF=1 (Not condition RCF=0) Conditional on RZF=0 and RCF=1 (Not condition RZF0 or RCF1) Conditional on RZF=1 (Not condition RZF=0) Conditional on value of Rx=0 Not available on Calls. (Not condition Rx0) Conditional on MSB of Rx=1. Not available on Calls. (Not condition MSB of Rx=0) Conditional on ZF=0 and SF=1 (Not condition ZF0 or SF1) reserved reserved Conditional on TF1=1 (Not condition TF1=0) Conditional on TF2=1 (Not condition TF2=0) Conditional on TAG=1 (Not condition TAG=0) Conditional on IN1=1 status. (Not condition IN1=0) Conditional on IN2=1 status. (Not condition IN2=0) Unconditional reserved reserved Conditional on XZF=1 (Not condition XZF=0) Conditional on XSF=1 (Not condition XSF=0) Conditional on XSF=0 and XZF=0 (Not condition XSF0 or XZF0) reserved reserved reserved reserved reserved
Assembly Language Instructions
4-195
Instruction Set Summary
4.16 Instruction Set Summary
Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction.
name
ADD ADD ADD ADD ADD ADD ADD ADDB ADDB ADDS ADDS ADDS ADDS AND AND AND AND AND ANDB ANDS ANDS ANDS BEGLOOP CALL CALL Ccc CMP
dest [, src] [, src1] [,mod]
An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5 APn, imm5 An, imm8 Rx, imm8 An[~], An, {adrs} An[~], An[~], pma16 An[~], An~, An An[~], An[~], PH An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx] An, imm8 An, {adrs} An[~], An[~], pma16 An[~], An~, An
Clock, clk Table 4-46 2 1 1 2 1 1 1 1 Table 4-46 nS+4 nS+3 nS+3
Words, w Table 4-46 2 1 1 2 1 1 1 1 Table 4-46 2 1 1
With RPT, clk Table 4-46 N/R nR+3 nR+3 N/R nR+3 N/R N/R N/R Table 4-46 N/R nR+3 nR+3 Table 4-46
Class 1a 2b 3 3 4c 4d 9c 2a 4b 1a 2b 3 3 1b 2b 3 8a 8b 2a 1b 2b 3 9d 7c 7c 7c 1b
Table 4-46 2 1 1 1 1 Table 4-46 nS+4 nS+3 1 1 1 1 2 2 2 Table 4-46 2 1 1 1 1
N/R nR+3 nR+3 nR+3 N/R Table 4-46 N/R nR+3 N/R N/R N/R N/R Table 4-46
pma16
*An
2 2 2
pma16
An, {adrs}
4-196
Instruction Set Summary
name
CMP CMP CMP CMP CMPB CMPB CMPS CMPS CMPS CMPS COR CORK ENDLOOP EXTSGN EXTSGNS FIR FIRK IDLE IN IN INS INTD INTE IRET JMP JMP JMP JMP JMP Jcc
dest [, src] [, src1] [,mod]
Rx, imm16 An[~], An[~] [, next A] An[~], imm16 [, next A] Rx, R5 An, imm8 Rx, imm8 An, {adrs} An[~], pma16 An, An~ An~, An An, *Rx An, *Rx
Clock, clk 2 1 2 1 1 1
Words, w 2 1 2 1 1 1
With RPT, clk N/R N/R N/R N/R N/R N/R Table 4-46
Class 2b 3 4c 4d 2a 4b 1b 2b 3 9a 9a 9d 3 3 9a 9a 9d 6a 6b 6b 9d 9d 5 7b 7b 7b 7b 7b 7b
Table 4-46 nS+4 nS+3 3 3 1 1 nS+3 2 2 1 2 1 1 1 1 1 1 1 1 1 Table 4-46 1 nS+4 1 1 2 1 2 1 1 1 2 2 2 2 1 2
N/R nR+3 3(nR+2) 3(nR+2) N/R nR+3 nR+3 2(nR+2) 2(nR+2) N/R Table 4-46 N/R nR+4 N/R N/R N/R N/R N/R N/R N/R N/R N/R
n
An[~] [, next A] An[~] An, *Rx An, *Rx
{adrs}, port4 An[~], port6 An[~], port6
pma16 pma16, Rx++ pma16, Rx-- pma16, Rx++R5
*An
2 2 2 2 2 2
pma16 [, Rmod]
Assembly Language Instructions
4-197
Instruction Set Summary
name
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
dest [, src] [, src1] [,mod]
{adrs}, An[~] [, next A] An[~], {adrs} [, next A] {adrs}, *An An[~], imm16 [, next A] MR, imm16 [, next A] An, An~ [, next A] An[~], PH [, next A] SV, An[~] [, next A] PH, An[~] [, next A] An[~], *An[~] [, next A] MR, An[~] [, next A] {adrs}, Rx Rx, {adrs} Rx, imm16 Rx, R5 SV, imm4 SV, {adrs} PH, {adrs} MR, {adrs} APn, {adrs} STAT, {adrs} TOS, {adrs} {adrs}, PH {adrs}, MR {adrs}, STAT {adrs}, STR {adrs}, DP
Clock, clk
Words, w
With RPT, clk Table 4-46 Table 4-46 Table 4-46
Class 1a 1a 1b 2b 2b 3 3 3 3 3 3 4a 4a 4c 4d 5 5 5 5 5 5 5 5 5 5 5 5
Table 4-46 Table 4-46 Table 4-46 2 2 1 1 1 1 1 1 Table 4-46 Table 4-46 2 1 1 1 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 2 1 1 1 2 2 1 1 1 1 1 1
N/R N/R nR+3 nR+3 nR+3 nR+3 nR+3 nR+3 Table 4-46 Table 4-46 N/R nR+3 N/R nR+3 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46
Signed multiplier mode resets UM (bit 1 in status register) to 0
4-198
Instruction Set Summary
name
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVB MOVB MOVB MOVB MOVB MOVBS MOVBS MOVS MOVS MOVS MOVS MOVS MOVS MOVS MOVS MOVS MOVS MOVT MOVU
dest [, src] [, src1] [,mod]
{adrs}, SV {adrs}, APn {adrs}, TOS STR, {adrs} {flagadrs}, TFn TFn, {flagadrs} TFn, {cc} [, Rx] STR, imm8 APn, imm5 An, {adrs} {adrs}, An An, imm8 MR, imm8 Rx, imm8 An, {adrs} {adrs}8, An An[~], {adrs} {adrs}, An[~] {adrs}, *An An[~], pma16 PH, An[~] SV, An[~] An[~], PH An, An~ MR, An[~] An[~], *An[~] {adrs}, TFn MR, An[~] [, next A]
Clock, clk
Words, w
With RPT, clk Table 4-46 Table 4-46 Table 4-46 Table 4-46
Class 5 5 5 5 8a 8a 8b 9b 9c 1b 1b 2a 2a 4b 1b 1b 1a 1a 1b 2b 3 3 3 3 3 3 5 3
Table 4-46 Table 4-46 Table 4-46 Table 4-46 1 1 1 1 1 Table 4-46 Table 4-46 1 1 1 Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 nS+4 nS+3 nS+3 nS+3 nS+3 nS+3 nS+3 Table 4-46 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
nR+3 nR+3 N/R N/R N/R Table 4-46 Table 4-46 N/R N/R N/R Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 N/R nR+3 nR+3 nR+3 nR+3 nR+3 nR+3 Table 4-46 nR+3
Flagadrs is 64 locations (global or relative to R6)
Assembly Language Instructions
4-199
Instruction Set Summary
name
MOVU MOVAPH MOVAPHS MOVSPH MOVSPHS MUL MUL MULR MULS MULAPL MULAPL MULAPLS MULAPLS MULSPL MULSPL MULSPLS MULSPLS MULTPL MULTPL MULTPLS MULTPLS NEGAC NEGACS NOTAC NOTACS NOP OR OR OR
dest [, src] [, src1] [,mod]
MR, {adrs} An, MR, {adrs} An, MR, {adrs} An, MR, {adrs} An, MR, {adrs} An[~] [, next A] {adrs} {adrs} An[~] An, {adrs} An[~], An[~] [, next A] An, {adrs} An[~], An[~] An, {adrs} An[~], An[~] [, next A] An, {adrs} An[~], An[~] An, {adrs} An[~], An[~] [, next A] An, {adrs} An[~] , An[~] An[~], An[~] [, next A] An[~] , An[~] An[~], An[~] [, next A] An[~] , An[~]
Clock, clk
Words, w
With RPT, clk Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46
Class 5 1b 1b 1b 1b 3 5 5 3 1b 3 1b 3 1b 3 1b 3 1b 3 1b 3 3 3 3 3 9d 1b 2b 3
Table 4-46 Table 4-46 Table 4-46 Table 4-46 Table 4-46 1 Table 4-46 Table 4-46 nS+3 Table 4-46 1 Table 4-46 nS+3 Table 4-46 1 Table 4-46 nS+3 Table 4-46 1 Table 4-46 nS+3 1 nS+3 1 nS+3 1 1 1 1 1 1 1 Table 4-46 2 1 2 1 1 1 1 1 1 1 1
nR+3 Table 4-46 Table 4-46 nR+3 Table 4-46 nR+3 Table 4-46 nR+3 Table 4-46 nR+3 Table 4-46 nR+3 Table 4-46 nR+3 Table 4-46 nR+3 nR+3 nR+3 nR+3 nR+3 nR+3 Table 4-46 N/R nR+3
An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A]
4-200
Instruction Set Summary
name
OR OR ORB ORS ORS ORS OUT OUTS RPT RPT RET RFLAG RFM ROVM RTAG RXM SFLAG SFM SHL SHLS SHLAPL SHLAPL SHLAPLS SHLAPLS SHLSPL SHLSPL SHLSPLS SHLSPLS SHLTPL SHLTPL
dest [, src] [, src1] [,mod]
TFn, {flagadrs} TFn, {cc} [, Rx] An, imm8 An, {adrs} An[~], An[~], pma16 An[~], An~, An
Clock, clk 1 1 1
Words, w 1 1 1
With RPT, clk nR+3 N/R N/R Table 4-46
Class 8a 8b 2a 1b 2b 3 6a 6b 5 9b 5 8a 9d 9d 5 9d 8a 9d 3 3 1b 3 1b 3 1b 3 1b 3 1b 3
Table 4-46 nS+4 nS+3 Table 4-46 nS+3 Table 4-46 1 1 1 1 1 1 1 Table 4-46 1 1 1 1 1 1 1 2 1
N/R nR+3 nR+3 nR+3 N/R N/R N/R nR+3 nR+3 N/R Table 4-46 N/R nR+3 N/R nR+3 nR+3 Table 4-46
port4, {adrs} port6, An[~]
{adrs}8
imm8
{flagadrs}
1 1 1
{adrs}
{flagadrs}
1 1
An[~] [, next A] An[~] An, {adrs} An[~], An[~] [, next A] An, {adrs} An[~] , An[~] An, {adrs} An[~], An[~] [, next A] An, {adrs} An[~] , An[~] An, {adrs} An[~], An[~] [, next A]
1 nS+3 Table 4-46 1 Table 4-46 nS+3 Table 4-46 1 Table 4-46 nS+3 Table 4-46 1
1
nR+3 Table 4-46
1
nR+3 Table 4-46
1
nR+3 Table 4-46
1
nR+3 Table 4-46
1
nR+3
Assembly Language Instructions
4-201
Instruction Set Summary
name
SHLTPLS SHLTPLS SHLAC SHLACS SHRAC SHRACS STAG SOVM SUB SUB SUB SUB SUB SUB SUB SUBB SUBB SUBS SUBS SUBS SUBS SUBS SXM VCALL XOR XOR XOR XOR XOR XORB
dest [, src] [, src1] [,mod]
An, {adrs} An[~], An[~] An[~], An[~] [, next A] An[~], An[~] An[~], An[~] [, next A] An[~], An[~] {adrs}
Clock, clk
Words, w
With RPT, clk Table 4-46
Class 1b 3 3 3 3 3 5 9d 1a 2b 3 3 3 4c 4d 2a 4b 1a 2b 3 3 3 9d 7a 1b 2b 3 8a 8b 2a
Table 4-46 nS+3 1 nS+3 1 nS+3 Table 4-46 1 1 Table 4-46 2 1 1 1 2 1 1 1 Table 4-46 2 1 1 1 1 2 1 1 1 1 1 Table 4-46 2 1 1 1 1 2 1 1 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1
nR+3 nR+3 nR+3 nR+3 nR+3 Table 4-46 N/R Table 4-46 N/R nR+3 nR+3 nR+3 N/R nR+3 N/R N/R Table 4-46 N/R nR+3 nR+3 nR+3 N/R N/R Table 4-46 N/R nR+3 nR+3 nR+3 N/R
An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An, An~ [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5 An, imm8 Rx, imm8 An[~], An, {adrs} An[~], An[~], pma16 An[~], An, An~ An[~], An~, An An[~], An[~], PH
vector8
An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx] An, imm8
2
4-202
Instruction Set Summary
name
XORS XORS XORS ZAC ZACS
dest [, src] [, src1] [,mod]
An, {adrs} An[~], An[~], pma16 An[~], An~, An An[~] [, next A] An[~]
Clock, clk
Words, w
With RPT, clk Table 4-46
Class 1b 2b 3 3 3
Table 4-46 nS+4 nS+3 1 nS+3 2 1 1 1
N/R nR+3 nR+3 nR+3
cc names
cc name Z S C B A G E O RC RA RE RZP RLZP L TF1 TF2 TAG IN1 IN2 XZ XS XG
Not cc name
NZ NS NC NB NA NG NE NO RNC RNA RNE RNZP RNLZP NL NTF1 NTF2 NTAG NIN1 NIN2 XNZ XNS XNG
Description p True Condition (Not true condition) Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF0 or CF0) Conditional on ZF=0 and CF=1 (Not condition ZF0 or CF1) Conditional on SF=0 and ZF=0 (Not condition SF0 or ZF0) Conditional if ZF=1 and OF=0 (Not condition ZF1 or OF0) Conditional if OF=1 (Not condition OF=0) Conditional on RCF=1 (Not condition RCF=0) Conditional on RZF=0 and RCF=1 (Not condition RZF0 or RCF1) Conditional on RZF=1 (Not condition RZF=0) Conditional on value of Rx=0 (Not condition Rx0) [Not available on Calls] Conditional on MSB of Rx=1. (Not condition MSB of Rx=0) [Not available on Calls] Conditional on ZF=0 and SF=1 (Not condition ZF0 or SF1) Conditional on TF1=1 (Not condition TF1=0) Conditional on TF2=1 (Not condition TF2=0) Conditional on TAG=1 (Not condition TAG=0) Conditional on IN1=1 status. (Not condition IN1=0) Conditional on IN2=1 status. (Not condition IN2=0) Conditional on XZF=1 (Not condition XZF=0) Conditional on XSF=1 (Not condition XSF=0) Conditional on XSF=0 and XZF=0 (Not condition XSF0 or XZF0)
Assembly Language Instructions
4-203
4-204
MSP50C614 (MSP50P614) IO Port Description Name Port A Data (bidirectional) (bidi i l) bit Ax = 0 PAx low R/W bit C = 0 PAx as input Port B Data (bidi i l) (bidirectional) bit Bx = 0 PBx low R/W bit C = 0 PBx as input Port C Data (bidirectional) (bidi i l) bit Cx = 0 PCx low R/W bit C = 0 PCx as input R/W falling edge PD4 triggers INT6 Port D Control multifunction control l if i l C=0 for interrupts (IO 0x18) R/W bit Ex = 0 PEx low R/W bit C = 0 PDx as input Port F Data (input only) (i l) Fx triggers INT5 R/W G15 G14 G13 G12 G11 Port G Data (output only) ( l) RTOTRIM MSP C l MSP50C614 only DAC Data S S O O O O R/W S O O D D D R T4-T0 = Resistor trim bits D D D D D D D D D O = overflow bit 10 bit DAC 9 bit DAC D D D D D D D D D G10 R F7 bit Fx = 0 input PFx low G9 G8 G7 G6 G5 F6 C C E7 Port E Data (bidirectional) (bidi i l) Port E Control E6 R/W C bit C = 0 PDx as input E5 PD5 triggers INT7 rising edge bit Dx = 0 PDx low D7 D6 D5 D4 D3 Port D Data multifunction port l if i (bidirectional) C C C C C C bit C = 1 PCx as output D2 D1 D0 bit Dx = 1 PDx high external input states i bit Cx = 1 PCx high C C Port C Control R/W C7 C6 C5 C4 C3 C2 C1 bit C = 1 PBx as output C0 external input states i 0x00 C C C C C C C C bit Bx = 1 PBx high Port B Control R/W B7 B6 B5 B4 B3 B2 B1 B0 bit C = 1 PAx as output external i input states 0x00 C C C C C C C C 0x00 bit Ax = 1 PAx high Port A Control R/W A7 A6 A5 A4 A3 A2 A1 A0 external input states i R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET
Address
Bits
0x00
8
0x04
8
Instruction Set Summay
0x08
8
0x0C
8
0x10
8
Assembly Language Instructions
PD = inverting and PD = positive comparator inputs if CE=1 in IO 0x38 4 5 PD2 triggers INT3 C C C C PD3 triggers INT4 C C C bit C = 1 PDx as output E4 E3 E2 bit Ex = 1 PEx high C C C C bit C = 1 PDx as output F5 F4 F3 F2 F1 bit Fx = 1 input PFx high G4 G3 G2 G1 bit Gx = 1 PGx high (output only) T4 D D D D = data bit # 8 bit DAC D D - T3 D - - T2 V = 1 T4-T0 are valid - - - - - - - = dont care see P1,P0 in IO 0x34 - - -# 0x0000 T1 T0 G0 F0 external input states i 0x00 all 0 outputs ll unaffected C C E1 E0 external input states i 0x00 0x00 bit Gx = 0 PGx low (output only) S = sign bit
0x14
8
0x18
8
0x1C
8
0x20
8
0x24
8
0x28
8
0x2C
16
0x2FA
8
0x30
16
MSP50C614 (MSP50P614) IO Port Description Name DAC Control DM 0 1 R/W EP AR CE S1 S2 0 = MC 1 = MC E1 E2 0 = disable 1 = enable D5 D5 D4 D3 PF R/W R/W W Resistor Trim bits 0 = disable 1 = enable Timer 2 period Timer 2 preset R/W T I R/W T I M M E E I C R R R T4 T3 T2 T1 T0 I T I M E R C T I M E R 1 1 R Idle bit CRO RTO 2 2 M7 PD5 falling edge interru t flag interrupt PD4 rising edge interrupt flag gg g PD3 falling edge interrupt flag F port falling edge interrupt flag DA T1 T2 D2 P P M6 D4 PF D3 D2 T2 T1 DAC Timer interrupt flag interru t Timer 1 interrupt flag g Timer 2 interrupt flag PD2 rising edge interrupt flag E R M5 R E M4 I S M3 O E M2 D T M1 PLLM bits MC = (PLLM value+1) x 131.07 kHz CPU clock = (PLLM value+1) x 65.536 kHz P P E R R E I S O E D T 0x0000 0x0000 M0 DA left unchanged Timer1 enable Timer2 enable Timer1 source Timer2 source F port Pull up Arm bit Comparator Timer Function Interrupt enable bits: 1=enable,0=disable Interrupt G l General Control CE AR PD EP E2 E1 S2 S1 D5 D4 PF D3 D2 T2 T1 DA 3x Style DAC y 5x Style DAC 0 1 Disable DAC Enable DAC 0 1 0 1 0 8 bit 9 bits 10 bits bi 0x0000 Drive Mode E Function P1 P0 DAC bits R/W DM E P1 P0 0x0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET
Address
Bits
0x34
4
0x38
16
0=disable 1=enable PD 0 1 PDM clock MC MC
1/2
1/2
DA T1 T2 D2 D3 PF D4 D5
DAC Timer interrupt Timer 1 interrupt Timer 2 interrupt PD2 rising edge interr pt interrupt PD3 falling edge interrupt interru t F port falling edge interrupt gg PD4 rising edge interrupt PD5 falling edge interrupt
0x39
8
Interrupt Flag Register
R/W
0x3A Timer 1 preset Clock Speed S d Control
16
Timer 1 period
0x0000 0x0000 0x0000
0x3B
16
0x3D
16
0x3E
16
Assembly Language Instructions
0x3F
16
Instruction Set Summay
4-205
4-206
Instruction Set Summay
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Vector 0x7FF0 0x7FF1 0x7FF2 0x7FF3 0x7FF4 0x7FF5 0x7FF6 0x7FF7
Source DAC Timer TIMER1 TIMER2 port PD2 port PD3 all port F port PD4 port PD5
Trigger Event timer underflow timer underflow timer underflow rising edge falling edge any falling edge rising edge falling edge
Priority highest 2nd 3rd 4th 5th 6th 7th lowest
Comment used to synch. speech data
Assembly Language Instructions
port PD2 goes HIGH port PD3 goes LOW F port goes from all-HIGH to LOW port PD4 goes HIGH port PD5 goes LOW
RESET 0x7FFF hardware RESET active low pulse nonmaskable Some internal I/O register INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set. Refer to section 3.3 for details 8 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) IntGenCtrl PDMCD Bit 1 ClkSpdCtrl p PLLM Register Value 0x 0F 0x 1E 0x 3E 0x 7C 0x 1E 0x 3E 0x 7C 0x 1E 0x 3E 0x 7C 0x 3E 0x 7C 0x 3E 0x 7C 0x 7C Master Clock Rate (Hz) 2.10 M 4.06 M 8.26 M 16.38 M 4.06 M 8.26 M 16.38 M 4.06 M 8.26 M 16.38 M 8.26 M 16.38 M 8.26 M 16.38 M 16.38 M PDM Rate (Hz) 2.10 M 4.06 M 8.26 M 16.38 M 2.03 M 4.13 M 8.19 M 4.06 M 8.26 M 16.38 M 4.13 M 8.19 M 8.26 M 16.38 M 8.19 M CPU Clock Rate (Hz) 1.05 M 2.03 M 4.13 M 8.19 M 2.03 M 4.13 M 8.19 M 2.03 M 4.13 M 8.19 M 4.13 M 8.19 M 4.13 M 8.19 M 8.19 M Output p Sampling pg Rate (Hz) 8.19 k 15.87 k 32.26 k 64.00 k 7.94 k 16.13 k 32.00 k 7.94 k 16.13 k 32.00 k 8.06 k 16.00 k 8.06 k 16.00 k 8.00 k Number of Instructs btwn DAC Interrupts 128 128 128 128 256 256 256 256 256 256 512 512 512 512 1024 Number of Instructs btwn 8 kHz Interrupts 128 256 512 1024 256 512 1024 256 512 1024 512 1024 512 1024 1024
DAC Precision 8 bits
Over-Sampling Factor 1x 2x 4x 8x
0
1x 2x 4x
9 bits
1
1x 2x 4x
0 10 bits 1 0
1x 2x 1x 2x 1x
10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) IntGenCtrl PDMCD Bit 1 ClkSpdCtrl PLLM Register g Value 0x 13 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 0x 4D 0x 9B 0x 4D 0x 9B 0x 9B Master Clock Rate (Hz) 2.62 M 5.11 M 10.22 M 20.45 M 5.11 M 10.22 M 20.45 M 5.11 M 10.22 M 20.45 M 10.22 M 20.45 M 10.22 M 20.45 M 20.45 M PDM Rate (Hz) 2.62 M 5.11 M 10.22 M 20.45 M 2.56 M 5.11 M 10.22 M 5.11 M 10.22 M 20.45 M 5.11 M 10.22 M 10.22 M 20.45 M 10.22 M CPU Clock Rate (Hz) 1.31 M 2.56 M 5.11 M 10.22 M 2.56 M 5.11 M 10.22 M 2.56 M 5.11 M 10.22 M 5.11 M 10.22 M 5.11 M 10.22 M 10.22 M Output Sampling Rate (Hz) 10.24 k 19.97 k 39.94 k 79.87 k 9.98 k 19.97 k 39.94 k 9.98 k 19.97 k 39.94 k 9.98 k 19.97 k 9.98 k 19.97 k 9.98 k Number of Instructs btwn DAC Interrupts 128 128 128 128 256 256 256 256 256 256 512 512 512 512 1024 Number of Instructs btwn 10 kHz Interrupts 128 256 512 1024 256 512 1024 256 512 1024 512 1024 512 1024 1024
DAC Precision 8 bits
Over-Sampling pg Factor 1x 2x 4x 8x
0
1x 2x 4x
9 bits
1
1x 2x 4x
0
1x 2x
10 bits
1
1x 2x
Assembly Language Instructions
4-207
0
1x
Instruction Set Summay
Instruction Set Summay
4-208
Assembly Language Instructions
Chapter 5
Code Development Tools
For code development purposes, the programmable MSP50P614 is used. The MSP50C6xx code development tool is used to compile, link, and debug assembly language programs. This tool can also be used to program an MSP50P614. A reduced function C compiler, (called C- -) is also available.
Topic
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 MSP Software Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Software Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 C- - Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.10 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 5.11 Beware of Stack Corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5.12 Reported Bugs With Code Development Tool . . . . . . . . . . . . . . . . . . 5-67
5-1
Introduction
5.1 Introduction
The MSP50C6xx development tools gain access to the core controller via a serial scan interface called the Scanport. The basic elements needed to do development with the MSP50C6xx devices are listed below in Section 5.3. The MSP50C6xx software development tool is included with the MSP scanport interface (TI part #MSPSCANPORTI/F) or MSPSI. The mask programmed MSP50C6xx devices are available in die form to support large volume production quantities. The MSP50C614/605 devices are available in a 100-pin 14x20 mm quad-flat pack (QFP) and the MSP50C604 is available in a 64 pin 10x10 QFP for medium volume application. The MSP50P614 is an EPROM based version of the MSP50C614, and is available in a 120-pin windowed ceramic pin grid array package. This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each person doing software development should have several of these PGA packaged devices. The MSP50C6xx software development tool supports non-real-time debugging by scanning the code sequence through the MSP50C6xx scanport without programming the EPROM. However, the rate of code execution is limited by the speed of the PC parallel port. Any MSP50C6xx device can be used in this debugging mode. The MSP50P614 EPROM must be programmed to debug the code in real time. The MSP50C6xx software development tool is used to program the EPROM, set a breakpoint, and evaluate the internal registers after the breakpoint is reached. If a change is made to the code, the code will need to be updated and programmed into another device while erasing previous devices. This cycle of programming, debugging and erasing typically requires 10-15 devices to be in the eraser at any one time, so 15-20 devices may be required to operate efficiently. The windowed PGA version of the MSP50P614 is required for this debugging mode. It is necessary to build preproduction application boards with a zero insertion force PGA socket that allows the device to be easily changed during software development. Use the PGA package pin assignment shown in Figure 1-7. These preproduction boards also have the following requirements for the development tools to function properly. (1) a 10 pin IDC header that connects the MSP50P614 to the MSP Scanport Interface should be provided. (2) the VPP pin of the MSP50P614 must be pulled up to +5V with a diode, so the development tool can apply 12V to this pin. (3) The development tool must be allowed to toggle the reset pin without being loaded by any low impedance reset circuit. This can be accomplished by inserting a 1K ohm resister between
5-2
MSP50C6xx Software Development Tool
the reset circuit and the reset pin, and connecting the scanport reset signal directly to the reset pin. See the recommended reset circuit shown in Figure 1-3. It is also recommended that all production boards be built with the scanport interface connector footprint connected to the appropriate pins and VPP-level translator circuit shown in Figure 5-1. This allows the MSP50C6xx Software Development Tools to facilitate any post production debugging. The 10 pin connector, transistor, zenor diode, and resistors can be added as needed. The development tool must be allowed to toggle the reset pin without being loaded by any low impedance reset circuit. This can be accomplished by inserting a 1-k resistor between the reset circuit and the reset pin, and connecting the scanport reset signal directly to the reset pin. See the recommended reset circuit shown in Figure 1-3. If this is not possible, it would be helpful to provide an easy way to connect the MSP50C6xx scanport pins to an external level translator circuit and scanport connector.
Figure 5-1. Level Translator Circuit
VDD 5.1 V Zener VPP To 10-pin IDC header connecting to MSP50C6xx scanport 10 k 10 k TEST To MSP50C6xx Device 100 k 2N2222
5.2 MSP50C6xx Software Development Tool
The development tool software is a Microsoft WindowsTM based integrated graphical development environment which includes the following:
-
Assembler Linker Make utility Debugger C-- compiler Application programming interface
Code Development Tools
5-3
Requirements
5.3 Requirements
The requirements for a complete MSP50C6xx development system are as follows: PC Requirements:
-
Intel i486TM or PentiumTM class processor Microsoft WindowsTM 3.11, Windows 95TM, or Windows 98TM operating system 16-MB memory 8-MB hard disk space Parallel port interface
Development Requirements: MSP50C6xx Scanport Interface (MSPSI) MSP50C6xx software development tool (Included with MSPSI) Several PGA packaged MSP50P614s EPROM eraser (UV light source) Application board (see the following note)
Note: The user may provide their own application board, but TI has a basic application board that may provide everything needed to start software development. This board is called the speech EVM and was designed to support several TI speech devices by using different personality cards. The user will need to use the appropriate personality card for the device that is being developed.
5-4
Hardware Installation
5.4 Hardware Installation
The following steps are used to set up the hardware (see Figure 5-2): 1) Connect the 18 V power supply to the MSPSI and connect the mains pins to a 120 V, 60 Hz ac source. 2) Connect one end of the IEEE1284 parallel cable to the MSPSI board and the other end to the PC parallel port. The red (power) LED should be ON. The yellow (Emul/Prog) LED comes ON when entering into emulation mode or during programming. The green (target) LED is ON if the MSPSI is connected to a target board that has power applied.
Figure 5-2. Hardware Installation
IEEE1284 Parallel Port Cable
MSP Scanport Interface (MSPSI) GREEN LED YELLOW LED
RED LED
Target board connector MSP50P614 Target development board
PC Parallel port
18 V DC
Target board power
LED DESCRIPTION Red Yellow Green MSPI power Emulation mode/programming (Emul/Prog) Target board power
Code Development Tools
5-5
Software Installation
Figure 5-3. 10-Pin IDC Connector (top view looking at the board)
10-PIN HEADER (3M PART# 2510-60024B) IDC2X5M VPP PGMPULSE GND SCANIN SCANOUT 1 3 5 7 9 2 4 6 8 10 RESET PAD DIA 0.060I SCANCLK SYNC N/C 0.1I VDD 0.800I HOLE DIA 0.038I 0.35I IDC2X5M
0.1I PINOUT DETAILS LAYOUT DETAILS
5.5 Software Installation
Install the MSP50P614/MSP50C614 development tool from the supplied floppy disk by running the setup.exe. Installation should not take much more than one minute. Following are the Software Installation steps: Step 1: Run the setup.exe application from Windows explorer or using the Run menu option by pressing the start button.
Figure 5-4. InstallShield Window
5-6
Software Installation
Figure 5-5. Setup Window
Step 2: After setup runs the InstallShield (see Figure 5-4), the setup window pops up (see Figure 5-5). Step 3: Press the Next > button to continue with installation or press Cancel to exit installation.
Code Development Tools
5-7
Software Installation
Figure 5-6. Exit Setup Dialog
Step 4: If you press Cancel, you can return to setup by pressing Resume button. You can exit setup by pressing Exit Setup button (Figure 5-6).
Figure 5-7. User Information Dialog
5-8
Software Installation
Step 5: If you continue with setup, you will be brought to User Information dialog. Enter your Name and Company Name in the two respective fields. To get into this screen, you must press yes to the license screen and press next to the Information dialog. Step 6: Type any alphanumeric value as Serial number. Press Next > when done. Press < Back to go to the previous dialog. Press Cancel to exit.
Figure 5-8. Choose Destination Location Dialog
Step 7: Select an installation directory by pressing the Browse... button if the default directory is not desired. Setup automatically created the installation directories. Step 8: Press Next > to continue with installation.
Code Development Tools
5-9
Software Installation
Figure 5-9. Select Program Folder Dialog
Step 9: Enter a new folder name in Select Program Folder dialog. Step 10: Press Next > to continue with installation.
5-10
Software Installation
Figure 5-10. Copying Files
Step 11: The program starts installation. When the installation is complete, an icon is also created on the desktop.
Code Development Tools
5-11
Software Installation
Figure 5-11.Setup Complete Dialog
Step 12: The Setup Complete dialog message is displayed when setup is completed. Press the Finish button to complete the installation.
5-12
Software Emulator
5.6 Software Emulator
Run the EMUC6xx.exe program which will be in the installation directory or on your desktop (icon). Your scanport interface and the target board must be connected and turned on before the emulator can be successfully used. If the opening window comes up without any messages, the system is working properly. If the "WARNING Development board not detected" message appears, there is a communication problem between the PC and the board. Possible reasons are: no power supply, no chip in socket, bad chip, bad connection, or board not working.
5.6.1
The Open Screen
The open screen is the initial screen blank screen of the emulator software as shown in Figure 5-12. If this is the first time you are using emulator software or you want to create a new project, you should choose the Project menu to create a new project. If you already created a project and it appears at the bottom of project menu project list, you can open the project just by clicking the appropriate project (see Figure 5-13).
Figure 5-12. Open Screen
Code Development Tools
5-13
Software Emulator
Figure 5-13. Project Menu
Figure 5-14. Project Open Dialog
5-14
Software Emulator
Figure 5-15. File Menu Options
5.6.2
Projects
The emulator can only work from project files created within the emulator itself. These files have the extension .rpj, and are not compatible with the .rpj files used in the old simulator. In other words, even to assemble a single assembly program, the user has to create a project and insert the name of the assembly file in the project. To create a new project: Menu Project/New Project, then enter a project name (Figure 5-14). To insert files in a project: Menu File/Insert (Figure 5-15), or activate the project window by placing the mouse over it, and hit the INS key. (Any window can be activated by placing the mouse cursor over it). Assembly files (extension .asm), and C- - files (extension .cmm) can be put in a project, as well as object files created by the emulator (extension .obj). In particular, do not forget to include the cmm6xx.asm (or cmm6xx.obj, once it has been assembled) file in any project containing C- - files. Once all necessary files have been inserted in a project, it is a good idea to save the project (Menu Project/Save). The user can then build (from scratch) or make (only files that have to be assembled/compiled/linked) the project. If errors are detected, the emulator will automatically bring up an editor
Code Development Tools
5-15
Software Emulator
(pfe32.exe) and an error dialog. The user can modify the source code and save the changes, before restarting the building action.
5.6.3
Description of Windows
Once a new project is created or an old project is opened, the following seven windows pops open (Figure 5-16).
Figure 5-16. MSP50P614/MSP50C614 Code Development Windows
5-16
Software Emulator
Figure 5-17. RAM Window
RAM Window : Displays 16-bit data memory hex values. The left most column is the address. Data memory is always addressable as bytes by MSP50C614 instructions. Each value displayed in this window is actually two consecutive byte data. Data memory values consist of the usual 16 bits, plus a 17th bit called the tag bit. If the tag bit is set, the background is yellow, otherwise it is white. The tag bit can be changed by clicking the right mouse button on the data memory value to be changed. The value is displayed in red if it has changed since the last time it was displayed. To edit a memory value, double click on the value to bring a small blinking cursor. Keep the mouse pointer within this window and enter a new hex value. Changes are only taken into account when the chip is not in run mode. To add or remove a watch, select the location by double clicking the data memory value and press W on the keyboard. The selected location will be added (if Watch window does not already contain this location) or removed (if Watch window contains this location) from the Watch window.
Code Development Tools
5-17
Software Emulator
Watch Window : Watch window displays the data memory location and data to be watched. It mirrors the value displayed in the RAM window. The Watch window is provided as a help to display locations that may not be visible in the RAM window without scrolling. See Ram Window above to know more about how to use Watch window.
Figure 5-18. CPU Window
CPU Window : Displays values in all MSP50P614/MSP50C614 system registers and some additional information. Editing a register value is similar to editing a data memory value in RAM Window. The first two columns have registers labeled 00h to 1Fh the 16-bit accumulators. R0 to R7 indicates indirect register values. Values in parenthesis indicates the values pointed by the register using indirect addressing. This value is displayed only when valid data memory address in present in the register. The fourth column is all status register (STAT) bits. AP0 to AP3 are accumulator pointers, 5 bits of which is active. CLK field is the clocks taken. The emulator keeps track of the number of cycles used. This counter can be reset by using the Init/All or Init/All Except Breakpoints menu options. It is provided as a convenience to time programs
5-18
Software Emulator
being run in emulation mode. STK field is the depth of the stack. The emulator keeps track of number of calls and returns and changes this variable accordingly. CUR field is the current subroutine name. In C-- programs it becomes very handy to display local variables of a subroutine. C- -
Figure 5-19. Program Window
Program Window : The program window displays program instructions, comments, preprocessor text, and program memory location. The project must be built (or made) to view the instructions on the program window. If the program is not properly built, the emulator displays error message and launches the PFE.EXE editor to correct the error. The programmer should fix the errors, save the new file, and try to rebuild again. The text in program window is displayed in a different color. Instructions are displayed as black text. Comments are always displayed as green text. Preprocessor text is displayed as comments. The current instruction pointed by program counter is displayed as text with yellow background. This highlight forwards as you step through the code. Lines containing software breakpoints are displayed in red. To set a software breakpoint, just click the right mouse button over the line you want to break. Only program lines that are not in a gray area can contain breakpoints. To remove a breakpoint, click the right mouse button over the line containing the breakpoint to be removed. Texts with cyan
Code Development Tools
5-19
Software Emulator
background is the line reached by a search command (by PC, line number or label). Search position can also be set by double clicking on it in the program window. The line (if any) contain the hardware breakpoint is displayed in green background. To set a hardware breakpoint, just click the right mouse button over the line you want to break, while holding the SHIFT key down. Only program lines that are not in a gray area can contain breakpoints. To remove a hardware breakpoint, click the right mouse button over the line containing the breakpoint to be removed, while holding the SHIFT key down. The 8 most recent hardware breakpoint addresses are kept in memory. The user can review them by clicking on the hardware breakpoint icon which pops up the Hardware Breakpoint dialog box as shown in Figure 5-20. Hardware Breakpoint dialog allows a name to be associated with a hardware breakpoint corresponding to the breakpoint address. Only one hardware breakpoint can be made active at any time.
Figure 5-20. Hardware Breakpoint Dialog
Inspect Window : This is the window where C- - variables can be examined. Variables are inserted in the Inspect window by hitting the INSERT key while this window is active (i.e., when the mouse cursor is in it). A dialog appears Figure 5-20, and the user should just type the name of the C- -variable. The
5-20
Software Emulator
variable value and its address in RAM are then displayed (Figure 5-21). Variables appearing on a gray background either are not defined, or are not active at this time. The user can also use the Inspect option in the Debug menu to insert a variable in the Inspect window.
Figure 5-21. Inspect Dialog
Figure 5-22. Inspect Window
I/O Ports Window : The 64 I/O Port values are displayed in this window (Figure 5-22) They can be modified the same way most values can be
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modified (i.e, by double clicking on a value and typing its new hexadecimal value over the existing value). Values of read only registers cannot be modified.
Figure 5-23. I/O Ports Window
Project Window : All source files making up the project are displayed in this window. Only assembly language files (.asm) and C- - source files (.cmm) should be inserted in a project. To insert a file, activate the project window by positioning the mouse over it, and hit the INS key. A file dialog will appear. It is also possible to use the File/Insert Menu option in the main window. To remove a file from a project, double click the left mouse button on the filename (only top level files can be removed). The file becomes highlighted in yellow, Hit the DEL key to remove it from the project. The indentations in the display reflect the depth of inclusion of dependent files.
5.6.4
Debugging a Program
The software emulator allows various types of debugging. The Debug menu Figure 5-23) options are explained in detail as follows. Step : This menu option, (key equivalent: F7), allows the user to execute one instruction in the program window. Note that the program window does not need to have the focus to execute a Step instruction. If the step instruction leads into a gray area, i.e., a program line, or group of program lines that cannot be stepped into, the system will automatically execute instructions until it gets out of the gray area.
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Step Over : This menu option, (key equivalent: F8), allows the user to step over a call instruction in the program window. Note that the program window does not need to have the focus to execute a Step instruction. If the Step Over instruction leads into a gray area, i.e., a program line, or group of program lines that cannot be stepped into, the system automatically execute the instructions until it gets out of the gray area. Stepping over a line that does not contain a call (or macro call) is equivalent to a single step instruction.
Figure 5-24. Debug Menu
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Software Emulator
Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user to execute a portion of the program window, until a breakpoint is encountered. The windows are not refreshed until the program stops, so that the execution speed is maximized. If no breakpoint is encountered, the user can stop the program by hitting the STOP option (CTRL+F10) in the debug menu. Since the emulator typically executes 20,000 instructions before it briefly releases control to Windows, the response to a stop command may take a few seconds. The number of instructions executed at a time in Fast Run mode is a parameter in the EMUC6xx.ini file. [Local Parameters] nb_fast_instruction =20000 Run : This menu option, (key equivalent: CTRL+F8), allows the user to execute a portion of the program windows, until a breakpoint is encountered. The windows are refreshed after every instruction (animation), so that the execution speed is rather slow. If no breakpoint is encountered, the user can stop the program by hitting the STOP option (CTRL+F10) in the debug menu. Stop : This menu option, (key equivalent: CTRL+F10), allows the user to stop execution of a program that was running fast or animated. Do not use this option to halt a program that is running internally: use the "stop internal" option instead. Inspect : This menu option is explained in section 5.6.3 under Inspect Window. Show/Hide Op Codes : This menu option can be toggled to show or hide the opcodes in the program window. Find Hardware Breakpoint : Finds a hardware breakpoint from the list of hardware breakpoint. A Hardware Breakpoint dialog box is opened and the presently enabled hardware breakpoint is selected as active. This option is useful if you have multiple hardware breakpoint list but like to find which is currently active. Find Next Breakpoint : Finds the next software breakpoint from present search position (cyan highlighted text). If no software breakpoint is found, it gives an error Error: No more software breakpoint. There is no limit on software breakpoints. This operation does not change the program counter value. EPROM Program : This menu option launches the EPROM Programming Dialog (Figure 5-24), that allows the user to program a project on a chip.
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Software Emulator
Figure 5-25. EPROM Programming Dialog
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Software Emulator
Trace Mode : This menu option launches the Trace Mode Dialog (Figure 5-25), that allows that user to run the chip in trace mode, i.e., running an internal program on the chip while monitoring its execution on the scanport.
Figure 5-26. Trace Mode
Optional Trace Mode start program memory location (hex). If this value is not provided, execution starts from current PC value. Optional PC location where execution should stop. If "Stop After" field is used, program stops which ever occurs first.
This radio button is checked when trace mode is running.
Start tracing.
Optional number of clock cycles to execute from Start location. If "Stop at PC" field is used, program stops which ever occurs first. Saves the result of trace to a file with the name as project with extension .trc.
Stop tracing.
Exit Trace Mode
Run Internal : This menu option launches execution on the program actually programmed on the chip. In the case of MSP50P614/MSP50C614, program execution will stop if a hardware breakpoint is encountered. Otherwise, the user will have to stop execution by hitting the Stop icon, for example. IMPORTANT: The hardware breakpoint has to be located more that one cycle away from the current program counter location. For example, if the current PC is 0x0800, and the instruction at 0x0800 is a one cycle instruction (like NOP), then the closest location for a hardware breakpoint is at PC+2. If a breakpoint was set at address PC+1, it would be ignored by the system. NOTE: The code to execute must be present on the chip.
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Stop Internal : This menu option halts execution of an internal program. It provides an internal picture of the chip at the time the internal program execution was halted. Note that due to the asynchronous nature of this halt, one erroneous instruction may be executed before the chip actually stops. For the MSP50P614/MSP50C614 chip, it restarts the emulation mode and reads the CPU and RAM values. Execution can then proceed either in emulation mode, or in internal mode to the hardware breakpoint. NOTE: A hardware breakpoint must be set using SHIFT+RIGHT mouse click to the line of interest. Synchronize Project/Chip : This menu option compares the currently opened project object code with that in the program memory of the chip. The number of location not matched is displayed.
5.6.5
Initializing Chip
When the Chip is RESET, the hardware initializes the chip's I/O registers to a know state. But the data memory, accumulators, accumulator pointers, indirect registers and other system registers are at a random state. Register initializations are done by the Init menu. There are five initialization options (Figure 5-26), each of which is described below:
Figure 5-27. Init Menu Option
All except BP : This menu option initializes all internal registers and all RAM locations on the chip to zero (except PC which is set to start of program). It also resets the cycle counter. The program counter set at the value indicated by the start vector at address 0xFFFF. However, the breakpoints (if any) are not reset. This is the preferred initialization when a program is being debugged.
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Init RAM : Initializes the data memory values to zero including tag bits. Init Registers : Initializes all the system registers (excluding accumulators) to zero except PC which is initialized to start vector. Init Accumulators : Initializes all the accumulators to zero. Init All : This menu option initializes all internal registers and all RAM location in the chip. It also resets the cycle counter. The program counter is set at the value indicated by the start vector at address 0x7FFF.
5.6.6
Emulator Options
The Software emulator has some user setup options. The first four options are to setup screen fonts for CPU window, RAM Window, Program Window and Project Window. The Verbose C- - menu selection can be toggled to inhibit the insertion of extraneous comment lines in the assembly code generated by the C- - compiler. The Debugging option is checked, the monitor routine output is sent to a dump file. The Misc... menu option allows the user to set a certain number of options for the emulator. When this option is clicked, a dialog box appears (Figure 5-27). The Chip Select... option allows the users to force a choice between the MSP50P60 and MSP50P614/MSP50C614 development systems. Note that the development systems are automatically detected when the software is started, as long as the development board is connected and powered up. Default is MSP50P614. Windows related options are available in the Windows menu as shown in Figure 5-28.
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Software Emulator
Figure 5-28. Options Menu
Figure 5-29. Miscellaneous Dialog
List of directories separated by semicolons that the C-- compiler will search for include files enclosed in angle brackets (<>) before searching current directory. Heap start address for C-- compiler. Beginning of Stack for C-- compiler. Parallel port address where the Scanport interface is connected. Note that the emulator tries to autodetect the scanport
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Figure 5-30. Windows Menu Options
5.6.7
Emulator Online Help System
The emulator has an online help which is launched when the Help menu option is left clicked with a mouse. The help window (Figure 5-30) is context sensitive and graphical in nature. Any topic selected by pointing the mouse to the topic and clicking the left mouse button. If a help is available on the topic, the cursor becomes a hand cursor. Some help topics launches more context sensitive help windows. Learning to use the emulator is extremely fast using this graphical help system with minimal text to read.
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Figure 5-31. Context Sensitive Help System
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5.6.8
Known Differences, Incompatibilities, Restrictions
-
Include statements in assembly language files must enclose the file name in double quotes. REF/DEF statements in assembly language files should be replaced with EXTERNAL/GLOBAL statements, but the old REF/DEF are still supported. There is no default type for variables in the C- - compiler. The user should always use int or char. Typedef is not supported in C- - To use external functions in C- -, put a function prototype in the file that calls the external function. To use external variables in C- -, declare them as extern. Note that only the file containing the main routine can contain global variable declarations. If cmm6xx.asm is included in a project file, the resulting linked file will have a start vector address (address 0x7FFF) of _main1, corresponding to a line in cmm6xx.asm that forces a jump to _main0. The C- - compiler automatically defines a _main0 label just prior to forcing a call to _main, if there is a C- - file containing the main routine. If not, it is up to the user to define a _main0 label in one of the assembly language routines: this will be the starting point of the program.
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5.7 Assembler
The MSP50P614/MSP50C614 assembler is implemented as a Windows DLL (Dynamic Linked Library).
5.7.1
Assembler DLL
The current name of the DLL file is asm6xx.dll. It can be invoked from any Windows program, provided that the user included the file called asm6xx.lib in the Windows project. The syntax of the call is:
extern int FAR PASCAL ASM_MAIN (LPSTR source_file, short *warn,short *errpass1,struct error_struct *,LPSTR include_list); /* .... */ short i,w,pass1_error; LPSTR source_file; struct error_struct{ short pass; short type; short error_msg; /* pass where error was detected */ /* type of error (error, warning */ /* error message number */
short file_number; /* file number in object file table */ long line_number; /* line number in file where error occurred */
char info[MAXIDENTIFIER+1]; /* character string containing some */ /* information on the error */ }; struct error_struct error_list[MAX_ERRORS]; /* ..... */
i=ASM_MAIN(source_file,&w,&pass1_error,error_list,include_list);
Where:
-
source file is the assembly source file name. w is the number of warnings returned by the assembler.
pass1_error is the number of errors returned in pass 1 of the assembler.
error_list is a structure containing information about the errors detected by the assembler. include_list is the list of directories to search first for include files (separated by semicolons). i is the total number of errors returned by the assembler.
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Assembler
5.7.2
Assembler Directives
Assembler directives are texts which have special meaning to the assembler. Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the assembler to initialize variable with values, assigning symbols to memory location, assigning origin of a program, etc. The assembler directives that start with a # (hash) sign cannot have spaces before the directive. The following assembler directives are recognized by the assembler. Some of these assembler directives uses expression and symbol. These are explained below: expression can be any numeric value. Addition, subtraction, and multiplication are allowed. Examples: (128 / 2 ) * 2 + (220 / 5) + 2 + *0x200 equates to 0xAE + *0x200, where *0x200 indicates data memory location. (2 * 2 / 2 + ((5 * 2) * 3) / 2) | (0x0F & 0x04) equates to 0x15. Note that bitwise AND (& operator) and OR (| operator) operation is allowed. (10 * 2) + 5 * *0x120 expression points to data memory content at 0x120 and multiplies decimal 5 to it and finally adds decimal 20. Note that a space is required between successive asterisks (*). Also note that *0x120 indicates content of memory location at 0x120 hex. The grammer for expression and symbol is as follows:
number: number | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 expression: number | expression + expression | expression - expression | expression * expression | expression / expression | expression | expression | expression & expression | ~expression | -expression | +expression | *expression | (expression)
(~ indicates bitwise complement)
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symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples:
SYM1 SYM2 SYM3 EQU (12 * 256) EQU SYM1 * (32 / 4) EQU SYM1 * SYM2 - *0x200
From the above example SYM1, SYM2 and SYM3 are symbols for some expression. The grammar for Symbol is as follows:
symbol: expression | symbol
Expression Restrictions: It is recommended that a space be inserted between the operator (i.e., +, -, *, /, |, &) and the symbol or numeric expression to perform arithmetic and bitwise operations. For example ADD A0, A0, 1 + -2, adds a -1 to A0, because the argument is read as 1+(-2) = -1; but writing the argument as 1+-2 may or may not give the correct result. Outside parenthesis are not allowed in instruction arguments. For example, ADD A0~,A0~,(1 + (2 * 300) - 256) causes compile time syntax error. But removing the outside parenthesis i.e., ADD A0~,A0~, 1 + (2 * 300) - 256, causes no error. #ELSE: see #IF and #IFDEF #END_FT : This directive is created by the C- - compiler when it outputs assembly code to a file. It marks the end of the function table used to track function calls and C- - variables in the emulator. Users should NEVER use this directive in an assembly language program. #ENDIF: marks the end of a conditional assembly structure started by #IF or #IFDEF #IF expression: Start of a conditional assembly structure expression is an arithmetic expression that can contain symbols. Caution: since the conditional assembly is resolved during the first pass of the assembler, no forward referenced symbols should be used in a conditional assembly expression. If an expression is TRUE (non zero), then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered. If an expression is FALSE (equal to zero), then all input lines are skipped until a #ELSE or a #ENDIF directive are encountered. If a #ELSE directive is encountered first, all lines following it are assembled, until a #ENDIF directive is found.
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Example: #IF expression ; do something here #ELSE ; do other things here #ENDIF #IFDEF symbol: Start of a conditional assembly structure. If symbol has been defined (either with a #DEFINE directive or an EQU directive) then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered. If symbol has not been defined, then all input lines are skipped until a #ELSE or a #ENDIF directive is encountered. If a #ELSE directive is encountered first, all lines following it are assembled, until a #ENDIF directive is found. #IFNDEF: Start of a conditional assembly structure. If symbol has NOT been defined then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered. If symbol has been defined (either with a #DEFINE directive or an EQU directive), then all input lines are skipped until a #ELSE or a #ENDIF directive are encountered. If a #ELSE directive is encountered first, all lines following it are assembled, until a #ENDIF directive is found. Example: #IFDEF symbol ; do something here #ELSE ; do other things here #ENDIF #IFNDEF symbol ; do something here #ELSE ; do other things here #ENDIF #START_FT: This directive is created by the C- - compiler when it outputs assembly code to a file. It marks the beginning of the function table used to track function calls and C- - variables in the emulator. Users should NEVER use this directive in an assembly language program. AORG expression: Marks the start of an ABSOLUTE segment code, i.e., a segment that cannot be relocated by the linker. expression evaluates to the starting address of the absolute segment in the program memory.
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BYTE expression[,expression]: Introduces one or more data items, of BYTE size (8 bits) . The bytes are placed in the program memory in the order in which they are declared. CHIP_TYPE chip_name: This directive is here for compatibility with future chips in the same family. It defines some chip parameters (like RAM and ROM size) for the assembler. For now, the only defined chip names are MSP50P614/MSP50C614 and MSP50P614/MSP50C614. DATA expression[,expression]: Introduces one or more data items, of WORD size (16 bits) . The words are placed in the program memory in the order in which they are declared. Even though the program memory is 17 bits wide, only 16 bits can be read using assembly instructions (like MOV A0,*A0), so the DATA directive only stores 16 bits per data expression. DB expression[,expression]: Equivalent to BYTE directive DEF symbol[,symbol]: Equivalent to GLOBAL directive DW expression[,expression]: Equivalent to DATA directive END expression: Expression defines the start-up vector for the current assembly program. This directive generates the following assembly code; AORG 0xFFFF DATA expression which defines the start-up vector of the program, i.e., the program address where execution starts following INIT of the chip. label EQU expression: Associates the value of expression with label. EXTERNAL symbol[,symbol]: This directive is used to indicate to the assembler that one or more symbols are external references, i.e., symbols that will be resolved by the linker. GLOBAL symbol[,symbol]: This directive is used to indicate to the assembler that one or more symbols are global references. These symbols MUST be defined in the current file, and will be used by the linker to resolve external references (present in other files). GLOBAL should only be used for PROGRAM labels. RAM variables are handled with the GLOBAL_VAR directive. GLOBAL_VAR symbol[,symbol]: This directive can be used to allow for RAM variables to be referenced in a different file from where they were defined. GLOBAL_VAR should be used prior to defining a RAM variable (with the RESW directive, for example). The variable to be referenced in another file
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should be declared there as EXTERNAL (or REF). Note that this technique can also be used to make constants defined with the EQU statement available to other files. INCLUDE filename: This directive is used to insert another file in the current assembly file. The name of the file to be included must be enclosed in double quotes. If the file name itself is enclosed in angled brackets (< >), then the assembler will first look for the include file in the include directory list that is passed as an argument during the DLL call. LIST: The lines following this directive are included in the listing file (extension .lst) created by the assembler. REF symbol[,symbol]: Equivalent to EXTERNAL directive label RESB expression: This directive is used to reserve the number of bytes indicated by expression, starting at the current RAM address. Label is given the value of the current RAM address. label RESW expression: This directive is used to reserve the number of words indicated by expression, starting at the current RAM address. label is given the value of the current RAM address. If the current RAM address is not EVEN, the assembler increments it by 1 before allocating the desired amount. (Note that RAM locations are accessed by their BYTE address in MSP50P614/ MSP50C614 assembly language, i.e., word 1 is at address 2, etc...) RORG expression: Marks the start of a RELATIVE segment code, i.e., a segment that can be relocated by the linker, expression is an arbitrary number, but it must be present or an assembly error will occur. STRING text_string: Equivalent to the TEXT directive, but the text is terminated by a 0. (automatically done by the assembler) TEXT text_string: Equivalent to the BYTE directive, but the data are a text string enclosed in double quotes. UNLIST: The lines following this directive are NOT included in the listing file (extension .lst) created by the assembler.
5.8 Linker
The MSP50P614/MSP50C614 linker is implemented as a Windows dynamic linked library (DLL). The current name of the DLL file is link6xx.dll. It can be invoked from any Windows program, provided that the user included the file called link6xx.lib in the Windows project.
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The syntax of the call is:
extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTR exe_file); ..... ierr=LINK_MAIN (source_file,exe_file);
Where:
-
source_file is the project file name, which contains the names of the files to be linked. exe_file is the name of the linked executable file. ierr is the total number of errors returned by the linker.
If errors occur during link, the error information is placed in a file with extension .rer, with the same name as the executable file.
5.9 C- - Compiler
The MSP50P614/MSP50C614 C- - compiler is implemented as a Windows dynamic linked library (DLL). The current name of the DLL file is cmm6xx.dll. It can be invoked from any Windows program, provided that the user included the file called cmm6xx.lib in the Windows project. The syntax of the call is:
extern int FAR PASCAL CMM_MAIN (LPSTR source_file,short *warn,
struct cmm_input *,struct error_struct *);
/* ..... */ #define MAX_LEN 256 LPSTR source_file; short w,i; struct error_struct{ short pass; short type; short error_msg; short file_number; long line_number; char info[MAXIDENTIFIER+1]; }; struct cmm_input{ short heap_st; short stack_st;
/* pass where error was detected */ /* type of error (error, warning */ /* error message number */ /* file number in object file table */ /* line number in file where error occurred */ /* character string containing some */ /*information on the error */
/* start of heap */ /* start of stack */
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short ram_size; short verbose; short c_code; short optimize; char dir_list; char directory[MAX_LEN];
/* /* /* /* /* /* /* /* /*
ram size for the chip */ refers to assembly code output */ if non zero, c code is included as */ assembly language comments */ should always be non zero */ string of include directories searched */ for C- - include directive */ name of data directory, i.e directory */ where tools where installed */
}; struct error_struct error_list[MAX_ERRORS]; /* ... */ i=CMM_MAIN (source_file,&w,&input,error_list);
Where:
-
source file is the source file name. w is the number of warnings generated by the compiler. input is a structure that is used to pass some parameters to the compiler. error_list contains the errors generated by the compiler upon return (similar as the one used in the assembler). The C- - compiler generates an assembly language file of the same name, with extension .opt. It also generates a file with extension .glb where global variable initialization is taken care of, if the routine main was encountered in the current file. A file with extension .ext is also generated to take care of global and external declarations that will be used by the assembler. These two files are included in the .opt file generated by the C- - compiler. Note that all symbols defined in C- - source code are changed before being written to assembly language: an underscore character is put in front of the first character of each symbol. Also note that local labels created by the C- - compiler are built using the current source file name followed by an ordinal number. Consequently, to avoid problems at link time due to symbols bearing the same name, it is a good idea to never use symbol names starting with an underscore in assembly language files, and it is imperative to use file names that are different for C- - files (extension .cmm) and assembly language files (extension .asm).
5.9.1
Foreword
C-- is a high level language to be used with the MSP50P614/MSP50C614 microprocessor, and its spin offs. Although it looks a lot like C, it has some limitations/restrictions which will be highlighted throughout this document. This language is compiled into MSP50P614/MSP50C614 assembly language.
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5.9.2
Variable Types
Type Name Integer Character Array of integer Array of characters Pointer to integer Pointer to character
Notes:
Mnemonic int char int char int * char *
Range [-32768,32767] [0,255] Not Applicable Not Applicable Not Applicable Not Applicable
Size in Bytes 2 1 Not Applicable forced to even 2 2
Example int i,j; char c,d; int array[12]; char text[20] int *j; char *string;
1) There is a major difference between an MSP50P614/MSP50C614 integer string and an array of integers: an array of integers is an ordered set of n 16 bit integers, whereas an integer string of length n represents a single integer with 16*n bits. In C- -, MSP50P614/MSP50C614 strings are declared as arrays of integers, but must be operated upon using the special purpose string arithmetic functions described below. 2) As in regular C, the above types can be qualified with the word unsigned. 3) There is another important qualifier that is special to C- - : constant. We made the mnemonic purposely different from the usual C const qualifier, because it is not exactly equivalent. It is used to initialize arrays in program ROM. A good use of it would be for a sine table, for example. The syntax is simple, for example: constant int array[10]={1,2,3,4,5,6,7,8,9,10},dummy; 4) will create a series of DATA statements in the assembly language output file. Uninitialized constants (like dummy above) generate a warning and are initialized to zero. Constants are to be handled with care. Since they cannot be accessed the same way as RAM variables, special purpose functions have to be used to utilize constants in a program. The most general of these functions is xfer_const, which transfers values from the program ROM to the RAM. Also, constants MUST BE GLOBAL. BEWARE OF PASSING A CONSTANT AS AN ARGUMENT = DON'T DO IT !!!!! 5) The common C types float, struct, union and long are not implemented. (Note that long is a subset of string of integer).
5.9.3
External References
The fact that all RAM allocations in the assembler are global has the following implications for C- - variables:
-
Only the file containing the main routine can contain global variable definitions. Global variables referenced in other files must have been declared as external (keyword extern) at the beginning of the file. A function referenced in a file but not defined in that same file must be introduced with a function prototype in the file where it is referenced (no need for the extern keyword).
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C- - Compiler
5.9.4
C- - Directives
C- - has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler.
5.9.4.1
#define
This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement string for a given string Example: #define PI 3.1415926535 Every occurrence of the token PI will henceforth be replaced with the string 3.1415926535. If there is no replacement string, the given string is deemed defined: this can be used in conjunction with the #ifdef / #ifndef directives. It is also possible to undefine a macro with the #undefine directive. With Arguments: The macro name must be immediately followed by a pair of parenthesis, which introduces the arguments. This is completely compatible with the usual C definition. Example: #define modulo(i,j)
(i%j)
Every occurrence of the word modulo followed by an expression in parentheses will be replaced by (i%j), where i is the first argument in the parenthesis, and j the second argument. modulo((a*b),c) will thus be replaced by ((a*b)%c).
5.9.4.2
#undefine
The string following this directive is removed from the list of macros. There is no warning if the string is not found in the macro list.
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5.9.4.3
#include
As in regular C, this directive allows for the insertion of a file into the current file. If the file name that follows is enclosed in < >, the system searches the include directories for the file, otherwise, if it is enclosed in " ", the current directory is searched. Example: #include "file.h" #include The include directories are defined on the cmm_input structure passed to the compiler. There is no limit to the nesting of include files.
5.9.4.4
#asm
All text following this directive is inserted as is in the output file, and is considered as assembly language (hence not compiled). The insertion continues until a #endasm directive is found. Note that both #asm and #endasm must be at the beginning of a line, and that all text following them on the same line is ignored.
5.9.4.5
#endasm
Signals the end of assembly language insertion. Must be paired with a #asm directive.
5.9.4.6
#ifdef, (#ifndef)
Starts conditional assembly if token following it has been defined (not been defined) by a #define directive. These directives are terminated by a #endif directive, and can be coupled with a #else directive, as in regular C. Note that the test can only check if the named token is currently defined or undefined.
5.9.4.7
#if
Starts conditional assembly if expression following it evaluates to a non zero value. This directive is terminated by a #endif directive, and can be coupled with a #else directive, as in regular C.
5.9.4.8
#else
See #if directive.
5.9.4.9
#endif
Must be present to terminate a #ifdef or #ifndef directive
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5.9.5
Include Files
There are currently two include files supplied with C- -, cmm_func.h, which contains function prototypes for the C- -functions and cmm_macr.h which contains some predefined macros. Both files are listed below:
/********************************/ /* Prototypes for C- -functions */
/********************************/
cmm_func cmm_func cmm_func cmm_func cmm_func cmm_func cmm_func add_string(int *result,int *str1,int *str2,int lg); sub_string(int *result,int *str1,int *str2,int lg); mul_string(int *result,int *str1,int mult,int lg1,int lgr); umul_string(int *result,int *str1,unsigned int mult,int lg1,int lgr); or_string(int *result,int *str1,int *str2,int lg); and_string(int *result,int *str1,int *str2,int lg); xor_string(int *result,int *str1,int *str2,int lg);
cmm_func not_string(int *result,int *str1,int lg); cmm_func neg_string(int *result,int *str1,int lg); cmm_func copy_string(int *output,int *input,int lg);
cmm_func rshift_string(int *output,int *input,int rshift,int lg);
#ifdef _CMM cmm_func strcpy(char *outstring,char *instring); cmm_func strlen(char *instring); cmm_func calloc(int nitems,int size); cmm_func malloc(int size); cmm_func free(int *ptr); #endif
cmm_func test_string(int *string1,int *string2,int lg,int oper);
cmm_func xfer_const(int *out,int *cst_addr,int lg); cmm_func xfer_single(int *out,int *cst_addr); /********************************/
Note the requirement that C- - function declarations (including main, of course) be preceded by the keyword cmm_func. Also note the conditional assembly portion, used for compatibility with Borland C.
/******************/
/* Macros for C- - */ /******************/
#define STR_LENGTH(i) (i-2) /******************/ Major Differences between C and C- - Although we have tried to keep the differences between regular C and C- - to a minimum, there are still a few that require some explanations.
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5.9.6
Function Prototypes and Declarations
As mentioned above, C- - function prototypes and declarations MUST be preceded with the keyword cmm_func. Also, since all functions return through accumulator A0, all functions are of type integer, so that the function type can be omitted in the function declaration. If present, it is ignored anyway. Trying to typecast a function as returning a pointer will result in a compiler error. Note: To change a C- - program back into a regular C program (at least from the point of view of function prototypes and declarations), the following line can be inserted at the beginning of the C- -program: #define cmm_func A library of regular C functions to substitute for the special MSP50P614/ MSP50C614 functions is supplied with the C- - compiler, allowing the user to compare the results of regular C programs with those of C- -programs. The library is contained in the C source file cmm_func.c .It should be linked with the C equivalent of the C- - program, and run in Borland C.
5.9.7
Initializations
Due (in part) to the architecture of the MSP50P614/MSP50C614 processor, initialization is only allowed for global variables. As a side effect, local static variables are not allowed. For example, a global array can be declared and initialized as follows: int int_array[5]={1,2,3,4,5}; Initialization values are store in program memory.
5.9.8
RAM Usage
RAM location 0 is reserved (and used intensively) by the compiler. The choice of location 0 does not conflict with the usual definition of a NULL pointer.
5.9.9
Variable Types
As mentioned above, there are strong restrictions to the variable types that are recognized by C- -.
5.9.10 String Functions
Arithmetic string functions are special functions that perform string arithmetic, of all things. The functions currently implemented are shown in Table 5-1.
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Table 5-1. String Functions
add_string(int *result,int *str1,int *str2,int lg)adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the result in string result. mul_string(int *result,int *str1,int mult,int lg1,int lgr)multiplies string str1 of length lg1 (+2) by integer multiple, and puts the result in string result, of length lgr (+2). umul_string(int *result,int *str1,int mult,int lg1,int lgr) same as previous one, with UNSIGNED multiply or_string(int *result,int *str1,int *str2,int lg) ors strings str1 and str2, of length lg (+2), and puts the result in string result. and_string(int *result,int *str1,int *str2,int lg) ands strings str1 and str2, of length lg (+2), and puts the result in string result. xor_string(int *result,int *str1,int *str2,int lg) exclusive ors strings str1 and str2, of length lg (+2), and puts the result in string result. not_string(int *result,int *str1,int lg) takes the 1's complement of string str1, of length lg (+2), and puts the result in strings result. neg_string(int *result,int *str1,int lg) takes the 2's complement of string str1, of length lg (+2), and puts the result in strings result. test_string(int *string1,int *string2,int lg,int oper) performs a logical test (operation) on strings string1 and string2 of length lg (+2). The logical value is returned in A0. If string2 is NULL, the logical test is performed between string string1 and a zero string. operator can take the following values: (predefined constants) EQS_N == ? NES_N !== ? LTS_N < ? LES_N <= ? GES_N >= ? GTS_N > ? ULTS_N < ? (unsigned) ULES_N <= ? (unsigned) UGES_N >= ? (unsigned) UGTS_N > ? (unsigned)
A major feature of the MSP50P614/MSP50C614 is that the string length present in the string register is the actual length of the string minus two. To avoid confusion, a macro is supplied that automatically translates the real length of the string to the MSP50P614/MSP50C614 length of the string. It is included in the cmm_macr.h file, and is called STR_LENGTH(lstr). For example, STR_LENGTH(8) is 8-2 = 6.
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Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string. Unpredictable results may occur if parameter lgr is not at least equal to lgr+1.
5.9.11 Constant Functions
The only two constant functions implemented in C- - are xfer_const and xfer_single. cmm_func xfer_const(int *out,int *constant_in,int lg) It transfers lg+2 integers from program ROM starting at address constant_in to RAM, starting at address out. Note that constant_in is not doubled, because it is used in A0 in a MOV A0,*A0 operation. The C- - compiler takes care of this. cmm_func xfer_single(int *out,int *constant_in) transfers a single value. An example of the use of xfer_const is:
int array[8],i; const int atan[80*8] ={.........640 integers ); /* .... */ for(i=0;i<80;i++){ xfer_const(array,&atan[i*8],STR_LENGTH(8)); /* ... now use array normally ..... */ }
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5.10 Implementation Details
This section is C- - specific.
5.10.1 Comparisons
We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~. CMP A0,A0~ : A0 contains a, A0~ contains b
A0 5 5 0 1 0 5 FFFF 0 FFFF FFFF FFFE A0~ 0 1 5 5 0 5 0 FFFF FFFF FFFE FFFF ACO 1 1 0 0 1 1 1 0 1 1 0 AZ 0 0 0 0 1 1 0 0 1 0 0 ANEG 0 0 1 1 0 0 1 0 0 0 1
-
Signed comparison of a and b. (a is in A0, b is in A0~)
Assembly _eq _ne _lt _le _ge _gt Test a=b a != b a= b a>b Condition AEQ !AEQ ALZ !AGT !ALZ AGT
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-
Unsigned comparison of a and b. (a is in A0, b is in A0~)
Assembly _ult _ule _uge _ugt Test a= b a>b Condition AULT !AUGT !AULT AUGT
The small number of comparisons was an invitation to use them as vector calls. We return a 1 or 0 in A0 as the result of the comparison, and also set flag 2 if the comparison is true. The flag is not currently used by the compiler. It is important to note that functions return their results via A0, but there is no guarantee that the absolute value of the A0 pointer is not changed by the function. To compare integers a and b: after loading a in A0, and b in A0~, do a vector call to the appropriate comparison routine:
Assembly _eq _ne _lt _le _ge _gt _ult _ule _uge _ugt _lneg Vector 0 1 2 3 4 5 6 7 8 9 10
We return the result of the comparison in Flag 2 ( set for TRUE, reset for FALSE), and in A0 (1 for TRUE, 0 for FALSE). We have also implemented vector calls for string comparisons. There are a few C callable routines that make use of those calls. (test_string, or_string, and_string, xor_string, neg_string, not_string)
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5.10.2 Division
The integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We return the quotient in A0~, and the remainder in A0. We make use of A3~ and A3 for scratch pads. We also set flag 1 if a division by zero is attempted, and zero out the quotient and the remainder in this case. We also use PH for temporary storage of the divisor.
5.10.3 Function Calls
Every function is associated with a stack frame. A regular C program is initially given control by a call to main(). A C- - program starts with a jump to the _main symbol, which must therefore be present in the C- - source code. The stack frame has the following structure:
First Argument
***
Low Address

Last Argument Return Address BP Previous BP Locals SP
High Address
BP is the frame pointer (base pointer), SP the stack pointer. We use R7 for stack pointer, and yet another register for BP, REG_BP (R5, because of its special arithmetic capabilities). Before a function is called, the arguments are pushed on the stack, first argument first. The function call automatically pushes the return address on the stack. Immediately upon entering the function body, the current BP is pushed on the stack to preserve it, so that the stack pointer now points to the next location. This location is copied to REG_BP, which becomes our fixed reference point for the current function. Locals are then allocated on the stack from this starting location. When the function returns, SP is made to point to the return address, after the previous BP is popped. The return is performed by a RET instruction. The calling routine is then responsible for moving the stack pointer to its previous location, before the arguments were put on the stack. Because all functions return via A0, the only function return type allowed is integer. Our implementation of C- - allows for function prototyping, and checks that prototyped functions are called with the correct number of arguments.
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Function declarations ( or function prototypes) are introduced by the mnemonic cmm_func. We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function's parentheses. For example: cmm_func bidon(int i1,char *i2) is valid, but: cmm_func bidon(i1,i2) int i1,char *i2; is invalid. Note: The exact implementation of the MSP50P614/MSP50C614 stack is as follows: on CALL: 1) Increment R7 2) Transfer TOS (top of stack) register to *R7 3) Transfer return address to TOS register on RET: 1) next PC = TOS 2) transfer *R7 to TOS 3) decrement R7 We can freely manipulate R7 before a CALL/Ccc and after a RET to load and unload arguments to and from the stack. Of course, it would be a bad idea to mess with the TOS register in the body of a function.
5.10.4 Programming Example
The following example implements string multiplication (i.e, the multiplication of 2 integer strings). The same source file (with the exception of the first line) can be used for C- - or regular C. In the case of regular C, it has to be compiled and linked with cmm_func.c
#define _CMM /*must be present for C- -compiler ONLY*/ #ifdef _CMM #else #include #include #include #include #include "cmm_back.h" #endif #include "cmm_func.h" #include "cmm_macr.h"
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constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) { /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multiplies string m1 of length lgm1+2 by string m2 of length lgm2+2, and puts the result into string p, of length lgp+2 */ int sign,i,j; int *mm1,*mm2,*pp; sign=1; mm1=calloc(sizeof(int),lgm1+2); mm2=calloc(sizeof(int),lgm2+2); pp =calloc(sizeof(int),lgp+2); if(test_string(m1,0,lgm1,LTS_N)) { neg_string(mm1,m1,lgm1); sign*=-1; } else copy_string(mm1,m1,lgm1); if(test_string(m2,0,lgm2,LTS_N)) { neg_string(mm2,m2,lgm2); sign*=-1; } else copy_string(mm2,m2,lgm2); for(j=0;j5-52
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free(mm2); free(pp); } cmm_func main(int argc,char *argv) { int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); }
5.10.5 Programming Example, C -- With Assembly Routines
There are several important considerations when using the C- - compiler. The ram allocation must be coordinated so that a location is not accidentally used twice. In assembly this is usually done with IRX files by making each label equal to the location of the previous one, plus whatever storage space is needed. All of the IRX files for a project are then combined in a master IRX file so that the space for each sub file can be allocated. For example ( a master IRX file ): RAM_SIZE equ 640 STACK equ 2 * (RAM_SIZE - 14) BEGIN_RAM equ 0 RESERVED equ BEGIN_RAM + 2 * 1 RAMSTART_INT include RAMSTART_ASM include equ RESERVED "..\inter\inter_ram.irx" equ RAMEND_INT ". .\asm_ram.irx"
Here the sub files are inter_ram.irx and asm_ram.irx. The allocation for inter_ram.irx begins at memory location 2. This is because the memory location 0 is reserved for use by the C- - compiler. The allocation for asm_ram.irx begins where the allocation ended for inter_ram.irx. More irx files can be chained on in this manner, and all of the allocation is kept organized. When C- - is added to a project, it is important to make sure that the C- - variables are not allocated in locations already used by assembly variables. This is accomplished with a dummy array, bogus, located in the file ram.irx. It is simply an integer array that is included in the C- - program so that it is the first variable allocated. By making its size equivalent to the amount of memory used for assembly variables, the C- - variables that the user defines are allocated in unused memory. It can be set by building the project and finding the location of the last assembly variable. This can then be converted from hexadecimal to decimal and divided by two ( because a C- - int is 16 bits ) to
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find the correct size for bogus. Bogus can be made larger for extra safety as long as enough memory is left over for the C- - variables and the stack. If space allows, it is a good idea to add a few extra words to bogus in case assembly variables are added to the project without modifying bogus. It is also important not to alter the contents of registers R5 and R7. R7 is the stack pointer and R5 is a frame pointer used in C to C function calls. Parameters are passed on the stack and the return value is always int and always located in a0. The stack usage for function calls is as follows. C to C function call. The stack is shown after the operation on the bottom is performed.
| || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || || | |---------------| |---------------| |---------------| | || |R7|Param 2 | |---------------| |---------------| |---------------| | || | |Param 2 | |---------------| |---------------| |---------------| | |R7|Param 1 | |Param 1 | |---------------| |---------------| |---------------| | | |Param 1 | |Param 1 | |---------------| |---------------| |---------------| R7,R5 |Stack data |R5|Stack data |R5|Stack data | |---------------| |---------------| |---------------| Before call Parameter 1 Parameter 2
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|--------------| |
|--------------|
|--------------| |
|R7 |
|R5,R7 |
|--------------| | |
|--------------| | |
|--------------| | |
|--------------| | |
|--------------| | R5 |
|--------------| |(old)R5 |<- This is the SP
|--------------| | |
|--------------| | R5 |
|--------------| before the |(old)R5 |C function call.
|--------------| R7 |Return Addr |
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| R5 |Stack data
|--------------| |
|--------------| |Stack data |
|R5 |Stack data
|--------------| Function call
|--------------| ADDB R7,2 MOV *R7++,R5
|--------------| MOV *0,R7 MOV R5,*0
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C to C function return (in cmm_return).
| | | | | | | | | | | |
|--------------| R5 | |
|--------------| | |
|--------------| | |
|--------------| | |
|--------------| | |
|--------------| | |
|--------------| R7 |(old)R5 |
|--------------| |(old)R5 |
|--------------| |(old)R5 |
|--------------| |(old)R5 |
|--------------| |(old)R5 |
|--------------| |(old)R5 |
|--------------| |Return Addr
|--------------| |
|--------------| |Return Addr |
|R7 |Return Addr
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Return Addr |
|--------------| |Param 2 |
|--------------| |Param 2
|--------------| |
|R7 |Param 2
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 2 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Param 1 |
|--------------| |Stack data
|--------------|
|--------------| |
|R5 |Stack data
|R5 |Stack data
|--------------| SUBB R7,2
|--------------| MOV A0~,*R7-- MOV *0,A0~ MOV R5,*0
|--------------| RET
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R7,R5
|--------------| | | |--------------| | | |--------------| | | |--------------| |(old)R5 | |--------------| |(old)R5 | |--------------| |Return Addr | |--------------| |Return Addr | |--------------| |Param 2 | |--------------| |Param 2 | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data | |--------------| SUBB R7,4
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C to ASM function call. The stack is shown after the operation on the bottom is performed.
| | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | |R7 |--------------| | | |--------------| |Stack data |R5 |--------------| Before call | | |--------------| | |--------------| | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| | |R7 |--------------| | | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data |R5 |--------------| Parameter 1 | | |--------------| | | | |--------------| | | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| |Param 2 | |--------------| |Param 2 | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data | |--------------| Parameter 2
R7,R5
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R7
R5
| | |--------------| | | |--------------| | | | | |--------------| | | |--------------| |Return Addr | |--------------| |Return Addr | |--------------| |Param 2 | |--------------| |Param 2 | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data | |--------------| Function call
C to ASM function return
| | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| |Return Addr | |--------------| |Return Addr | |--------------| |Param 2 | |--------------| |Param 2 | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data |R7,R5 |--------------| RET | | |--------------| | | |--------------| | | |--------------| | | |--------------| | | |--------------| |Return Addr | |--------------| |Return Addr | |--------------| |Param 2 | |--------------| |Param 2 | |--------------| |Param 1 | |--------------| |Param 1 | |--------------| |Stack data | |--------------| SUBB R7, 4
R7
R5
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To call an assembly routine from C- -, the routine must be defined as GLOBAL in the assembly file and as a CMM_FUNC in the C- - file. The following contains C- - callable assembly routines for accessing the I/O ports, and a wait routine. A C- - program which calls the assembly routines is also provided.
RORG 0x0
GLOBAL _wait GLOBAL _asminit GLOBAL _oport GLOBAL _iport GLOBAL _cport GLOBAL TIMER1_ISR, DAC_ISR GLOBAL TIMER2_ISR, PORTD2_ISR GLOBAL PORTD4_ISR, PORTD5_ISR GLOBAL PORTD3_ISR, PORTF_ISR GLOBAL reset, DUMMY_ISR EXTERNAL _main0 include "ram\ram.irx" include "control\control.irx" include "control\io_ports.irx" include "control\control.asm" ;**************************************************************** ; Reset ; Begin at init614 in INIT.ASM. ; This sets the 614 to run at 8 MHz, 10 bit DAC at 8 kHz reset ;***************************************************************** reset include ".\control\init.asm" ;**************************************************************** ; _MAINASM ; The start of the assembly code, which is called from ; main routine in main.cmm ;**************************************************************** _asminit nop ;pause for breath nop nop out IFR,a0 ;clear all interrupt flags ;**************************************************************** ; Main program ;**************************************************************** mainbegin mov r4,1000 * 2 ;pause for a second call _wait ; Set TIMER2 to run from the RTO/CTO (32 kHz) and with a one second period in a0,IntGenCtrl or a0,TIM2REFOSC ;set bit 9, CTO clock (32 kHz) out IntGenCtrl,a0 INTE ;enable all interrupts ret
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;----------------------------------------------------- ; called from C-- ; void oport(char Port, int Data) ; Writes Data to the I/O port specified by the letter Port. ; Example: ; oport('B', 0xAA); //Write 0xAA to port B. ;----------------------------------------------------- _oport mov a0, *r7 - 4 ; port address mov a0~, *r7 - 2 ; data add a0, _out_port_access - 'A' ; find the location in the table mov a0, *a0 ; get the value of the label in the table jmp *a0 ; jump to the label from the table _prta out 0x00, a0~ ; write to PortA ret _prtb out 0x08, a0~; write to PortB ret _prtc out 0x10, a0~ ; write to PortC ret _prtd out 0x18, a0~ ; write to PortD ret _prte out 0x20, a0~ ; write to PortE ret _out_port_access ; table for table lookup DATA _prta DATA _prtb DATA _prtc DATA _prtd DATA _prte ;----------------------------------------------------- ;----------------------------------------------------- ; called from C-- ; int iport(char Port) ; Reads data from the I/O port specified by the letter Port. ; Example: ; int data = iport('F'); //Read port F. ;----------------------------------------------------- _iport mov a0, *r7 - 2 ; port address add a0, _in_port_access - 'A' ; find the location in the table mov a0, *a0 ; get the value of the label in the table jmp *a0 ; jump to the label from the table _iprta in a0, 0x00 ; read from PortA ret _iprtb in a0, 0x08 ; read from PortB ret
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_iprtc in ret _iprtd in ret _iprte in ret _iprtf in a0, 0x28 ; read from PortF ret _in_port_access ; table for table lookup DATA _iprta DATA _iprtb DATA _iprtc DATA _iprtd DATA _iprte DATA _iprtf ;----------------------------------------------------- ;----------------------------------------------------- ; called from C-- ; void cport(char Port, int Control) ; Writes Control bits for the I/O port specified by the letter Port. ; Example: ; cport('B', 0xFF); //Configure all bits of Port B as output ;----------------------------------------------------- _cport mov a0, *r7 - 4 ; port address mov a0~, *r7 - 2 ; data add a0, _cont_port_access - 'A' ; find the location in the table mov a0, *a0 ; get the value of the label in the table jmp *a0 ; jump to the label from the table _cprta out 0x04, a0~ ; write to PortA control ret _cprtb out 0x0C, a0~ ; write to PortB control ret _cprtc out 0x14, a0~ ; write to PortC control ret _cprtd out 0x1C, a0~ ; write to PortD control ret _cprte out 0x24, a0~ ; write to PortE control ret _cont_port_access ; table for table lookup DATA _cprta DATA _cprtb DATA _cprtc DATA _cprtd 5-62 a0, 0x20 ; read from PortE a0, 0x18 ; read from PortD a0, 0x10 ; read from PortC
Implementation Details
DATA _cprte ;----------------------------------------------------- ;----------------------------------------------------- ; called from C-- ; void wait(int msec) ; waits for the amount of msec passed ; Calls: wait1ms ;----------------------------------------------------- _wait mov a0, *r7 - 2 shlac a0, a0 mov *tempa, a0 mov r4, *tempa _rep call wait1ms ;wait 1ms jrnzp _rep,r4-- ;decrement counter by 2 ret ;----------------------------------------------------- ;**************************************************************** ; Pause for 1ms ; ; Input ; Output ; Uses ; Calls wait200us ;**************************************************************** wait1ms call wait200us call wait200us call wait200us call wait200us call wait200us ret ;**************************************************************** ; Pause for 200us ; ; Input ; Output ; Uses ;**************************************************************** wait200us rpt 256-2 nop rpt 256-2 nop rpt 256-2 nop rpt 256-2 nop rpt 256-2 nop rpt 256-2 nop rpt 64-2
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nop ret ;**************************************************************** ; Dummy interrupt routines ;**************************************************************** DAC_ISR TIMER2_ISR TIMER1_ISR PORTD2_ISR PORTD3_ISR PORTF_ISR PORTD4_ISR PORTD5_ISR DUMMY_ISR nop INTE iret Here is a sample C-- file that accesses the routines. #ifdef DOC_FILE #******************************************************************************* #File: main.cmm # #Version: Release 1.00 25 MAY 99 # #Description: Main routine for 614 lock demo # Demonstrates use of assembly routines with C-- # Utilizes the microswitches and LED's on a Speech # Code Development Unit. Waits for user input on the switches. # The correct sequence is MS7, MS9, MS7, MS10. If the correct # sequence is detected then all LED's will light for 5 seconds. # As soon as an incorrect sequence or portion of the sequence is # detected the LED's will flash and the procedure will repeat. # Due to the indication of an incorrect sequence partway through, # there are only 4! combinations needed to find a sequence of length 4. # The difficulty of determining the code could be increased greatly by # using multiple key combinations (MS7 and MS8 simultaneously for example ) # or by only indicating an incorrect code after the sequence is complete. # #Revisions: # #Copyright: (c) Copyright 1999 Texas Instruments, Inc. # All Rights Reserved #******************************************************************************* #endif #include "ram\ram.h" cmm_func asminit(); cmm_func wait(int x) ; // wait function ( x is ms) cmm_func oport(int x, int y) ; // output to a port cmm_func cport(int x, int y) ; // configure a port 5-64
Implementation Details
cmm_func iport(int x); // read a port int i,j,k,l; // various temp and loop variables int x[4]; // array holding the correct key sequence int locked=1; //variable returned by lock() cmm_func lock(){ x[0]= 0xEF; //MS7 x[1]= 0xBF; //MS9 x[2]= 0xEF; //MS7 x[3]= 0x7F; //MS10 locked=0; cport('B', 0xFF);
//Configure port B as output. //Port B is the LED's on the //code development unit.
oport('B', 0xFF); //Turn off all 4 LEDs. for (i=0; i<4; i++){ // loop through all required inputs k=iport('F'); // read port F while( k == 0xFF ){ // wait for keypress k=iport('F'); // read port F oport('B', k); // output the value from F wait(100); // delay 100ms for key debouncing } l=iport('F'); // read port F while( l != 0xFF ){ // wait for key release wait(100); // delay 100ms for key debouncing l=iport('F'); // read port F } if (x[i] != k) { // compare to correct input locked=1; // if incorrect then lock and return return locked; } } // end for (i=0; i<4; i++){ return locked; // If the program reaches this return then all inputs were correct // and the main program can unlock. } cmm_func main() // code begins executing here after init614.asm is executed { asminit(); // configure everything cport('B', 0xFF); //configure port B as output for (j=0; j<1000; j++){ //semi-infinite loop if (lock()){ // get input and see if correct // if lock()==1 the input was incorrect // The LED's are then flashed and the program repeats. oport('B', 0x00); wait(100); oport('B', 0xFF); wait(100); oport('B', 0x00); wait(100); oport('B', 0xFF);
Code Development Tools
5-65
Implementation Details
wait(100); oport('B', wait(100); oport('B', wait(100); oport('B', wait(100); oport('B', wait(100);
0x00); 0xFF); 0x00); 0xFF);
} else{ // If the correct inputs were given. oport('B',0x00); // Light all LED's wait(5000); // Keep lit for 5 seconds ( unlock the door ) } } // end for return; }
5-66
Beware of Stack Corruption
5.11 Beware of Stack Corruption
MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get corrupted if care is not taken. Notice the following table read code:
SUBB R7, 4 MOV A0, *R7-- ADD A0, address MOV A0, *A0 ADD A0, *R7-- MOV A0, *A0 RET
This code will work perfectly well if no interrupts happen before SUBB and MOV instruction. If interrupts do happen between SUBB and MOV instructions, the parameter in the stack is corrupted by the return address pushed by the hardware. This problem may not be easily observed in the system level. But once it happens, it is very difficult to debug. Use the following method to modify stack pointer instead:
MOV A0, *R7 + -2 * 2 ADD A0, address MOV A0, *A0 ADD A0, *R7 + -2 * 1 MOV A0, *A0 RET
This method will not have the stack corruption problem since the MOV instruction performs the entire operation either before or after an interrupt.
5.12 Reported Bugs With Code Development Tool
The following are the reported bugs for code development tool version 2.14. Breakpoint: Hardware breakpoint within two instruction cycles after the IDLE instruction causes the program to hang. Avoid putting breakpoint after IDLE instruction within two instruction cycle.
Code Development Tools
5-67
5-68
Chapter 6
Applications
This chapter contains application information on application circuits, processor initialization sequence, resistor trim setting, synthesis code, memory overlays, and ROM usage.
Topic
6.1 6.2 6.3 6.4
Page
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 MSP50C614/MSP50P614 Initialization Codes . . . . . . . . . . . . . . . . . . . . 6-4 Texas Instruments C614 Synthesis Code . . . . . . . . . . . . . . . . . . . . . . . . 6-8 ROM Usage With Respect to Various Synthesis Algorithms . . . . 6-14
6-1
Application Circuits
6.1 Application Circuits
Minimum Circuit Configuration for the C614/P614 Using Resistor-Trimmed Oscillator To pin 1 of Scan Port Connector 5V (optional )
0.1 F (5)
To pin 2 of Scan Port Connector 1N914 (optional )
5 VDD VPP (MSP50P614 only) 100 k OSCIN RREFERENCE 470 k (1%) OSCOUT MSP50C614/ MSP50P614 PLL DACP VSS 3300 pF 5 DACM 32 1 F 20% RESET
5V
1N914
1 k Reset Switch
The diode across VDD and VPP may be omitted (shorted), if the application does not require use of the Scan Port Interface. The same applies for the 1 k resistor which appears at the RESET pin; the resistor may be shorted if not using the Scan Port. However, the footprint for the resistor is strongly recommended for any C614 production board. Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7.
Note that there are 5 each of the pins VDD and VSS. Each of these should be connected, with separate decoupling capacitors (0.1 F) included for each VDD.
6-2
Application Circuits
It is of particular importance to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. An alternate circuit, for better clock-precision and better battery life, includes a crystal oscillator:
Minimum Circuit Configuration for the C614/P614 Using Crystal-Referenced Oscillator 5V To pin 1 of Scan Port Connector (optional )
0.1 F (5)
1N914
To pin 2 of Scan Port Connector (optional )
5 VDD 22 pF VPP (MSP50P614 only) 10 M OSCIN 32 kHz 10 M OSCOUT 22 pF PLL DACP VSS 3300 pF 5 DACM 32 MSP50C614/ MSP50P614 1 F (20%) RESET 100 k
5V 1N914
1 k Reset Switch
The diode across V DD and VPP may be omitted (shorted), if the application does not require use of the Scan
Port Interface. The same applies for the 1 k resistor which appears at the RESET pin; the resistor may be shorted if not using the Scan Port. However, the footprint for the resistor is strongly recommended for any C614 production board. Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7.
Applications
6-3
MSP50C614/MSP50P614 Initialization Codes
In any C614 application, it is important for certain components to be located as close as possible to the C614 die or package. These include any of the decoupling capacitors at VDD (0.1 F). It also includes all of the components in the crystal-reference network between OSCIN and OSCOUT (22 pF, 10 M, 32 kHz).
6.2 MSP50C614/MSP50P614 Initialization Codes
Before any kind of application code can be written, the MSP50C614/ MSP50P614 processor state must be initialized. The initialization code is init.asm, where file extension .asm is for an assembly language file. The entry point to the initialization routine is INIT_DEVICE_614. This entry point must not be called (call INIT_DEVICE_614). A jump to this routine should be used (jmp INIT_DEVICE_614). After the end of initialization, the routine always jumps to the _main, which is the beginning of MSP50P614/ MSP50C614 user code. It is recommended that INIT_DEVICE_614, is performed immediately after RESET to ensure that device initialization is always performed at RESET. Users modifying the initialization routine is not recommended. The initialization routine does the following:
-
-
Disables all interrupts. Zeros out all accumulators. Zeros out all memory. Starts oscillators at frequency 8.192 MHz. If CRO_FLAG is 1, then crystal oscillator is started. If CRO_FLAG is 0, then the resistor trim oscillator is started. If resistor trim oscillator is chosen in P614 part, then RESISTORTRIM must be defined by the user (this value is written under the P614 part). If the C614 part is used, then the resistor trim is read from I/O location RTRIM (0x2F). Delays execution of the core for 200 ms for PLL to stabilize. Zeros out system registers. Finally jumps to the label _main.
WARNING If P614 parts are used for development, then the user MUST CHANGE the resistor trim initialization to read from port 0x2F when switching to the C6xx part.
6-4
MSP50C614/MSP50P614 Initialization Codes
6.2.1
File init.asm
;**************************************************************** ; INIT.ASM ; ; ; Copyright: 1998 Texas Instruments, Inc. All rights reserved. ; ; ------------------------------------------------------------------------- ; This Initialization Routine has the following Dependent Files. ; These should be "included" once within the MAIN program .ASM file: ; ; IMPORTANT: ; Texas Instruments reserves the right to change this routine at any time ; without notice. ; ------------------------------------------------------------------------- ; This Initialization Routine performs the following Functions: ; ; 1. Disable interrupt. ; 2. Zeros all accumulators. ; 3. Clears memory ; 4. Starts PLL with clock frequency defined by PLLMBITS. Appropriately ; sets the RTO trim bits (for C614 only). Switch to idle mode for 200ms ; for PLL to stabilize. ; 5. If DAC interrupt is replaced by Timer 1 interrupt, the period of ; timer 1 is stored in TIM1 register. ; 6. Zeros all system registers except R7 (STACK). ; ; Turn off TIMER 2 rather than leave it running. ; ; Modified to cope with 6 bit trim value. Top 5 bits go to bits ; 15-11 in ClkSpdCtrl, LSB of trim goes to bit 9 in ClkSpdCtrl. ; ; A fairly basic but compact initialization routine for the 614. ; This sets the 614 to run at 8 MHz, 10 bit DAC at 8 kHz. ; ;**************************************************************** C614FLAG EQU 0 ;EQU 1 if MSP50C614 part RESISTORTRIM EQU 0x20 ;Resistor trim value for MSP50P614 ONLY! CRO_FLAG EQU 0 ;EQU 0 : for resistor-trimmed osc, RTO ;EQU 1 : for external crystal ref, CRO PLLMBITS EQU 0x7C ;For CPU clock of 8MHz ;**************************************************************** ; Start off by clearing all the RAM (and tags) and then zero ; every register. The status register (STAT) must be cleared ; immediately upon power up. ;**************************************************************** init614 zac a0 ;clear a0 mov *0x000,a0 ;clear first RAM location mov STAT,*0x000 ;clear status register mov STR,32-2 ;set string register to loop 32 times zacs a0 ;clear all accumulators out IFR,a0 ;clear pending interrupts
Applications
6-5
MSP50C614/MSP50P614 Initialization Codes
out IntGenCtrl,a0 ;clear all interrupt mask bits, disable timers mov r0,0x000 ;point to beginning of RAM mov r4,RAM_SIZE - 2 ;do a loop RAM_SIZE times BEGLOOP rtag *r0 ;reset tag mov *r0++,a0 ;clear the RAM ENDLOOP mov STR,0 ;clear string register mov ap0,0 ;clear accum pointer 0 mov ap1,0 ;clear accum pointer 1 mov ap2,0 ;clear accum pointer 2 mov ap3,0 ;clear accum pointer 3 mov r0,0 ;clear register 0 mov r1,0 ;clear register 1 mov r2,0 ;clear register 2 mov r3,0 ;clear register 3 mov r4,0 ;clear register 4 mov r5,0 ;clear register 5 mov r6,0 ;clear register 6 mov r7,0 ;clear register 7 mov sv,0 ;clear shift value register mov TOS,*0x000 ;clear top of stack register mov PH,*0x000 ;clear product high register mov MR,*0x000 ;clear multiplier register ;**************************************************************** ; Choose the source for the reference oscillator. Set the PLLM ; register accordingly (in this case for a CPU clock of 8 MHz) ; and then set TIMER 2 to a 200 ms period. ; Go to sleep (do an IDLE) and wake up when the clock has ; reached full speed and is stable. ;**************************************************************** #if CRO_FLAG mov a0,CROENABLE ;enable crystal oscillator #else #if C614_FLAG in a0,RTRIM ;for C614 read trim value from register #else mov a0,RESISTORTRIM ;for P614 the user supplies the trim value #endif and a0,0x3f ;only want lower 6 bits mov a0~,a0 ;save a copy for later mov sv,10 ;need to shift left by 10 shltpl a0,a0 ;bit 1 is now bit 11, bit 0 now bit 10 or a0,RTOENABLE ;enable resistor-trimmed oscillator and a0,~IDLEBIT ;clear bit 10 ; 6 bit trim resides in bits 15-11 and bit 9 (LSB of trim value) and a0~,a0~,0x01 ;look at bit 0 of trim value jz trimbit0 ;do nothing if it is zero or a0,0x0200 ;else set bit 9 trimbit0 #endif orb a0,PLLMBITS ;set PLLM for CPU clock of 8 MHz 6-6
MSP50C614/MSP50P614 Initialization Codes
mov
*save_clkspdctrl,a0
mov 0~,TIM2REFOSC + TIM2IMR out IntGenCtrl,a0~ mov a0~,6553 ;setup a 200 ms period out TIM2,a0~ ;load TIM2 and PRD2 in one fell swoop mov a0~,TIM2ENABLE + TIM2REFOSC + TIM2IMR out IntGenCtrl,a0~ ;use 32 kHz crystal as source, wake up from TIM2 out ClkSpdCtrl,a0 ;set clock to full speed! idle ;go to sleep... nop ;wake up 200 ms later, clock running at full speed nop nop ;**************************************************************** ; Upon reset all ports are set to input and port G output is set ; low (0x0000). Therefore it remains only to enable the pullups ; on port F. ;**************************************************************** in a0,IntGenCtrl or a0,PFPULLUPS ;enable port F pullups and a0,~TIM2IMR ;turn off TIMER 2 interrupt and a0,~TIM2ENABLE ;turn off TIMER 2 out IntGenCtrl,a0 ;**************************************************************** ; Set the DAC to 10 bits, C3x style. For C5x style set bit 3 ; high. ;**************************************************************** movb a0,0x02 ;choose 10 bit DAC, C3x style orb a0,DACON ;enable DAC out DACCTRL,a0 ;switch DAC on ;**************************************************************** ; Initialization complete. Now tidy up and branch to the main ; user code. ;**************************************************************** zac a0 ;tidy up zac a0~ jmp _main ;jump to the main program
;save the ClkSpdCtrl value for later, when ;waking up from mid or deep sleep ;disable TIMER 2
Applications
6-7
Texas Instruments C614 Synthesis Code
6.3 Texas Instruments C614 Synthesis Code
Some sample codes are supplied with the development tools. These samples are in the .\Examples subdirectory where the tool is installed. In this manual only one example code is explained. This description applies to all the code development. The following example assumes that you have the MSP scanport interface connected to the parallel port of your PC, and TI speech code development unit connected to the MSP Scanport interface. You should have the MSP50C6xx code development tool already installed on the system before attempting to continue with this example. Overview This example code demonstrates MELP running at 2400 bps. It shows how to use the timer interrupts to scan a keyboard and flash LEDs while speaking. Activation of the sleep modes is also illustrated. Getting Started Connect the MSP scanport (the small grey metal box) to the PC and to the speech development board. Ensure that the scanport and the development board are powered on (the red LED and the green LED on the MSP Scanport are both illuminated) before attempting to start the code development tool. Click on Start menu, go to Programs - EMUC6xx and click on MSP50C6xx development tool menu item. To open a project click on Project - New Project and select the desired project file. e.g., C:\614\PROJECTS\MELP1\MELP1.RPJ. Click on Project - Build to assemble and link the constituent files of the project. Then click Debug - Eprom Programming and select Blank Check + Program to burn the code onto a P614 device. Alternatively, press F3 then ENTER. Set the breakpoint at the _main label. To do this click on the blue magnifying glass icon at the top of the screen, then from the Symbol list choose _main. Click OK and the Program Window will display the label and the surrounding code. The line of code at _main - MOV R7,STACK - is highlighted in cyan. Set the breakpoint by moving the mouse to this line, holding the SHIFT key and clicking the right mouse button. Click on Init - Init All to reset the P614. All the values in the RAM window should turn blue and should be zero (0000). To run the program, click on the yellow lightning/black centipede (Run Internal) icon at the end of the tool bar. The program should halt at the _main label. All the values in the CPU window should be blue and zero apart from PC, STAT, DP, RZF and ZF.
6-8
Texas Instruments C614 Synthesis Code
To continue, click on the Run Internal icon again. The LEDs should flash during MELP synthesis (Extra, extra, read all about it) and should flash in a different pattern after MELP synthesis. Running the Program The MELP1 program can run on either the demo box or the code development board. The latter has only two switches (SW1 and SW2) while the former has ten switches (SW1 to SW10), four LEDs, an LCD, an EPROM socket and a flash card socket. Upon power-up the 614 should say Extra, extra etc and the LEDs should flash in alternating pairs. When the LED pattern becomes a rolling one the program is sitting in a loop and scanning SW1 and SW2. Pressing SW1 launches the MELP synthesizer into 11 character phrases. Pressing SW2 begins a more complex sequence of events. One MELP phrase is synthesized and then the 614 goes into midsleep mode (the LEDs will cease flashing). This sleep mode can be exited by pressing SW1, after which another character voice will be synthesized. Finally, if an EPROM is plugged in and it contains MELP speech data (at address 0x0000) then this data will be synthesized before the program returns to the tight keyscan loop. At any time during speech you can press one of the port F keys (SW3 to SW10) to skip to the next phrase. This feature is not available when running the code on the demo box. Directory Structure
melp1 | | -------- dsp | | | | | | | | | -------- general dsputil.asm getbits.asm speak.asm dsp_var.irx speak.irx
Applications
6-9
-------- common util.obj
Texas Instruments C614 Synthesis Code
| | | | | |
spk_ram.irx
-------- melp melp.obj melp.irx
-------- modules | | | | | | | | | | | | | | -------- ram | | -------- speech | | | | main.asm main.irx main_ram.irx melp1.rpj
6-10
-------- 605 605.asm 605.irx
-------- general init.asm sleep.asm io_ports.irx
-------- isr dac_isr.asm tim1_isr.asm tim2_isr.asm
ram.irx
-------- melp 1kbps.qfm 24kbps.qfm
Texas Instruments C614 Synthesis Code
File Description Util.obj Dsputil.asm Getbits.asm Speak.asm Dsp_var.irx Speak.irx Spk_ram.irx Melp.obj Melp.irx 605.asm 605.irx Init.asm Sleep.asm Io_ports.irx Dac_isr.asm Tim1_isr.asm Tim2_isr.asm Ram.irx 1kbps.qfm 24kbps.qfm Trey.qfm Trey.bin Main.asm Main.irx Main_ram.irx Flags.irx Melp1.rpj Maths functions and tables used by the vocoders. Oversampling and miscellaneous functions. Routine to get data from ROM. Routines to speak a phrase or sentence. Various vocoder constants. Speech header constants. RAM map of variables common to all vocoders. MELP object code. MELP include file. Routines to read data from external ROM. Port usage constants for address and data bus. Initialization code to set the clock speed etc. Edit at your peril! Routines to enter and wake up from the light, mid and deep sleep. Control register and bitmask definitions. DAC interrupt service routine. Timer 1 interrupt service routine (keyscan). Timer 2 interrupt service routine (LED flash). RAM overlay for the entire program. MELP speech at 1000 bps. MELP speech at 2400 bps. MELP speech at 2400 bps. MELP speech (binary format) for external ROM. Main user code. User constants. User RAM requirements. Flags used to configure the 614 and set the resistor trim value. Project file for the MELP1 program.
Applications
6-11
Texas Instruments C614 Synthesis Code
RAM Usage The file MAIN.LST contains the variable RAM assignments. Do a search for BEGIN_RAM to find the start of the RAM locations. Adding Another Module There are three steps to adding a new module to a project. First, the project file (.RPJ) must be updated to include the ASM file (click on File - Insert to add files to a project). Second, the RAM overlay file MAIN_RAM.IRX should be updated with the RAM required by the new module. And finally, any functions which are called from MAIN.ASM should be declared as external at the top of MAIN.ASM. Here, the self-extracting zipfile MELP2.ZIP contains the necessary extra files to implement the N factorial (N!) function, normally referred to as N shriek. This function is called do_shriek and is in SHRIEK.ASM under the MODULES\SHRIEK directory. Under the MELP2 directory the file MAIN.ASM should now contain the following two extra lines of code, just below the shriek4 label: shriek4 movb call a0,4 do_shriek
To test this code, build the MELP2 project and program another P614. Set a breakpoint at shriek4 and then do a Run Internal (yellow lightning/black centipede icon). Step over (press F8) and the accumulator 00 will be 0004 after the movb instruction. Step over once more and the accumulator 00 will be 0018 after calling the do_shriek function. Understanding the RAM Map In the above code, the value of 4 is stored in the variable shriekvar. The list file MAIN.LST shows the location of this variable to be 0x448, which is an offset of 0x448 bytes from the beginning of the RAM at 0x000. Since the RAM window displays words of RAM the shriekvar variable is shown at (0x448/2) which is 0x224. To verify this, step over the do_shriek function and watch RAM location 0x224 change from 0000 (blue) to 0018 (red). Modifying Files and Projects The 614 code contains certain files which may be edited, some files which should only be edited with good reason, and a few files which should never be edited. In general: These files may be edited MAIN.ASM, MAIN.IRX, MAIN_RAM.IRX and FLAGS.IRX
6-12
Texas Instruments C614 Synthesis Code
These files may be edited for special purpose code
INIT.ASM and SPEAK.ASM
These files should never be edited
SLEEP.ASM, RAM.IRX and SPK_RAM.IRX
A good rule of thumb to follow is that files under the DSP directory should be left alone, and all custom code should be added either to MAIN.ASM or to a new directory under MODULES, e.g., MODULES\CUSTCODE. Creating a New Project The easiest way to create a new project is to copy the entire MELP1 directory into another directory. Rename the project file as desired, eg NEWPROJ.RPJ. It is not necessary to change the paths of the files in the project - this will be done automatically by the code development tool.
6.3.1
Memory Overlay
C614 release code uses memory overlay to accommodate multiple synthesis algorithms. If the user is interested in using the data memory, the starting memory location has to start from the last memory location used by the program + 2. The synthesis code has a file named MAIN_RAM.IRX. This file is provided for maintaining overlay. New variables are added as follows: ; bytes byte1 byte2 ; words word1 word2 ; byte arrays array1 ; word arrays array2 ; End of RAM RAMEND_CUSTOMER RAMLENGTH_CUSTOMER equ equ equ equ equ equ equ equ RAMSTART_CUSTOMER + 1 byte1 + 1 byte2 + 2 * 1 word1 + 2 * 1 word2 + 10 array1 + 2 * 4 array2 RAMEND_CUSTOMER - RAMSTART_CUSTOMER
Two byte variables, two word variables and two arrays are assigned storage space in realtion to the previous variable. The last two rows must be present and the constant RAMEND_CUSTOMER should equate to the name of the last used variable in the list. Note that the C614 RAM is always accessed as byte, therefore 1 word memory location is equal to 2 bytes. Hence the multiplication by 2.
Applications
6-13
ROM Usage With Respect to Various Synthesis Algorithms
6.4 ROM Usage With Respect to Various Synthesis Algorithms
The following table lists some possible synthesis options and their ROM requirements. The models assume that just enough program space, as necessary for storage of the synthesis algorithm, is used. The remainder of the ROM is dedicated entirely to the speech data, with the goal of maximizing the synthesis playback time. If any two synthesis algorithms are to be used in combination, e.g., MELP and LPC together, then a separate allocation must be made for each algorithm within the same fixed pool of ROM. (The program space must hold two algorithms, and the speech data is allocated in proportion to how much speech duration is used for each algorithm.)
The bit-rates and program sizes given in this table are only approximations. The estimates are applicable at the time of this printing, but they are subject (and likely) to change. Also, the data-rate is sometimes dependent on the properties of the speech.
C614 Total ROM Storage 32,768 words MELP speech data 26 k words
BIST 2048 words BIST 2048 words BIST 2048 words BIST 2048 words BIST 2048 words
MELP program 4.2 k words CELP program 6 k words LPC program 1.5 k words ADPCM program 0.3 k words
rate 2.4 k bits-per-second 170 seconds of speech
CELP speech data rate 5.0 k bits-per-second 25 k words 79 seconds of speech D6 LPC speech data 29 k words rate 2.0 k bits-per-second 230 seconds of speech
ADPCM speech data rate 32.0 k bits-per-second (@ 8 kHz S.R.) 30 k words 15 seconds of speech (@ 8 kHz S.R.)
8-bit PCM speech data rate 64.0 k bits-per-second 30 k words 7.5 seconds of speech
6-14
Chapter 7
Customer Information
Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter.
Topic
7.1 7.2 7.3 7.4 7.5 7.6
Page
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Customer Information Fields in the ROM . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Device Production Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 New Product Release Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7-1
Mechanical Information
7.1 Mechanical Information
The C614 is normally sold in die form but is also available in 100-pin PJM packages. The P614 is available in a windowed ceramic package, 120-pin PGA. NOTE: Scan Port Bond Out The Scan Port Interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx development tools. The SCANIN, SCANOUT, SCANCLK, SYNC, and TEST pins are dedicated to the scan port interface. The RESET pin is shared with the application. These pins may play an important role in debugging any system problems. For this reason, these pins MUST be bonded out on any C614 production board. Furthermore, it is recommended that these pins be connected to test points, so the development tool can be connected. Since the development tool requires VDD and VSS, test points connected these signals are also needed. The application circuits appearing in section 6.1 show the minimum recommended configuration for any C614 application board. For production purposes the 10 k resistor which appears at the RESET pin is optional. It is required for use with the Scan Port Interface, but they may be shorted otherwise. The footprints for this resistor is strongly recommended.
7.1.1
Die Bond-Out Coordinates
Die bond-out coordinates are available upon request from Texas Instruments.
7-2
Mechanical Information
7.1.2
Package Information
The MSP50C614 will be available in the 100-pin PJM package (see Figure 7-1 and Table 7-1). Contact your local TI sales office for more information.
Table 7-1. MSP50C614 100-Pin PJM Plastic Package Pinout Description
Description GND3/DA NC NC NC DACM VCC3/DA DACP VCC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 NC PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description GND4 VCC4 NC NC PG7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 SCANOUT TEST SYNC SCANCLK SCANIN RESET PE7 PE6 PE5 PE4 PE3 PE2 PE1 Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description PE0 GND NC NC NC X2 X1 PLL PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 GND1 VCC1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Pin # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Description PB0 NC NC NC NC NC NC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 GND2 VCC2 PD7 PD6 PD5 PD7 PD73 PD2 PD1 PD0 Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Customer Information
7-3
Mechanical Information
Figure 7-1. 100-Pin PJM Mechanical Information
0,38 0,22
0,65 80
0,13 M 51
81
50
12,35 TYP
14,20 13,80
17,45 16,95
100
31
1 18,85 TYP 20,20 19,80 23,45 22,95
30
0,16 NOM
Gage Plane 0,25 0,25 MIN 1,03 0,73 Seating Plane 3,40 MAX 0,10 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 0- 7
2,90 2,50
7-4
Mechanical Information
The C614 is sold in die form for its volume production. For software development and prototyping, a windowed ceramic 120 pin grid array packaged P614 is available. The P614's PGA package is shown in Figure 7-2.
Figure 7-2. 120-Pin Grid Array Package for the Development Device, P614
N
M
L K J H G F E D C B A 13 12 11 10 9 8 7 6 5 4 3 2 1 (TOP VIEW)
N M L K J H G F E D C B A
extra pin
1 2 3 4 5 6 7 8 9 10 11 12 13 (BOTTOM VIEW)
Note: The PGA package is only available in limited quantities for development purposes.
Customer Information
7-5
Mechanical Information
The pin assignments for the 120-pin PGA are outlined in the following table. (Refer to Section 1.6 for more information on the signal functions.) Figure 7-3 provides a cross-reference between the C614 (die) pad numbers and the P614's PGA package leads.
Figure 7-3. 120 Pin Grid Array (PGA) Package Leads, P614
N M L K J H G F E D C B A
nc nc PD0 PD3 PD5 VDD VSS PC2 PC5 PC7 nc nc nc nc nc nc PD1 PD4 PD7 PC1 PC3 PC6 nc nc nc nc VDD DAC M nc nc PD2 PD6 PC0 PC4 nc nc nc nc nc extra nc PB0 PB2 PB1 PB3 PB4 PB5 PB6 PB7 VSS PA0 VDD PA3 PA2 PA1 PA7 PA5 PA4 nc PLL PA6 (bottom view) PF7 DACP VSS PF5 PF6 VDD PF2 PF3 PF4 VPP PF1 PF0 PG15 PG14 PG13 PG12 PG11 PG9 PG10 PG8 nc VSS nc nc PG6 PG2 pgmpuls RESET PE4 PE0 nc nc OSCOUT OSCIN VDD nc PG5 PG3 PG0 SYNC scanin PE5 PE2 VSS nc nc nc nc PG7 PG4 PG1 scanout scanclk PE7 PE6 PE3 PE1 nc nc nc
1
2
3
4
5
6
7
8
9
10
11
12
13
It is important to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are PGA numbers N3 and L4, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. Refer to section 6.1 for details.
The following table provides a cross-reference between the C614 (die) pad numbers and the P614's PGA package leads.
7-6
Customer Information Fields in the ROM
7.2 Customer Information Fields in the ROM
In those cases where the customer code is programmed by Texas Instruments, some registration of the code-release is provided within the ROM. This information appears as 7 distinct fields within the ROM test-area. The ROM test-area extends from address 0x0000 to 0x07FF. The code-release information is stored in locations 0x0006 through 0x000C. Assuming these addresses are not specifically read-protected by the ROM security, they are read-accessible to the programmer. The fields appear as follows:
MSP50C614 EPROM Test-Area Customer Information Fields (16-bit wide, the 17th bit is ignored) Address 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Field Description Device number Mask number (assigned by TI) Reserved Customer code version number Customer code revision number Year mask generated Data mask generated (mm/dd) 0x0001 0x0005 (e.g., version 1.5) 0x1999 0x0816 (e.g., 8/16/1999) Example Value 0x0614 (for C614) 0x0005
Customer Information
7-7
Speech Development Cycle
7.3 Speech Development Cycle
Figure 7-4. Speech Development Cycle
Speech Specification
Speaker Selection
Recording Script Preparation
Software Design
Hardware Design Prototype Construction
Speech Recording Speech Analysis
Software Writing
Speech Editing Speech Evaluation
Software Debugging
System Evaluation
A sample speech development cycle is shown in Figure 7-4. Some of the components, such as speech recording, speech analysis, speech editing, and speech evaluation, require different hardware and software. TI provides a speech development tool, called the SDS6000, which allows the user to perform speech analysis using various algorithms, speech editing for certain algorithms, and to evaluate synthesis results through playback of encoded speech. Design of the software and hardware, development of software, and prototype construction are all customer-dependent aspects of the speech development cycle.
7.4 Device Production Sequence
For the speech development group at TI to accept a custom device program, the customer must submit a new product release form (NPRF). This form describes the custom features of the device (e.g., customer information, prototype and production qualities, symbolization, etc.). Sections 1 and 2A of the NPRF are completed by TI personnel. A copy of the NPRF can be found in section 7.6. TI generates the prototype photomask, then processes, manufactures, and tests 25 prototype devices for shipment to the customer. Limited quantities in addition to the 25 prototypes may be purchased for use in customer evaluation.
7-8
Device Production Sequence
All prototype devices are shipped with the following disclaimer: It is understood that, for expediency purposes, the initial 25 prototype devices (and any additional prototype devices purchased) were assembled on a prototype (i.e., not production-qualified) manufacturing line, whose reliability has not been characterized. Therefore, the anticipated inherent reliability of these devices cannot be expressly defined. The customer verifies the operation and quality of the prototypes and responds with either written customer prototype approval or disapproval. A nonrecurring mask charge that includes the 25 prototype devices is incurred by the customer. A minimum purchase is required during the first year of production.
Customer Sends Code (in QBN or TITAG format) and completes Section 1 of the NPRF TI completes Section 2A of NPRF and sends verification code (in QBN format) with BIST included & NPRF form to customer
TI sends sample devices to customer for verification
Customer verifies the devices work properly and completes Section 4 of the NPRF.
Customer verifies code is correct. Customer signs Section 3 of the NPRF and sends it to TI TI generates prototype parts for Customer verification
TI produces the chip in production quantities
Texas Instruments recommends that prototype devices not be used in production systems. The expected end-use failure rate of these devices is undefined; however, it is predicted to be greater than that of the standard qualified production.
Customer Information
7-9
Ordering Information
7.5 Ordering Information
Because the MSP50C614 is a custom device, it receives a distinct identification, as follows:
CSM 614 XXX X X
Gate Code CSM: Custom Synthesizer With Memory
Family Member
ROM Code
Revision Letter
Package or Die PJM: Loopin QFP (Preliminary) Y: Die
7.6 New Product Release Forms
The new product release form is used to track and document all the steps involved in implementing a new speech code onto one of the parent speech devices. This section is to be completed by the customer and sent to TI along with the code.
7-10
New Product Release Forms
NEW PRODUCT RELEASE FORM FOR MSP50C614 (DIE ONLY) SECTION 1. ORDER INFORMATION Division:____________________________ Company:___________________________ Project Name:________________________ Purchase Order #:_____________________ Management Contact: ___________________________ Technical Contact : ___________________________ Phone:(___) ____________ Phone:(___) ____________
Customer Code Version and Revision:____________________ (of format vv.rr) (vv = version, rr = revision; numberic values only) ************************************************************************ SECTION 2A. ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI. TI Part Number: ____ CSM614xxxy___ ************************************************************************ SECTION 3. AUTHORIZATION TO GENERATE MASKS, PROTOTYPES, AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met: 1) The customer has verified that the TI-generated data matches the original data. I hereby certify that the TI generated verification data has been checked and found to be correct, and I authorize TI to generate masks, prototypes, and risk units in accordance with the purchase order in Section 1 above. In addition, By:_____________________________________________ Title:__________________________________________ SECTION 4. Date________________ ************************************************************************ APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested. I hereby certify that the prototype devices have been received and tested and found to be acceptable, and I authorize TI to start normal production in accordance with purchase order #______________________. By:_____________________________________________ Title:__________________________________________ Return to: Texas Instruments Incorporated Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266-0199 OR Fax to: (972)480-7301 Attn: Code Release Team Have Questions?: CALL: OR E-MAIL: Code Release Team (972)480-4444 code-rel@msp.sc.ti.com Date________________ ************************************************************************
Customer Information
7-11
7-12
Appendix A Appendix A
MSP50C605 Preliminary Data
This Appendix contains preliminary data for the MSP50C605 device. Note: MSP50C605 MSP50C605 is in the Product Preview stage of development. For more information contact your local TI sales office.
Topic
A.1 A.2 A.3
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-1
Introduction
A.1 Introduction
MSP50C605 is a spin off of the core processor MSP50C614. It uses three IO ports of MSP50C614 and maps a 1.835 Mbits of internal ROM. Using a 1 kbps MELP algorithm, the C605 can provide over 30 minutes of uninterrupted speech. There is no Port A and Port B control register in MSP50C605. Port DRD is read only, and Port DRP and DRA are write only. Apart from the additional ROM and corresponding IO port changes, all other functionality of the processor is similar to MSP50C614. The mapping is as follows:
Port Name Port A Port B Port G IO Location 0x00 0x08 0x2C MSP50C614 General purpose bit configurable IO General purpose bit configurable IO General purpose 16 bit output MSP50C605 Data ROM data (DRD) Data ROM page (DRP) Data ROM address (DRA)
A.2 Features
A.3 Architecture
30k word ROM customer program memory Approximately 1.835 Mbits data ROM 8 MHz uDSP core 32 input or output pins
J J
24 Pins general-purpose, bit configurable as input or output 8 input pins with programmable 100- pull-up resistors
1 bit comparator with edge-detection interrupt service (IMPORTANT: Not currently supported) PLL clock synthesizer Resistor trimmed oscillator or 32 kHz crystal 640 word RAM PDM DAC w/direct speaker drive (32 ) Serial scan port for in-circuit emulation/monitor/test
The MSP50C605 uses the MSP50C614 core, including breakpoint capability. It has identical instruction sets and uses the same development tool. MSP50P614 (EPROM device) is used for code development and testing. MSP50C605 architecture is shown in Figure A-1.
A-2
Architecture
A.3.1 RAM
The MSP50C605 (like MSP50C614) has 640 17-bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space.
A.3.2 ROM
The MSP50C605 contains 32K by 17-bit words of internal program ROM and 229,376 bytes by 8 bits (i.e., 1,835,008 bits) of slow data ROM. The program ROM space is divided into three areas: 1) The initial 2K words of ROM (0x0000 - 0x07FF) is reserved for built in selftest (BIST) that is provided by Texas Instruments during mass production. 2) Customer can use the program ROM from address extending from 0x0800 to 0x7FFF. Restrictions on using certain program ROM location is shown in Figure A-2. The Data ROM is a slower ROM dedicated only to hold data. Data ROM cannot execute program instructions. The Data ROM locations start from 0x00000 and ends at 0x37FFF. The lower 16 bits of the address to be read is provided into IO port DRA register (0x2C), the upper 2 bits goes into IO port DRP register (0x08). After 1.5 instruction cycle delay, the 8 bit data appears at IO port DRD (0x00). Discharging time is always 3 processor cycle and data is latched to port DRD during this time. There is 3.5 page in MSP50C605; pages 0, 1, and 2 are full; page 3 is half. Using 1Kbps MELP algorithm, this ROM can provide over 30 minutes of uninterrupted speech.
Port Name DRA DRP DRD IO Address 0x2C 0x08 0x00
Description Data ROM Address Data ROM Page Data ROM Data
Function write into this port to access 16 bit of the data ROM address. write into this port to select ROM page read this port to get data at specified ROM page and address
A.3.3 I/O Pins
The MSP50C605 has 32 input/output pins. 24 of the pins are software configurable as either input or output (port C, D, and E). Eight of the pins are dedicated as input pins with programmable pullout resistors (port F). These ports are identical to the similar ports in MSP50C614, see Chapter 2 and Chapter 3 for details.
MSP50C605 Preliminary Data
A-3
Architecture
Figure A-1. MSP50C605 Architecture
V SS 5 V DD 5 V PP
SCAN IN SCAN OUT SCAN CLK SYNC TEST PGM PULSE
Scan Interface Break Point Emulation OTP Program Serial Comm.
Power (EP)ROM
(P614 only) 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF Data ROM access DRA DRP DRD 0x2C 0x08 0x00 Data ROM 229,376 x 8 bit
Test-Area (reserved) User ROM
(C605 only) (P614 only) INT vectors
DAC P DAC M RESET
DAC
0x30
Core Instr. Decoder C port I/0 DATA Control 0x10 0x14 PC0..7
32 Ohm PDM Initialization Logic
PCU Prog. Counter Unit CU Computational Unit
/
8
RTOTRIM Register 0x2F TIMER1 PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F Comparator 1 bit: PD 5 vs. PD 4 + D port I/0 DATA Control E port I/0 DATA Control 0x20 0x24 PF0..7 0x18 0x1C PE0..7 - PD0..7
OSC Reference Resistor Trimmed 32 kHz nominal
TIMER2
OSC IN OSC OUT
or or Crystal Referenced 32.768 kHz
DAC Data/Control Control Data 0x34 0x30 Clock Control 0x3D Gen. Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
/
8
/
8
PLL
PLL Filter
RAM 640 x 17 bit (data) 0x0000 to 0x027F
F port INPUT DATA 0x28
/
8
A-4
Architecture
Figure A-2. MSP50C605 Memory Organization
Program Memory
0x0000
Data Memory
0x 0000
Peripheral Ports
0x 00 DRD0-7 DRP0-3 PC0..7 data PC0..7 ctrl PD0..7 data PD0..7 ctrl PE0..7 data PE0..7 ctrl PF0..7 data DRA0-15 RTRIM DAC data DAC ctrl IntGenCtrl IFR PRD1 TIM1 ClkSpdCtrl PRD2 TIM2 0x 08 0x 10 0x 14 0x 18 0x 1C
Internal Test Code 2048 x 17 bit
0x 027F
RAM 640 x 17 bit
(reserved )
0x07FF 0x0800 0x 00000
Data ROM
DATA ROM (slow)
0x 20 0x 24 0x 28 0x 2C 0x 2F 0x 30 0x 34 0x 38
User ROM 30704 x 17 bit (C605 : read-only) (P614 : EPROM)
229,376 x 8 bit
0x7F00 Macro Call Vectors 255 x 17 bit (overlaps interrupt vector locations) 0x7FF0
0x 39 0x 3A 0x 3B 0x 3D 0x 3E
0x7FF7 0x7FF8 0x7FFE 0x7FFF
Usable Interrupt Vectors 8 x 17 bit
Unusable Interrupt Vectors
0x 3F
(reserved) RESET vector
0x 38000
MSP50C605 Preliminary Data
A-5
Architecture
Figure A-3. MSP50C605 100-Pin PJM Package
80 81 51
50
MSP50C605 100 PIN PJM PLASTIC PACKAGE
100
31
1
30
A-6
Architecture
Table A-1. MSP50C605 100-Pin PJM Plastic Package Pinout Description
Description NC NC NC NC DACM VCC3 DACP VCC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 GND NC NC NC NC NC NC NC NC Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description NC NC NC NC NC VCC VCC1 SCAN_OUT TEST SYNC SCNCLK SCANIN INITZ PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PLL X1 X2 GND Pin# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Description NC NC NC NC NC NC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 GND VCC2 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 GND3 Pin# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
MSP50C605 Preliminary Data
A-7
A-8
Appendix B Appendix A
MSP50C604 Preliminary Data
This Appendix contains preliminary data for the MSP50C604 device. Note: MSP50C604 MSP50C604 is in the Product Preview stage of development. For more information contact your local TI sales office.
Topic
B.1 B.2 B.3 B.4
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
B-1
Introduction
B.1 Introduction
MSP50C604 is a spin off of the core processor MSP50C614. It is targeted as a slave device. An external microprocessor is needed to interface with MSP50C604 in slave mode. It can also be used a stand alone device if desired.
B.2 Features
-
30k word ROM customer program memory 8 MHz uDSP core 2 IO pins can be used as a comparator 4 pins for synthesizer syncronization Host read or write interrupts core PLL clock synthesizer Resistor trimmed oscillator or 32 kHz crystal 640 word RAM PDM DAC w/direct speaker drive (32 ohm) 1 bit comparator with edge-detection interrupt service (IMPORTANT: Not currently supported) Serial scan port for in-circuit emulation/monitor/test Host Mode
J J J J J
14 general-purpose I/O pins Can generate interrupts
Slave Mode Works as microprocessor peripheral STROBE, R/W lines for host read/write control INPUTREADY, OUTPUTREADY for handshake
B.3 Architecture
The MSP50C604 will use the 6xx device family core, including breakpoint capability. It has identical instruction sets and uses the same development tool. MSP50P614 (EPROM device) is used for code development and testing. The architecture block diagram is shown in Figure B-1.
B-2
Architecture
B.3.1 RAM
The MSP50C604 (like MSP50C614) has 640 17-bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space.
B.3.2 ROM
The MSP50C604 contains 32K by 17-bit words of internal program ROM. The program ROM space is divided into two areas: 1) The initial 2K words of ROM (0x0000 - 0x07FF) is reserved for built in selftest (BIST) that is provided by Texas Instruments during mass production. 2) Customer can use the ROM from address extending from 0x0800 to 0x7FFF. Restrictions on using certain program ROM location is shown in Figure B-2.
B.3.3 I/O Pins
The MSP50C604 has 14 output pins. There are two different configurations for these pins, host mode, and slave mode. In host mode, 6 of the 14 pins are the same as pins PD0 to PD5 on port D of the MSP50C614. The other 8 pins are the same as one of I/O port C. All of the functions of port D on the MSP50C614 are available on the MSP50C604, including four interrupts, the conditional branch control and the comparator. In slave mode, only PD4 and PD5 are be available for general purpose I/O including two interrupts and the comparator. PD0, PD1, PD2, and PD3, are used to control the slave mode interface internally, and becomes INRDY, OUTRDY, STROBE, and R/(WZ) on the I/O pinout respectively. The other 8 pin port C, becomes a data bus controlled by STROBE and R/WZ externally. Internally, the port is used to transfer data between the core and the I/O latches. External interrupts can be caused by transitions on the PD2, PD3, PD4, and PD5. The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs.
MSP50C604 Preliminary Data
B-3
Architecture
Figure B-1. MSP50C604 Block Diagram
V SS 5 SCAN IN SCAN OUT SCAN CLK SYNC TEST PGM PULSE (C604 only) (P614 only) INT vectors Scan Interface Break Point Emulation OTP Program Serial Comm. V DD 5 V PP
Power (EP) ROM Test-Area (reserved) User ROM
(P614 only) 32k x (16 + 1) bit 0x0000 to 0x07FF 0x0800 to 0x7FEF 0x7FF0 to 0x7FFF G port I/0 DATA Control C port I/0 DATA Control 0x10 0x14 0x10 0x14 PG 0
DAC P DAC M RESET
DAC
0x30
Core Instr. Decoder
32 Ohm PDM Initialization Logic
PCU Prog. Counter Unit CU Computational Unit RTOTRIM Register 0x2F TIMER1 PRD1 0x3A PRD2 0x3E TIM1 0x3B TIM2 0x3F
/8
PC 0..7
OSC Reference Resistor Trimmed 32 kHz nominal
Comparator 1 bit: PD5 vs. PD4 + D port I/0 DATA Control 0x18 0x1C INRDY/PD0 OUTRDY/PD1 STROBE/PD2 R/WZ/PD3 PD 4 PD 5 PD 6 PD 7 -
TIMER2
OSCIN OSCOUT
or or Crystal Referenced 32.768 kHz
DAC Data/Control ControlData 0x34 0x30 Clock Control 0x3D Gen. Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data Mem. Addr.
PLL
PLL Filter
RAM 640 x 17 bit 0x0000 to (data) 0x027F
B-4
Architecture
B.3.4 Slave Mode Operation
The MSP50C604 is used as a peripheral device in slave mode. A microprocessor/microcontroller controls the R/WZ, STROBE, INRDY, OUTRDY pins of MSP50C604 to use it as a slave processor. No special programming is required to switchthe 'C604 to slave mode. Slave mode is exclusively controlled by the four pins mentioned above.
B.3.5 Host Write Sequence
1) MSP50C604 signals readiness to receive data by taking INRDY low 2) Host takes R/WZ low. 3) Host puts 8 bit data on port C pins PC0-PC7. 4) Host takes STROBE low. 5) On rising edge of STROBE, data latched into port A, INRDY goes high, rising edge interrupt (INT3) is activated. 6) When input latch is read, INRDY goes low to restart cycle
B.3.6 Host Read Sequence
1) MSP50C604 signals readiness to receive data by taking OUTRDY low. 2) Host takes R/WZ high. 3) Host takes STROBE low. 4) Data port C sets as output by MSP50C604. 5) MSP50C604 program has already written 8 bit data into IO port C. 6) Host reads data from port pins PC0-PC7. 7) Host takes STROBE high. 8) On rising edge of STROBE, OUTRDY goes high, data port goes 3-state and falling edge interrupt (INT4) is activated. 9) When MSP50C604 writes to the output latch, OUTRDY goes low to restart cycle.
MSP50C604 Preliminary Data
B-5
Architecture
Figure B-2. MSP50C604 Memory Organization and I/O ports
Program Memory 0x0000 Internal Test Code 2048 x 17 bit 0x 027F (reserved ) 0x07FF 0x0800 Data Memory 0x 0000 RAM 640 x 17 bit
0x 10 0x 14 0x 18 0x 1C PC0..7 data PC0..7 ctrl PD0..7 data PD0..7 ctrl
Peripheral Ports
User ROM 30704 x 17 bit (C604 : read-only) (P614 : EPROM)
0x 2C 0x 2F 0x 30 0x 34 0x 38
PG0 RTRIM DAC data DAC ctrl IntGenCtrl IFR PRD1 TIM1 ClkSpdCtrl PRD2 TIM2
0x7F00 Macro Call Vectors 255 x 17 bit (overlaps interrupt vector locations) 0x7FF0
0x 39 0x 3A 0x 3B 0x 3D 0x 3E
0x7FF7 0x7FF8 0x7FFE 0x7FFF
Usable Interrupt Vectors 8 x 17 bit Unusable Interrupt Vectors (reserved)
0x 3F
RESET vector
B-6
Architecture
B.3.7 Interrupts
Interrupts for MSP50C604 are the same as MSP50C614 in host mode except INT5 (port F interrupt) is not available. But in slave mode, INT3 and INT4 are external interrupts triggered by write sequence and read sequence as explained before. A summary of the interrupts is given below:
Interrupt 0 1 2 3 4 5 6 7 Vector Source 7FF0h 7FF1h 7FF2h 7FF3h 7FF4h 7FF5h 7FF6h 7FF7h DAC Timer TIMER1 TIMER2 Port D2 Port D3 Port F Port D4* Port D5* Condition Priority Host Mode DAC interrupt Timer 1 underflow Timer 2 underflow Port D2 goes high Port D3 goes low Reserved, not used Port D4 goes high Port D5 goes low Slave Mode Dac interrupt Timer 1 underflow Timer 2 underflow Host write Host read Reserved, not used Port D4 goes high Port D5 goes low
Timer underflow Highest
Timer underflow Timer underflow
2nd 3rd 4th 5th 6th 7th Lowest
Rising edge
Falling edge
Falling edge Rising edge Falling edge
INT6 and INT7 may be associated with the comparator function if the comparator enable bit has been set. See the section entitled Comparator for details.
Note: Interrupts may be lost if interrupts occur during power up or wake up from deep sleep mode. The interrupts are generated as a divided signal from the master clock. The frequency of the several timer interrupts will therefore vary depending upon the operating master clock frequency.
MSP50C604 Preliminary Data
B-7
Packaging
B.4 Packaging
The MSP50C604 is sold in die form. A 64 pin plastic package is also available.
Table B-1. MSP50C604 64-Pin PJM Plastic Package Pinout Description
Description VCC VCC3 PD3 PD2 PD1 PD0 TEST SCAN_OUT SYNC SCAN_CLK SCAN_IN RESET X2 X1 PLL GND Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PC7 Pin# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 VCC1 DACM VCC2 DACP GND1 Pin# 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND Pin# 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
B-8
Packaging
Figure B-3. MSP50C604 Slave Mode Signals
Host write sequence Host read sequence
INRDY
OUTRDY R/WZ STROBE
PC0-PC7
New Data Data latched to Port A
Valid Data
Figure B-4. MSP50C604 64-Pin PJM Package
48 33
49
32
MSP50C604 64 PIN PJM PLASTIC PACKAGE
64
17
1
16
MSP50C604 Preliminary Data
B-9
Packaging
B-10
Appendix C Appendix A
MSP50C605 Data Sheet
This appendix contains the data sheet for the MSP50C605 mixed-signal processor.
Topic
C.1
Page
MSP50C605 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C-1
C.1 MSP50C605 Data Sheet
This appendix contains the data sheet for the MSP50C605 mixed-signal processor.
C-2

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