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SPT7722
8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS PRELIMINARY INFORMATION
FEATURES
* * * * * * * TTL/CMOS/PECL compatible High conversion rate: 250 MSPS Single +5 V power supply Very low power dissipation: 450 mW 350 MHz full power bandwidth Power-down mode +3.0 V/+5.0 V (LVCMOS) digital output logic compatibility * Demuxed output ports NOVEMBER 8, 2001
APPLICATIONS
* * * * *
RGB video processing Digital communications High-speed instrumentation Digital sampling oscilloscopes (DSO) Projection display systems
GENERAL DESCRIPTION
The SPT7722 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. It is a performance-enhanced version of the SPT7721, offering better linearity and dynamic performance with slightly higher power. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 450 mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5 V common mode reference is provided on
chip for the single-ended input mode to minimize external components. The SPT7722 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0 V and +5.0 V compatible. The SPT7722 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40 to +85 C.
BLOCK DIAGRAM
AGND
DGND
AVCC
OVDD
VIN+ VIN
8-Bit 250 MSPS ADC
CLK CLK
Data Output Latches
DA0DA7
DB0DB7
Common Mode Voltage Reference
Data Output Mode Control
2 2
DCLKOUT DCLKOUT
+2.5 V VCM
PD
CLK CLK
Reset DMODE1,2 & Reset
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages AVCC ...................................................................... +6 V OVDD ..................................................................... +6 V Input Voltages Analog Inputs ............................... -0.5 V to VCC +0.5 V Digital Inputs ................................ -0.5 V to VCC +0.5 V Temperatures Operating Temperature ........................... -40 to +85 C Storage Temperature ............................ -65 to +125 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, AVCC = +5.0 V, OVDD = +5.0 V, CLK = 250 MHz, unless otherwise specified.
PARAMETERS Resolution DC Performance Differential Linearity Error (DLE) Integral Linearity Error (ILE) Best Fit No Missing Codes @250 MSPS
TEST CONDITIONS
TEST LEVEL
MIN
SPT7722 TYP 8
MAX
UNITS Bits LSB LSB LSB LSB
IN=1 kHz +25 C -40 C to +85 C +25 C -40 C to +85 C
V V V V V
0.4 0.9 1.2 1.7 Guaranteed
Analog Input Input Voltage Range (with respect to VIN-) Input Common Mode (VCM) Input Bias Current Input Resistance +25 C Input Capacitance +25 C Input Bandwidth +25 C (-3 dB of FS) Gain Error Offset Error Offset Power Supply Rejection Ratio Timing Characteristics Conversion Rate Output Delay (Clock-to-Data) (tpd1) Output Delay Tempco Aperture Delay Time (tap) Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time Single Channel Mode (tpd2) Dual Channel Mode (tpd3) Dynamic Performance Effective Number of Bits (ENOB) IN = 70 MHz IN = 70 MHz Signal-to-Noise Ratio (SNR) IN = 70 MHz IN = 70 MHz
V V V V V V V V V V V V V V V V V V V V
512 2.5 5 50 5 350 5 10 35 250 8 21 0.5 2 2.5 2.5 2.5 3.5 6 6
mVP-P V A k pF MHz % mV mV/V MSPS ns ps/C ns ps rms Clocks Clocks Clocks Clocks ns ns
-40 to +85 C
+25 C -40 C to +85 C +25 C -40 C to +85 C
VI V VI V
6.3 44
7.0 5.9 46 39
Bits Bits dB dB
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ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, AVCC = +5.0 V, OVDD = +5.0 V, CLK = 250 MHz, unless otherwise specified.
PARAMETERS
TEST CONDITIONS
TEST LEVEL
MIN
SPT7722 TYP
MAX
UNITS
Dynamic Performance Total Harmonic Distortion (THD) +25 C IN = 70 MHz -40 C to +85 C IN = 70 MHz Signal-to-Noise and Distortion (SINAD) +25 C IN = 70 MHz -40 C to +85 C IN = 70 MHz Power Supply Requirements AVCC Voltage (Analog Supply) OVDD Voltage (Digital Supply) AVCC Current AVCC Current Powerdown Power Dissipation with Internal Voltage Reference Common Mode Reference Output Voltage Voltage Tempco Output Impedance Power Supply Rejection Ratio
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 4.75 2.75
-47 -45 43 41 5.0 90 2.7 450 2.45 2.5 119 1 34 5.25 5.25 110 5 550 2.55
dB dB dB dB V V mA mA mW V ppm/C k mV/V mVP-P V V V V V A A V V A A V V ns ns ns ns
IOUT = 50 A
Clock and Reset Inputs (Differential and Single-Ended) Differential Signal Amplitude (VDIFF) Differential High Input Voltage (VIHD) Differential Low Input Voltage (VILD) Differential Common-Mode Input (VCMD) Single-Ended High Input Voltage (VIH) Single-Ended Low Input Voltage (VIL) VID = 1.5 V Input Current High (IIH) Input Current Low (IIL) VID = 1.5 V Power Down and Mode Control Inputs (Single-Ended) High Input Voltage Low Input Voltage Maximum Input Current Low Maximum Input Current High <4.0 V Digital Outputs Logic "1" Voltage Logic "0" Voltage TR/TF Data TR/TF DCLK = (10 pF load) OVDD = 3 V OVDD = 5 V IOH = -0.5 mA IOL = +1.6 mA 10 pF load OVDD = 3 V OVDD = 5 V
400 1.7 0 1.5 1.8 0 -100 -100 2.0 0 -100 -100 OVDD - 0.2 20 20
AVCC AVCC -0.4 1.2 +100 +100 AVCC 1.0 +100 +100
10 10
0.2 3.5 2.0 1.3 0.7
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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THEORY OF OPERATION
The SPT7722 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two single-bit folding interpolator stages. There are pipelining THAs between each ADC block. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand railto-rail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. The three MSBs of the ADC are generated in the first three-bit folder block, the output of which drives a differential reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is crosscoupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs.
The digital decode consists of comparators, exclusive of cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 2.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The output data mode is controlled by the state of the demux mode inputs. There are three output modes. * All data on bank A with clock rate limited to one-half maximum * Interleaved mode with data alternately on banks A and B on alternate clock cycles * Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is LVCMOS with output VDD supply adjustable from 2.75 volts to 5.25 volts. There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 10 mW. There is a 2.5 V reference to supply common mode for single-ended inputs that is not shut down in power-down mode.
Figure 1 - Single Mode Timing Diagram
N
2.5 CLK Cycles of Latency
tap
VIN
CLK /CLK D0D7 (Port A) DCLKOUT /DCLKOUT
tpd2
N+1
N+2
N+3
N+4
N+5
tpd1
N3
tpd2
N2
N1
N
N+1
N+2
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Figure 2 - Dual Mode Timing Diagram
N-2
2.5 CLK Cycles
tap N-1 N N+1
of Latency
N+2 N+3 N+4
Vin
/CLK CLK
Refer to AN7722
U6-Reset /Reset Reset
550ps
550ps
treset
ts
tpd1
tpd1
tpd1
INTERLEAVED DATA OUTPUT
Port A Port B
N-5 N-6 N-4
Invalid Data
N-1 N-2 N
N+1
tpd2
Port A Port B DCLKOUT /DCLKOUT
tpd3
N-7 N-6 N-5 N-4
PARALLEL DATA OUTPUT
Invalid Data N-2 N N-1
tpd2
N-2
2.5 CLK Cycles o f Latenc y
tap N-1 N N+1 N+2 N+3 N+4
Vin
/CLK CLK
Refer to AN7722
U6-Reset /Reset Reset
550ps
550ps
treset
ts
tpd1
tpd1
tpd1
INTERLEAVED DATA OUTPUT
Port A Port B
N-6 N-5
N-4
Invalid Data N-2
N-1 N
N+1
tpd2
Port A Port B /DCLKOUT DCLKOUT
PARALLEL DATA OUTPUT
N-6 N-5
tpd1
Invalid Data N-2 N
N-1
Data Output Possibilities w/o Reset
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Figure 3 - Typical Interface Circuit
Mode Select Reset Diff In Clock Diff In
DMode1
DMode2
Reset
Reset
AIN
T1
VIN+ 50 VIN
VCMOUT
CLK
DA0DA7
SPT7722
AGND1 (4) AGND2 (2) AVCC1 (2) AVCC2 (2)
DCLKOUT DCLKOUT
DGND (3)
CLK
Interfacing Logics
.01
Notes:
.01(2x) .01(3x)
.01(3x) +
+A5
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the SPT7722 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance. ANALOG INPUT The input of the SPT7722 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in figure 3. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal trackand-hold. Figure 4 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired. It is very important to select op amps with a high open-loop gain, a bandwidth high enough so as not to impair the performance of the ADC, low THD, and high SNR.
Figure 4 - DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown)
R3 VCM (R3)/2 + R2 R2 R3 R + R ADC 51 W 15 pF VIN 51 W R R VIN+
INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times. POWER SUPPLIES AND GROUNDING The SPT7722 is operated from a single power supply in the range of 4.75 to 5.25 volts. Normal operation is suggested to be 5.0 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible.
6
+
1) FB = Ferrite bead. It must placed as close to the ADC as possible. 2) All inputs are internally biased: a) DMode1 to GND through 100K Default = interleave dual channel output b) DMode2 to VCC through 50K c) CLK, PD and Rest pins to GND through 100K d) /CLK and /Reset pins to 1.5 V through 5K e) VIN+ and VIN to +2.5 V through 50K 3) All 0.01microfarad capacitors are surface mount caps. They must be placed as close to the respective pin as possible
}
FB
10
10
OVDD (3)
Mini-Circuit T1-6T
DB0DB7
+D3/5 +D3/5
Input Voltage (0.5 V)
+ R
51 W
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POWER DOWN MODE To save on power, the SPT7722 incorporates a powerdown function. This function is controlled by the signal on pin PD. When pin PD is set high, the SPT7722 enters the power-down mode. All outputs are set to high impedance. In the power-down mode the SPT7722 dissipates 10 mW typically. REFERENCES To save on parts count, design time, and PC board real estate, the SPT7722 utilizes an internal reference. Only a 0.01 F bypass capacitor is required to implement this feature. COMMON MODE VOLTAGE REFERENCE CIRCUIT The SPT7722 has an on-board common-mode voltage reference circuit (VCM). It is 2.5 volts and is capable of driving 50 A loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. CLOCK INPUT The clock input on the SPT7722 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/CMOS single-ended clock inputs, the rise time of the signal also becomes an important consideration. DIGITAL OUTPUTS The output circuitry of the SPT7722 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel
mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (table I). Table I - Output Data Format
Output Code D7-D0 +FS 1111 1111 +FS - 1/2 LSB 1111 111O 0 OOOO OOOO -FS + 1/2 LSB 0000 000O -FS 0000 0000 O indicates the flickering bit between logic 0 and 1 Analog Input
The data output mode is set using the DMODE1 and DMODE2 inputs (pins 32 & 31 respectively). Table II describes the mode switching options. Table II - Output Data Modes
Output Mode DMODE1 Parallel Dual Channel Output 0 Interleaved Dual Channel Output 0 Single Channel Data Output (Bank A only 125 MSPS max) 1 DMODE2 0 1 X
EVALUATION BOARD
The EB7721/22 evaluation board is available to aid designers in demonstrating the full performance of the SPT7722. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (AN7721/22) describing the operation of this board, as well as information on the testing of the SPT7722, is also available. Contact the factory for price and availability of the EB7721/22.
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PACKAGE OUTLINE
44-Lead TQFP
A B
INCHES SYMBOL A B MIN MAX 0.472 Typ 0.394 Typ 0.394 Typ 0.472 Typ 0.031 Typ 0.012 0.053 0.002 0.018 0.018 0.057 0.006 0.030 0-7
MILLIMETERS MIN MAX 12.00 Typ 10.00 Typ 10.00 Typ 12.00 Typ 0.80 Typ 0.300 1.35 0.05 0.450 0-7 0.45 1.45 0.15 0.750
Pin 1 Index
C D E
C D
F G H I J K
0.039 Typ
1.00 Typ
E
F
G I J K
H
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PIN ASSIGNMENTS
AGND 44 AGND AGND AGND AVCC 42 AVCC 43 AVCC AVCC VIN+ 40 VIN VCM
DB0-DB7 DCLKOUT DCLKOUT
Data output; Bank B. 3 V / 5 V LVCMOS compatible. Non-Inverted data output clock. 3 V / 5 V LVCMOS compatible. Inverted data output clock. 3 V / 5 V LVCMOS compatible. Non-Inverted clock input pin; 100k pulldown to AGND, internally Inverted clock input pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally RESET synchronizes the data sampling and data output bank relationship when in Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally Inverted RESET input pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally Internally: 100k pulldown to AGND on DMODE1 50k pullup to VCC on DMODE2 Data Output Mode pins: DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A (125 MSPS max) Power Down pin; PD = 1 for power-down mode. Outputs set to high impedance in power-down mode; 100k pulldown to AGND, internally 2.5 V Common Mode Voltage Reference Output +5 V Analog Supply +3 V / +5 V Digital Output Supply Analog Ground Digital Ground
41
39
38
37
36
35
34
AGND DMODE1 DMODE2 OVDD DGND DCLKOUT DCLKOUT DB7 (MSB) DB6 DB5 DB4
AGND PD CLK CLK RESET RESET OVDD DGND DA7 (MSB) DA6 DA5
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30
CLK CLK RESET
SPT7722
TOP VIEW 44L TQFP
29 28 27 26 25 24 23
RESET DMODE1,2
PIN FUNCTIONS
Pin Name VIN+ Description Non-Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AGND, internally Inverted Analog Input; nominally 1 VP-P; 100k pullup to VCC and 100k pulldown to AGND, internally Data output; Bank A. 3 V / 5 V LVCMOS compatible. PD
12 DA4
13 DA3
14 DA2
15 DA1
16 DA0 (LSB)
17 OVDD
18 DGND
19 DB0 (LSB)
20 DB1
21 DB2
22 DB3
VCM AVCC OVDD AGND DGND
VIN-
DA0-DA7
ORDERING INFORMATION
PART NUMBER SPT7722SIT TEMPERATURE RANGE -40 to +85 C PACKAGE 44L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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