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Features
* Three high-side and three low-side drivers * Outputs freely configurable as switch, half bridge or H-bridge * Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors * * * * * * * * * * * *
and inductors 0.6 A continuous current per switch Low-side: RDSon < 1.5 vs. total temperature range High-side: RDSon < 2.0 vs. total temperature range Very low quiescent current Is < 20 A in standby mode Outputs short-circuit protected Overtemperature prewarning and protection Undervoltage and overvoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power supply fail Serial data interface Daisy chaining possible Loss of ground protection SSO20 package
Dual Triple DMOS Output Driver with Serial Input Control T6817
Description
The T6817 is a fully protected driver interface designed in 0.8-m BCDMOS technology. It is used to control up to 6 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, under- and overvoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications.
Ordering Information
Extended Type Number T6817-TKS T6817-TKQ Package SSO20 SSO20 Remarks Power package, tube Power package, taped and reeled
Rev. A3, 12-Nov-01
1 (16)
Block Diagram
Figure 1.
HS3 12 HS2 14 HS1 16
Osc
Fault detect Fault detect Fault detect
VS 6 VS
DI
2 S C T O L D H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R
VS
S I n. u. n. u. n. u. n. u. n. u. n. u.
7
CLK
OV protection
4
VS
Input register
CS
Vcc
VCC 19
3
Output register
Serial interface
Control logic
H S 1 LT SP 1
UV protection -
INH
5
P S F
I N H
S C D
n. u.
n. u.
n. n. u. u.
n. u.
n. u.
H S 3
L S 3
H S 2
L S 2
Power-on reset
GND
1
GND 10 GND 11
DO 18
Vcc
Fault detect
Fault detect
Fault detect
Thermal protection
17
GND 13 GND
8
LS3 LS2
15 LS1
20
2 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Pin Configuration
Figure 2. Pinning SSO20
GND DI CS CLK INH VS VS LS3 n.c. GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND VCC DO LS1 HS1 LS2 HS2 GND HS3 GND
Pin Description
Pin 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND DI CS CLK INH VS LS3 n.c. GND GND HS3 GND HS2 LS2 HS1 LS1 DO VCC GND Function Ground; reference potential; internal connection to Pin 10, 11, 13 and 20; cooling tab Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first Chip-select input; 5-V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating Power supply output stages HS1, HS2 and HS3 Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load Not connected Ground, see Pin 1 Ground, see Pin 1 High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load Ground, see Pin 1 High-side driver output 2; see Pin 12 Low-side driver output 2; see Pin 8 High-side driver output 1; see Pin 12 Low-side driver output 1; see Pin 8 Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the mC (LSB is transferred first); output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Logic supply voltage (5 V) Ground, see Pin 1
3 (16)
Rev. A3, 12-Nov-01
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data transfer input data protocol
CS
DI
SRR 0
LS1 1
HS1 2
LS2 3
HS2 4
LS3 5
HS3 6
n.u. 7
n.u. 8
n.u. 9
n.u. 10
n.u. 11
n.u. 12
OLD 13
SCT 14
SI 15
CLK
DO
TP
SLS1
SHS1
SLS2
SHS2
SLS3
SHS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
SCD
INH
PSF
Input Data Protocol
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n.u. n.u. n.u. n.u. n.u. n.u. OLD SCT Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Open load detection (low = on) Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high / low = 100 ms / 12.5 ms, overvoltage shutdown delay high / low = 14 ms / 3.5 ms Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered)
15
SI
4 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Output Data Protocol Output (Status) Register TP
Bit 0
Function Temperature prewarning: high = warning (overtemperature shutdown see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17). High = standby, low = normal operation Power supply fail: undervoltage at Pin VS detected
1
Status LS1
2
Status HS1
3 4 5 6 7 8 9 10 11 12 13
Status LS2 Status HS2 Status LS3 Status HS3 n.u. n.u. n.u. n.u. n.u. n.u. SCD
14 15 Note:
INH PSF
Bit 0 to 15 = high: overtemperature shutdown
After power-on reset, the input register has the following status
Bit 15 (SI) Bit 14 (SCT) Bit 13 (OLD) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR)
H
H
H
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
L
L
L
L
L
L
L
Power-Supply Fail
In case of undervoltage at Pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register.
5 (16)
Rev. A3, 12-Nov-01
Open-Load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-3, ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the openload function for this output. If bit SI is set to low, the open-load function is also switched off. If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the C has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
Overtemperature Protection
Short-Circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-3 , ILS1-3 ) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. There are two ways to inhibit the T6817: 1. Set bit SI in the input register to zero 2. Switch Pin 5 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by Pin 5 (INH) switched back to 5 V
Inhibit
6 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Absolute Maximum Ratings
All values refer to GND pins Parameter Supply voltage Supply voltage tt0.5 s; ISu-2 A Supply voltage difference |VS_Pin6 - VS_Pin7| Supply current Supply current t < 200 ms Logic supply voltage Input voltage Logic input voltage Logic output voltage Input current Output current Output current Reverse conducting current (tPulse = 150 ms) Junction temperature range Storage temperature range Pins 6, 7 Pins 6, 7 Pin 19 Pin 5 Pins 2 to 4 Pin 18 Pins 5, 2 to 4 Pib 18 Pins 1 to 4, 11 to 16, 27 and 28 Pins 12, 14, 16 towards 6, 7 Pins 6, 7 Pins 6, 7 Symbol VVS VVS VVS IVS IVS VVCC VINH VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO ILS1 to ILS3 IHS1 to IHS3 IHS1 to IHS3 Tj TSTG Value - 0.3 to 40 -1 150 1.4 2.6 -0.3 to 7 -0.3 to 17 -0.3 to VVCC + 0.3 -0.3 to VVCC + 0.3 -10 to +10 -10 to +10 Internal limited, see output specification 17 -40 to 150 -55 to 150 A C C Unit V V mV A A V V V V mA mA
Thermal Resistance
All values refer to GND pins Parameter Junction - pin Junction ambient Test Conditions Measured to GND Pins 1, 10, 11, 13 and 20 Symbol RthJP RthJA Min. Typ. Max. 25 65 Unit K/W K/W
Operating Range
All values refer to GND pins Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Notes: Pin 19 Pin 2 to 4 and 5 Pin 4 Test Conditions Pins 6, 7 Symbol VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj -40 Min. VUV
1)
Typ. 5
Max. 40
2)
Unit V V V MHz C
4.5 -0.3
5.5 VVCC 2 150
1. Threshold for undervoltage detection 2. Outputs disabled for VVS > VOV (threshold for overvoltage detection)
7 (16)
Rev. A3, 12-Nov-01
Noise and Surge Immunity
Parameter Conducted interferences Interference Suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5: VSmax = 40 V ISO 7637-1 VDE 0879 Part 2 MIL-STM 5.1 - 1998 JEDEC EIA / JESD 22 - A115-A Test Conditions Value Level 4 1) Level 5 2 kV 150 V
Electrical Characteristics
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 1.3 Supply current (VS) 1.4 Supply current (VS) 1.5 2 2.1 3 3.1 3.2 3.3 3.4 3.6 3.7 38 Parameters Current Consumption Quiescent current (VS) Quiescent current (VCC) VVS < 16 V, INH or bit SI = lo 4.5 V < VVCC < 5.5 V, INH or bit SI = low VVS < 16 V normal operating, all output stages off, VVS < 16 V normal operating, all output stages on, no load 4.5 V < VVCC < 5.5 V, normal operating Pin 6, 7 19 IVS IVCC IVS 0.8 40 20 A A mA A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
6, 7
1.2
A
6, 7
IVS IVCC
10
mA A
A
Supply current (VCC)
19
150
A
Internal Oscillator Frequency Frequency (timebase for delay timers) Over- and Undervoltage Detection, Power-On Reset Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay Overvoltage detection threshold Overvoltage detection hysteresis After switching on VVCC 19 19 6, 7 6, 7 6, 7 6, 7 6, 7 VVCC tdPor VUV VUV tdUV VOV VOV 7 18.0 1 3.4 30 5.5 0.4 21 22.5 3.9 95 4.4 160 7.0 V s V V ms V V A A A A A A A fOSC 19 45 kHz A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Electrical Characteristics
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 3.9 Parameters Undervoltage detection delay Test Conditions Input register bit 14 (SCT) = high bit 14 (SCT) = low Pin Symbol tdOV tdOV TjPWset TjPWreset TjPW Tj switch off Tj switch on Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset Min. 7 1.75 125 105 3 150 130 3 145 125 20 170 150 20 190 170 Typ. Max. 21 5.25 165 145 Unit ms ms C C K C C K A A A A A A Type* A
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7
Thermal Prewarning and Shutdown Thermal prewarning Thermal prewarning Thermal prewarning hysteresis Thermal shutdown Thermal shutdown Thermal shutdown hysteresis Ratio thermal shutdown / thermal prewarning Ratio thermal shutdown / thermal prewarning 8, 15, 17 12, 14, 16 8, 15, 17 8, 15, 17 2, 3, 12, 13, 15, 28 8, 12, 14 to 17 8, 12, 14 to 17 8, 15, 17 12, 14, 16
1.05
1.17
A
4.8
1.05
1.2
A
5 5.1 5.2 5.3 5.4 5.5
Output Specification (LS1 - LS6, HS1 - HS6) 7.5 V < VVS < VOV On resistance On resistance Output clamping voltage Output leakage current Output leakage current IOut = 600 mA IOut = -600 mA ILS1-3= 50 mA VLS1-3 = 40 V all output stages off VHS1-3 = 0 V all output stages off
RDS OnL RDS OnH
VLS1-3 40
1.5 2.0
60

V
A A A A A
ILS1-3 IHS1-3 -10
10
A A
5.7
Inductive shutdown energy Output voltage edge steepness Overcurrent limitation and shutdown threshold Overcurrent limitation and shutdown threshold
Woutx
15
mJ
D
5.8
dVLS1-3/dt dVHS1-3/dt
50
200
400
mV/s
A
5.9
A ILS1-3 650 950 1250 mA A IHS1-3 -1250 -950 -650 mA
5.10
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9 (16)
Rev. A3, 12-Nov-01
Electrical Characteristics
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 5.11 Parameters Overcurrent shutdown delay time Open load detection current Open load detection current Open load detection current ratio Open load detection threshold Open load detection threshold Output switch on delay 1) Output switch off delay 1) Inhibit Input Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current Input voltage lowlevel threshold Input voltage highlevel threshold Hysteresis of input voltage Pull-down current Pin DI, CLK VDI, VCLK = VVCC VINH = VVCC Serial Interface - Logic Inputs DI, CLK, CS 2-4 2-4 2-4 2, 4 VIL VIH VI IPDSI 50 2 0.3VVCC 0.7VVCC 500 50 V V mV A A A A A A 5 5 5 5 VIL VIH VI IPD 100 10 0.3VVCC 0.7VVCC 700 80 V V mV A A A A A Input register bit 13 (OLD) =low, output off Input register bit 13 (OLD) =low, output off RLoad = 1 k RLoad = 1 k Test Conditions Input register bit 14 (SCT) = high bit 14 (SCT) = low Input register bit 13 (OLD) =low, output off Input register bit 13 (OLD) =low, output off 8, 15, 17 12, 14, 16 8, 15, 17 12, 14, 16 2, 3, 12, 13 15, 28 Pin Symbol tdSd tdSd ILS1-3 IHS1-3 ILS1-3 / IHS1-3 VLS1-3 VVS- VHS1-3 tdon tdoff Min. 8 1.0 60 -150 1.2 0.6 4 V Typ. 12 1.5 Max. 16 2.0 200 -30 Unit ms ms A A Type* A A A
5.12 5.13 5.14 5.15 5.16
A A A
0.6
4
V
A
5.17 5.18 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5
0.5 1
ms ms
A A
Pull-up current 3 IPUSI -50 -2 A VCS= 0 V Pin CS Note: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Electrical Characteristics
7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 8 8.1 8.2 8.3 Parameters Output voltage low level Output voltage high level Leakage current (tristate) Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Serial Interface - Logic Output DO IOL = 3 mA IOL = -2 mA VCS = VVCC, 0 V < VDO < VVCC 18 18 18 VDOL VDOH IDO VVCC1V -10 10 0.5 V V A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Serial Interface - Timing
Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No. 1 2 10 4 8 Input register Bit 14 (SCT) = high Input register Bit 14 (SCT) = low 9 9 5 6 7 3 11 12
Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time
Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold
Min.
Typ.
Max. 200 200 100 100 200
Unit ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns
225 225 140 17.5 225 225 500 225 225 40 40
11 (16)
Rev. A3, 12-Nov-01
Figure 4. Serial interface timing with chart numbers
1
2
CS
DO
9
CS
4
7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Application Circuit
Figure 5.
Vcc
Enable
U5021M Watchdog
Trigger
Reset
M
HS3 HS2
M
HS1
12
Fault detect Fault detect
14
Fault detect
16 Osc
VS
Vs
BYT41D
6 VS 7 + +
VS
V Batt
13 V
DI
2
S I S C T O L D n. u. n. u. n. n. n. u. u. u. H n. S u. 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R
CLK
OVprotection VS Vcc 19
VCC
4
Vcc
5V
C
CS
3 5
P S F I
N H
Input register Output register S C D n. u. n. n. u. u. n. u. n. u. n. u.
Serial interface
H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1
Control logic
UVprotection
INH
Power-on reset Vcc
1 10 11
GND
DO
GND
18
GND GND GND
Fault detect
Fault detect
Fault detect
Thermal protection 17
13 20
8
LS3 LS2
15
LS1
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolut Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins.
13 (16)
Rev. A3, 12-Nov-01
Package Information
Figure 6.
5.7 5.3 6.75 6.50 4.5 4.3
Package SSO20
Dimensions in mm
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
14 (16)
T6817
Rev. A3, 12-Nov-01
T6817
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
15 (16)
Rev. A3, 12-Nov-01
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Web Site
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(c) Atmel Germany GmbH 2001. Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel Germany GmbH's Terms and Conditions. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH's products are not authorized for use as critical components in life support devices or systems. Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com
Rev. A3, 12-Nov-01

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