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Triple-Half-Bridge
Preliminary Data Sheet Overview Features * * * * * * * * Three Half-Bridges Optimized for DC motor management applications Delivers up to 0.6 A continuous, 1.2 A peak current RDS ON; typ. 0.8 , @ 25 C per switch Output: short circuit protected and diagnosis Overtemperature-Protection with hysteresis and diagnosis Standard SPI-Interface/Daisy chain capable Very low current consumption (typ. 10 A for power and 2 A for logic supply, @ 25 C) in stand-by (Inhibit) mode Over- and Undervoltage-Lockout CMOS/TTL compatible inputs with hysteresis No crossover current Internal clamp diodes Enhanced power P-DSO-Package Full compatibility to the TLE 5208-6 Ordering Code on request
TLE 6208-3 G
P-DSO-14-4 Enhanced Power
* * * * * *
Type TLE 6208-3 G Description
Package P-DSO-14-4
The TLE 6208-3 G is a fully protected Triple-Half-Bridge-Driver designed specifically for automotive and industrial motion control applications. The part is based on the Siemens power technology SPT(R) which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuitry. In motion control up to 2 actuators (DC-Motors) can be connected to the 3 halfbridgeoutputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard SPI-Interface. The possibility to control the outputs via software from a central logic, allows limiting the power dissipation. So the standard P-DSO-14-package meets the application requirements and saves PCB-Board-space and cost. Furthermore the build-in features like Over- and Undervoltage-Lockout, Over-Temperature-Protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications.
Semiconductor Group
1
1998-06-16
TLE 6208-3 G
)
P-DSO-14-4
GND OUT 3
1 2 3 4 5 6 7 Chip Leadframe
14 GND 13 OUT 1 12 OUT 2 11 V CC 10 INH 9 DO 8 GND
AEP02438
VS
CSN DI CLK GND
Figure 1
Pin Configuration (top view)
Semiconductor Group
2
1998-06-16
TLE 6208-3 G
Pin Definitions and Functions Pin No.
1
Symbol
GND
Function
Ground; Reference potential; internal connection to pin 7, 8 and 14; cooling tab; to reduce thermal resistance place cooling areas on PCB close to these pins. Halfbridge-Output 3; Internally contected to Highside-Switch 3 and Lowside-Switch 3. The HS-Switch is a Power-MOS open drain with internal reverse diode; The LS-Switch is a Power-MOS open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. Power supply; needs a blocking capacitor as close as possible to GND Value: 22 F electrolytic in parallel to 220 nF ceramic. Serial data input; receives serial data from the control device; serial data transmitted to DI is an 16bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table Input Data Protocol. Chip-Select-Not input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs. Serial clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs. Ground; see pin 1. Serial-Data-Output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table Diagnosis Data Protocol. Inhibit input; has an internal pull down; device is switched in standby condition by pulling the INH terminal low. Logic supply voltage; needs a blocking capacitor as close as possible to GND; Value: 10 F electrolytic in parallel to 220 nF ceramic. Halfbridge-Output 1; see pin 2. Halfbridge-Output 2; see pin 2.
2
OUT3
3
VS
5
DI
4
CSN
6 7, 8, 14 9
CLK GND DO
10
INH
11
VCC
12 13
OUT1 OUT2
Semiconductor Group
3
1998-06-16
TLE 6208-3 G
V CC
11 Bias Charge Pump
VS
DRV1 3 13 OUT 1
INH
10
Inhibit
FaultDetect
CSN DI CLK DO
4 5 6 9 SPI 16 Bit Logic and Latch
DRV2 12 OUT 2
UV OV TSD >1
DRV3 2 OUT 3
1,7,8,14 GND
AEB02439
Figure 2
Block Diagram
Semiconductor Group
4
1998-06-16
TLE 6208-3 G
Circuit Description Figure 2 shows a block schematic diagram of the module. There are 3 halfbridge drivers on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge driver in each case. The drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD), charge pump and fault detect. Two connection interfaces are provided for supply to the module: All power drivers are connected to the supply voltage VS. These are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally generated Power-On Reset (POR) to initialize the module at power-on. The advantage of this system is that information stored in the logic remains intact in the event of shortterm failures in the supply voltage VS. The system can therefore continue to operate following VS undervoltage, without having to be reprogrammed. The "undervoltage" information is stored, and can be read out via the interface. The same logically applies for overvoltage. "Interference spikes" on VS are therefore effectively suppressed. The situation is different in the case of undervoltage on the VCC connection pin. If this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). The module is initialized by VCC following restart (Power-On Reset = POR). The 16-bit wide programming word or control word (see Table Input Data Protocol) is read in via the DI data input, and this is synchronized with the clock input CLK. The status word appears synchronously at the DO data output (see Table Diagnosis Data Protocol). It is also possible to connect two TLE 6208-3 G in a daisy chain configuration. The DO data output of one device is connected with the DI data input of the second device. In this configuration these two devices are controlled with a single CSN chip select and using a 32-bit wide control word. The transmission cycle begins when the chip is selected with the CSN input (H to L). If the CSN input changes from L to H then the word which has been read in becomes the control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. The INH inhibit input can be used to cut off the complete module. This reduces the current consumption to just a few A, and results in the loss of any data stored. The output levels are switched to tristate status. The module is reinitialized with the internally generated POR (Power-On Reset) at restart. This feature allows the use of this module in battery-operated applications (vehicle body control applications).
Semiconductor Group
5
1998-06-16
TLE 6208-3 G
Every driver block from DRV 1 to 3 contains a low-side driver and a high-side driver. Both drivers are connected internally to form a half-bridge at the output. This reduction of output pins was necessary to meet the small P-DSO-14 package. When commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. A special, integrated "timer" for power ON/OFF times ensures that there is no crossover current. Input Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF OVLO on/off not used Overcurrent SD on/off not used not used not used not used not used not used HS-Switch 3 LS-Switch 3 HS-Switch 2 LS-Switch 2 HS-Switch 1 LS-Switch 1 Status Register Reset Diagnosis Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF Power supply fail Underload Overload not used not used not used not used not used not used Status HS-Switch 3 Status LS-Switch 3 Status HS-Switch 2 Status LS-Switch 2 Status HS-Switch 1 Status LS-Switch 1 Temp. Prewarning
Semiconductor Group
6
1998-06-16
TLE 6208-3 G
Fault Result Table Fault Overcurrent (load) Short circuit to GND (high-side-switch) Short circuit to VS (low-side-switch) Temperature shut down (SD) Underload/Openload Diag.-Bit 13 13 13 Result Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Reaction of control device needed. All outputs OFF. Temperature warning is set before. Reaction of control device needed. All outputs OFF. All outputs OFF. Function can be deactivated by bit No. 15.
Temperature warning 0 - 14
Undervoltage lockout 15 (UVLO) Overvoltage lockout (OVLO) H = failure; L = no failure. 15
Semiconductor Group
7
1998-06-16
TLE 6208-3 G
Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Limit Values min. Voltages Supply voltage Supply voltage Logic supply voltage Logic input voltages (DI, CLK, CSN, INH) Logic output voltage (DO) Output voltage (OUT 1-3) Currents Output current (cont.) Output current (peak) max. Unit Remarks
VS VS VCC VI VDO VOUT
- 0.3 -1 - 0.3 - 0.3 - 0.3 - 0.3
40 - 5.5 5.5 5.5 40
V V V V V V
-
t < 0.5 s; IS > - 2 A 0 V < VS < 40 V 0 V < VS < 40 V 0 V < VCC < 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V 0 V < VS < 40 V
IOUT1-3 IOUT1-3
- -
- -
A A
internal limited internal limited
Limit is mentioned in the overcurrent section of operating range Temperatures Junction temperature Storage temperature
Tj Tstg
- 40 - 50
150 150
C C
- -
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
8
1998-06-16
TLE 6208-3 G
Operating Range Parameter Supply voltage Supply voltage slew rate Logic supply voltage Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, INH) SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient Symbol Limit Values min. max. V V/s V After VS rising above VUV ON - - Outputs in tristate Outputs in tristate - - - Unit Remarks
VS
dVS /dt
VUV OFF 40
- 4.75 - 0.3 - 0.3 - 0.3 - - 40 10 5.50
VCC VS VS VI fCLK Tj
VUV ON V VUV OFF V VCC V
1 150 MHz C
Rthj-pin RthjA
- -
30 65
K/W K/W
measured to pin 1, 7, 8, 14 -
Semiconductor Group
9
1998-06-16
TLE 6208-3 G
Electrical Characteristics
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Current Consumption Quiescent current Quiescent current
IS IS
- -
20 20
50 30
A A
INH = Low;
VS = 13.2 V
INH = Low; VS = 13.2 V; Tj = 25 C INH = Low - -
Logic-Supply current Logic-Supply current Supply current
ICC ICC IS
- - -
2 1 2
20 6 5
A mA mA
Over- and Under-Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis
VUV ON VUV OFF VUV HY VOV OFF VOV ON VOV HY
- 5.5 - 34 30 -
6.5 6.2 0.3 37 33 4
7 - - 40 36 -
V V V V V V
VS increasing VS decreasing VUV ON - VUV OFF VS increasing VS decreasing VOV OFF - VOV ON
Semiconductor Group
10
1998-06-16
TLE 6208-3 G
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Outputs OUT1-3 Static Drain-Source-On Resistance Source (High-Side) IOUT = - 0.5 A
RDS ON H
-
0.8 - 1.6 -
1 2 - 4 1 2 - 4

Sink (Low-Side)
RDS ON L
-
0.75 - 1.6 -
IOUT = 0.5 A
8 V < VS < 40 V Tj = 25 C 8 V < VS < 40 V VS OFF < VS 8 V Tj = 25 C VS OFF < VS 8 V 8 V < VS < 40 V Tj = 25 C 8 V < VS < 40 V VS OFF < VS 8 V Tj = 25 C VS OFF < VS 8 V
Leakage Current Source-Output-Stage 1 to 3 Sink-Output-Stage 1 to 3 Overcurrent Source shutdown threshold Sink shutdown threshold Current limit Shutdown delay time
IQLH IQLL
- 50 -
-2 150
- 500
A A
VOUT1-3 = 0 V VOUT1-6 = VS
ISDU ISDL IOCL tdSD
-2 1 - 10
- 1.3 - 1 1.2 2.4 28 2 5 40
A A A s
- - sink and source sink and source
Semiconductor Group
11
1998-06-16
TLE 6208-3 G
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Open Circuit/Underload detection Detection current Delay time
IOCD tdOC
15 200
30 370
60 500
mA s
- -
Output Delay Times; VS = 13.2 V; RLoad = 25 (device not in stand-by for t > 1 ms) Source ON Source OFF Sink ON Sink OFF Dead time Dead time
td ON H td OFF H td ON L td OFF L tD HL tD LH
- - - - 1 1
8 4 7 3 3 6
20 20 30 20 - -
s s s s s s
- - - -
td ON L - td OFF H td ON H - td OFF L
Output Switching Times; VS = 13.2 V; RLoad = 25 (device not in stand-by for t > 1 ms) Source ON Source OFF Sink ON Sink OFF
tON H tOFF H tON L tOFF L
- - - -
5 2 2.5 1
30 5 10 5
s s s s
- - - -
Clamp Diodes Forward Voltage Upper Lower
VFU VFL
- -
0.9 0.9
1.5 1.5
V V
IF = 0.5 A IF = 0.5 A
Semiconductor Group
12
1998-06-16
TLE 6208-3 G
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Inhibit Input H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance
VIH VIL VIHY II CI
- 0.2 50 10 -
0.52 0.48 200 25 10
0.7 - 500 50 15
VCC VCC
mV A pF
- - -
VI = 0.2 x VCC 0 V < VCC <
5.25 V
SPI-Interface Delay Time from Stand-by to Data In/Power on reset Setup time
tset
-
-
100
s
-
Logic Inputs DI, CLK and CSN
VIH L-input voltage threshold VIL Hysteresis of input voltage VIHY Pull up current at pin CSN IICSN Pull down current at pin DI IIDI Pull down current at pin CLK IICLK Input capacitance CI
H-input voltage threshold at pin CSN, DI or CLK Logic Output DO H-output voltage level L-output voltage level
- 0.2 50 - 50 10 10 -
0.52 0.48 200 - 25 25 25 10
0.7 - 500 - 10 50 50 15
VCC VCC
mV A A A pF
- - -
VCSN = 0.7 x VCC VDI = 0.2 x VCC VCLK = 0.2 x VCC 0 V < VCC <
5.25 V
VDOH VDOL
VCC
-
VCC
0.2
- 0.4
V V
IDOH = 1 mA IDOL = - 1.6 mA
- 1.0 - 0.7
Semiconductor Group
13
1998-06-16
TLE 6208-3 G
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter Tri-state leakage current Tri-state input capacitance
Symbol
Limit Values min. typ. - 10 max. 10 15 - 10 -
Unit Test Condition A pF
IDOLK CDO
VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC <
5.25 V
Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time
tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN tfIN
1000 500 500 500 500 500 500 250 250 - -
- - - - - - - - - - -
- - - - - - - - - 200 200
ns ns ns ns ns ns ns ns ns ns ns
- - - - - - - - - - -
trDO tfDO tENDO tDISDO tVADO
- - - - -
50 50 - - 100
100 100 250 250 250
ns ns ns ns ns
CL = 100 pF CL = 100 pF
low impedance high impedance
VDO < 0.1 VCC; VDO > 0.9 VCC; CL = 100 pF
1998-06-16
Semiconductor Group
14
TLE 6208-3 G
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Thermal Prewarning and Shutdown Thermal prewarning junction TjPW temperature Temperature prewarning hysteresis Thermal shutdown junction temperature Thermal switch-on junction temperature Temperature shutdown hysteresis Ratio of SD to PW temperature T 120 - 150 120 - 145 30 175 - 30 1.20 170 - 200 170 - - C K C C K - - - - - - -
TjSD TjSO
T
TjSD/TjPW 1.05
Semiconductor Group
15
1998-06-16
TLE 6208-3 G
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register CSN time CSN Low to High: Data from Shift-Register is transfered to Output Power Switches CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 time Actual Data DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 New Data 01 ++ time DI: Data will be accepted on the falling edge of CLK-Signal Previous Status DO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ------Actual Status 0 1 time DO: State will change on the rising edge of CLK-Signal e.g. HS1 Old Data Actual Data time
AET02551
Figure 3
Data Transfer Timing
Semiconductor Group
16
1998-06-16
TLE 6208-3 G
0.7 VCC CSN 0.2 VCC
t CLKH
0.7 VCC CLK 0.2 VCC
t lead t bef
t DISU
t CLKL t DIHO
Don't Care
t lag t beh
0.7 VCC Valid Don't Care 0.2 VCC
AET02178
DI
Don't Care
Valid
Figure 4
SPI-Input Timing
t rIN t fIN
90% CSN 50% 10%
t dOFF
90% Case 1 OUT ON State OFF State 50% 10%
t OFF t dON t ON
90% Case 2 OUT OFF State ON State 50% 10%
AET02179
Figure 5
Turn OFF/ON Time
Semiconductor Group
17
1998-06-16
TLE 6208-3 G
t rIN
_ t fIN < 10 ns
0.9 VCC CLK 50% 0.1VCC
t rDO
0.9 VCC DO (low to high) 0.1VCC
t VADO t fDO
0.9 VCC (high to low) 0.1VCC
AET02180
DO
Figure 6
DO Valid Data Delay Time and Valid Time
t fIN
_ t rIN < 10 ns
0.9 VCC CSN 50% 0.1VCC
t ENDO
t DISDO
10 k Pullup to VCC
DO
50%
t ENDO
t DISDO
10 k Pulldown to GND
DO
50%
AET02181
Figure 7
DO Enable and Disable Time
Semiconductor Group
18
1998-06-16
TLE 6208-3 G
Watchdog Reset Q D
TLE 4278G
D01 1N4001 D02 Z39
V S = 12V
CQ 22 F V CC
CD 47 nF V CC
11 Bias
CS 10 F
WD R
VS
DRV1 2 Charge Pump 13 OUT 1
INH 10
Inhibit
FaultDetect
M
CSN 4 DI 5 P CLK 6 DO 9 SPI 16 Bit Logic and Latch
DRV2 12 OUT 2
M
UV OV TSD >1
DRV3 2 OUT 3
1,7,8,14 GND GND
AEB02441
Figure 8
Application Circuit
Semiconductor Group
19
1998-06-16
TLE 6208-3 G
Package Outlines P-DSO-14-4 (Plastic Dual Small Outline Package)
0.35 x 45
1.75 max 1.45 -0.2
0.19 +0.06
0.2 -0.1
4 -0.2 1)
1.27 0.35 +0.15 2) 14 0.1 0.2 14x 6 0.2 8 0.4 +0.8
1 7 8.75 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side
GPS05093
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 20
8 max.
Dimensions in mm
1998-06-16

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