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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
3-W STEREO CLASS-D AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL
FEATURES D 3-W/Ch Into an 8- Load From 12-V Supply D Efficient, Class-D Operation Eliminates D D
Heatsinks and Reduces Power Supply Requirements 32-Step DC Volume Control From -40 dB to 36 dB Third Generation Modulation Techniques - Replaces Large LC Filter With Small Low-Cost Ferrite Bead Filter Thermal and Short-Circuit Protection
DESCRIPTION
The TPA3003D2 is a 3-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3003D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3003D2 eliminates the need for external heatsinks when playing music. Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from -40 dB to 36 dB.
D APPLICATIONS D LCD Monitors and TVs D Powered Speakers
PVCC 10 nF Cbs
10 F Cs 0.1 F Cs
10 F Cs 0.1 F Cs
PVCC 10 nF Cbs
ROUTN
ROUTN
PVCCR
PVCCR
PVCCR
PGNDR
PGNDR
ROUTP
ROUTP
PVCCR
BSRN
BSRP
Ccpr NC MUTE AVCC NC NC 1 F MUTE CONTROL AVCC Cs 0.1 F Cvcc 10 F
SYSTEM CONTROL RINN RINP
Crinn Crinp 1 F 1 F C2p5
SD RINN RINP V2P5 LINP LINN AVDDREF VREF AGND AGND
VCLAMPR
LINP LINN
Clinp 1 F 1 F Clinn 1 F
TPA3003D2
FADE AVDD COSC ROSC AGND VCLAMPL
AVDD Cosc 220 pF
Cvdd 100 nF Rosc 120 k
SYSTEM CONTROL
VOLUME
VOLUME REFGND PGNDL PGNDL LOUTN LOUTN LOUTP LOUTP PVCCL PVCCL PVCCL PVCCL BSLN
Ccpl 1 F
Cs Cbs 10 nF PVCC 0.1 F Cs 10 F
Cs 0.1 F Cs 10 F Cbs 10 nF PVCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
BSLP
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
AVAILABLE OPTIONS TA PACKAGED DEVICE 48-PIN TQFP (PFB)
- 40C to 85C TPA3003D2PFB The PFB package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3003D2PFBR). PHP PACKAGE (TOP VIEW)
PGNDR
PGNDR
ROUTN
ROUTN
PVCCR
PVCCR
PVCCR
PVCCR
ROUTP
ROUTP
BSRN
48 47
46 45 44
43 42
41 40 39 38
37 36 35 34 33 32
BSRP
SD RINN RINP V2P5 LINP LINN AVDDREF VREF AGND AGND VOLUME REFGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 BSLN PVCCL 15 16 17 PVCCL LOUTN LOUTN 18 19 PGNDL PGNDL 20 21 22 23 PVCCL PVCCL LOUTP LOUTP 24 BSLP
VCLAMPR NC MUTE AVCC NC NC FADE AVDD COSC ROSC AGND VCLAMPL
TPA3003D2
31 30 29 28 27 26 25
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
functional block diagram
V2P5
V2P5
PVCC VClamp Gen
VCLAMPR
BSRN PVCCR(2)
Gate Drive
ROUTN(2)
RINN RINP
V2P5
Gain Adj.
Deglitch &
Modulation Logic
PGNDR BSRP PVCCR(2)
Gate Drive
VREF VOLUME FADE REFGND
V2P5
ROUTP(2)
Gain Control
To Gain Adj. Blocks
PGNDR
Short Circuit Detect Startup Protection Logic Thermal VDD VDDok AVCC VCCok
ROSC COSC AVDDREF AVDD
Ramp Generator
Biases
&
References
AVDD
5V LDO
AVCC AGND VCLAMPL
PVCC
SD
TTL Input Buffer
VClamp Gen
MUTE
BSLN PVCCL(2)
Cint2
V2P5
Gate Drive
LOUTN(2)
LINN LINP
Gain Adj.
Deglitch &
Rfdbk2
Modulation Logic
PGNDL BSLP PVCCL(2)
Gate Drive
Rfdbk2
Cint2
LOUTP(2)
PGNDL
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
Terminal Functions
TERMINAL NO. AGND AVCC AVDD AVDDREF BSLN BSLP BSRN BSRP COSC FADE LINN LINP LOUTN LOUTP MUTE NC PGNDL PGNDR PVCCL PVCCL PVCCR PVCCR REFGND RINP RINN ROSC ROUTN ROUTP SD VCLAMPL VCLAMPR VOLUME VREF V2P5 NAME 9, 10, 26 33 29 7 13 24 48 37 28 30 6 5 16, 17 20, 21 34 31, 32, 35 18, 19 42, 43 14, 15 22, 23 38,39 46, 47 12 3 2 27 44, 45 40, 41 1 25 36 11 8 4 I/O - - O O I/O I/O I/O I/O I/O I I I O O I - - - - - - - - I I I/O O O I - - I I O DESCRIPTION Analog ground for digital/analog cells in core High-voltage analog power supply (8.5 V to 14 V) 5-V Regulated output 5-V Reference output--provided for connection to adjacent VREF terminal. Bootstrap I/O for left channel, negative high-side FET Bootstrap I/O for left channel, positive high-side FET Bootstrap I/O for right channel, negative high-side FET Bootstrap I/O for right channel, positive high-side FET I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5 Input for controlling volume ramp rate when cycling SD or during power-up. A logic low on this pin places the amplifier in fade mode. A logic high on this pin allows a quick transition to the desired volume setting. Negative differential audio input for left channel Positive differential audio input for left channel Class-D 1/2-H-bridge negative output for left channel Class-D 1/2-H-bridge positive output for left channel A logic high on this pin disables the outputs. A low on this pin enables the outputs. Not internally connected Power ground for left channel H-bridge Power ground for right channel H-bridge Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC. Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC. Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC. Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC. Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC ground to this terminal. Positive differential audio input for right channel Negative differential audio input for right channel Current setting resistor for ramp generator. Nominally equal to 1/8*VCC Class-D 1/2-H-bridge negative output for right channel Class-D 1/2-H-bridge positive output for right channel Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC. Internally generated voltage supply for left channel bootstrap capacitors. Internally generated voltage supply for right channel bootstrap capacitors. DC voltage that sets the gain of the amplifier. Analog reference for gain control section. 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: AVCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V Input voltage range, VI: MUTE, VREF, VOLUME, FADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V RINN, RINP, LINN, LINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Supply current, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA AVDDREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE PFB TA 25C 2.8 W DERATING FACTOR 22.2 mW/C TA = 70C 1.8 W TA = 85C 1.4 W
recommended operating conditions
MIN Supply voltage, VCC Volume reference voltage Volume control pins, input voltage PVCC, AVCC VREF VOLUME SD High level input High-level in ut voltage, VIH MUTE FADE SD Low-level in ut voltage, VIL Low level input MUTE FADE MUTE, VI= 5 V, VCC = 14 V High level input High-level in ut current, IIH Low level input current IIL Low-level current, Oscillator frequency, fOSC Operating free-air temperature, TA SD, VI= 14 V, VCC = 14 V FADE, VI= 5 V, VCC = 14 V MUTE SD FADE, VI= 0 V, VCC = 14 V V MUTE, SD, FADE 225 -40 2 3.5 4 0.8 2 2 1 50 150 1 275 85 A A kHz C A V V 8.5 3.0 MAX 14 5.5 5.5 UNIT V V V
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
dc characteristics, TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER | VOS | V2P5 (terminal 4) PSRR ICC ICC(MUTE) ICC(max power) ICC(SD) rds(on) Output offset voltage (measured differentially) 2.5-V Bias voltage Power supply rejection ratio Supply quiescent current MUTE mode quiescent current Supply current at max power Supply current in shutdown mode TEST CONDITIONS INN and INP connected together, Gain = 36 dB No load VCC = 11.5 V to 12.5 V MUTE = 2 V, SD = 2 V MUTE = 3.5 V, SD = 2 V RL = 8 , PO = 3 W SD = 0.8 V High side Low side Total 0.45x AVDD MIN TYP 10 0.5x AVDD -80 16 7 0.6 1 10 600 600 700 700 28.5 9 MAX 65 0.55x AVDD UNIT mV V dB mA mA A A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A
Drain-source on-state resistance VCC = 12 V, IO = 1 A, TJ = 2 C 25C m 1200AAA 1400
ac characteristics, TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER TEST CONDITIONS kSVR PO(max) Vn Supply ripple rejection ratio Maximum continuous output power Output integrated noise floor Crosstalk, Left Right SNR Signal-to-noise ratio Thermal trip point Thermal hystersis VCC = 11.5 V to 12.5 V from 10 Hz to 1 kHz, Gain = 36 dB THD+N = 1%, f = 1 kHz, RL = 8 THD+N = 10%, f = 1 kHz, RL = 8 20 Hz to 22 kHz, No weighting filter, Gain = 0.5 dB Gain = 13.2 dB, PO = 1 W, RL = 8 Maximum output at THD+N < 0.5%, f= 1 kHz, Gain = 0.5 dB
MIN
TYP
MAX
UNITS dB W W dBV dB dB C C
-67 3 3.75 -82 -77 102 150 20
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
Table 1. DC Volume Control
VOLTAGE ON THE VOLUME PIN AS A PERCENTAGE OF VREF (INCREASING VOLUME OR FIXED GAIN) % 0 - 4.5 4.5 - 6.7 6.7 - 8.91 8.9 - 11.1 11.1 - 13.3 13.3 - 15.5 15.5 - 17.7 17.7 - 19.9 19.9 - 22.1 22.1 - 24.3 24.3 - 26.5 26.5 - 28.7 28.7 - 30.9 30.9 - 33.1 33.1 - 35.3 35.3 - 37.5 37.5 - 39.7 39.7 - 41.9 41.9 - 44.1 44.1 - 46.4 46.4 - 48.6 48.6 - 50.8 50.8 - 53.0 53.0 - 55.2 55.2 - 57.4 57.4 - 59.6 59.6 - 61.8 61.8 - 64.0 64.0 - 66.2 66.2 - 68.4 68.4 - 70.6 VOLTAGE ON THE VOLUME PIN AS A PERCENTAGE OF VREF (DECREASING VOLUME) % 0 - 2.9 2.9 - 5.1 5.1 - 7.2 7.2 - 9.4 9.4 - 11.6 11.6 - 13.8 13.8 - 16.0 16.0 - 18.2 18.2 - 20.4 20.4 - 22.6 22.6 - 24.8 24.8 - 27.0 27.0 - 29.1 29.1 - 31.3 31.3 - 33.5 33.5 - 35.7 35.7 - 37.9 37.9 - 40.1 40.1 - 42.3 42.3 - 44.5 44.5 - 46.7 46.7 - 48.9 48.9 - 51.0 51.0 - 53.2 53.2 - 55.4 55.4 - 57.6 57.6 - 59.8 59.8 - 62.0 62.0 - 64.2 64.2 - 66.4 66.4 - 68.6 GAIN OF AMPLIFIER
dB -75 -40.0 -37.5 -35.0 -32.4 -29.9 -27.4 -24.8 -22.3 -19.8 -17.2 -14.7 -12.2 -9.6 -7.1 -4.6 -2.0 0.5 3.1 5.6 8.1 10.7 13.2 15.7 18.3 20.8 23.3 25.9 28.4 30.9 33.5 36.0
> 70.6 >68.6 Tested in production. Remaining steps are specified by design.
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE Efficiency PO IQ ICC IQ(sd) Output power Quiescent supply current Supply current Quiescent shutdown supply current Input impedance THD+N kSVR Total harmonic distortion + noise Supply ripple rejection ratio Closed loop response Intermodulation performance Input offset voltage Crosstalk Mute attenuation Shutdown attenuation Common-mode rejection ratio vs Frequency vs Frequency vs Common-mode input voltage vs Frequency vs Output power vs Load resistance vs Supply voltage vs Supply voltage vs Output Power vs Supply voltage vs Gain vs Frequency vs Output power vs Frequency 1 2 3 4 5 6 7 8, 9 10, 11 12 13, 14 15 16 17 18 19 20
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS
EFFICIENCY vs OUTPUT POWER
80 70 VCC = 12 V, RL = 8 60 VCC = 8.5 V, RL = 8 Efficiency - % 50 40 30 20 10 0 0 0.5 1 1.5 2 PO - Output Power - W 2.5 3 LC Filter Resistive Load P - Output Power - W O 6 5 4 3 2 1 0 8 9 8 7
OUTPUT POWER vs LOAD RESISTANCE
VCC = 12 V, THD = 10% Thermally Limited
VCC = 12 V, THD = 1%
VCC = 8.5 V, THD = 10%
VCC = 8.5 V, THD = 1%
10 11 12 13 14 RL - Load Resistance -
15
16
Figure 1
OUTPUT POWER vs SUPPLY VOLTAGE
6 18 I Q - Quiescent Supply Current - mA 17 16 15 14 13 12 11 1 8.5 9 10 11 12 VDD - Supply Voltage - V 13 14 10 8.5
Figure 2
QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
TA = 25C
5 PO - Output Power - W Thermally Limited 4 8 , THD = 10% 8 , THD = 1% 3
2
9
10 11 12 VCC - Supply Voltage - V
13
14
Figure 3
Figure 4
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs OUTPUT POWER (TOTAL)
0.8 0.7 - Supply Current - A 0.6 0.5 0.4 0.3 0.2 0.1 0 - Quiescent Shutdown Supply Current - A VCC = 12 V, RL = 8 1
QUIESCENT SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
0.8
0.6
I
CC
0.4
VSD = 0.8 V
0.2 VSD = 0 V 0 8.5 9 10 11 12 13 VCC - Supply Voltage - V 14
0
1
2 3 4 5 PO - Output Power (Total) - W
6
Figure 5
INPUT IMPEDANCE vs GAIN
120 THD+N - Total Harmonic Distortion + Noise - % 10 5 2 1 0.5 VCC = 12 V, RL = 8 , TA = 25C
I
CC
Figure 6
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
100 Z i - Input Impedance - k
80
60
PO = 1 W 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k PO = 3 W
PO = 0.5 W
40
20
0 -50
-30
-10 10 Gain - dB
30
50
5 k 10 k 20 k
f - Frequency - Hz
Figure 7
Figure 8
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
10 THD+N - Total Harmonic Distortion + Noise - % 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1 k 2 k f - Frequency - Hz 5 k 10 k 20 k PO = 3.5 W PO = 0.5 W PO = 1 W VCC = 12 V, RL = 8 , TA = 25C THD+N - Total Harmonic Distortion + Noise - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 20m f = 20 KHz f = 1 kHz f = 20 Hz VCC = 8.5 V, RL = 8 , TA = 25C
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
50m 100m 200m 500m 1 2 PO - Output Power - W
5
10
Figure 10 Figure 9
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
10 THD+N - Total Harmonic Distortion + Noise - % k SVR - Supply Ripple Rejection Ratio - dB 5 2 1 0.5 f = 20 Hz 0.2 0.1 0.05 0.02 0.01 20m 50m 100m 200m 500m 1 2 5 10 f = 20 kHz f = 1 kHz VCC = 12 V, RL = 8 , TA = 25C -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 20 100 1k f - Frequency - Hz 10 k 100 k VCC = 12 V, RL = 8
SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY
PO - Output Power - W
Figure 11
Figure 12
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS
CLOSED LOOP RESPONSE
50 Gain 0 Phase -50 Gain - dB -50 Phase - Deg Gain - dB 0 50 100 50 0
CLOSED LOOP RESPONSE
100 Gain 50 0 Phase -50 -100 -150 -50
-100
-100
-100 -150 VCC = 12 V, Gain = +36 dB, RL = 8 -200 -250 1M
-150 VCC = 12 V, Gain = +5.6 dB, RL = 8 100 1k 10 k 100 k
-150
-200
-200
-200 -250 10
-250 10
-250 1M
100
f - Frequency - Hz
1k 10 k f - Frequency - Hz
100 k
Figure 13
Figure 14
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
6 VCC = 12 V 5 VIO - Input Offset Voltage - mV 4 3
INTERMODULATION PERFORMANCE
0 -20 VCC = 12 V, 19 kHz, 20 kHz, 1:1, PO = 1 W, RL = 8 Gain= +13.2 dB, BW =20 Hz to 22 kHz, Class-D No Filter
-40 FFT - dBr -60 -80
2 1
-100
-120
0 -1
-140 50
100
1k f - Frequency - Hz
10 k
1
1.5
2
2.5
3
3.5
4
4.5
5
VICM - Common-Mode Input Voltage - V
Figure 15
Figure 16
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Phase - Deg
TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
TYPICAL CHARACTERISTICS
CROSSTALK vs FREQUENCY
-60 -65 -70 Crosstalk - dB -75 VCC = 12 V, Gain = +13.2 dB, RL = 8 , PO = 1 W Mute Attenuation - dB -30 -40 -50 -60 -70 -80 -90 -100 -110 -90 -95 10 -120 -130 100 1k 10 k f - Frequency - Hz 100 k 10
MUTE ATTENUATION vs FREQUENCY
VCC = 12 V, RL = 8 , VI = 1 Vrms Class-D, VOLUME = 0 V
-80 -85
100
1k
10 k
f - Frequency - Hz
Figure 17
SHUTDOWN ATTENUATION vs FREQUENCY
-80 -85 Shutdown Attenuation - dB -90 -95 -100 -105 -110 -115 -120 -125 -130 10 100 1k 10 k f - Frequency - Hz CMRR - Common-Mode Rejection Ratio - dB VCC = 12 V, RL = 8 , VI = 1 Vrms Gain = +13.2 dB, Class-D -60 VCC = 12 V
Figure 18
COMMON-MODE REJECTION RATIO vs FREQUENCY
-70
-80
-90
-100 20
100
1k f - Frequency - Hz
10 k 20 k
Figure 19
Figure 20
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
APPLICATION INFORMATION
ROUT- ROUT+ C23 1 nF L2 (Bead) PGND 10 nF C18 C9 C10 C15 0.1uF 10 nF 0.1uF C19 GND VCC VCC PVCCR PVCCR
C22 1 nF
L1 (Bead) 10 F
BSRN
PVCCR
PGNDR
PVCCR
PGNDR
ROUTN
ROUTN
ROUTP
ROUTP
BSRP
C7 NC MUTE AVCC NC C13 0.1 F C16 10 F VCC 1 F GND PGND MUTE CONTROL
SHUTDOWN RIN- C2
C1 1 F
SD RINN RINP V2P5 LINP LINN AVDDREF VREF AGND AGND
VCLAMPR
AGND
1 F C5 C3 LIN- 1 F
1 F C4 1 F
TPA3003D2
NC FADE AVDD COSC ROSC AGND VCLAMPL 220pF C6 C14 100 nF R1 120 k C8 AGND GND 1 F PGND AVDD
P1 50 k GND
VOLUME REFGND PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL PVCCL PVCCL C21 10 nF PGND L4 (Bead) LOUTP LOUTP BSLN
AGND
C11 C20 10 nF 0.1 F C17 10 F L3 (Bead)
C12 0.1 F
C24 1nF
C25 1nF
LOUT-
LOUT+
VCC
Figure 21. Stereo Configuration With Single-Ended Inputs
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GND
VCC
BSLP
TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
APPLICATION INFORMATION class-D operation
This section focuses on the class-D operation of the TPA3003D2. traditional class-D modulation scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 22. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss, thus causing a high supply current.
OUTP
OUTN +12 V Differential Voltage Across Load 0V -12 V
Current
Figure 22. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an Inductive Load With No Input TPA3003D2 modulation scheme The TPA3003D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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TPA3003D2
SLOS406A - FEBRUARY 2003 - REVISED MARCH 2003
APPLICATION INFORMATION
TPA3003D2 modulation scheme (continued)
OUTP
OUTN Differential Voltage Across Load Output = 0 V +12 V 0V -12 V
Current
OUTP
OUTN Differential Voltage Across Load -12 V +12 V 0V
Output > 0 V
Current
Figure 23. The TPA3003D2 Output Voltage and Current Waveforms Into an Inductive Load efficiency: LC filter required with the traditional class-D modulation scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3003D2 modulation scheme has very little loss in the load without a filter because the pulses are very short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker, which results in less power dissipation, therefore increasing efficiency.
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APPLICATION INFORMATION
effects of applying a square wave into a speaker Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for frequencies beyond the audio band. Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency switching current. The amount of power dissipated in the speaker may be estimated by first considering the overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the dominant loss in the system, then the maximum theoretical efficiency for the TPA3003D2 with an 8- load is as follows: Efficiency (theoretical, %) + R L R )r L ds(on) 100% + 8 (8 ) 1.4) 100% + 85.11% (1)
The maximum measured output power is approximately 3 W with an 12-V power supply. The total theoretical power supplied (P(total)) for this worst-case condition would therefore be as follows: P (total) +P O Efficiency + 3 W 0.8511 + 3.52 W (2)
The efficiency measured in the lab using an 8- speaker was 75%. The power not accounted for as dissipated across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power: Other losses + P (total) (measured) * P (total) (theoretical) + 4 * 3.52 + 0.48 W (3)
The quiescent supply current at 12 V is measured to be 28.5 mA. It can be assumed that the quiescent current encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any remaining power is dissipated in the speaker and is calculated as follows: P (dis) + 0.48 W * (12 V 28.5 mA) + 0.14 W (4)
Note that these calculations are for the worst-case condition of 3 W delivered to the speaker. Since the 0.14 W is only 5% of the power delivered to the speaker, it may be concluded that the amount of power actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the power generated from a clipping waveform. when to use an output filter Design the TPA3003D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from the amplifier to the speaker.
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when to use an output filter (continued)
33 H OUTP L1 33 H OUTN L2 C1 0.47 F C3 0.1 F C2 0.1 F
Figure 24. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8
Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF
Figure 25. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
volume control operation
The VOLUME terminal controls the internal amplifier gain. This pin is controlled with a dc voltage, which should not exceed VREF. Table 1 lists the gain as determined by the voltage on the VOLUME pin in reference to the voltage on VREF. If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 21 in the Application Information Section). For fixed gain, calculate the resistor divider values necessary to center the voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7 dB is desired, the resistors in the divider network can both be 10 k. With these resistor values, a voltage of 50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB. If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the VREF input and any fluctuations in the DAC output voltage will not affect the TPA3003D2 gain. The percentages in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME terminal is increased. The percentages in the second column should be used for the DAC voltages when decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the gain based on an increase or decrease in the desired system volume. This is explained further in a section below.
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APPLICATION INFORMATION volume control operation (continued)
If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND. VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column in Table 1 should be used to determine the point at which the gain changes depending on the direction that the potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the second column should be referenced. The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of the volume control can be found in Figure 26. The graph focuses on three gain steps with the trip points defined in the first and second columns of Table 1. The dotted lines represent the hysteresis about each gain step. The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is reached. For example, if the TPA3003D2 is currently in the +0.53 dB gain step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach +36 dB is 14 steps x 67ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step of +36 dB.
Decreasing Voltage on VOLUME Terminal 5.6
Class-D Gain - dB
3.1 Increasing Voltage on VOLUME Terminal
0.5
2.00 (40.1%*VREF)
2.21 2.10 2.11 (44.1%*VREF) (41.9%*VREF) (42.3%*VREF) Voltage on VOLUME Pin - V
Figure 26. DC Volume Control Operation, VREF = 5 V
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TPA3003D2
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APPLICATION INFORMATION FADE operation
The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions to and from the shutdown state and during power-up. A logic low on this terminal places the amplifier in the fade mode. During power-up or recovery from the shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute state, -75 dB, to the desired volume setting determined by the voltage on the volume control terminal. Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is reached. For example, if the TPA3003D2 is currently in the +0.53 dB class-D gain step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36 dB is 14 steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step of +36 dB. Figure 27 shows a scope capture of the differential output (measured across OUT+ and OUT-) with the amplifier in the fade mode. A 1 Vpp dc voltage was applied across the differential inputs and a logic low was applied to the SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step to the next lower step at approximately 67 ms/step. A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and during power-up. During power-up or recovery from the shutdown state (a logic high is applied to the SD terminal), the transition from the mute state, -75 dB, to the desired volume setting is less than 1 ms. Conversely, the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD terminal. Figure 28 shows a scope capture of the differential output with the fade effect disabled. The outputs transition to the lowest gain state within 1ms of applying a logic low to the SD terminal.
SD = 0V
GND
Figure 27. Differential Output With FADE (Terminal 30) Held Low
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SD = 0 V
GND
Figure 28. Differential Output With FADE Terminal Held High
MUTE operation
The MUTE pin is an input for controlling the output state of the TPA3003D2. A logic high on this pin disables the outputs. A logic low on this pin enables the outputs. This pin may be used as a quick disable or enable of the outputs without a volume fade. Quiescent current is listed in the dc characteristics specification table. The MUTE pin should never be left floating. For power conservation, the SD pin should be used to reduce the quiescent current to the absolute minimum level. The volume will fade, slowly increase or decrease, when leaving or entering the shutdown state if the FADE terminal is held low. If the FADE terminal is held high, the outputs will transition very quickly. Refer to the FADE operation section.
SD operation
The TPA3003D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. SD should never be left unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing the power supply voltage.
selection of COSC and ROSC
The switching frequency is determined using the values of the components connected to ROSC (pin 20) and COSC (pin 21) and may be calculated with the following equation: fOSC = 6.6 / (ROSC * COSC) The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC. The recommended values are COSC = 220 pF, ROSC=120 k for a switching frequency of 250 kHz.
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APPLICATION INFORMATION internal 2.5-V bias generator capacitor selection
The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stage. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance. During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75 x V2P5, or 75% of its final value, the device turns on and the class-D outputs start switching. The startup time is not critical for the best depop performance since any pop sound that is heard is the result of the class-D outputs switching on and not the startup time. However, at least a 0.47-F capacitor is recommended for the V2P5 capacitor. A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency also changes by over six times.
Zf Ci Input Signal IN Zi
The -3-dB frequency can be calculated using equation 5. f *3dB + 1 2p Z iC i (5)
input capacitor, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level (V2P5) for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-pass filter with the corner frequency determined in equation 6.
-3 dB
(6)
1 fc + 2 p Zi Ci
fc
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APPLICATION INFORMATION
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Zi is 20 k and the specification calls for a flat bass response down to 20 Hz. Equation 6 is reconfigured as equation 7. Ci + 1 2p Z i f c (7)
In this example, Ci is 0.4 F, so one would likely choose a value in the range of 0.47 F to 1 F. If the gain is known and will be constant, use Zi to calculate Ci. Calculations for Ci should be based off the impedance at the lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. power supply decoupling, CS The TPA3003D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 F placed as close as possible to the device VCC lead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 F or greater placed near the audio power amplifier is recommended. The 10-F capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. BSN and BSP capacitors The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit diagram in Figure 21.) VCLAMP capacitors To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-F capacitors must be connected from VCLAMPL (pin 25) and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary with VCC and may not be used for powering any other circuitry. internal regulated 5-V supply (AVDD) The AVDD terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator, preamplifier, and volume control circuitry. It requires a 0.1-F to 1-F capacitor, placed very close to the pin, to ground to keep the regulator stable. The regulator may not be used to power any external circuitry.
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APPLICATION INFORMATION
differential input The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3003D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3003D2 with a single-ended source, ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the audio source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the audio source instead of at the device input for best noise performance.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor.
short-circuit protection
The TPA3003D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the outputs, the output drive is immediately disabled. This is a latched fault and must be reset by cycling the voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the protection circuitry will again activate.
thermal protection
Thermal protection on the TPA3003D2 prevents damage to the device when the internal die temperature exceeds 150C. There is a 15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20C. The device begins normal operation at this point with no external system interaction.
thermal considerations: output power and maximum ambient temperature
To calculate the maximum ambient temperature, the following equation may be used: TAmax = TJ - JAPDissipated where: TJ = 150C JA = 45C/W (The derating factor for the 48-pin PFB package is given in the dissipation rating table.) To estimate the power dissipation, the following equation may be used: PDissipated = PO(average) x ((1 / Efficiency) - 1) Efficiency = ~75% for an 8- load (9) (8)
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APPLICATION INFORMATION thermal considerations: output power and maximum ambient temperature (continued)
Example. What is the maximum ambient temperature for an application that requires the TPA3003D2 to drive 3 W into an 8- speaker (stereo)? PDissipated = 6 W x ((1 / 0.75) - 1) = 2 W TAmax = 150C - (45C/W x 3.5 W) = 60C This calculation shows that the TPA3003D2 can drive 3 W of continuous RMS power per channel into an 8- speaker up to an ambient temperature of 60C. (PO = 3 W * 2)
printed circuit board (PCB) layout
Because the TPA3003D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.
D Decoupling capacitors -- As described on page 23, the high-frequency 0.1-uF decoupling capacitors
should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC (pin 33) terminals as possible. The V2P5 (pin 4) capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the device as possible. Large (10 uF or greater) bulk power supply decoupling capacitors should be placed near the TPA3003D2 on the PVCCL, PVCCR, and AVCC terminals.
D Grounding -- The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor,
COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26. The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42, 43). Basically, an AGND island should be created with a single connection to PGND.
D Output filter -- The ferrite EMI filter (Figure 25, page 18) should be placed as close to the output terminals
as possible for the best EMI performance. The LC filter (Figure 24, page 18 should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to PGND. For an example layout, please refer to the TPA3003D2 Evaluation Module (TPA3003D2EVM) User Manual, TI literature number SLOU159. The EVM user manual is available on the TI web site at http://www.ti.com.
basic measurement system
This section focuses on methods that use the basic equipment listed below:
D D D D D D D D D
Audio analyzer or spectrum analyzer Digital multimeter (DMM) Oscilloscope Twisted pair wires Signal generator Power resistor(s) Linear regulated power supply Filter components EVM or other complete audio circuit
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APPLICATION INFORMATION
Figure 29 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 k). Conversely the analyzer-input impedance should be high. The output impedance, ROUT, of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 29(a) shows a class-AB amplifier system, which is relatively simple because these amplifiers are linear their output signal is a linear representation of the input signal. They take analog signal input and produce analog signal output. These amplifier circuits can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 29(b), which requires low pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.
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APPLICATION INFORMATION
Power Supply
Signal Generator
APA
RL
Analyzer 20 Hz - 20 kHz
(a) Basic Class-AB
Power Supply
Low-Pass RC Filter Signal Generator Class-D APA RL Low-Pass RC Filter Analyzer 20 Hz - 20 kHz
(b) Filter-Free and Traditional Class-D
Figure 29. Audio Measurement Systems The TPA3003D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave.
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APPLICATION INFORMATION differential input and BTL output
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor. A block diagram of the measurement circuit is shown in Figure 30. The differential input is a balanced input, meaning the positive (+) and negative (-) pins will have the same impedance to ground. Similarly, the BTL output equates to a balanced output.
Evaluation Module Generator CIN VGEN RGEN CIN RGEN RIN RIN ROUT ROUT RL Low-Pass RC Filter Audio Power Amplifier Low-Pass RC Filter RANA RANA CANA CANA Analyzer
Twisted-Pair Wire
Twisted-Pair Wire
Figure 30. Differential Input--BTL Output Measurement Circuit The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
D D D D D
Use a balanced source to supply the input signal. Use an analyzer with balanced inputs. Use twisted-pair wire for all connections. Use shielding when the system environment is noisy. Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 2).
Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25C.
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Table 2. Recommended Minimum Wire Size for Power Cables
POUT (W) 1 < 0.75 RL () 8 8 AWG SIZE 22 to 28 22 to 28 DC POWER LOSS (mW) 2.0 1.5 8.0 6.1 AC POWER LOSS (mW) 2.1 1.6 8.1 6.2
Class-D RC low-pass filter
A RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 31. RL is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops.
Load RC Low-Pass Filters RFILT CFILT RL VL= VIN RFILT CFILT To APA GND CANA RANA VOUT CANA AP Analyzer Input
RANA
Figure 31. Measurement Low-Pass Filter Derivation Circuit--Class-D APAs
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APPLICATION INFORMATION
The transfer function for this circuit is shown in equation (10) where O = REQCEQ, REQ = RFILTRANA and CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal. Equation (11) provides this cutoff frequency, fC. The value of RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A rule of thumb is that RFILT should be small (~100 ) for most measurements. This reduces the measurement error to less than 1% for RANA 10 k. R + ANA )R ANA FILT w 1)j w O (10) (11) R
V
OUT V IN
f
C
+2
f
MAX
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same cutoff frequency. See Table 3 for the recommended filter component values. Once fC is determined and RFILT is selected, the filter capacitance is calculated using equation (12). When the calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value calculated in equation (11). C FILT + 1 2p f C R FILT (12)
Table 3 shows recommended values of RFILT and CFILT based on common component values. The value of fC was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57000 pF, but the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead, and fC is 34 kHz, which is above the desired value of 28 kHz. Table 3. Typical RC Measurement Filter Values
MEASUREMENT Efficiency All other measurements RFILT 1 000 100 CFILT 5 600 pF 56 000 pF
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MECHANICAL DATA
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
0,50 36 25
0,27 0,17
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0- 7 12
1,20 MAX
0,08 4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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