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TPA6011A4
SLOS392 - FEBRUARY 2002
2-W STEREO AUDIO POWER AMPLIFIER WITH ADVANCED DC VOLUME CONTROL
FEATURES D Advanced DC Volume Control With 2-dB Steps
From -40 dB to 20 dB - Fade Mode - Maximum Volume Setting for SE Mode - Adjustable SE Volume Control Referenced to BTL Volume Control 2 W Into 3- Speakers Stereo Input MUX Differential Inputs
DESCRIPTION
The TPA6011A4 is a stereo audio power amplifier that drives 2 W/channel of continuous RMS power into a 3- load. Advanced dc volume control minimizes external components and allows BTL (speaker) volume control and SE (headphone) volume control. Notebook and pocket PCs benefit from the integrated feature set that minimizes external components without sacrificing functionality. To simplify design, the speaker volume level is adjusted by applying a dc voltage to the VOLUME terminal. Likewise, the delta between speaker volume and headphone volume can be adjusted by applying a dc voltage to the SEDIFF terminal. To avoid an unexpected high volume level through the headphones, a third terminal, SEMAX, limits the headphone volume level when a dc voltage is applied. Finally, to ensure a smooth transition between active and shutdown modes, a fade mode ramps the volume up and down.
D D D
APPLICATIONS D Notebook PC D LCD Monitors D Pocket PC
APPLICATION CIRCUIT
Right Speaker ROUT+ 1 PGND SE/BTL CS Power Supply Ci Right HP Audio Source Right Line Audio Source 4 Ci 5 Ci 6 CS VDD 7 Ci 8 VDD LIN AGND BYPASS 18 C(BYP) 17 CC 1 k Headphones RIN 19 SEMAX RLINEIN RHPIN 21 VOLUME In From DAC or Potentiometer (DC Voltage) 2 3 ROUT- HP/LINE PVDD 22 100 k 1 k 24 23 VDD 100 k CC
DC VOLUME CONTROL
30 20 10 0 -10 Volume - dB -20 -30 -40 -50 -60 -70 SE Volume, SEDIFF [Pin 20] = 1 V SE Volume, SEDIFF [Pin 20] = 0 V BTL Volume
SEDIFF
20
Ci Left Line Audio Source Left HP Audio Source Power Supply CS 9 Ci 10 11 12 LLINEIN FADE 16 15 14 13 System Control
LHPIN SHUTDOWN PVDD LOUT- LOUT+ PGND
-80
Left Speaker
BTL Volume (dB) Volume (V) SE Volume (dB) Volume (V) - SEDIFF (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-90 Volume [Pin 21] - V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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TPA6011A4
SLOS392 - FEBRUARY 2002
AVAILABLE OPTIONS PACKAGE TA - 40C to 85C 24-PIN TSSOP (PWP) TPA6011A4PWP
NOTE: The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA6011A4PWPR).
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD+0.3 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE PWP TA 25C POWER RATING 2.7 mW DERATING FACTOR ABOVE TA = 25C 21.8 mW/C TA = 70C POWER RATING 1.7 W TA = 85C POWER RATING 1.4 W
recommended operating conditions
MIN Supply voltage, VDD, PVDD SE/BTL, HP/LINE, FADE High-level High level input voltage VIH voltage, Low level input voltage VIL Low-level voltage, Operating free-air temperature, TA SHUTDOWN SE/BTL, HP/LINE, FADE SHUTDOWN -40 4.0 0.8xVDD 2 0.6xVDD 0.8 85 MAX 5.5 UNIT V V V V V C
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TPA6011A4
SLOS392 - FEBRUARY 2002
electrical characteristics, TA = 25C, VDD = PVDD = 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS VDD = 5.5 V, Gain = 0 dB, SE/BTL = 0 V | VOO | Output offset voltage (measured differentially) VDD = 5.5 V, Gain = 20 dB, SE/BTL = 0 V VDD = PVDD = 4.0 V to 5.5 V VDD=PVDD = 5.5 V, VI = VDD = PVDD VDD = PVDD = 5.5 V, VI = 0 V 6.0 3.0 7.5 5 -42 -70 1 1 9.0 mA 6 MIN TYP MAX 30 50 UNIT mV mV dB A A
PSRR | IIH | | IIL |
Power supply rejection ratio High-level input current (SE/BTL, FADE, HP/LINE, SHUTDOWN, SEDIFF, SEMAX, VOLUME) Low-level input current (SE/BTL, FADE, HP/LINE, SHUTDOWN, SEDIFF, SEMAX, VOLUME)
VDD=PVDD = 5.5 V, SE/BTL = 0 V, SHUTDOWN = 2 V IDD Supply current no load current, VDD=PVDD = 5.5 V, SE/BTL = 5.5 V, SHUTDOWN = 2 V VDD= 5 V = PVDD,SE/BTL = 0 V, SHUTDOWN = 2 V, RL = 3, PO = 2 W, stereo SHUTDOWN = 0.0 V
IDD IDD(SD)
Supply current, max power into a 3- load Supply current, shutdown mode
1.5 1 20
ARMS A
operating characteristics, TA = 25C, VDD = PVDD = 5 V, RL = 3 , Gain = 6 dB (unless otherwise noted)
PARAMETER PO THD+N VOH VOL VBypass BOM Output power Total harmonic distortion + noise High-level output voltage Low-level output voltage Bypass voltage (Nominally VDD/2) Maximum output power bandwidth Supply ripple rejection ratio Noise output voltage ZI Input impedance (see figure 25) TEST CONDITIONS THD = 1%, f=1 kHz PO=1 W, RL=8 , f=20 Hz to 20 kHz RL = 8 , Measured between output and VDD RL = 8 , Measured between output and GND Measured at pin 17, No load, VDD = 5.5 V THD=5% f = 1 kHz, Gain = 0 dB, C(BYP) = 0.47 F f = 20 Hz to20 kHz, Gain = 0 dB, C(BYP) = 0.47 F VOLUME = 5.0 V BTL SE BTL 2.65 2.75 >20 -63 -57 36 14 MIN TYP 2 <0.4% 700 400 2.85 mV mV V kHz dB dB VRMS k MAX UNIT W
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TPA6011A4
SLOS392 - FEBRUARY 2002
PWP PACKAGE (TOP VIEW)
PGND ROUT- PVDD RHPIN RLINEIN RIN VDD LIN LLINEIN LHPIN PVDD LOUT-
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
ROUT+ SE/BTL HP/LINE VOLUME SEDIFF SEMAX AGND BYPASS FADE SHUTDOWN LOUT+ PGND
Terminal Functions
TERMINAL NAME PGND LOUT- PVDD LHPIN LLINEIN LIN VDD RIN RLINEIN RHPIN ROUT- ROUT+ SHUTDOWN FADE BYPASS AGND SEMAX SEDIFF VOLUME HP/LINE SE/BTL LOUT+ NO. 1, 13 12 3, 11 10 9 8 7 6 5 4 2 24 15 16 17 18 19 20 21 22 23 14 I/O - O - I I I - I I I O O I I I - I I I I I O Power ground Left channel negative audio output Supply voltage terminal for power stage Left channel headphone input, selected when HP/LINE is held high Left channel line input, selected when HP/LINE is held low Common left channel input for fully differential input. AC ground for single-ended inputs. Supply voltage terminal Common right channel input for fully differential input. AC ground for single-ended inputs. Right channel line input, selected when HP/LINE is held low Right channel headphone input, selected when HP/LINE is held high Right channel negative audio output Right channel positive audio output Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high is placed on this terminal Tap to voltage divider for internal midsupply bias generator used for analog reference Analog power supply ground Sets the maximum volume for single ended operation. DC voltage range is 0 to VDD. Sets the difference between BTL volume and SE volume. DC voltage range is 0 to VDD. Terminal for dc volume control. DC voltage range is 0 to VDD. Input MUX control. When logic high, RHPIN and LHPIN inputs are selected. When logic low, RLINEIN and LLINEIN inputs are selected. Output MUX control. When this terminal is high, SE outputs are selected. When this terminal is low, BTL outputs are selected. Left channel positive audio output. DESCRIPTION
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TPA6011A4
SLOS392 - FEBRUARY 2002
functional block diagram
RHPIN RLINEIN
R MUX HP/LINE
_ _ + + BYP BYP + _ BYP _ + EN SE/BTL PVDD PGND VDD BYPASS SHUTDOWN AGND ROUT- ROUT+
RIN
SE/BTL HP/LINE
MUX Control
VOLUME SEDIFF SEMAX FADE LHPIN LLINEIN L MUX HP/LINE LIN 32-Step Volume Control
Power Management
_ _ + + BYP BYP + _ BYP _ + EN SE/BTL LOUT- LOUT+
NOTE: All resistor wipers are adjusted with 32 step volume control.
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TPA6011A4
SLOS392 - FEBRUARY 2002
Table 1. DC Volume Control (BTL Mode, VDD = 5 V)
VOLUME (PIN 21) FROM (V) 0.00 0.33 0.44 0.56 0.67 0.78 0.89 1.01 1.12 1.23 1.35 1.46 1.57 1.68 1.79 1.91 2.02 2.13 2.25 2.36 2.47 2.58 2.70 2.81 2.92 3.04 3.15 3.26 3.38 3.49 3.60 3.71 TO (V) 0.26 0.37 0.48 0.59 0.70 0.82 0.93 1.04 1.16 1.27 1.38 1.49 1.60 1.72 1.83 1.94 2.06 2.17 2.28 2.39 2.50 2.61 2.73 2.83 2.95 3.06 3.17 3.29 3.40 3.51 3.63 5.00 GAIN OF AMPLIFIER (Typ) -85 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20
Tested in production. Remaining gain steps are specified by design. NOTE: For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
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TPA6011A4
SLOS392 - FEBRUARY 2002
Table 2. DC Volume Control (SE Mode, VDD = 5 V)
SE_VOLUME = VOLUME - SEDIFF or SEMAX FROM (V) 0.00 0.33 0.44 0.56 0.67 0.78 0.89 1.01 1.12 1.23 1.35 1.46 1.57 1.68 1.79 1.91 2.02 2.13 2.25 2.36 2.47 2.58 2.70 2.81 2.92 3.04 3.15 3.26 3.38 3.49 3.60 3.71 TO (V) 0.26 0.37 0.48 0.59 0.70 0.82 0.93 1.04 1.16 1.27 1.38 1.49 1.60 1.72 1.83 1.94 2.06 2.17 2.28 2.39 2.50 2.61 2.73 2.83 2.95 3.06 3.17 3.29 3.40 3.51 3.63 5.00 GAIN OF AMPLIFIER (Typ) -85 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
14 Tested in production. Remaining gain steps are specified by design. NOTE: For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE THD+N THD N Total harmonic distortion plus noise (BTL) vs Frequency vs Output power vs Frequency THD+N Total harmonic distortion plus noise (SE) lus Closed loop response ICC PD PO Supply current Power Dissipation Output power Crosstalk HP/LINE attenuation PSRR PSRR ZI Vn Power supply ripple rejection (BTL) Power supply ripple rejection (SE) Input impedance Output noise voltage vs Temperature vs Supply voltage vs Output power vs Load resistance vs Frequency vs Frequency vs Frequency vs Frequency vs BTL gain vs Frequency vs Output power vs Output voltage 1, 2 3 6, 7, 8 4, 5 9 10 11, 12 13 14, 15, 16 17, 18 19 20, 21 22 23 24 25 26
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY
10 5 2 1 0.5 PO = 0.5 W 0.2 0.1 0.05 0.02 0.01 20 100 1k f - Frequency - Hz 10 k 20 k PO = 1 W VDD = 5 V RL = 3 Gain = 20 dB BTL
THD+N - Total Harmonic Distortion + Noise (BTL) - %
THD+N - Total Harmonic Distortion + Noise (BTL) - %
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY
10 5 2 1 0.5 PO = 0.25 W 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k PO = 1 W VDD = 5 V RL = 4 Gain = 20 dB BTL PO = 1.5 W
PO = 1.75 W
f - Frequency - Hz
Figure 1
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY
THD+N - Total Harmonic Distortion + Noise (BTL) - % THD+N - Total Harmonic Distortion + Noise (SE) - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k PO = 1 W 5 k 10 k 20 k PO = 0.25 W VDD = 5 V RL = 8 Gain = 20 dB BTL
Figure 2
TOTAL HARMONIC DISTORTION + NOISE (SE) vs FREQUENCY
10 5 2 1 0.5 0.2 0.1 0.05 PO = 75 mW 0.02 0.01 20 50 100 200 500 1k 2k 5 k 10 k 20 k VDD = 5 V RL = 32 Gain = 14 dB SE
PO = 0.5 W
f - Frequency - Hz
f - Frequency - Hz
Figure 3
Figure 4
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE (SE) vs FREQUENCY
THD+N - Total Harmonic Distortion + Noise (SE) - % THD+N - Total Harmonic Distortion + Noise (BTL) - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1 k 2 k f - Frequency - Hz 5 k 10 k 20 k VO = 1 VRMS VDD = 5 V RL = 10 k Gain = 14 dB SE
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER
10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.01 f = 20 Hz VDD = 5 V RL = 3 Gain = 20 dB BTL
f = 20 kHz
f = 1 kHz
0.1 1 PO - Output Power - W
10
Figure 5
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise (BTL) - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.02 0.05 0.1 0.2 0.5 1 PO - Output Power - W 2 5 20 kHz THD+N - Total Harmonic Distortion + Noise (BTL) - % VDD = 5 V RL = 4 Gain = 20 dB BTL
Figure 6
TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER
10 5 2 1 0.5 20 kHz 0.2 0.1 0.05 0.02 0.01 0.02 0.05 0.1 0.2 0.5 1 PO - Output Power - W 2 5 1 kHz 20 Hz VDD = 5 V RL = 8 Gain = 20 dB BTL
1 kHz 20 Hz
Figure 7
Figure 8
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE (SE) vs OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise (SE) - % THD+N - Total Harmonic Distortion + Noise (SE) - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 10 m 20 kHz 1 kHz 50 m 100 m PO - Output Power - W 200 m 20 Hz VDD = 5 V RL = 32 Gain = 14 dB SE
TOTAL HARMONIC DISTORTION + NOISE (SE) vs OUTPUT VOLTAGE
10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0 500 m 1 1.5 VO - Output Voltage - rms 2 1 kHz 20 Hz 20 kHz VDD = 5 V RL = 10 k Gain = 14 dB SE
Figure 9
CLOSED LOOP RESPONSE
40 30 20 10 Closed Loop Gain - dB 0 -10 -20 -30 -40 -50 -60 -70 -80 10 100 1k 10 k 100 k Phase VDD = 5 Vdc RL = 8 Mode = BTL Gain = 0 dB Gain 180 150 120 Phase - Degrees Closed Loop Gain - dB 90 60 30 0 -30 -60 -90 -120 -150 -180 1M 40 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 10 VDD = 5 Vdc RL = 8 Mode = BTL Gain = 20 dB 100
Figure 10
CLOSED LOOP RESPONSE
180 Gain 150 120 90 60 30 Phase 0 -30 -60 -90 -120 -150 1k 10 k 100 k -180 1M Phase - Degrees 11
f - Frequency - Hz
f - Frequency - Hz
Figure 11
Figure 12
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
10 VDD = 5 V Mode = BTL SHUTDOWN = VDD I DD - Supply Current - mA 9 8 7 6 5 4 3 2 1 1 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 -1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD - Supply Voltage - V TA = -40C TA = 25C Mode = BTL SHUTDOWN = VDD TA = 125C
10 9 I DD - Supply Current - mA 8 7 6 5 4 3 2
SUPPLY CURRENT vs SUPPLY VOLTAGE
TA - Free-Air Temperature - C
Figure 13
SUPPLY CURRENT vs SUPPLY VOLTAGE
7 6 I DD - Supply Current - mA 5 Mode = SE SHUTDOWN = VDD TA = 125C I DD - Supply Current - nA 450 400 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VDD - Supply Voltage - V 5 5.5
Figure 14
SUPPLY CURRENT vs SUPPLY VOLTAGE
Mode = SD SHUTDOWN = 0 V
TA = 125C
4 TA = 25C
3
2 TA =-40C 1 0
TA = -40C
TA = 25C
0
0.5
1
1.5 2 2.5 3 3.5 VDD - Supply Voltage - V
4
4.5
5
Figure 15
Figure 16
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
POWER DISSIPATION (PER CHANNEL) vs OUTPUT POWER
2 PD- Power Dissipation (PER CHANNEL) - W 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 PO - Output Power - W 8 4 VDD = 5 V BTL 3 PD- Power Dissipation (PER CHANNEL) - mW 200 180 160 140 120 100 80 60 32 40 20 0 0 50 100 150 200 250 300 16 VDD = 5 V SE 8
POWER DISSIPATION (PER CHANNEL) vs OUTPUT POWER
PO - Output Power - mW
Figure 17
OUTPUT POWER vs LOAD RESISTANCE
2.2 2 1.8 PO - Output Power - W 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 8 16 24 32 40 48 56 RL - Load Resistance - 64 Crosstalk - dB VDD = 5 V THD+N = 1% Gain = 20 dB BTL 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 100 VDD = 5 V PO = 1 W RL = 8 Gain = 0dB BTL
Figure 18
CROSSTALK vs FREQUENCY
Left to Right
Right to Left 1k f - Frequency - Hz 10 k 20 k
Figure 19
Figure 20
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
CROSSTALK vs FREQUENCY
0 -10 -20 -30 Crosstalk - dB -40 -50 -60 -70 -80 -90 -100 -110 -120 20 100 Right to Left Left to Right VDD = 5 V PO = 1 W RL = 8 Gain = 20 dB BTL
HP/LINE ATTENUATION vs FREQUENCY
0 -10 -20 HP/Line Attenuation - dB -30 -40 -50 -60 -70 HP Active -80 -90 -100 -110 -120 20 100 1k 10 k 20 k Line Active VDD = 5 V VI = 1 VRMS RL = 8 BTL
1k f - Frequency - Hz
10 k 20 k
f - Frequency - Hz
Figure 21
POWER SUPPLY REJECTION RATIO (BTL) vs FREQUENCY
PSRR - Power Supply Rejection Ratio (BTL) - dB PSRR - Power Supply Rejection Ratio (SE) - dB 0 -10 -20 -30 -40 -50 -60 -70 -80 20 Gain = 1 VDD = 5 V RL = 8 C(BYP) =0.47 F BTL +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100
Figure 22
POWER SUPPLY REJECTION RATIO (SE) vs FREQUENCY
VDD = 5 V RL = 32 C(BYP) =0.47 F SE
Gain = 0 dB
Gain = 10
Gain = 14 dB
100
1k f - Frequency - Hz
10 k 20 k
1k f - Frequency - Hz
10 k 20 k
Figure 23
Figure 24
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TPA6011A4
SLOS392 - FEBRUARY 2002
TYPICAL CHARACTERISTICS
INPUT IMPEDANCE vs BTL GAIN
90 80 70 ZI - Input Impedamce - k 60 50 40 30 20 10 0 -40 -30 -20 -10 0 10 20
BTL Gain - dB
Figure 25
OUTPUT NOISE VOLTAGE vs FREQUENCY
180 V n - Output Noise Voltage - V RMS 160 140 120 100 80 60 Gain = 0 dB 40 20 0 10 100 1k 10 k 20 k VDD = 5 V BW = 22 Hz to 22 kHz RL = 8 BTL Gain = 20 dB
f - Frequency - Hz
Figure 26
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION selection of components
Figure 27 and Figure 28 are schematic diagrams of typical notebook computer application circuits.
Right Speaker ROUT+ 1 PGND SE/BTL CS Power Supply Ci Right HP Audio Source Right Line Audio Source 4 Ci 5 Ci VDD 7 Ci 8 VDD LIN AGND BYPASS 16 15 SHUTDOWN LOUT+ PGND 14 13 CC 1 k 18 C(BYP) 17 Headphones 6 RLINEIN RIN RHPIN 21 VOLUME SEDIFF SEMAX 20 19 In From DAC or Potentiometer (DC Voltage) 2 3 ROUT- HP/LINE PVDD 22 100 k 1 k 24 23 VDD CC
100 k
CS
Ci Left Line Audio Source Left HP Audio Source Power Supply CS 9 Ci 10 11 12 LHPIN PVDD LOUT- LLINEIN FADE
System Control Left Speaker
NOTE A:
A 0.1-F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of 10 F or greater should be placed near the audio power amplifier.
Figure 27. Typical TPA6011A4 Application Circuit Using Single-Ended Inputs and Input MUX
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION
Right Speaker ROUT+ 1 PGND SE/BTL CS Power Supply 2 3 ROUT- HP/LINE PVDD RHPIN RLINEIN RIN 21 VOLUME SEDIFF SEMAX 18 C(BYP) 17 BYPASS 16 15 SHUTDOWN LOUT+ PGND 14 13 CC 1 k Headphones 20 19 In From DAC or Potentiometer (DC Voltage) 22 100 k 1 k 24 23 VDD CC
100 k
NC Ci Right Negative Differential Input Signal Right Positive Differential Input Signal CS
4 5
Ci VDD
6
7 Ci Left Positive Differential Input Signal Ci Left Negative Differential Input Signal NC Power Supply CS 9 10 11 12 8
VDD LIN
AGND
LLINEIN LHPIN PVDD LOUT-
FADE
System Control Left Speaker
NOTE A:
A 0.1-F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of 10 F or greater should be placed near the audio power amplifier.
Figure 28. Typical TPA6011A4 Application Circuit Using Differential Inputs
SE/BTL operation
The ability of the TPA6011A4 to easily switch between BTL and SE modes is one of its most important cost saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the TPA6011A4, two separate amplifiers drive OUT+ and OUT-. The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-. When SE/BTL is held low, the amplifier is on and the TPA6011A4 is in the BTL mode. When SE/BTL is held high, the OUT- amplifiers are in a high output impedance state, which configures the TPA6011A4 as an SE driver from LOUT+ and ROUT+. IDD is reduced by approximately one-third in SE mode. Control of the SE/BTL input can be from a logic-level CMOS source or, more typically, from a resistor divider network as shown in Figure 29. The trip level for the SE/BTL input can be found in the recommended operating conditions table on page 4.
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION SE/BTL operation (continued)
4 5
RHPIN RLINEIN R MUX _ _ + ROUT+ 24 Input MUX Control + Bypass
22 6
HP/LINE RIN
Bypass VDD + _ _ + Bypass EN SE/BTL 23 100 k ROUT- 2 100 k
CO 330 F 1 k
LOUT+
Figure 29. TPA6011A4 Resistor Divider Network Circuit Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed the 100-k/1-k divider pulls the SE/BTL input low. When a plug is inserted, the 1-k resistor is disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT- amplifier is shut down causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output capacitor (Co) into the headphone jack.
HP/LINE operation
The HP/LINE input controls the internal input multiplexer (MUX). Refer to the block diagram in Figure 29. This allows the device to switch between two separate stereo inputs to the amplifier. For design flexibility, the HP/LINE control is independent of the output mode, SE or BTL, which is controlled by the aforementioned SE/BTL pin. To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches from BTL mode to SE mode, simply connect the SE/BTL control input to the HP/LINE input. When this input is logic high, the RHPIN and LHPIN inputs are selected. When this terminal is logic low, the RLINEIN and LLINEIN inputs are selected. This operation is also detailed in Table 3 and the trip levels for a logic low (VIL) or logic high (VIH) can be found in the recommended operating conditions table on page 4.
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION shutdown modes
The TPA6011A4 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, IDD = 20 A. SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable. Table 3. HP/LINE, SE/BTL, and Shutdown Functions
INPUTS HP/LINE X Low Low High SE/BTL X Low High Low SHUTDOWN Low High High High AMPLIFIER STATE INPUT X Line Line HP OUTPUT Mute BTL SE BTL
High High High HP SE Inputs should never be left unconnected. X = don't care NOTE: The Low and High trip levels can be found in the recommended operating conditions table.
FADE operation
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs. When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the recommended operating conditions table on page 4. When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock frequency of 58 Hz, this equates to 34 ms (1/24 Hz) per step. The gain steps down until the lowest gain step is reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown. For example, if the amplifier is in the highest gain mode of 20 dB, the time it takes to ramp down the channel gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the highest gain, or 31 steps, and multiplying by the time per step, or 34 ms. After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a 0.47-F capacitor that is used in the application diagram in Figure 27, the time is approximately 500 ms. This time scales linearly with the value of bypass capacitor. For example, if a 1-F capacitor is used for bypass, the time period to discharge the capacitor to ground is twice that of the 0.47-F capacitor, or 1 second. Figure 30 below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode. The gain is set to the highest level and the output is at VDD when the amplifier is shut down. When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of VDD/2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage applied to the VOLUME, SEDIFF, and SEMAX pins.
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TPA6011A4
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APPLICATION INFORMATION FADE operation (continued)
In the fade-off mode, the amplifier stores the gain value prior to starting the shutdown sequence. The output of the amplifier immediately drops to VDD/2 and the bypass capacitor begins a smooth discharge to ground. When shutdown is released, the bypass capacitor charges up to VDD/2 and the channel gain returns immediately to the value stored in memory. Figure 31 below is a waveform captured at the output during the shutdown sequence when the part is in the fade-off mode. The gain is set to the highest level, and the output is at VDD when the amplifier is shut down. The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not change the power-up sequence. Upon a power-up condition, the TPA6011A4 begins in the lowest gain setting and steps up 2 dB every 2 clock cycles until the final value is reached as determined by the dc voltage applied to the VOLUME, SEDIFF, and SEMAX pins.
Device Shutdown ROUT+
Figure 30. Shutdown Sequence in the Fade-on Mode
Device Shutdown ROUT+
Figure 31. Shutdown Sequence in the Fade-off Mode
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION VOLUME, SEDIFF, and SEMAX operation
Three pins labeled VOLUME, SEDIFF, and SEMAX control the BTL volume when driving speakers and the SE volume when driving headphones. All of these pins are controlled with a dc voltage, which should not exceed VDD. When driving speakers in BTL mode, the VOLUME pin is the only pin that controls the gain. Table 1 shows the gain for the BTL mode. The voltages listed in the table are for VDD = 5 V. For a different VDD, the values in the table scale linearly. If VDD = 4 V, multiply all the voltages in the table by 4 V/5 V, or 0.8. The TPA6011A4 allows the user to specify a difference between BTL gain and SE gain. This is desirable to avoid any listening discomfort when plugging in headphones. When switching to SE mode, the SEDIFF and SEMAX pins control the singe-ended gain proportional to the gain set by the voltage on the VOLUME pin. When SEDIFF = 0 V, the difference between the BTL gain and the SE gain is 6 dB. Refer to the section labeled bridged-tied load versus single-ended load for an explanation on why the gain in BTL mode is 2x that of single-ended mode, or 6dB greater. As the voltage on the SEDIFF terminal is increased, the gain in SE mode decreases. The voltage on the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to determine the SE gain. Some audio systems require that the gain be limited in the single-ended mode to a level that is comfortable for headphone listening. Most volume control devices only have one terminal for setting the gain. For example, if the speaker gain is 20 dB, the gain in the headphone channel is fixed at 14 dB. This level of gain could cause discomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging in headphones. The SEMAX terminal controls the maximum gain for single-ended mode. The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain. A block diagram of the combined functionality is shown in Figure 32. The value obtained from the block diagram for SE_VOLUME is a dc voltage that can be used in conjunction with Table 2 to determine the SE gain. Again, the voltages listed in the table are for VDD = 5V. The values must be scaled for other values of VDD. Tables 1 and 2 show a range of voltages for each gain step. There is a gap in the voltage between each gain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. If a potentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer is turned in one direction and decreases as it is turned back the other direction. The trip point, where the gain actually changes, is different depending on whether the voltage is increased or decreased as a result of the hysteresis about each trip point. The gaps in tables 1 and 2 can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensure that the desired gain is achieved. A pictorial representation of the volume control can be found in Figure 33. The graph focuses on three gain steps with the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about each gain step.
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TPA6011A4
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APPLICATION INFORMATION VOLUME, SEDIFF, and SEMAX operation (continued)
SEDIFF (V) SEMAX (V)
- + VOLUME (V) VOLUME-SEDIFF
Is SEMAX> (VOLUME-SEDIFF) ?
NO
SE_VOLUME (V) = VOLUME (V) - SEDIFF (V)
YES
SE_VOLUME (V) = SEMAX (V)
Figure 32. Block Diagram of SE Volume Control
4
BTL Gain - dB
2
0
2.61
2.70
2.73
2.81
Voltage on VOLUME Pin - V
Figure 33. DC Volume Control Operation
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency also changes by over six times. If an additional resistor is connected from the input pin of the amplifier to ground, as shown in the figure below, the variation of the cutoff frequency is much reduced.
Rf C Input Signal IN Ri
Figure 34. Resistor on Input for Cut-Off Frequency The input resistance at each gain setting is given in Figure 34. The -3-dB frequency can be calculated using equation 1.
*3 dB + input capacitor, Ci
1 2p CR
i
(1)
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Ri) form a high-pass filter with the corner frequency determined in equation 2.
-3 dB
f c(highpass) +
1 2 p Ri Ci
(2)
fc
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TPA6011A4
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APPLICATION INFORMATION input capacitor, Ci (continued)
The value of Ci is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Ri is 70 k and the specification calls for a flat-bass response down to 40 Hz. Equation 2 is reconfigured as equation 3.
Ci + 1 2 p Ri fc
(3)
In this example, Ci is 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. power supply decoupling, C(S) The TPA6011A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 F placed as close as possible to the device VDD lead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 F or greater placed near the audio power amplifier is recommended. midrail bypass capacitor, C(BYP) The midrail bypass capacitor (C(BYP)) is the most critical capacitor and serves several important functions. During start-up or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD+N. Bypass capacitor (C(BYP)) values of 0.47-F to 1-F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. For the best pop performance, choose a value for C(BYP) that is equal to or greater than the value chosen for Ci. This ensures that the input capacitors are charged up to the midrail voltage before C(BYP) is fully charged to the midrail voltage.
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION output coupling capacitor, C(C)
In the typical single-supply SE configuration, an output coupling capacitor (C(C)) is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation 4.
-3 dB
f c(high) +
1 2 p R L C (C)
(4)
fc
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives the low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass low frequencies into the load. Consider the example where a C(C) of 330 F is chosen and loads vary from 3 , 4 , 8 , 32 , 10 k, and 47 k. Table 4 summarizes the frequency response characteristics of each configuration. Table 4. Common Load Impedances Vs Low Frequency Output Characteristics in SE Mode
RL 3 4 8 32 10,000 47,000 C(C) 330 F 330 F 330 F 330 F 330 F 330 F Lowest Frequency 161 Hz 120 Hz 60 Hz 15 Hz 0.05 Hz 0.01 Hz
As Table 4 indicates, most of the bass response is attenuated into a 4- load, an 8- load is adequate, headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.
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TPA6011A4
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APPLICATION INFORMATION bridged-tied load versus single-ended lode
Figure 35 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6011A4 BTL amplifier consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differential drive configuration, but, initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Plugging 2 x VO(PP) into the power equation, where voltage is squared, yields 4x the output power from the same supply rail and load impedance (see equation 5).
V (rms) + Power + V O(PP)
22 2
(5)
V (rms) RL
VDD
VO(PP)
RL VDD
2x VO(PP)
-VO(PP)
Figure 35. Bridge-Tied Load Configuration In a typical computer sound channel operating at 5 V, bridging raises the power into an 8- speaker from a singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the single-supply SE configuration shown in Figure 36. A coupling capacitor is required to block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately 33 F to 1000 F), so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance and is calculated with equation 6.
f (c) + 1 2 p RL CC
(6)
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION bridged-tied load versus single-ended lode (continued)
For example, a 68-F capacitor with an 8- speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor.
VDD -3 dB
VO(PP)
C(C) RL
VO(PP)
fc
Figure 36. Single-Ended Configuration and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4x the output power of the SE configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal considerations section.
single-ended operation
In SE mode (see Figure 36), the load is driven from the primary amplifier output for each channel (OUT+). The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative outputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.
BTL amplifier efficiency
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that varies inversely to output power. The second component is due to the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power dissipation of the amplifier. An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 37).
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APPLICATION INFORMATION BTL amplifier efficiency (continued)
VO V(LRMS) IDD IDD(avg)
Figure 37. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency. Efficiency of a BTL amplifier + Where: PL + PL P SUP
2
(7)
V Lrms 2 V V , and V LRMS + P , therefore, P L + P RL 2 RL 2 and I DDavg + 1 p
p
and P SUP + V DD I DDavg Therefore, P SUP + 2 V DD V P p RL
0
VP 1 sin(t) dt + p RL
VP RL
p [cos(t)] 0 + 2V P
p RL
substituting PL and PSUP into equation 7,
VP 2 RL 2 V DD V P p RL
2
Efficiency of a BTL amplifier + Where: VP + Therefore, h BTL + 2 PL RL
+
p VP 4 V DD
(8) p 2 PL RL 4 V DD
VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage BTL = Efficiency of a BTL amplifier
PL = Power delivered to load PSUP = Power drawn from power supply VLRMS = RMS voltage on BTL load RL = Load resistance
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION BTL amplifier efficiency (continued)
Table 5 employs equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1-W audio system with 8- loads and a 5-V supply, the maximum draw on the power supply is almost 3.25 W. Table 5. Efficiency vs Output Power in 5-V, 8- BTL Systems
Output Power (W) 0.25 0.50 1.00 Efficiency (%) 31.4 44.4 62.8 Peak Voltage (V) 2.00 2.83 4.00 4.47 Internal Dissipation (W) 0.55 0.62 0.59 0.53
1.25 70.2 High peak voltages cause the THD to increase.
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation 8, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up.
crest factor and thermal considerations
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal dissipated power at the average output power level must be used. From the TPA6011A4 data sheet, one can see that when the TPA6011A4 is operating from a 5-V supply into a 3- speaker, that 4-W peaks are available. Use equation 9 to convert watts to dB. P dB + 10Log PW P ref + 10 Log 4 W + 6 dB 1W (9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields: 6 dB - 15 dB = -9 dB (15-dB crest factor) 6 dB - 12 dB = -6 dB (12-dB crest factor) 6 dB - 9 dB = -3 dB (9-dB crest factor) 6 dB - 6 dB = 0 dB (6-dB crest factor) 6 dB - 3 dB = 3 dB (3-dB crest factor)
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TPA6011A4
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APPLICATION INFORMATION crest factor and thermal considerations (continued)
To convert dB back into watts use equation 10. P W + 10 PdB 10 P ref (10)
= 63 mW (18-db crest factor) = 125 mW (15-db crest factor) = 250 mW (12-db crest factor) = 500 mW (9-db crest factor) = 1000 mW (6-db crest factor) = 2000 mW (3-db crest factor) This is valuable information to consider when attempting to estimate the heat dissipation requirements for the amplifier system. Comparing the worst case, which is 2 W of continuous power output with a 3-dB crest factor, against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system. Using the power dissipation curves for a 5-V, 3- system, the internal dissipation in the TPA6011A4 and maximum ambient temperatures is shown in Table 6. Table 6. TPA6011A4 Power Rating, 5-V, 3- Stereo
PEAK OUTPUT POWER (W) 4 4 4 4 4 4 AVERAGE OUTPUT POWER 2 W (3 dB) 1 W (6 dB) 500 mW (9 dB) 250 mW (12 dB) 125 mW (15 dB) 63 mW (18 dB) POWER DISSIPATION (W/Channel) 1.7 1.6 1.4 1.1 0.8 0.6 MAXIMUM AMBIENT TEMPERATURE - 3C 6C 24C 51C 78C 96C
Table 7. TPA6011A4 Power Rating, 5-V, 8- Stereo
PEAK OUTPUT POWER (W) 2.5 2.5 2.5 2.5 AVERAGE OUTPUT POWER 1250 mW (3-dB crest factor) 1000 mW (4-dB crest factor) 500 mW (7-dB crest factor) 250 mW (10-dB crest factor) POWER DISSIPATION (W/Channel) 0.55 0.62 0.59 0.53 MAXIMUM AMBIENT TEMPERATURE 100C 94C 97C 102C
The maximum dissipated power (PD(max)) is reached at a much lower output power level for an 8- load than for a 3- load. As a result, this simple formula for calculating PD(max) may be used for an 8- application. P D(max) + 2V 2
DD
p 2R L
(11)
However, in the case of a 3- load, the PD(max) occurs at a point well above the normal operating power level. The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula for a 3- load.
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TPA6011A4
SLOS392 - FEBRUARY 2002
APPLICATION INFORMATION crest factor and thermal considerations (continued)
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the PWP package is shown in the dissipation rating table. Use equation 12 to convert this to JA.
JA +
1 1 + 0.022 Derating Factor
+ 45C W
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per channel, so the dissipated power needs to be doubled for two channel operation. Given JA, the maximum allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be calculated using equation 13. The maximum recommended junction temperature for the TPA6011A4 is 150C. The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs. T A Max + T J Max * JA P D + 150 * 45 (0.6 2) + 96C (15-dB crest factor)
NOTE: Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel.
(13)
Tables 6 and 7 show that some applications require no airflow to keep junction temperatures in the specified range. The TPA6011A4 is designed with thermal protection that turns the device off when the junction temperature surpasses 150C to prevent damage to the IC. Table 6 and 7 were calculated for maximum listening volume without distortion. When the output level is reduced the numbers in the table change significantly. Also, using 8- speakers increases the thermal performance by increasing amplifier efficiency.
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MECHANICAL DATA
PWP (R-PDSO-G**)
20 PINS SHOWN
PowerPAD PLASTIC SMALL-OUTLINE
0,65 20
0,30 0,19 11
0,10 M
Thermal Pad (See Note D) 4,50 4,30 6,60 6,20 0,15 NOM
Gage Plane 1 A 10 0- 8 0,25 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 PINS ** DIM A MAX A MIN 0,10
14 5,10 4,90
16 5,10 4,90
20 6,60 6,40
24 7,90 7,70
28 9,80 9,60 4073225/F 10/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
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Copyright 2002, Texas Instruments Incorporated

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