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| MAIN FEATURES 8-bit resolution. ADC gain adjust. 1.5 GHz full power input bandwidth. 1 Gsps (min) sampling rate. SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc @ FS = 1 Gsps, FIN = 20 MHz : SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc @ FS = 1 Gsps, FIN = 500 MHz : SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc @ FS = 1 Gsps, FIN = 1000 MHz (-3 dB FS) 2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS. DNL = 0.3 LSB INL = 0.7 LSB. -13 Low Bit Error Rate (10 ) @ 1 Gsps Very low input capacitance : 3 pF 500 mVpp differential or single-ended analog inputs. Differential or single-ended 50 ECL compatible clock inputs. ECL or LVDS/HSTL output compatibility. Data ready output with asynchronous reset. Gray or Binary selectable output data ; NRZ output mode. Power consumption : 3.4 W @ Tj = 70C typical CQFP package enhanced with heatspreader : Rthjc = 1.56C/W Dual power supply : 5 V Radiation tolerance oriented design (150 Krad (Si) measured). ADC 8-bit 1 Gsps TS8388BFS 1/ Die form : JTS8388B 2/ Evaluation board : TSEV8388BF 3/ Demultiplexer : TS81102G0 : companion device available APPLICATIONS Digital Sampling Oscilloscopes. Satellite receiver. Electronic countermeasures / Electronic warfare. Direct RF down-conversion. SCREENING Mil-PRF-38535, QML level Q for package version, DSCC 5962-0050401QYC Space screening according to ESA/SCC 9000. Temperature range: up to -55C < Tc ; Tj < +125C DESCRIPTION The TS8388BFS is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 Gsps. The TS8388BFS is using an innovative architecture, including an on chip Sample and Hold (S/H), and is fabricated with an advanced high speed bipolar process. The on-chip S/H has a 1.5 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). January 2002 FS Suffix : CQFP 68 Ceramic Quad Flat Pack With heatspreader Product Specification Product Specification TABLE OF CONTENTS 1. 2. 3. SIMPLIFIED BLOCK DIAGRAM ....................................................................................................................................3 FUNCTIONAL DESCRIPTION ........................................................................................................................................3 SPECIFICATIONS ..............................................................................................................................................................4 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).................................................................................................................... 4 RECOMMENDED CONDITIONS OF USE ............................................................................................................................................. 4 ELECTRICAL OPERATING CHARACTERISTICS ................................................................................................................................. 5 TIMING DIAGRAMS................................................................................................................................................................................ 9 EXPLANATION OF TEST LEVELS ...................................................................................................................................................... 10 FUNCTIONS DESCRIPTION................................................................................................................................................................ 10 DIGITAL OUTPUT CODING ................................................................................................................................................................. 10 TS8388BFS PIN DESCRIPTION .......................................................................................................................................................... 11 TS8388BFS PINOUT ............................................................................................................................................................................ 12 OUTLINE DIMENSIONS - 68 PINS CQFP .......................................................................................................................................... 13 THERMAL CHARACTERISTICS .......................................................................................................................................................... 14 STATIC LINEARITY - FS = 50 MSPS / FIN = 10 MHZ......................................................................................................................... 15 EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION ..................................................................................... 16 TYPICAL FFT RESULTS ...................................................................................................................................................................... 17 SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE ................................................................................................ 18 DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ............................................................................................. 20 EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY .................................................................................. 21 SFDR VERSUS SAMPLING FREQUENCY ......................................................................................................................................... 21 TS8388BFS ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE ................................................................................... 22 TYPICAL FULL POWER INPUT BANDWIDTH .................................................................................................................................... 23 ADC STEP RESPONSE................................................................................................................................................................... 24 4. PACKAGE DESCRIPTION. ............................................................................................................................................11 4.1. 4.2. 4.3. 4.4. 5. TYPICAL CHARACTERIZATION RESULTS .............................................................................................................15 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10. 6. 7. DEFINITION OF TERMS ................................................................................................................................................25 TS8388BFS MAIN FEATURES .......................................................................................................................................27 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.10. TIMING INFORMATIONS ..................................................................................................................................................................... 27 PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND............................................................................ 28 ANALOG INPUTS (VIN) (VINB) ............................................................................................................................................................ 28 CLOCK INPUTS (CLK) (CLKB) ............................................................................................................................................................ 29 NOISE IMMUNITY INFORMATIONS.................................................................................................................................................... 32 DIGITAL OUTPUTS .............................................................................................................................................................................. 32 OUT OF RANGE BIT................................................................................................................................................................................... 34 GRAY OR BINARY OUTPUT DATA FORMAT SELECT...................................................................................................................... 35 DIODE PIN 49 ....................................................................................................................................................................................... 35 ADC GAIN CONTROL PIN 60.......................................................................................................................................................... 36 8. EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................37 8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS ................................................................................................ 37 8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS................................................................................... 37 8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS .................................................................................. 38 ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS.......................................................................................... 38 8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS.............................................................................................. 39 8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS .............................................................................................. 39 9. 10. TSEV8388BFS : DEVICE EVALUATION BOARD ......................................................................................................40 ORDERING INFORMATION .....................................................................................................................................41 PACKAGE DEVICE .......................................................................................................................................................................... 41 EVALUATION BOARD ..................................................................................................................................................................... 41 10.1. 10.2. 2 TS8388BFS TS8388BFS 1. SIMPLIFIED BLOCK DIAGRAM GAIN MASTER/SLAVE TRACK & HOLD VIN,VINB G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK 4 INTERPOLATION STAGES 4 5 REGENERATION LATCHES 4 ERROR CORRECTION & DECODE LOGIC 8 OUTPUT LATCHES & BUFFERS 8 DRRB DR,DRB GORB DATA,DATAB OR,ORB 5 CLK, CLKB CLOCK BUFFER 2. FUNCTIONAL DESCRIPTION The TS8388BFS is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8388BFS includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 differential output buffers. The TS8388BFS works in fully differential mode from analog inputs up to digital outputs. The TS8388BFS features a full power input bandwidth of 1.5 GHz. Control pin GORB is provided to select either Gray or Binary data output format. Gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8388BFS. The TS8388BFS uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150kRad total dose). Product Specification 3 Product Specification 3. SPECIFICATIONS 3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK and VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Notes : Symbol VCC DVEE VPLUSD VEE DVEE to VEE Comments Value GND to 6 GND to -5.7 GND-0.3 to 2.8 GND to -6 0.3 Unit V V V V V VIN or VINB VIN - VINB VD VD Vo VCLK or VCLKB VCLK - VCLKB Tj Tstg Tleads GORB DRRB -1 to +1 -2 to +2 -0.3 to VCC +0.3 VEE -0.3 to +0.9 VPLUSD-3 to VPLUSD -0.5 -3 to +1.5 -2 to +2 +135 -65 to +150 +300 V V V V V V V o C C C o o Absolute maximum ratings are limiting values (referenced to GND=0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory (see Thermal characteristics). 3.2. RECOMMENDED CONDITIONS OF USE Parameter Positive supply voltage Positive digital supply voltage Symbol VCC VPLUSD VPLUSD Negative supply voltages Differential analog input voltage (Full Scale) Clock input power level Operating temperature range VEE, DVEE VIN, VINB VIN -VINB PCLK PCLKB TJ 50 single-ended clock input Commercial grade: "C" Industrial grade: "V" Military grade: "M" 50 differential or single-ended ECL output compatibility LVDS output compatibility +1.4 -5.25 113 450 3 Comments Min. 4.75 Typ. +5 GND +2.4 -5.0 125 500 4 0 < Tc ; Tj < 90 -40 < Tc ; Tj < 110 -55 < Tc ; Tj < +125 +2.6 -4.75 137 550 10 Max. 5.25 Unit V V V V mV mVpp dBm o C 4 TS8388BFS TS8388BFS 3.3. ELECTRICAL OPERATING CHARACTERISTICS VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ; Digital outputs 75 or 50 differentially terminated ; Tj (typical) = 70C. Full Temperature Range: up to -55C Symb Test level Min Typ Max Unit VCC VPLUSD VPLUSD ICC IPLUSD VEE AIEE DIEE PD PSRR 1, 2, 6 4 4 1, 2 6 1, 2 6 1, 2, 6 1, 2 6 1, 2 6 1, 2 6 4 4.7 1.4 5 0 2.4 385 395 115 120 5.3 2.6 445 445 145 145 -4.7 200 200 180 180 4.1 4.3 2 V V V mA mA mA mA V mA mA mA mA W W mV/V bits -5.3 -5 165 170 135 145 3.4 3.6 0.5 8 VIN VINB VIN VINB CIN IIN RIN FPBW SSBW 4 4 -125 -125 -250 0 125 125 250 mV mV mV mV 4 4 4 4 4 0.5 1.3 1.5 3 10 1 1.5 1.7 3.5 20 pF A M GHz GHz ECL or specified clock input power level in dBm 4 VIL VIH IIL IIH -1.1 5 5 DBm into 50 4 CCLK 4 -2 4 3 10 3.5 dBm pF 50 50 -1.5 V V A A Clock input power level into 50 termination Clock input power level Clock input capacitance Product Specification 5 Product Specification Parameter DIGITAL OUTPUTS (notes 1,6) Symb Test level Min Typ Max Unit Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj (typical) = 70C. Logic compatibility for digital outputs ( Depending on the value of VPLUSD ) (see Application Notes) Differential output voltage swings ( assuming VPLUSD = 0V) : 75 open transmission lines ( ECL levels ) 75 differentially terminated 50 differentially terminated Output levels ( assuming VPLUSD = 0V) 75 open transmission lines * * Logic "0" voltage Logic "1" voltage (note 6) VOL VOH (note 6) VOL VOH DOS 1, 2 6 * Logic "1" voltage 1, 2 6 Differential Output Swing Output level drift with temperature DC ACCURACY Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj (typical) = 70C. Differential non linearity (notes 2,3) DNLDNL+ Integral non linearity (notes 2,3) INLINL+ 1, 2 6 1, 2 6 1, 2 6 1, 2 6 No missing codes Gain error (note 3) -1.0 -1.2 -0.5 -0.6 -0.25 -0.35 0.3 0.4 0.7 0.9 0.7 0.9 1.0 1.2 0.6 0.7 LSB LSB LSB LSB LSB LSB LSB LSB 4 4 -1.16 -1.25 270 -1.40 -1.40 -1.10 -1.10 300 1.6 -1.32 -1.25 V V V V mV mV/C -1.07 -1.41 -1 -1.34 V V 4 (note 6) VOL VOH 4 -0.88 -1.62 -0.8 -1.54 V V 4 1.50 0.70 0.54 1.620 0.825 0.660 V V V ECL or LVDS Output levels ( assuming VPLUSD = 0V) 75 differentially terminated * * Logic "0" voltage Logic "1" voltage Output levels ( assuming VPLUSD = 0V) 50 differentially terminated * Logic "0" voltage Guaranteed over specified temperature range 1, 2 6 -10 -11 -26 -30 100 40 -2 -2 -5 -5 125 50 10 11 26 30 150 60 % FS % FS mV mV ppm/C ppm/C Input offset voltage Gain error drift Offset error drift 1, 2 6 4 4 6 TS8388BFS TS8388BFS Parameter TRANSIENT PERFORMANCE Bit Error Rate FS = 1 Gsps Fin = 62.5 MHz (note 2) (note 2) TS TOR 4 4 0.5 0.5 1 1 (notes 2, 4) BER 4 1E-12 Error/ sample ns ns Symb Test level Min Typ Max Unit ADC settling time VIn -VinB = 400 mVpp Overvoltage recovery time AC PERFORMANCE Single ended or differential input and clock mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj. = 70C, unless otherwise specified. Signal to Noise and Distortion ratio FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps Fin = 20 MHz Fin = 500 MHz Fin = 1000 MHz (-1dB Fs) (note 2) SINAD 4 4 4 1, 2, 6 ENOB 4 4 4 1, 2, 6 (note 2) SNR 4 4 4 1, 2, 6 (note 2) THD 4 4 4 1, 2, 6 (note 2) SFDR 4 4 4 4 1, 2, 6 (note 2) IMD 4 - 47 - 52 dBc 52 47 42 45 40 57 52 47 50 54 dBc dBc dBc dBc dBc 50 46 42 46 54 50 46 51 dB dB dB dB 42 41 41 44 45 44 44 45 dB dB dB dB 7.0 6.6 6.2 7.0 7.2 6.8 6.4 7.2 Bits Bits Bits Bits 42 41 38 40 44 43 40 44 dB dB dB dB FS = 50 Msps Fin = 25 MHz Effective Number Of bits FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps Fin = 20 MHz Fin = 500 MHz Fin = 1000 MHz (-1dBFs) FS = 50 Msps Fin = 25 MHz Signal to Noise Ratio FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps Fin = 20 MHz Fin = 500 MHz Fin = 1000 MHz (-1dBFs) FS = 50 Msps Fin = 25 MHz Total Harmonic Distortion FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps Fin = 20 MHz Fin = 500 MHz Fin = 1000 MHz (-1dBFs) FS = 50 Msps Fin = 25 MHz Spurious Free Dynamic Range FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps FS = 1 Gsps Fin = 20 MHz Fin = 500 MHz Fin = 1000 MHz (-1dBFs) Fin = 1000 MHz (-3dBFs) FS = 50 Msps Fin = 25 MHz Two-tone inter-modulation distortion FIN1 = 489 MHz @ FS = 1 Gsps FIN2 = 490 MHz @ FS = 1 Gsps Product Specification 7 Product Specification Parameter Symb Test level Min Typ Max Unit SWITCHING PERFORMANCE AND CHARACTERISTICS - See Timing Diagrams Figure 1, Figure 2 Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay (Note 2) (Notes 2, 5) (Notes 2, 10, 11, 12) (Note 14) (Note 15) FS FS TC1 TC2 TA Jitter TOD TR/TF TR/TF 4 4 4 4 4 4 4 4 1150 250 250 1 10 0.280 0.350 100 0.500 0.500 +250 0.4 1360 350 350 1.4 50 50 50 400 0.6 1660 550 550 Gsps Msps ns ns ps ps (rms) ps ps ps Output rise/fall time for DATA (20 % - 80 %) (note 11) Output rise/fall time for DATA READY (20 % - 80 % ) Data ready output delay Data ready reset delay Data to data ready - clock low pulse width (See timing diagram, notes 9, 13,14) Data to data ready output delay (50% duty cycle) (See timing diagram, notes 2, 15) @ 1Gsps Data pipeline delay (note 11) (Notes 2,10, 11, 12) TDR TRDR TODTDR TD1 4 4 4 1110 1320 720 1620 1000 80 ps ps ps 0 40 4 420 460 500 ps TPD 4 4 clock cycles Note 1 : Note 2 : Note 3 : Note 4 : Note 5 : Differential output buffers are internally loaded by 75 resistors. Buffer bias current = 11 mA. See definition of terms Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS. Output error amplitude < 4 LSB around worst code. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board) : 200 fs. (500 fs expected on TS8388BG) Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 . Note 7 : With a typical value of TD = 465 ps, at 1 Gsps, the timing safety margin for the data storing using the ECLinPS 10E452 output registers from Motorola is of 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB). Note 8 : The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into the 50 termination resistor of the inphase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level for the clock generator.) Note 9 : At 1GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate. Note 10 : Specified loading conditions for digital outputs : - 50 or 75 controlled impedance traces properly 50 / 75 terminated, or unterminated 75 controlled impedance traces. - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic capacitance of 1.5 pF including package and ESD protections. ) Note 11 : Termination load parasitic capacitance derating values : - 50 or 75 controlled impedance traces properly 50 / 75 terminated : 60 ps / pF or 75 ps per additionnal ECLinPS load. - Unterminated ( source terminated ) 75 controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS termination load. Note 12 : apply proper 50 / 75 impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8388BFS Evaluation Board. o Note 13 : Values for TOD and TDR track each other over temperature, ( 1 % variation for TOD - TDR per 100 C. temperature variation ). Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and package skews between each Data TODs and TDR effect can be considered as negligible.Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation over temperature in section 7). Note 14 : Min value guaranties performance. Max value guaranties functionality. Note 15 : Min value guaranties functionality. Max value guaranties performance. 8 TS8388BFS TS8388BFS 3.4. TIMING DIAGRAMS TA= 250 ps (VIN, VINB ) X X N N-1 N+1 TC=1000 ps TC1 TC2 1. X N+2 X N+3 X N+4 X N+5 (CLK, CLKB) 1360 ps TPD: 4.0 Clock periods TOD = 1360 ps DIGITAL OUTPUTS 1000 ps DATA N-5 DATA N-4 TDR = 1320 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TDR = 1320 ps Data Ready (DR, DRB) TD1=TC1+TDR-TOD = TC1-40 ps = 460 ps ps DRRB TRDR = 720 ps 1ns (min) TD2 = TC2+TOD-TDR = TC2+40ps = 540 ps Figure 1 : TS8388BFS TIMING DIAGRAM ( 1 GSPS CLOCK RATE ) Data Ready Reset , Clock held at LOW level TA= 250ps (VIN, VINB ) X N-1 X N 2. N+1 TC = 1000 ps TC1 TC2 X N+2 3. N+3 X N+4 X N+5 (CLK, CLKB) DIGITAL OUTPUTS 1360 ps 1000 ps TPD: 4.0 Clock periods TOD = 1360 ps DATA N-5 DATA N-4 TDR = 1120 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TDR = 1320 ps TD1=TC1+TDR-TOD = TC1-40 ps = 460 ps Data Ready (DR, DRB) TD2 = TC2+TOD-TDR = TC2+40ps = 540 ps TRDR = 720ps DRRB 1ns (min) Figure 2 : TS8388BFS TIMING DIAGRAM ( 1 GSPS CLOCK RATE ) Data Ready Reset , Clock held at HIGH level Product Specification 9 Product Specification 3.5. EXPLANATION OF TEST LEVELS 1 2 3 4 5 6 100% production tested at +25C 100 % production tested at +25C (1) (1) (for "C" Temperature range (2) ). (2) , and sample tested at specified temperatures (for "V" and "M" Temperature ranges ). Sample tested only at specified temperatures Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). Parameter is a typical value only 100 % production tested over specified temperature range (for "B/Q" Temperature range (2) ). Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). (1) Unless otherwise specified, all tests are pulsed tests : therefore Tj = Tc = Ta, where Tj ,Tc and Ta are junction, case and ambient temperature respectively. (2) Refer to ORDERING INFORMATION chapter. 3.6. FUNCTIONS DESCRIPTION Name VCC VEE VPLUSD GND VIN, VINB CLK, CLKB VIN VINB CLK CLKB GAIN GORB 16 OR ORB D0 D7 DR DRB TS8388BFS D0B D7B DIOD/ DRRB 3.7. DIGITAL OUTPUT CODING NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearity voltage errors. Differential analog input Binary GORB = VCC or floating > +251 mV +251 mV +249 mV +126 mV +124 mV +1 mV -1 mV -124 mV -126 mV -249 mV -251 mV < -251 mV > Positive full scale + 1/2 LSB Positive full scale + 1/2 LSB Positive full scale - 1/2 LSB Positive 1/2 scale + 1/2 LSB Positive1/2 scale - 1/2 LSB Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB Negative 1/2 scale + 1/2 LSB Negative 1/2 scale - 1/2 LSB Negative full scale + 1/2 LSB Negative full scale - 1/2 LSB < Negative full scale - 1/2 LSB 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000 Gray GORB = GND 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000 1 0 0 0 0 0 0 0 0 0 0 1 Voltage level Digital output Out of Range 10 TS8388BFS TS8388BFS 4. PACKAGE DESCRIPTION. 4.1. TS8388BFS PIN DESCRIPTION Symbol GND Pin number 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58, 59 1, 2, 16, 17, 18, 68 Function Ground pins. To be connected to external ground plane. Digital positive supply. (0V for ECL compatibility, +2.4V for LVDS compatibility). (note 2) +5 V positive supply. -5 V analog negative supply. -5 V digital negative supply. In phase (+) analog input signal of the Sample and Hold differential preamplifier. Inverted phase (-) of analog input signal (VIN). In phase (+) ECL clock input signal. The analog input is sampled and held on the rising edge of the CLK signal. Inverted phase (-) of ECL clock input signal (CLK). In phase (+) digital outputs. B0 is the LSB. B7 is the MSB. Inverted phase (-) Digital outputs. B0B is the inverted LSB. B7B is the inverted MSB. In phase (+) Out of Range Bit. Out of Range is high on the leading edge of code 0 and code 256. Inverted phase (+) of Out of Range Bit (OR). In phase (+) output of Data Ready Signal. Inverted phase (-) output of Data Ready Signal (DR). Gray or Binary select output format control pin. - Binary output format if GORB is floating or VCC. - Gray output format if GORB is connected at ground (0 V). ADC gain adjust pin. This pin has a double function (can be left open or grounded if not used) : DIOD : die junction temperature monitoring pin. DRRB : asynchronous data ready reset function VPLUSD VCC VEE DVEE VIN VINB CLK CLKB D0, D1, D2, D3, D4, D5, D6, D7 D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B OR ORB DR DRB GORB 26, 29, 32, 33, 46, 47, 61 30, 31, 44, 45, 48 8, 9, 10 54 , 55 56, 57 (1) (1) (1) 37 , 38 39, 40 (1) 23, 21, 19, 14, 6, 3, 66, 64 24, 22, 20, 15, 7, 4, 67, 65 62 63 11 12 25 GAIN DIOD/DRRB 60 49 Note 1 : Note 2 : Following pin numbers 37 (CLK), 40 (CLKB), 54 (VIN) and 57 (VINB) have to be connected to GND through a 50 resistor as close as possible to the package.(50 termination preferred option). The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground ). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. Product Specification 11 Product Specification 4.2. TS8388BFS PINOUT TOP VIEW : VPLUSD VPLUSD DRB D4B D5 VPLUSD D3B VPLUSD D5B D3 DR D4 VPLUSD VPLUSD D2 D2B D1 D1B D0 D0B D6B D6 D7B D7 ORB OR TS8388BFS 12 TS8388BFS TS8388BFS 4.3. OUTLINE DIMENSIONS - 68 PINS CQFP 68 pins Ceramic Quad Flat Pack 0.8 BCS 20.32 BSC .023 .002 0.58 0.05 O .005 0.050 BCS 1.27 BSC . Pin N 1 index 1.133 - 1.147 28.78 - 29.13 .950 .006 24.13 0.152 o CQFP 68 M Z X Y .007 .005 0.18 0.13 .020 .005 0.51 0.13 .950 .006 24.13 0.152 1.133 - 1.147 28,78 - 29.13 .0385 0.978 .0310 0.787 .027 - .037 0.70 - 0.95 .005 - .010 0.13 - 0.25 0o - 8o Product Specification 13 Product Specification 4.4. THERMAL CHARACTERISTICS 4.4.1. ENHANCED CQFP The CQFP68 has been modified, in order to improve the thermal characteristics : A CuW heatspreader has been added at the bottom of the package. The die has been electrically isolated with the ALN substrate. 4.4.2. THERMAL RESISTANCE FROM JUNCTION TO AMBIENT : RTHJA The following table lists the convector thermal performances parameters of the device itself, with no external heatsink added. 4.4.3. THERMAL RESISTANCE FROM JUNCTION TO CASE : RTHJC o Typical value for Rthjc is given to 1.56 C/W. This value does not include thermal contact resistance between package and external component (heatsink or PCBoard). o As an example, 2.0 C/W can be taken for 50 m of thermal grease. 4.4.4. HEATSINK It is recommended to use an external heatsink, or PCBoard special design. The stand off has been calculated to permit the simultaneous soldering of the leads and of the heatspreader with the solder paste. Suggested assembly : 28.78 24.13 Printed circuit board CuW heatspreader Thermal via Solid ground plane Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. 14 TS8388BFS TS8388BFS 5. TYPICAL CHARACTERIZATION RESULTS 5.1. STATIC LINEARITY - FS = 50 MSPS / FIN = 10 MHZ 5.1.1. INTEGRAL NON LINEARITY LSB INL = +/- 0.7 LSB code Clock Frequency = 50Msps Positive peak : 0.78 LSB Signal Frequency = 10MHz Negative peak : -0.73 LSB 5.1.2. DIFFERENTIAL NON LINEARITY LSB DNL = +/- 0.4 LSB code Clock Frequency = 50Msps Positive peak : 0.3 LSB Signal Frequency = 10MHz Negative peak : -0.39 LSB Product Specification 15 Product Specification 5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION Effective number of bits = f (VEEA) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 -7 -6,5 -6 -5,5 -5 -4,5 -4 VEEA ( V) Effective number of bits = f (VCC) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 3 3,5 4 4,5 5 5,5 6 6,5 7 VCC (V) Effective number of bits = f (VEED) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 -6 -5,5 -5 -4,5 -4 -3,5 -3 VEED (V) 16 TS8388BFS TS8388BFS 5.3. TYPICAL FFT RESULTS 5.3.1 FS = 1 GSPS, FIN=20 MHZ Single Ended or differential H11 H2 H3 H12 Fs =1 GSPS Fin = 20 MHz Eff. Bits =7.2 SINAD = 44.3 dB SNR = 44.7dB THD = -54dBc SFDR = -57 dBc Binary output coding clock duty cycle = 50 % 5.3.2. FS = 1 GSPS, FIN = 495 MHZ H2 H12 H14 H3 H11 Single Ended or differential Fs =1 GSPS Fin=495MHz Eff. Bits =6.8 SINAD =43 dB SNR = 44.1 dB THD = -50 dBc SFDR= -52 dBc Binary output coding clock duty cycle = 50 % 5.3.3. FS = 1 GSPS, FIN = 995 MHZ ( -3DB FULL SCALE INPUT) H3 H2 H10 Single Ended or differential Fs =1 GSPS Fin=995 MHz Eff. Bits =6.6 SINAD =40.8 dB SNR = 44 dB THD = -48 dBc SFDR= -50 dBc Binary output coding clock duty cycle = 50 % Product Specification 17 Product Specification 5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE 5.4.1. SAMPLING FREQUENCY FS=1 GSPS ; INPUT FREQUENCY FIN=995 MHZ ; GRAY OR BINARY OUTPUT CODING Full Scale H3 H2 SFDR = -47 dBc magnitude (code) Fs = 1 GSPS ENOB = 6 4 SINAD = 40 dB Fin = 995 MHz SNR = 44dB Full Scale THD = -46 dBc SFDR = -47 dBc 18 TS8388BFS TS8388BFS -3dB Full Scale SFDR = -50 dBc H3 magnitude (code) H2 Fs = 1 GSPS ENOB = 6.6 SINAD = 40.8 dB Fin = 995 MHz SNR = 44dB (-3 dB Full Scale) THD = -48dBc SFDR = -50dBc Product Specification 19 Product Specification 5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY Fs=1 Gsps, Fin = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB Clock duty cycle 50 / 50, Binary/Gray output coding, fully differential or single-ended analog and clock inputs 8 7 6 5 4 3 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) ENOB (dB) -3 dB FS FS 50 48 46 44 42 SNR (dB) 40 38 36 34 32 30 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) FS -3 dB FS -20 -25 -30 SFDR (dBc) -35 -40 -45 -50 -55 -60 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) -3 dB FS FS 20 TS8388BFS TS8388BFS 5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Fs / 2 ) Clock duty cycle 50 / 50 , Binary output coding 8 Fi FS/ n= 2 7 Fi n=500 M H z 6 ENOB (dB) 5 4 3 2 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (Msps) 5.7. SFDR VERSUS SAMPLING FREQUENCY Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Fs / 2 ) Clock duty cycle 50 / 50 , Binary output coding -20 -25 -30 -35 SFDR (dBc) -40 -45 Fin= FS/2 -50 Fin=500 MHz -55 -60 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (Msps) Product Specification 21 Product Specification 5.8. TS8388BFS ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE Effective number of bits versus junction temperature Fs = 1 GSPS ; Fin = 500 MHz ; Duty cycle = 50% 8 7 ENOB (bits) 6 5 4 3 -40 -20 0 20 40 60 80 o 100 120 140 160 Temperature ( C) Signal to noise ratio versus junction temperature Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs) 46 45 SNR (dB) 44 43 42 -60 -40 -20 0 20 40 o 60 80 100 120 Temperature ( C) Total harmonic distorsion versus junction temperature Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs) 53 51 THD (dB) 49 47 45 43 -60 -40 -20 0 20 40 o 60 80 100 120 Temperature ( C) 22 TS8388BFS TS8388BFS Power consumption versus junction temperature Fs = 1 G S P S ;Fi = 500 M H z ;D ut cycl = 50% n y e 5 Power consumption (W 4 3 2 1 0 40 20 0 20 40 60 o 80 100 120 140 160 Tem per ur ( C ) at e 5.9. TYPICAL FULL POWER INPUT BANDWIDTH 1.5 GHz at -3 dB (-2dBm full power input) Frequency (MHz) 100 0 -1 -2 -3 -4 -5 -6 300 500 700 900 1100 1300 1500 1700 Magnitude (dB) Product Specification 23 Product Specification 5.10. ADC STEP RESPONSE Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps. Note : This step response was obtained with the TSEV8388B chip on board (device in die form). 5.10.1. TEST PULSE DIGITIZED WITH 20 GHZ DSO Vpp ~ 260 mV Tr ~ 240 ps 50 mV/div 50 mV/div 500 ps/div 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (ns) 5.10.2. SAME TEST PULSE DIGITIZED WITH TS8388BFS ADC 200 150 ADC code 100 Tr ~ 280 ps 50 codes/div (Vpp ~260 mV) 500 ps/div ADC calculated rise time : between 150 and 200 ps. 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (ns) N.B. : ripples are due to the test setup (they are present on both measurements) 24 TS8388BFS TS8388BFS 6. DEFINITION OF TERMS (BER) (BW) Bit Error Rate Full power input bandwidth Probability to exceed a specified error threshold for a sample. An error code is a code that differs by more than +/- 4 LSB from the correct code. Analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 Db with respect to its low frequency value (determined by FFT analysis) for input at Full Scale. Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS sum of all other spectral components, including the harmonics except DC. Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS sum of all other spectral components excluding the five first harmonics. Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component. Ratio expressed in Db of the RMS signal amplitude, set at 1Db below Full Scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application ( Radar systems, digital receiver, network analyzer ....). It may be reported in dBc (i.e., degrades as signal levels is lowered), or in Dbfs (i.e. always related back to converter full scale). SINAD - 1.76 + 20 log (A/V/2) Where A is the actual input amplitude and V ENOB = is the full scale range of the ADC under test 6.02 The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic. The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC) Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC) Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point), and the time at which (VIN,VINB) is sampled. Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input. Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is reduced to midscale. Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. Time delay from Data transition to Data ready. General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. TC1 = Minimum clock pulse width (high) TC = TC1 + TC2 TC2 = Minimum clock pulse width (low) Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8388BFS the TPD is 4 clock periods. Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and (SINAD) (SNR) (THD) (SFDR) Signal to noise and distortion ratio Signal to noise ratio Total harmonic distorsion Spurious free dynamic range (ENOB) (DNL) Effective Number Of Bits Differential non linearity (INL) Integral non linearity (DG) (DP) (TA) (JITTER) (TS) (ORT) (TOD) (TD1) (TD2) (TC) (TPD) Differential gain Differential phase Aperture delay Aperture uncertainty Settling time Overvoltage recovery time Digital data Output delay Time delay from Data to Data Ready Time delay from Data Ready to Data Encoding clock period Pipeline Delay (TRDR) (TR) Data Ready reset delay Rise time Product Specification 25 Product Specification high level. (TF) (PSRR) (NRZ) Fall time Power supply rejection ratio Non return to zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at - 7Db Full Scale. The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and high level. Ratio of input offset variation to a change in power supply voltage. (IMD) (NPR) InterModulation Distortion Noise Power Ratio 26 TS8388BFS TS8388BFS 7. 7.1. 7.1.1. TS8388BFS MAIN FEATURES TIMING INFORMATIONS TIMING VALUE FOR TS8388BFS Timing values as defined in 3.3 are advanced data, issuing from electric simulations and first characterizations results fitted with measurements. Timing values are given at CQFP68 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, gullwing pin model, and specified termination loads. Propagation delays in 50/75 ohms impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions : Note 1 : Specified Termination Load (Differential output Data and Data Ready) : 50 ohms resistor in parallel with 1 standard ECLinPS register from Motorola, (e.g : 10E452) (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections) If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below. Note 2 : Output Termination Load derating values for TOD and TDR : ~ 35 ps/pF or 50 ps per additional ECLinPS load. Note 3 :Propagation time delay derating values have also to be applied for TOD and TDR : ~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board. Apply proper time delay derating value if a different dielectric layer is used. 7.1.2. PROPAGATION TIME CONSIDERATIONS TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8388B Evaluation Board, the propagation time delay is 6ps/mm (155ps/inch) corresponding to 3.4 (@10GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data. (TD is the time difference between Data Ready output delay and digital Data output delay) TD is also the most straightforward data to measure, again because it is differential : TD can be measured directly onto termination loads, with matched Oscilloscopes probes. 7.1.3. TOD - TDR VARIATION OVER TEMPERATURE Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees Celsius temperature variation). Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal (onchip) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other terms : If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ). If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD - TDR values may be dictated by total digital datas skews between every TODs (each digital data) and TDR : MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches. The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR. 7.1.4. PRINCIPLE OF OPERATION The Analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture delay) of typically 250ps . The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD. The Data Ready differential output signal frequency (DR,DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR,DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB ( ECL compatible single-ended input) is available for initializing the differential Data Ready output signal ( DR,DRB ) .This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital datas in a defined order. Product Specification 27 Product Specification 7.2. 7.2.1. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND DATA READY OUTPUT SIGNAL RESET The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V for Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains at logical zero and is independant of the external free running encoding clock. The Data Ready output signal (DR,DRB) is reset to logical zero after TRDR= 920 ps typical. TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready output signal (DR,DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width. 7.2.2. DATA READY OUTPUT SIGNAL RESTART The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant : 1) 2) The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is LOW : The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove. The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH : The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps. Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition ( N ) after Data Ready signal restart ( rising edge ) is always strobed by the third rising edge of the data ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,DRB) (zero crossing point). Note 1 : For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped. Note 2 : One single pin is used for both DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. ) Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. 7.3. ANALOG INPUTS (VIN) (VINB) The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor. In differential mode input configuration, that means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common mode is GROUND. The typical input capacitance is 3 pF for TS8388B in CQFP package. The input capacitance is mainly due to the package.(note : the ESD protections are not connected(but present) on the inputs. Differential inputs voltage span [mV] 125 250 mV VIN VINB -250 mV 500mV Full Scale analog input -125 0 Volt t (VIN,VINB) = +/- 250 mV = 500 mV diff Differential versus single ended analog input operation The TS8388BFS can operate at full speed in either differential or single ended configuration. This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the Sample and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode. 28 TS8388BFS TS8388BFS This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN). Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as common mode effects. In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms termination resistor. In single-ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak,centered on 0V. (or -2 dBm into 50 ohms.) The inverted phase input is at ground potential through the 50 ohms termination resistor. However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode. Typical Single ended analog input configuration [mV] 250 500 mV VIN VIN or VINB double pad (pins 54, 55 or 56, 57) VIN or VINB 500 mV Full Scale analog input -250 VINB = 0V VINB 50 (external) 1M 3 pF t VIN = +/- 250 mV 500 mV diff 50 reverse termination 7.4. CLOCK INPUTS (CLK) (CLKB) The TS8388BFS can be clocked at full speed without noticeable performance degradation in either differential or single ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, @ 1 KHz from carrier , assuming a single tone 4 dBm input for the clock signal. 7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE) Although the clock inputs were intended to be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8388BFS clock buffer can manage a single-ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not require the use of a power splitter. No performance degradation ( e.g. : due to timing jitter) is observed in this particular single-ended configuration up to 1.2GSPS Nyquist conditions ( Fin = 600 MHz ). This is true so long as the inverted phase clock input pin is 50 ohms terminated very closely to one of the neighbouring shield ground pin, which constitutes the local Ground reference for the inphase clock input. Thus the TS8388BFS differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. The inverted phase clock input is grounded through the 50 ohms termination resistor. Product Specification 29 Product Specification Single ended Clock input (Ground common mode) VCLK common mode = 0 Volt VCLKB=0 Volt 4 dBm typical clock input power level (into 50 ohms termination resistor) [V] +0.5V VCLK CLK or CLKB double pad (pins 37, 38 or 39, 40) CLK or CLKB VCLKB = ( 0 V ) 50 (external) 1M 0.4 pF -0.5V t 50 reverse termination Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level. 7.4.2. DIFFERENTIAL ECL CLOCK INPUT The clock inputs can be driven differentially with nominal -0.8V / -1.8V ECL levels. In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels. Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the GSPS range. Differential Clock inputs (ECL Levels) [mV] -0.8V VCLK CLK or CLKB double pad (pins 37, 38 or 39, 40) VCLKB CLK or CLKB Common mode = -1.3 V 50 (external) -2V 1M 0.4 pF -1.8V t 50 reverse termination 7.4.3. SINGLE ENDED ECL CLOCK INPUT In single-ended configuration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respectively CLK) connected to 1.3V through the 50 ohms termination resistor. The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode. Single ended Clock input (ECL): VCLK common mode = -1.3 Volt. VCLKB = -1.3 Volt 30 TS8388BFS TS8388BFS [V] -0.8V VCLK VCLKB = -1.3 V -1.8V t Product Specification 31 Product Specification 7.5. NOISE IMMUNITY INFORMATIONS Circuit noise immunity performance begins at design level. Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.) Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs : The analog inputs and clock inputs of the TS8388BFS device have been surrounded by ground pins, which must be directly connected to the external ground plane. 7.6. DIGITAL OUTPUTS The TS8388BFS differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital ground pins through a -0.8v level shift diode (see Figures 3,4,5 on next page). The TS8388BFS output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD=0V for ECL output compatibility) to +1.2V (VPLUSD=2.4V for LVDS output compatibility). Therefore, the single ended output voltages vary approximately between -0.8V and -1.625V, ( outputs unterminated ), around -1.2V common mode voltage. Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD=0V) : 1 ) 75 Ohms impedance transmission lines, 75 ohms differentially terminated (Fig. 3) : Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V). 2 ) 50 ohms impedance transmission lines, 50 ohms differentially termination (Fig. 4) : Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to +/- 0.33V=660 mV in differential, around 1.18V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V). 3 ) 75 ohms impedance open transmission lines (Fig. 5) : Each output voltage varies between -1.6 V and -0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, leading to +/- 0.8V=1.6V in differential, around -1.2V (respectively +1.2V) common mode for VPLUSD=0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms transmission lines. In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the 75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will occur. Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance. Each differential output termination length must be kept identical . It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from MOTOROLA. At sampling rates exceeding 1GSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BFS at its optimum performance conditions. 32 TS8388BFS TS8388BFS 7.6.1. DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR ECL COMPATIBILITY) VPLUSD = 0V -0.8V 75 75 75 + 75 impedance 10 nF 75 75 Out -1V / -1.41V Differential output : 0.41V = 0.825V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB -1.41V / -1V 11 mA DVEE VPLUSD = 0V Figure 3 : DIFFERENTIAL OUTPUT : 75 TERMINATED -0.8V 75 75 50 + 50 impedance 10 nF 50 50 Out -1.02V / -1.35V Differential output : 0.33V = 0.660V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB -1.35V / -1.02V 11 mA DVEE Figure 4 : DIFFERENTIAL OUTPUT : 50 TERMINATED VPLUSD = 0V -0.8V 75 75 75 75 + impedance VPLUSD = 2.4V Out -0.8V / -1.6V Differential output : 0.8V = 1.6V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB -1.6V / -0.8V Out 1.4V / 0.99V 11 mA 75 DVEE 7.6.1. 1.6V 75 75 Figure 5 : DIFFERENTIAL OUTPUT : OPEN LOADED = 0.825V 75 0.41V Differential output : DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS nF LVDS COMPATIBILITY) Common mode level : -1.2V 75 10 FOR + 75 impedance (-1.2V below VPLUSD level) OutB 11 mA 0.99V / 1.4V Product Specification DVEE 33 Figure 6 : DIFFERENTIAL OUTPUT : 75 TERMINATED Product Specification VPLUSD = 2.4V 1.6V 75 75 50 + 50 impedance 10 nF 50 50 Out 1.38V / 1.05V Differential output : 0.33V = 0.660V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB 1.05V / 1.38V 11 mA DVEE Figure 7 : DIFFERENTIAL OUTPUT : 50 TERMINATED VPLUSD = 2.4V 1.6V 75 75 75 + 75 impedance Out 1.6V / 0.8V Differential output : 0.8V = 1.6V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB 0.8V / 1.6V 11 mA DVEE Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED 7.7. OUT OF RANGE BIT An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (OR,ORB) at logical one. When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR,ORB) at logical one again. 7.8. GRAY OR BINARY OUTPUT DATA FORMAT SELECT The TS8388BFS internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t) : Av= exp((t)/) , with the positive feedback regeneration time constant. The TS8388BFS has been designed for reducing the probability of occurence of such errors to approximately 10 TS8388BFS at 1GSPS). -13 (targetted for the A standard technique for reducing the amplitude of such errors down to +/-1 LSB consists to output the digital datas in Gray code format. -13 Though the TS8388BFS has been designed for featuring a Bit Error Rate of 10 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occuring, by storing Gray output codes. Digital Datas format selection : BINARY output format if GORB is floating or VCC. GRAY output format if GORB is connected to ground (0V). 7.9. DIODE PIN 49 One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. 34 TS8388BFS TS8388BFS (See section 7.2 for Data Ready Reset input command). The operating die junction temperature must be kept below145 C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below. 1000 960 920 880 VBE (mV) 840 800 760 720 680 640 600 -55 -35 -15 5 25 45 65 85 105 125 Junction temperature (deg.C) Product Specification 35 Product Specification 7.10. ADC GAIN CONTROL PIN 60 The ADC gain is adjustable by the means of the pin 60 (input impedance is 1M in parallel with 2pF) The gain adjust transfert function is given below : 1,20 1,15 1,10 ADC Gain 1,05 1,00 0,95 0,90 0,85 0,80 -500 -400 -300 -200 -100 0 100 200 300 400 500 Vgain (command voltage) (mV) Note : A specific document "DEMUX and ADCs APPLICATION NOTES" has been edited and is available ... 36 TS8388BFS TS8388BFS 8. EQUIVALENT INPUT / OUTPUT SCHEMATICS 8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS VCC=+5V GND=0V -0.8V VCC VCLAMP= +2.4V -0.8V GND -5.8V -5.8V 50 +1.65V VEE E21V E21V 50 VIN Pad capacitance 340fF 200 200 VEE VINB Pad capacitance 340fF 5.8V -1.55V 0.8V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. 8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS VCC=+5V +0.8V -5.8V -5.8V VCC -5.8V GND=0V -5.8V -5.8V -5.8V VEE CLK Pad capacitance 340fF VEE CLKB 150 150 5.8V 380 A 0.8V 380 A 5.8V Pad capacitance 340fF 0.8V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. Product Specification 37 Product Specification 8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS VPLUSD=0V to 2.4V -5.8V 75 75 -5.8V VEE OUT Pad capacitance 180 fF VEE OUTB Pad capacitance 180 fF 5.8V 5.8V I=11mA 0.8V -3.7V 0.8V 0.8V 0.8V VEE=-5V DVEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. VEE=-5V 8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS VCC=+5V -0.8 V NP1032C2 -5.8 V VCC +1.6V -0.8 V -5.8 V NP1032C2 VEE GA 0.8V Pad capacitance 180 fF 0.8V 5.8V 1 k 1 k VEE GAB 0.8V 0.8V 5.8V Pad capacitance 180 fF 2 pF 2 pF GND 500 A GND 500 A VEE VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. VEE 38 TS8388BFS TS8388BFS 8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS GORB: gray or binary select input; floating or tied to VCC -> binary VCC=+5V -0.8V 1 k 1 k -0.8V 1 k -5.8V VEE GORB Pad capacitance 180fF 5 k 5.8V 5.8V 250 A 250 A 5.8V VEE=-5V GND=0V Note : the ESD protection equivalent capacitance is 150 fF. 8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS VCC=+5V Actual protection range: 6.6V above VEE, In fact stress above GND are clipped by the CB diode used for Tj monitoring GND=0V NP1032C2 10 k DRRB 200 Pad capacitance 180 fF -1.3V -2.6V 5.8 V VEE 0.8 V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. Product Specification 39 Product Specification 9. TSEV8388BFS : DEVICE EVALUATION BOARD For complete specification, see separate TSEV8388BFS document. GENERAL DESCRIPTION The TSEV8388BFS Evaluation Board (CEB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8388BFS device up to its 1.5 GHz full power bandwidth at up to 1 Gsps in the military temperature range. The high speed of the TS8388BFS requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8388BFS ADC performances over the temperature range. The TSEV8388BFS Evaluation Board is very straightforward as it only implements the TS8388BFS ADC, SMA connectors for input / output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de-embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8388BFS in CQFP68 package installed. 40 TS8388BFS TS8388BFS 10. ORDERING INFORMATION 10.1. PACKAGE DEVICE TS 8388B M FS 9 N B 3 Lot acceptance test : Manufacturer prefix Device or family 1 : LAT 1 2 : LAT 2 3 : LAT 3 As described in ESA/SCC 9000 ESA/SCC 9000 specification : B : Level B selection C : Level C selection Qualification status : N : Non ESA/SCC qualified Q : ESA/SCC qualified Screening according to ESA/SCC 9000 B/Q : Mil-PRF-38535, QML level Q According to DSCC number 5962_0050401 Q4C Temperature range : M : -55 < Tc ; Tj < 125C Package : FS : Enhanced Rth CQFP68 gullwing 10.2. EVALUATION BOARD TS Prototype board (X) EV 8388B F ZA2 ZA2 : with MC100EL16 digital receivers Evaluation board prefix Std CQFP68 package The evaluation board is delivered with an ADC and includes the heat sink. Product Specification 41 Product Specification Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. This product is manufactured and commercialized by Atmel Grenoble. For further information, please contact : Atmel Grenoble - Route Departementale 128 - BP 46 - 91901 Orsay Cedex - France Phone +33 (0) 1 69 33 03 24 - Fax +33 (0) 1 69 33 03 21 Email monique.lafrique@gfo.atmel.com - Web site http://www.atmel-grenoble.com For further technical information, please contact the technical support : Email HOTLINE-BDC@gfo.atmel.com 42 TS8388BFS |
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