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TSB43CA43A/TSB43CB43A/TSB43CA42 iceLynx-Micro
IEEE 1394a-2000 Consumer Electronics Solution ABBREVIATED DATA MANUAL
SLLS546 - February 2003
Texas Instruments Incorporated, Copyright 2003
For more information and/or a complete data manual on this product, contact the Texas Instruments Product Information Center (PIC). Local PIC contact numbers are listed on http://www.ti.com/corp/technical_support.htm
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
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PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
2
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Table of Contents
1 Hardware IC Characteristics .................................................................................................... 8 1.1 Feature List ....................................................................................................................... 9 1.1.1 1394 Features............................................................................................................ 9 1.1.2 DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio( TSB43CA43A & TSB43CA42 Only).................................................................................................................... 9 1.1.3 High Speed Data Interface (HSDI) ............................................................................ 9 1.1.4 External CPU Interface .............................................................................................. 9 1.1.5 Internal ARM7 .......................................................................................................... 10 1.1.6 Data Buffers ............................................................................................................. 10 1.1.7 Hardware Packet Formatting for the Following Standards ...................................... 10 1.1.8 Additional Features .................................................................................................. 10 1.2 Application Diagram ........................................................................................................ 11 1.3 Block Diagram................................................................................................................. 12 1.3.1 TSB43Cx43A Block Diagram................................................................................... 12 1.3.2 TSB43CA42 Block Diagram .................................................................................... 13 1.4 Pin Out ............................................................................................................................ 14 1.4.1 TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP) ................................ 14 1.4.2 TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array (*BGA) .......................... 15 1.4.3 TSB43CA42 Plastic Quad Flat Pack (PQFP) .......................................................... 16 1.4.4 TSB43CA42 Micro-Star Ball Grid Array (*BGA) .................................................... 17 1.5 Pin Description ................................................................................................................ 18 1.6 Memory Map ................................................................................................................... 30 1.7 DTCP Encryption - Hardware Implementation (TSB43CA43A & TSB43CA42 Only) .... 31 1.8 Program Memory ............................................................................................................ 31 1.8.1 Overview/Description ............................................................................................... 31 1.8.2 External CPU ( Parallel Mode)................................................................................. 31 1.9 External CPU Interface ................................................................................................... 32 1.9.1 Overview/Description ............................................................................................... 32 1.9.2 Endian Setting (Parallel and Memory Accesses) .................................................... 34 1.9.2.1 Parallel Mode and Memory Access...................................................................... 34 1.9.3 Ex-CPU Access ....................................................................................................... 35 1.9.3.1 Ex-CPU and ARM Communication Sequence in Parallel Ex-CPU I/F Mode....... 36 1.9.3.1.1 Ex-CPU Read ................................................................................................. 36 1.9.3.1.2 Ex-CPU Write ................................................................................................. 37 1.9.3.1.3 Ex-CPU Access Limitation.............................................................................. 37 1.9.4 Ex-CPU Timing ........................................................................................................ 38 1.9.4.1 I/O Type-0 68K + Wait.......................................................................................... 38 1.9.4.2 I/O TYPE-1 SH3 SRAM-like + WAIT.................................................................... 42 1.9.4.3 I/O TYPE-2 M16C SRAM-like + WAIT ................................................................. 46 1.9.4.4 I/O TYPE-3 MPC850 ............................................................................................ 50 1.9.4.5 Memory Type ....................................................................................................... 54 1.9.5 DES Encryption........................................................................................................ 57 1.10 Integrated CPU ............................................................................................................... 58 1.10.1 Description/Overview ............................................................................................... 58 1.10.2 Interaction with External CPU.................................................................................. 59 1.10.3 External Interrupts.................................................................................................... 59 1.10.4 Timer ........................................................................................................................ 59 1.11 High Speed Data Interface.............................................................................................. 60 1.11.1 Overview/Description ............................................................................................... 60
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
3
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.11.2 Frame Sync Detection Circuit .................................................................................. 62 1.11.3 HSDI Pass Through Function .................................................................................. 62 1.11.4 HSDI Maximum Clock Rates and Through-Put ....................................................... 63 1.11.5 HSDI Mode Settings ................................................................................................ 64 1.11.6 HSDI Transmit Modes.............................................................................................. 65 1.11.6.1 TX Mode 1: Serial Burst I/F (MPEG2) .............................................................. 66 1.11.6.2 TX Mode 2: Serial Video Burst I/F (MPEG2) with Frame Sync Detect Circuit 66 1.11.6.3 TX Mode 3: Serial Video Burst I/F (MPEG2) Clock Active Only When Data Is Valid .......................................................................................................................... 66 1.11.6.4 TX Mode 4: Serial Video Burst I/F (MPEG2) with Data Valid........................... 67 1.11.6.5 TX Mode 5: Parallel Burst Video I/F (MPEG2) ................................................ 67 1.11.6.6 TX Mode 6: Parallel Video Burst I/F (MPEG2) with Frame Sync Detect Circuit .. .......................................................................................................................... 67 1.11.6.7 TX Mode 7: Parallel Video Burst I/F (MPEG2) with Data Valid ....................... 68 1.11.6.8 TX Mode 8: MPEG2 I/F Mode .......................................................................... 68 1.11.6.9 TX Mode 9: DV I/F Mode.................................................................................. 69 1.11.7 HSDI Receive Modes............................................................................................... 69 1.11.7.1 RX Mode 1: Serial Burst Video I/F (MPEG2) ................................................... 69 1.11.7.2 RX Mode 2: Parallel Burst Video I/F (MPEG2)................................................. 70 1.11.7.3 RX Mode 3: Parallel Burst Video I/F (MPEG2) Mode...................................... 70 1.11.7.4 RX Mode 4: Parallel Burst Video I/F (DV) Mode ............................................. 70 1.11.7.5 HSDI A/C Timing .............................................................................................. 71 1.11.7.5.1 Transmit HSDI AC Timing............................................................................. 71 1.11.7.5.2 Receive HSDI AC Timing............................................................................. 72 1.11.8 Audio Interface on HSDI .......................................................................................... 73 1.11.8.1 HSDI0 ............................................................................................................... 73 1.11.8.2 HSDI1 ............................................................................................................... 73 1.11.8.3 IEC60958 I/F AC Timing Characteristic............................................................ 74 1.12 UART Interface ............................................................................................................... 77 1.12.1 UART Registers ....................................................................................................... 77 1.12.2 UART Baud Rate ..................................................................................................... 78 1.13 JTAG - Boundary Scan and ARM .................................................................................. 79 1.14 Integrated 3-Port PHY..................................................................................................... 79 1.14.1 3 Port PHY ............................................................................................................... 79 1.14.2 PHY Registers ......................................................................................................... 80 1.14.3 PHY Application Information.................................................................................... 86 1.14.3.1 PHY Reference Documents ............................................................................. 89 1.15 Power Management ........................................................................................................ 89 1.15.1 PU to A (Power Up State to Active State)................................................................ 91 1.15.2 A to LP1 (Active State to Low Power 1 State) ......................................................... 91 1.15.3 LP1 to A (Low Power 1 State to Active State) ......................................................... 91 1.15.4 A to LP2 (Active State to Low Power 2 State) ......................................................... 91 1.15.5 LP2 to A (Low Power 2 State to Active State) ......................................................... 92 1.15.6 A to LP4 (Low Power 3 State to Active State) ......................................................... 92 1.15.7 LP4 to A (Low Power 3 State to Active State) ......................................................... 92 1.16 16.5K Byte Memory - FIFO ............................................................................................. 94 1.16.1 Overview/Description ............................................................................................... 94 1.16.2 Isochronous FIFOs 0 and 1: .................................................................................... 94 1.16.3 Asynchronous/Asynchronous Stream FIFOs: ......................................................... 95 1.16.4 Broadcast Receive FIFO: ........................................................................................ 95 1.16.5 FIFO Priority............................................................................................................. 96 1.16.6 FIFO Monitoring ....................................................................................................... 96
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
4
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
2
3
4
5 6 7
1.17 GPIO Configurations ....................................................................................................... 97 1.17.1 GPIO Setup.............................................................................................................. 97 1.18 IEEE 1394a-2000 Requirements .................................................................................... 98 1.18.1 Features................................................................................................................... 98 1.18.2 Cycle Master ............................................................................................................ 98 Appendix A: Configuration Registers ..................................................................................... 99 2.1 Configuration Registers................................................................................................... 99 2.2 Description Notes............................................................................................................ 99 2.3 CFR Address Ranges (Offset from CFR Base Address)................................................ 99 2.4 Register Access ............................................................................................................ 100 General Information.............................................................................................................. 101 3.1 Package Size ................................................................................................................ 101 3.2 Operating Voltage ......................................................................................................... 101 3.3 Operating Temperature................................................................................................. 101 Absolute Maximum Ratings Over Operating Temperature Ranges................................... 101 4.1 Recommended Operating Conditions (Analog IEEE 1394 I/F)..................................... 102 4.2 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) ...................................................................................................................... 104 4.3 Thermal Characteristics ................................................................................................ 105 4.4 Switching Characteristics for PHY Port Interface ......................................................... 105 4.5 Operating, Timing, and Switching Characteristics of XI................................................ 106 Reset Power States.............................................................................................................. 106 Configuration Register Map.................................................................................................. 106 Mechanical Data................................................................................................................... 107 7.1 PQFP Package Information .......................................................................................... 107 7.2 Microstar BGA Package Dimensions............................................................................. 108
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
5
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
List Of Figures
Figure 1. TSB43Cx43 Typical Application.................................................................................... 11 Figure 2: TSB43Cx43 System Block Diagram ............................................................................. 12 Figure 3: TSB43CA42 System Block Diagram............................................................................. 13 Figure 4: TSB43CA43A Plastic QFP Pin Out................................................................................ 14 Figure 5: TSB43CA43A *BGA Pin Out........................................................................................ 15 Figure 6: TSB43CA42 Plastic QFP Pin Out .................................................................................. 16 Figure 7: TSB43CA42 *BGA Pin Out ......................................................................................... 17 Figure 8: TSB43Cx43 Memory Map ............................................................................................. 30 Figure 10: Ex-CPU Access........................................................................................................... 35 Figure 11: I/O Type-0 68K + Wait Read ....................................................................................... 38 Figure 12: I/O Type-0 68K + Wait Write ....................................................................................... 40 Figure 13: I/O TYPE-1 SH3 Read ................................................................................................ 42 Figure 14: I/O TYPE-1 SH3 Write................................................................................................. 44 Figure 15: I/O TYPE-2 M16C SRAM-like + WAIT Read .............................................................. 46 Figure 16: I/O TYPE-2 M16C SRAM-like + WAIT Write............................................................... 48 Figure 17: I/O TYPE-3 MPC850 Read ......................................................................................... 50 Figure 18: I/O TYPE-3 MPC850 Write........................................................................................... 52 Figure 20: Memory Type ............................................................................................................... 54 Figure 21: Memory Write .............................................................................................................. 56 Figure 26: WatchDog Timer Waveform........................................................................................ 59 Figure 27: Data Pass-Through Function ...................................................................................... 63 Figure 28: MPEG2 Serial Burst I/F (TX Mode 1).......................................................................... 66 Figure 29: MPEG2 Serial Video Burst I/F with Frame Sync Detect Circuit (TX Mode 2)............. 66 Figure 30: MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3) .. 66 Figure 31: MPEG2 Serial Video Burst I/F with Data Valid (TX Mode 4) ...................................... 67 Figure 32: MPEG2 Parallel Burst Video I/F (TX Mode 5)............................................................. 67 Figure 33: MEPG2 Parallel Video Burst I/F with Frame Sync Detect Circuit (TXMode 6) ........... 67 Figure 34: MPEG2 Parallel Video Burst I/F with Data Valid (TX Mode 7).................................... 68 Figure 35: MPEG2 I/F (TX Mode 8).............................................................................................. 68 Figure 36: DV I/F (TX Mode 9) ..................................................................................................... 69 Figure 37: MPEG2 Serial Burst Video I/F (RX Mode 1) ............................................................... 69 Figure 38: MPEG2 Parallel Burst Video I/F (RX Mode 2) ............................................................ 70 Figure 39: MPEG2 Parallel Burst Video I/F (RX Mode 3) ............................................................ 70 Figure 40: DV Parallel Burst Video I/F (RX Mode 4) .................................................................... 70 Figure 41: Transmit HSDI AC Timing ........................................................................................... 71 Figure 42: Receive HSDI AC Timing ............................................................................................ 72 Figure 43: Example 1 Sampling frequency (fs): 192kHz, Master clock frequency: 256fs........... 75 Figure 44: Example 2 Sample frequency (fs): 48kHz, Master clock frequency: 768fs.............. 75 Figure 45: AC timing characteristic on receiving .......................................................................... 76 Figure 46: AC timing characteristic on transmitting...................................................................... 76 Figure 47: TPBP and TPBN Connection ....................................................................................... 86 Figure 48: TPAP, TPAN, and TPBIAS Connection ....................................................................... 87 Figure 49: R0 and R1 Connection ................................................................................................. 87 Figure 50: FILTER0 and FILTER1 Connection ............................................................................. 88 Figure 51: TPB, TPA, TPBIAS Connection for Terminated Port (Port is not used) ...................... 88 Figure 52: Isochronous FIFOs...................................................................................................... 94 Figure 53: Asynchronous/ Asynchronous Stream FIFOs ............................................................. 95 Figure 54: Broadcast Receive FIFO ............................................................................................. 96 Figure 102: Test Load Diagram.................................................................................................. 105
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
6
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
List Of Tables
Table 1. External CPU MCIF Pin Assignment Modes .................................................................. 33 Table 3: Ex-CPU I/F Signals.......................................................................................................... 33 Table 4 EX-CPU access limitation................................................................................................. 37 Table 5: I/O Type-0 68K + Wait Read MCIF AC Timing Parameters........................................... 39 Table 6: I/O Type-0 68K + Wait Write MCIF AC Timing Parameters ........................................... 41 Table 7: I/O TYPE-1 SH3 Critical Timing (Read) ......................................................................... 43 Table 8: I/O TYPE-1 SH3 AC Timing (Write) ............................................................................... 45 Table 9: I/O TYPE-2 M16C SRAM-like + WAIT AC Timing Parameters (Read).......................... 47 Table 10: I/O TYPE-2 M16C SRAM-like + WAIT AC Timing Parameters (Write)........................ 49 Table 11: I/O TYPE-3 MPC850 Read AC Timing Parameters..................................................... 51 Table 12: I/O TYPE-3 MPC850 Write AC Timing Parameters ..................................................... 53 Table 13: Memory Type Read AC Timing Parameters ................................................................ 55 Table 14: Memory Type Write AC Timing Parameters................................................................. 57 Table 17: Ex-CPU Encryption First Quadlet................................................................................. 58 Table 18: Ex-CPU Encryption Reference..................................................................................... 58 Table 19: HSDI Signals ................................................................................................................ 60 Table 20: Application Counter Values .......................................................................................... 62 Table 21: HSDI Pass Through Function....................................................................................... 63 Table 22: HSDI Maximum Clock Rates and Through-Put............................................................ 64 Table 23: General HSDI Mode Settings ........................................................................................ 64 Table 24: HSDI Video Modes ........................................................................................................ 65 Table 25: AC Timing Parameters for Serial I/F (Modes 1 and 4) ................................................. 71 Table 26: AC Timing Parameters for Serial I/F (Modes 2 and 3) ................................................. 71 Table 27: AC Timing Parameters for Parallel I/F (Modes 5, 6, and 7) ......................................... 71 Table 28: AC Timing Parameters for Parallel I/F (Modes 8 and 9) .............................................. 71 Table 29: AC timing parameters for Serial I/F (Mode1)................................................................ 72 Table 30: AC timing parameters for Parallel I/F (Mode2)............................................................. 72 Table 31: AC timing parameters for Parallel I/F (Mode3 and 4)................................................... 72 Table 32: HSDI0 DVD Audio Signals ........................................................................................... 73 Table 33: HSDI1 DVD-Audio Signals ........................................................................................... 73 Table 34: AC Timing Parameters ................................................................................................. 75 Table 35: AC Timing Parameters ................................................................................................. 76 Table 36: AC Timing Parameters ................................................................................................. 77 Table 37: UART CFR Address Offsets......................................................................................... 77 Table 38: UART Registers............................................................................................................ 78 Table 39: PHY Access Register ................................................................................................... 79 Table 40: Base Register Configuration ........................................................................................ 80 Table 41: Base Register Field Descriptions ................................................................................. 80 Table 42: Page 0 (Port Status) Register Configuration ................................................................ 84 Table 43: Page 0 (Port Status) Register Field Descriptions......................................................... 84 Table 44: Page 1 (Vendor ID) Register Configuration.................................................................. 85 Table 45: Page 1 (Vendor ID) Register Field Descriptions .......................................................... 86 Table 46: Power State Summary.................................................................................................. 89 Table 47: I/O Pin and CFR Descriptions for Controlling Power Management States .................. 92 Table 49: FIFO Monitoring Bits..................................................................................................... 96 Table 50: Summary of GPIO use ................................................................................................ 97 Table 149: CFR Address Ranges................................................................................................. 99 Table 151: Pin state during power on reset , just after power on reset and DISABLE_IFn=L .... 106
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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7
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS References
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
The following sources of information were used in the generation of this document: IEEE Standard for a High Performance Serial Bus, IEEE Standard 1394-1995 IEEE 1394a-2000 Serial Bus Supplement Digital Interface for consumer audio/video equipment, IEC Document 61883 Home Digital Network Interface Spec, revision 1.1 5C Digital Transmission Content Protection Specification Acronyms The acronyms used in this document are defined below. 5C CFR DSS DV DVB DVD HSDI IEC IEEE IP MPEG Five Company (Intel, Sony, Matsushita, Hitachi, Toshiba) Configuration Register Direct Satellite System Digital Video Digital Video Broadcasting Digital Versatile Disc High Speed Data Interface International Electrotechnical Commission Institute of Electronics and Electrical Engineers Internet Protocol Motion Pictures Experts Group
Device Ordering Information Ordering Number TSB43CA43APGF TSB43CA43AGGW TSB43CB43APGF TSB43CA42GGW TSB43CA42PGF Name iceM 5C iceM 5C iceM non-5C iceM 5C (2 Port) iceM 5C (2 Port) Package PQFP 176 *BGA 176 PQFP 176 *BGA 176 PQFP 176
1
Hardware IC Characteristics
iceLynx-Micro Overview
iceLynx-Micro( Consumer Electronics Link with Integrated Micro Controller and Physical Layer) is a high performance 1394 link layer device designed as a "total solution" for digitally interfacing advanced audio/video consumer electronics applications. The device is offered in both a DTCP encryption/decryption version (TSB43CA43A & TSB43CA42) and a non-DTCP encryption/decryption version (TSB43CB43). In addition to supporting transmit and receive of MPEG2 and DSS formatted transport streams with encryption and decryption, iceLynx-Micro supports the IEC 61883-6 and Audio Music Protocol standards for audio format and packetizing, and Async and Async Stream (as defined by 1394). The device also features an embedded ARM7TDMI microprocessor core with access to 256K bytes of internal program memory. The ARM7 is embedded to process 1394 specific
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
transactions, thus significantly reducing the processing power required by the host CPU and the development time required by the user. The ARM7 is accessed from the 16/1bit host CPU interface, from a UART communication port, or from a JTAG debug port. iceLynx-Micro integrated 3-port PHY allows the user enhanced flexibility as two additional devices can be utilized in a system application. The PHY's speeds are capable of running at 100Mbps, 200Mbps, or 400Mbps. The PHY follows all requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards. The TSB43CA43A & TSB43CA42 version of iceLynx-Micro incorporates two M6 baseline ciphers(one per HSDI port) per the 5C specification to support transmit and receive of MPEG2 formatted transport streams with encryption and decryption. The TSB43CB43 version of iceLynx-Micro is identical to the TSB43CA43A without implementation of the encryption/decryption features. The TSB43CB43 device allows customers that do not require the encryption/decryption features to incorporate iceLynx-Micro without becoming DTLA licensees. Both devices support the IEC 61883-6 and Audio Music Protocol standards for audio format and packetizing. 1.1 1.1.1 Feature List 1394 Features
Integrated 400 Mbps 3-port PHY Compliant to IEEE 1394-1995 and IEEE 1394a-2000 standards Supports bus manager functions and automatic 1394 self-id verification. Separate Async Ack FIFO decreases the ack-tracking burden on In-CPU and Ex-CPU 1.1.2 DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio( TSB43CA43A & TSB43CA42 Only)
Two M6 baseline ciphers (one per HSDI port) * Content key generation from exchange key AKE acceleration features in hardware * Random Number Generator * Secure Hash Algorithm, Revision 1 (SHA-1) Other AKE acceleration features * Elliptical Curve Digital Signature Algorithm ("EC-DCA") both signature and verification * Elliptical Curve Diffie-Hellman ("EC-DH"), first phase value and shared secret calculation * 160-bit math functions 1.1.3 High Speed Data Interface (HSDI)
Two configurable High Speed Data Interfaces support the following audio and video modes: MPEG2-DVB Interface MPEG2-DSS Interface DV Codec Interface IEC60958 Interface Audio DAC Interface SACD Interface 1.1.4 External CPU Interface 16 bit parallel asynchronous IO-type 16 bit parallel synchronous IO-type 16 bit parallel synchronous memory type
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.1.5 Internal ARM7
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
50MHz Operating Frequency 32-bit and Thumb (16-bit) Mode Support UART included for communication 256K bytes of Program Memory included on chip ARM JTAG included for software debug 1.1.6 Data Buffers
Large 16.5K byte total FIFO Programmable data/space available indicators for buffer flow control 1.1.7 Hardware Packet Formatting for the Following Standards DVB MPEG2 transport stream (IEC61883-4) DSS MPEG2 transport stream per standard DV Stream (IEC 61883-2) SD-DV Audio over 1394 (IEC 61883-6) Audio Music Protocol (Version 1.0 and Enhancements) Async and Async Stream (as defined by 1394) 1.1.8 Additional Features PID filtering for transmit function (up to 16 separate PIDs per HSDI) Packet Insertion - 2 insertion buffers per HSDI 11 general purpose Inputs/Outputs (GPIOs) Interrupt driven to minimize CPU polling. Single 3.3V supply JTAG interface to support post-assembly scan of device I/O - boundary scan
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.2 Application Diagram
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Broadcast
Cable
OR Digital Set Top Box / HDTV Receiver / Satellite Receiver
Encrypt
MPEG2 Demux TSB43Cx43
Digital TV
Decrypt
MPEG2 Decoder
TSB43Cx43
E n c r y p t
TSB43Cx43
DVD
d e c r y p t
e n c r y p t
TSB43Cx43
TSB43Cx43
d e c r y p t
e n c r y p t
Copy Protected 1394 =
AV Receiver
D-VHS/PVR
Figure 1. TSB43Cx43 Typical Application
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
11
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.3 1.3.1 Block Diagram
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43Cx43A Block Diagram
MPEG2 DVB
OR 8 8 8
MPEG2 DSS
OR
HSDI 0 ISO PORT M6 CIPHER
DIGITAL VIDEO (DV)
OR
ISO HSDI 0 FIFO 4KB
CFRs
PCM-AUDIO
OR
IEC60958 (S/PDIF)
H/W AKE
8 8 8
1394a-2000 LINK LAYER CORE
1394a-2000 S400 3-PORT PHY CORE
1394 BUS
MPEG2 DVB
OR
MPEG2 DSS
OR
HSDI 1 ISO PORT
M6 CIPHER
DIGITAL VIDEO (DV)
OR
ISO HSDI 1 FIFO 4KB
PACKETIZER
SUPER AUDIO CD
OR
IEC60958 (S/PDIF)
OR
PCM-AUDIO
AUDIO RX SYT PLL
ASYNC TX 0 FIFO 2KB
ASYNC RX 0 FIFO 2KB
ASYNC TX 1 FIFO 2KB
ASYNC RX 1 FIFO 2KB
BCAST RX FIFO 512 B
CONFIGURATION REGISTERS (CFRs)
L E B DATA
16
256KB RAM PROGRAM MEMORY
UART
MONITOR
EXT. ADDRESS
10
TIMER 0 AND COMM MEMORY
MCU
20
I/F
CONTROL
TIMER 1
1KB
1KB WDOG / TIMER 2 ARM7TDMI RISC CORE
SHARED RAM
11
GP I/O
CFRs
JTAG PORT
ARM DEBUGGER
LEB is an acronym for Local Encryption Block (Note: only included in TSB43CA43)
Figure 2: TSB43Cx43 System Block Diagram
Note: The M6 Cipher is only included in the TSB43CA43.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
12
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.3.2
8 8 8
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43CA42 Block Diagram
MPEG2 DVB
OR
MPEG2 DSS
OR
HSDI 0 ISO PORT M6 CIPHER
DIGITAL VIDEO (DV)
OR
ISO HSDI 0 FIFO 4KB
CFRs
PCM-AUDIO
OR
IEC60958 (S/PDIF)
H/W AKE
8 8 8
1394a-2000 LINK LAYER CORE
1394a-2000 S400 2-PORT PHY CORE
1394 BUS
MPEG2 DVB
OR
MPEG2 DSS
OR
HSDI 1 ISO PORT
M6 CIPHER
DIGITAL VIDEO (DV)
OR
ISO HSDI 1 FIFO 4KB
PACKETIZER
SUPER AUDIO CD
OR
IEC60958 (S/PDIF)
OR
PCM-AUDIO
AUDIO RX SYT PLL
ASYNC TX 0 FIFO 2KB
ASYNC RX 0 FIFO 2KB
ASYNC TX 1 FIFO 2KB
ASYNC RX 1 FIFO 2KB
BCAST RX FIFO 512 B
CONFIGURATION REGISTERS (CFRs)
L E B DATA
16
256KB RAM PROGRAM MEMORY
UART
MONITOR
EXT. ADDRESS
10
TIMER 0 AND COMM MEMORY
MCU
20
I/F
CONTROL
TIMER 1
1KB
1KB WDOG / TIMER 2 ARM7TDMI RISC CORE
SHARED RAM
11
GP I/O
CFRs
JTAG PORT
ARM DEBUGGER
LEB is an acronym for Local Encryption Block (Note: only included in TSB43CA42) Figure 3: TSB43CA42 System Block Diagram
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
13
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.4 1.4.1 Pin Out
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP)
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
3.3v
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
JUNE 10, 2003
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
AG ND R1 R0 AVd d FIL TER0 FIL TER1 PLL _Vdd XI XO PLL _GND Vss Vdd TEST_MODE2 TEST_MODE3 RESETn RESET_ARMn LINK_ON HPS LO W_ PWR_RDY DIS ABLE_IFn GP IO 0 GP IO 1 TEST4 TEST5 GP IO 6 GP IO 7 GP IO 8 GP IO 9 REG_E Nn REG_O UT0 Vdd Vss JTA G_TMS JTA G_TDI JTA G_TDO JTA G_TCK JTA G_TRS Tn ARM_TMS ARM_TDI ARM_TDO UART_TxD UART_RxD GP IO 10 WTCHDOG_TMRn
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Vss Vdd HSDI1_ 60958_ OUT HSDI1_ 60958_ IN HSDI1_ AUDIO_MUTE HSDI1_ AUDIO_ERR HSDI1_ AMCLK _OUT HSDI1_ AMCLK _IN HSDI1_ D7 HSDI1_ D6 HSDI1_ D5 HSDI1_ D4 HSDI1_ D3 HSDI1_ D2 Vss Vdd REG_O UT2 HSDI1_ D1 HSDI1_ D0 HSDI1_ DVA LIDz HSDI1_ SYNCz HSDI1_ AVz HSDI1_ ENz HSDI1_ CLK z HSDI0_ D7 HSDI0_ D6 HSDI0_ D5 HSDI0_ D4 HSDI0_ D3 HSDI0_ D2 Vss Vdd HSDI0_ D1 HSDI0_ D0 HSDI0_ DVA LIDz HSDI0_ SYNCz HSDI0_ AVz HSDI0_ ENz HSDI0_ CLK z HSDI0_ AMCLK _IN HSDI0_ 60958_ IN MCIF_MODE2 MCIF_MODE1 MCIF_MODE0
Vss TEST_MODE0 TEST_MODE1 Vdd VCO_CLK REF_SYT DIV _VCO PLL _TE ST MLPCM_BCLK MLPCM_LRCL K MLPCM_D0 MLPCM_D1 MLPCM_D2 MLPCM_A GP IO 2 GP IO 3 GP IO 4 GP IO 5 MSPCTL Vdd Vss CPS AVd d AG ND TPB0_N TPB0_P AG ND AVd d TPA0_N TPA0_P TPBIAS0 AVd d TPB1_N TPB1_P AG ND TPA1_N TPA1_P TPBIAS1 TPB2_N TPB2_P AVd d TPA2_N TPA2_P TPBIAS2
TSB43CA43 (iceLynx-Micro) INTEGRATED LLC / PHY Plastic QFP
MCIF_ENDIAN Vss Vdd MCIF_ADDR10 MCIF_ADDR9 MCIF_ADDR8 MCIF_ADDR7 MCIF_ADDR6 MCIF_ADDR5 MCIF_ADDR4 MCIF_ADDR3 MCIF_ADDR2 MCIF_ADDR1 MCIF_DATA15 MCIF_DATA14 Vss Vdd REG_O UT1 MCIF_DATA13 MCIF_DATA12 MCIF_DATA11 MCIF_DATA10 MCIF_DATA9 MCIF_DATA8 MCIF_DATA7 MCIF_DATA6 MCIF_DATA5 MCIF_DATA4 MCIF_DATA3 MCIF_DATA2 Vss Vdd MCIF_DATA1 MCIF_DATA0 MCIF_BUSCLKz MCIF_WEz MCIF_OE z MCIF_ACKz MCIF_WAITz MCIF_STRBz MCIF_R_nWz MCIF_CS_MEMz MCIF_CS_IOz MCIF_INTz
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
Figure 4: TSB43CA43A Plastic QFP Pin Out
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
14
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.4.2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array (*BGA)
U16 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 T17 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T1 R17 R16 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R2
3.3v
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B17 C1 C2 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16
WTCHDOG_TMRn UART_RxD ARM_TDI JTA G_TCK JTA G_TMS REG_E Nn GP IO 6 GP IO 0 LINK_ON RESET_ARMn Vdd XO FIL TER1 R0 AG ND MCIF_INTz GP IO 10 ARM_TDO JTA G_TRS Tn JTA G_TDI REG_O UT0 GP IO 7 TEST5 DIS ABLE_IFn RESETn Vss XI FIL TER0 R1 TPBIAS2 MCIF_CS_MEMz MCIF_CS_IOz UART_TxD ARM_TMS JTA G_TDO Vdd GP IO 9 TEST4 LO W_ PWR_RDY TEST_MODE3 PLL _GND PLL _Vdd AVd d TPA2_P
Vss HSDI1_ 60958_ OUT HSDI1_ AUDIO_ERR HSDI1_ D7 HSDI1_ D4 Vdd HSDI1_ DVA LIDz HSDI1_ CLK z HSDI0_ D4 HSDI0_ D3 HSDI0_ D1 HSDI0_ SYNCz HSDI0_ CLK z MCIF_MODE2 MCIF_MODE0 Vss Vdd HSDI1_ AUDIO_MUTE HSDI1_ AMCLK _IN HSDI1_ D5 Vss HSDI1_ D0 HSDI1_ SYNCz HSDI0_ D7 HSDI0_ D2 HSDI0_ D0 HSDI0_ AVz HSDI0_ AMCLK _IN MCIF_MODE1 MCIF_ENDIAN TEST_MODE1 TEST_MODE0 HSDI1_ 60958_ IN HSDI1_ AMCLK _OUT HSDI1_ D6 HSDI1_ D2 REG_O UT2 HSDI1_ AVz HSDI0_ D6 Vss HSDI0_ DVA LIDz HSDI0_ ENz HSDI0_ 60958_ IN Vss
TSB43CA43 (iceLynx-Micro) INTEGRATED LLC / PHY *BGA
TPA2_N MCIF_WAITz MCIF_STRBz MCIF_R_nWz Vss GP IO 8 GP IO 1 HPS TEST_MODE2 AVd d TPB2_P TPB2_N MCIF_WEz MCIF_OE z MCIF_ACKz TPBIAS1 TPA1_P TPA1_N MCIF_DATA1 MCIF_DATA0 MCIF_BUSCLKz AG ND TPB1_P TPB1_N MCIF_DATA3 MCIF_DATA2 Vss Vdd AVd d TPBIAS0 TPA0_P TPA0_N MCIF_DATA4 MCIF_DATA7 MCIF_DATA6 MCIF_DATA5 AG ND AVd d TPB0_P TPB0_N MCIF_DATA8 MCIF_DATA11 MCIF_DATA10 MCIF_DATA9
R1 P17 P16 P15 P11 P10 P9 P8 P7 P3 P2 P1 N17 N16 N15 N3 N2 N1 M17 M16 M15 M3 M2 M1 L17 L16 L15 L14 L4 L3 L2 L1 K17 K16 K15 K14 K4 K3 K2 K1 J17 J16 J15 J14
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
JUNE 10, 2003
C17 D1 D2 D3 D7 D8 D9 D10 D11 D15 D16 D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G4 G1 4 G1 5 G1 6 G1 7 H1 H2 H3 H4 H14 H15 H16 H17 J1 J2 J3 J4
Vdd REF_SYT VCO_CLK Vdd HSDI1_ D3 HSDI1_ D1 HSDI1_ ENz HSDI0_ D5 Vdd MCIF_ADDR10 MCIF_ADDR9 MCIF_ADDR8 MLPCM_BCLK PLL _TE ST DIV _VCO MCIF_ADDR7 MCIF_ADDR6 MCIF_ADDR5 MLPCM_D1 MLPCM_D0 MLPCM_LRCL K MCIF_ADDR4 MCIF_ADDR3 MCIF_ADDR2 GP IO 3 GP IO 2 MLPCM_A MLPCM_D2 MCIF_ADDR1 MCIF_DATA15 MCIF_DATA14 Vss GP IO 4 Vdd MSPCTL GP IO 5 REG_O UT1 Vdd MCIF_DATA13 MCIF_DATA12 Vss AG ND AVd d CPS
Figure 5: TSB43CA43A *BGA Pin Out
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
15
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.4.3
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43CA42 Plastic Quad Flat Pack (PQFP)
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 3.3v
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
JUNE 10, 2003
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
AG ND R1 R0 AVd d FIL TER0 FIL TER1 PLL _Vdd XI XO PLL _GND Vss Vdd TEST_MODE2 TEST_MODE3 RESETn RESET_ARMn LINK_ON HPS LO W_ PWR_RDY DIS ABLE_IFn GP IO 0 GP IO 1 TEST4 TEST5 GP IO 6 GP IO 7 GP IO 8 GP IO 9 REG_E Nn REG_O UT0 Vdd Vss JTA G_TMS JTA G_TDI JTA G_TDO JTA G_TCK JTA G_TRS Tn ARM_TMS ARM_TDI ARM_TDO UART_TxD UART_RxD GP IO 10 WTCHDOG_TMRn
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Vss Vdd HSDI1_ 60958_ OUT HSDI1_ 60958_ IN HSDI1_ AUDIO_MUTE HSDI1_ AUDIO_ERR HSDI1_ AMCLK _OUT HSDI1_ AMCLK _IN HSDI1_ D7 HSDI1_ D6 HSDI1_ D5 HSDI1_ D4 HSDI1_ D3 HSDI1_ D2 Vss Vdd REG_O UT2 HSDI1_ D1 HSDI1_ D0 HSDI1_ DVA LIDz HSDI1_ SYNCz HSDI1_ AVz HSDI1_ ENz HSDI1_ CLK z HSDI0_ D7 HSDI0_ D6 HSDI0_ D5 HSDI0_ D4 HSDI0_ D3 HSDI0_ D2 Vss Vdd HSDI0_ D1 HSDI0_ D0 HSDI0_ DVA LIDz HSDI0_ SYNCz HSDI0_ AVz HSDI0_ ENz HSDI0_ CLK z HSDI0_ AMCLK _IN HSDI0_ 60958_ IN MCIF_MODE2 MCIF_MODE1 MCIF_MODE0
Vss TEST_MODE0 TEST_MODE1 Vdd VCO_CLK REF_SYT DIV _VCO PLL _TE ST MLPCM_BCLK MLPCM_LRCL K MLPCM_D0 MLPCM_D1 MLPCM_D2 MLPCM_A GP IO 2 GP IO 3 GP IO 4 GP IO 5 MSPCTL Vdd Vss CPS AVd d AG ND TPB0_N TPB0_P AG ND AVd d TPA0_N TPA0_P TPBIAS0 AVd d TPB1_N TPB1_P AG ND TPA1_N TPA1_P TPBIAS1 N/C N/C AVd d N/C N/C N/C
TSB43CA42 (iceLynx-Micro) INTEGRATED LLC / PHY Plastic QFP
MCIF_ENDIAN Vss Vdd MCIF_ADDR10 MCIF_ADDR9 MCIF_ADDR8 MCIF_ADDR7 MCIF_ADDR6 MCIF_ADDR5 MCIF_ADDR4 MCIF_ADDR3 MCIF_ADDR2 MCIF_ADDR1 MCIF_DATA15 MCIF_DATA14 Vss Vdd REG_O UT1 MCIF_DATA13 MCIF_DATA12 MCIF_DATA11 MCIF_DATA10 MCIF_DATA9 MCIF_DATA8 MCIF_DATA7 MCIF_DATA6 MCIF_DATA5 MCIF_DATA4 MCIF_DATA3 MCIF_DATA2 Vss Vdd MCIF_DATA1 MCIF_DATA0 MCIF_BUSCLKz MCIF_WEz MCIF_OE z MCIF_ACKz MCIF_WAITz MCIF_STRBz MCIF_R_nWz MCIF_CS_MEMz MCIF_CS_IOz MCIF_INTz
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
Figure 6: TSB43CA42 Plastic QFP Pin Out
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
16
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.4.4
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TSB43CA42 Micro-Star Ball Grid Array (*BGA)
U16 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 T17 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T1 R17 R16 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R2 3.3v
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B17 C1 C2 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16
WTCHDOG_TMRn UART_RxD ARM_TDI JTA G_TCK JTA G_TMS REG_E Nn GP IO 6 GP IO 0 LINK_ON RESET_ARMn Vdd XO FIL TER1 R0 AG ND MCIF_INTz GP IO 10 ARM_TDO JTA G_TRS Tn JTA G_TDI REG_O UT0 GP IO 7 TEST5 DIS ABLE_IFn RESETn Vss XI FIL TER0 R1 N/C MCIF_CS_MEMz MCIF_CS_IOz UART_TxD ARM_TMS JTA G_TDO Vdd GP IO 9 TEST4 LO W_ PWR_RDY TEST_MODE3 PLL _GND PLL _Vdd AVd d N/C
Vss HSDI1_ 60958_ OUT HSDI1_ AUDIO_ERR HSDI1_ D7 HSDI1_ D4 Vdd HSDI1_ DVA LIDz HSDI1_ CLK z HSDI0_ D4 HSDI0_ D3 HSDI0_ D1 HSDI0_ SYNCz HSDI0_ CLK z MCIF_MODE2 MCIF_MODE0 Vss Vdd HSDI1_ AUDIO_MUTE HSDI1_ AMCLK _IN HSDI1_ D5 Vss HSDI1_ D0 HSDI1_ SYNCz HSDI0_ D7 HSDI0_ D2 HSDI0_ D0 HSDI0_ AVz HSDI0_ AMCLK _IN MCIF_MODE1 MCIF_ENDIAN TEST_MODE1 TEST_MODE0 HSDI1_ 60958_ IN HSDI1_ AMCLK _OUT HSDI1_ D6 HSDI1_ D2 REG_O UT2 HSDI1_ AVz HSDI0_ D6 Vss HSDI0_ DVA LIDz HSDI0_ ENz HSDI0_ 60958_ IN Vss
TSB43CA42 (iceLynx-Micro) INTEGRATED LLC / PHY *BGA
N/C MCIF_WAITz MCIF_STRBz MCIF_R_nWz Vss GP IO 8 GP IO 1 HPS TEST_MODE2 AVd d N/C N/C MCIF_WEz MCIF_OE z MCIF_ACKz TPBIAS1 TPA1_P TPA1_N MCIF_DATA1 MCIF_DATA0 MCIF_BUSCLKz AG ND TPB1_P TPB1_N MCIF_DATA3 MCIF_DATA2 Vss Vdd AVd d TPBIAS0 TPA0_P TPA0_N MCIF_DATA4 MCIF_DATA7 MCIF_DATA6 MCIF_DATA5 AG ND AVd d TPB0_P TPB0_N MCIF_DATA8 MCIF_DATA11 MCIF_DATA10 MCIF_DATA9
R1 P17 P16 P15 P11 P10 P9 P8 P7 P3 P2 P1 N17 N16 N15 N3 N2 N1 M17 M16 M15 M3 M2 M1 L17 L16 L15 L14 L4 L3 L2 L1 K17 K16 K15 K14 K4 K3 K2 K1 J17 J16 J15 J14
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
JUNE 10, 2003
C17 D1 D2 D3 D7 D8 D9 D10 D11 D15 D16 D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G4 G1 4 G1 5 G1 6 G1 7 H1 H2 H3 H4 H14 H15 H16 H17 J1 J2 J3 J4
Vdd REF_SYT VCO_CLK Vdd HSDI1_ D3 HSDI1_ D1 HSDI1_ ENz HSDI0_ D5 Vdd MCIF_ADDR10 MCIF_ADDR9 MCIF_ADDR8 MLPCM_BCLK PLL _TE ST DIV _VCO MCIF_ADDR7 MCIF_ADDR6 MCIF_ADDR5 MLPCM_D1 MLPCM_D0 MLPCM_LRCL K MCIF_ADDR4 MCIF_ADDR3 MCIF_ADDR2 GP IO 3 GP IO 2 MLPCM_A MLPCM_D2 MCIF_ADDR1 MCIF_DATA15 MCIF_DATA14 Vss GP IO 4 Vdd MSPCTL GP IO 5 REG_O UT1 Vdd MCIF_DATA13 MCIF_DATA12 Vss AG ND AVd d CPS
Figure 7: TSB43CA42 *BGA Pin Out
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
17
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.5 Pin Name Pin Description Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
I/O
Description
Miscellanous Pins DISABLE_IFn HPS
T8 P8
64 62
I I
LOW_PWR_RDY WTCH_DG_TMRn RESET_ARMn RESETn
R8 U16 U7 T7
63 88 60 59 1, 21, 55, 76, 102, 117, 131, 146, 162, 176 24, 27, 35, 45, 54 4, 20, 56, 75, 101, 116, 130, 145, 161, 175
O O I I
Interface Disable. When asserted, the interfaces are put into a Hi-Z state. Interfaces include: ex-CPU, HSDI, GPIO, and WTCH_DG_TMRn. Host Power Status. This indicates the power status of the external system to iceLynx-Micro. A rising edge indicates the system CPU has been turned ON. (The internal ARM should wake up.) A falling edge indicates the system CPU has been turned OFF. (The internal ARM decides if power down is necessary.) Output to system to indicate iceLynx-Micro is ready to go into a low power state. The ARM and WTCH_DG_TMRn control this pin. Watch Dog Timer (for the ARM.) iceLynx-Micro hardware asserts this pin whenever ARM software has not updated the Timer2 register within the allowed time period. ARM reset. This signal resets the internal ARM processor. Device reset. This signal resets all logic. This includes the PHY, Link core, memory, the ARM, and random logic. Digital Ground.
Power & Ground Pins VSS A2, B1, B7, C11, C16, G17, J1, L15, P11, T6 AGND J2, K4, M3, U2 PLL_GND R6 VDD A7, B3, C17, D3, D11, H2, H15, L14, R11, U6
Analog Ground.
PLL Ground. Digital Power Supply. Must be set to 3.3V nominal.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
18
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name AVDD Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O Description Analog Power Supply. Must be set to 3.3V nominal.
PLL_VDD Regulator Pins REG_ENn REG_OUT0 REG_OUT1 REG_OUT2
J3, K3, L4, P3, R4 R5 U11 T11 H14 C8
23, 28, 32, 41, 48 51 73 74 115 160 95 I O O O I/O
PLL Power Supply. Must be set to 3.3V nominal. Internal Regulator Enable. The iceLynx-Micro core voltage is 1.8V. Internal regulators are used to regulate the 3.3V VDD inputs to 1.8V. This pin enables the regulators. 1.8V Regulator Output. This pin should be connected to ground using a 0.1uF capacitor. 1.8V Regulator Output. This pin should be connected to ground using a 0.1uF capacitor. 1.8V Regulator Output. This pin should be connected to ground using a 0.1uF capacitor. MCIF Acknowledge pin. Default active low. iceLynx-Micro asserts this signal if it has completed the MCIF request. This signal is driven when Chip Select (CS) is asserted. This signal is used for the following modes: 68000 + Wait I/O Access I/O TYPE-3 MPC850 MCIF Address 1 pin. This data pin is the least significant bit of the MCIF Address Bus. MCIF_ADDR0 is internally grounded. Only 16-bit addressing is allowed. MCIF_ADDR1 should be connected to the Address1 signal of the system CPU. MCIF Address 2 pin MCIF Address 3 pin MCIF Address 4 pin MCIF Address 5 pin MCIF Address 6 pin MCIF Address 7 pin MCIF Address 8 pin MCIF Address 9 pin MCIF Address 10 pin. This data pin is the most significant bit of the MCIF Address Bus. MCIF Bus Clock. This pin is only used for the MCIF synchronous mode. (I/O TYPE-3 MPC850) and the Memory Access. This signal should be pulled high if not used. MCIF Chip Select for all I/O MCIF modes. MCIF Chip Select for the Memory MCIF mode. MCIF DATA 0 pin. This data pin is the least significant bit of the MCIF Data Bus. MCIF DATA 1 pin.
External CPU Interface Pins MCIF_ACKz N15
MCIF_ADDR1
G14
120
I
MCIF_ADDR2 MCIF_ADDR3 MCIF_ADDR4 MCIF_ADDR5 MCIF_ADDR6 MCIF_ADDR7 MCIF_ADDR8 MCIF_ADDR9 MCIF_ADDR10 MCIF_BUSCLKz
F17 F16 F15 E17 E16 E15 D17 D16 D15 M15
121 122 123 124 125 126 127 128 129 98
I I I I I I I I I I
MCIF_CS_IOz MCIF_CS_MEMz MCIF_DATA0 MCIF_DATA1
R16 R17 M16 M17
90 91 99 100
I I I/O I/O
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
19
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name MCIF_DATA2 MCIF_DATA3 MCIF_DATA4 MCIF_DATA5 MCIF_DATA6 MCIF_DATA7 MCIF_DATA8 MCIF_DATA9 MCIF_DATA10 MCIF_DATA11 MCIF_DATA12 MCIF_DATA13 MCIF_DATA14 MCIF_DATA15 MCIF_ENDIAN Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Description MCIF DATA 2 pin. MCIF DATA 3 pin. MCIF DATA 4 pin. MCIF DATA 5 pin. MCIF DATA 6 pin. MCIF DATA 7 pin. MCIF DATA 8 pin. MCIF DATA 9 pin. MCIF DATA 10 pin. MCIF DATA 11 pin. MCIF DATA 12 pin. MCIF DATA 13 pin. MCIF DATA 14 pin. MCIF DATA 15 pin. This data pin is the most significant bit of the MCIF Data Bus. MCIF Endian Pin. This sets the Endianess for accesses between the external CPU and the internal iceLynx-Micro memory. This pin sets Endianess for all MCIF modes. When set to a logical 0, data is read/written to the ex-CPU exactly as it is stored in iceLynx-Micro memory. (Big Endian) When set to a logical 1, data is swapped on half-word and byte boundaries before it is read/written to the ex-CPU. (Little Endian) MCIF Interrupt. This signal is push-pull. (always asserted) It does not require a pull-up resistor. MCIF Mode 0. Used to select MCIF mode. MCIF Mode 1. Used to select MCIF mode. MCIF Mode 2. Used to select MCIF mode. MCIF Output Enable. Default active low. This input pin indicates if the system CPU wants to perform a MCIF read access. This signal is used for the following modes: SH-3 I/O Access M16C/62 I/O Access Memory Access This signal should be pulled high if not used. MCIF Read/Write pin. Default value for read is a logical 1. Default value for write is a logical 0. MCIF Strobe pin. Default active low. This pin is used (along with MCIF_CS_IOz) to validate the MCIF access. This signal is used for the following modes: 68000 + Wait I/O Access MPC850 I/O Access When not used, this pin should be pulled high.
L16 L17 K17 K14 K15 K16 J17 J14 J15 J16 H17 H16 G16 G15 B17
103 104 105 106 107 108 109 110 111 112 113 114 118 119 132
MCIF_INTz MCIF_MODE0 MCIF_MODE1 MCIF_MODE2 MCIF_OEz
T17 A16 B15 A15 N16
89 133 134 135 96
O I I I I
MCIF_R_nWz MCIF_STRBz
P15 P16
92 93
I I
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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20
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name MCIF_WAITz Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O O Description MCIF Wait pin. Default active high. iceLynx-Micro asserts this signal if it is not ready to service an MCIF request. When not asserted, this signal is in high-Z state. This signal is used for the following modes: 68000 + Wait I/O Access SH-3 I/O Access M16C/62 I/O Access
P17
94
MCIF_WEz
MCIF Write Enable. Default active low. This input pin indicates if the system CPU wants to perform a MCIF write access. This signal is used for the following modes: * SH-3 I/O Access * M16C/62 I/O Access * Memory Access This signal should be pulled high if not used. Universal Asynchronous Receiver Transmitter Pins UART_RxD U15 86 I UART receive port. Data from the system is input to the UART buffer using this pin. UART_TxD R14 85 O UART transmit port. Data from the UART buffer is output to the system using this pin. Joint Test Action Group (JTAG) & ARM Pins JTAG_TCK U13 80 I JTAG Clock pin. Both the boundary scan and ARM JTAG uses this input for the JTAG clock. JTAG_TDI T12 78 I JTAG Test Data Input pin JTAG_TDO R12 79 O JTAG Test Data Output pin JTAG_TMS U12 77 I JTAG Test Mode Selector pin. JTAG_TRSTn T13 81 I JTAG Reset Pin. Both the boundary scan and ARM JTAG uses this input for the JTAG clock. Note 1: TSB43Cx43A/TSB43CA42 must have JTAG_TRSTn=0 for correct ARM interrupt operation. Note 2: JTAG_TRST must be asserted once after powerup for correct operation of the iceLynx-Micro. ARM_TDI U14 83 I ARM JTAG Test Data Input pin ARM_TDO T14 84 O ARM JTAG Test Data Output pin ARM_TMS R13 82 I ARM JTAG Test Mode Selector pin General Purpose Input/Out Pins (GPIO) GPIO0 U9 65 I/O GPIO0. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO1 P9 66 I/O GPIO1. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO2 G2 15 I/O GPIO2. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO3 G1 16 I/O GPIO3. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
N17
97
I
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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21
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 Physical Layer Pins TPA0_N TPA1_N TPA2_N TPA0_P TPA1_P TPA2_P TPB0_N TPB1_N TPB2_N TPB0_P TPB1_P TPB2_P TPBIAS0 TPBIAS1 TPBIAS2 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O I/O I/O I/O I/O I/O I/O Description GPIO 4. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO 5. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO6. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO7. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO8. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO9. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. GPIO10. Can be programmed as general-purpose input, general-purpose output, or specific function. Power-up default is input. Twisted Pair A Differential Signal Terminals. For an unused port, TPAN and TPAP signals are left open.(i.e. TSB43CA42 for Port 2)
H1 H4 U10 T10 P10 R10 T15
17 18 69 70 71 72 87
L1, N1, R1, L2, N2, R2 K1, M1, P1, K2, M2, P2 L3, N3, T1
29, 36, 42, 30, 37, 43 25, 33, 39, 26, 34, 40 31, 38, 44
I/O
I/O
Twisted Pair B Differential Signal Terminals. For an unused port, TPBN and TPBP signals is left open.(i.e. TSB43CA42 for Port 2)
I/O
R1 R0
T3, U3
46, 47 -
Twisted Pair Bias Output. These signals provide the 1.86V nominal bias voltage needed for proper operation of the twisted pair driver and receivers for signaling an "active connection" to a remote node. For an unused port, TPBIAS is left unconnected.(i.e. TSB43CA42 for Port 2) Current Setting Resistors. These pins are connected to external resistors to set the internal operating currents and cable driver output currents. A resistance of 6.34k 1% is required to meet the IEEE 1394-1995 output voltage limits.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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22
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name FILTER0 FILTER1 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O Description PLL Filter Terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency-multiplier PLL, which is using the crystal oscillator. A 0.1 F 10% capacitor is the only external component required to complete this filter. Crystal Oscillator Inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the crystal used. Cable Power Status. Input to iceLynx-Micro used to detect if cable power is present. This pin should be connected to the cable power through 390 k resistor. Maximum speed of PHY. When this signal = High; S100 and S200 operation. When this signal = Low; S100, S200 and S400. Link On output. This signal is asserted whenever LPS is low and a Link On packet is received from the 1394 bus.
T4, U4
49, 50
I/O
XI X0 CPS MSPCTL LINKON
T5, U5 J4 H3 U8
52, 53 22 19 61
I I O
High Speed Data Interface (HSDI) Port 0 Pins HSDI0_60958_IN C14 136 I 60958 Data Input. HSDI0_AMCLK_IN B14 137 I Audio Master Clock Input. This clock is used to decode the bi-phase encoding of 60958 data. This pin is also used to input the 1.5*BCLK for Flow Control mode. HSDI Port 0 Available. Programmable. Default active low. For receive from 1394, this signal indicates if a 1394 packet is available in the receive buffer for reading. The HSDI_AV signal for MPEG2 data also depends on time stamp based release. For transmit onto 1394, this signal is used to indicate buffer level in HSDI TX mode 8 and 9 by programming a CFR. If the buffer level is above a programmed level, HSDI_AV will be asserted. HSDI Port 0 Clock. Programmable. Default rising edge sample. This clock is used to operate the HSDI port 0 logic. In parallel mode, the maximum clock is 27MHz. In serial mode, the maximum clock is 70MHz. This signal is output to HSDI1_CLKz in pass thru mode. This signal is used as HSDI0_MLPCM_BCLK for DVDAudio Transmit.
HSDI0_AVz
B13
140
O
HSDI0_CLKz
A14
138
I
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
23
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name HSDI0_D0 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O Description
B12
143
HSDI Port 0 Data 0 Pin. Data 0 is the least significant bit on the HSDI data bus. In serial mode, only HSDI0_D0 is used. This signal is output to HSDI1_D0 in pass thru mode. This signal is used as HSDI0_MLPCM_D0 for DVD-Audio Transmit. HSDI Port 0 Data 1 Pin This signal is output to HSDI1_D1 in pass thru mode. This signal is used as HSDI0_MLPCM_D1 for DVD-Audio Transmit. HSDI Port 0 Data 2 Pin This signal is output to HSDI1_D2 in pass thru mode. This signal is used as HSDI0_MLPCM_D2 for DVD-Audio Transmit. HSDI Port 0 Data 3 Pin This signal is output to HSDI1_D3 in pass thru mode. This signal is used as HSDI0_MLPCM_A for DVD-Audio Transmit. HSDI Port 0 Data 4 Pin This signal is output to HSDI1_D4 in pass thru mode HSDI Port 0 Data 5 Pin This signal is output to HSDI1_D5 in pass thru mode HSDI Port 0 Data 6 Pin This signal is output to HSDI1_D6 in pass thru mode HSDI Port 0 Data 7 Pin. Data 0 is the most significant bit on the HSDI data bus. This signal is output to HSDI1_D7 in pass thru mode HSDI Port 0 Data Valid Pin. Programmable. Default active high. This pin indicates if data on the HSDI data bus valid for reading or writing. For transmit onto 1394, this signal is provided by the system with the data. For receive from 1394, iceLynx-Micro provides this signal with the data. For HSDI DV modes, this signal is used as HSDI0_FrameSync indicating DV frame boundary. This signal is output to HSDI1_DVALIDz in pass thru mode If not used in transmit mode, this signal is pulled low.
HSDI0_D1
A12
144
I/O
HSDI0_D2
B11
147
I/O
HSDI0_D3
A11
148
I/O
HSDI0_D4 HSDI0_D5 HSDI0_D6 HSDI0_D7
A10 D10 C10 B10
149 150 151 152
I/O I/O I/O I/O
HSDI0_DVALIDz
C12
142
I/O
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
24
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name HSDI0_ENz Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I Description HSDI Port 0 Enable. Programmable. Default active low. Input by the system to enable the HSDI for both transmit and receive from 1394. If not used, this signal is pulled enabled (low or high depending on the polarity set). The application can use HSDI_DVALID or HSDI_SYNC to validate the HSDI data. This signal is used as HSDI0_MLPCM_LRCLK for DVDAudio Transmit. HSDI Port 0 Sync Signal. Programmable. Default active high. This signal is used to indicate the start of packet. For transmit onto 1394, this signal is provided by the system with the data. For receive from 1394, iceLynx-Micro provides this signal with the data. This signal is output to HSDI1_SYNCz in pass thru mode. If not used in transmit mode, this signal is pulled low or high depending on the polarity.
C13
139
HSDI0_SYNCz
A13
141
I/O
High Speed Data Interface (HSDI) Port 1 Pins HSDI1_AMCLK_IN B5 169 I Audio Master Clock Input. This clock is used to decode the bi-phase encoding of 60958 data. This pin is also used to input the 1.5*BCK for Flow Control mode. MLPCM Interface, HSDI1 Audio Port, and HSDI1 video port share IsoPathBuffer 1. Only one interface can access the buffer at a time. Audio Master Clock Output. This clock is derived from the VCO_CLK input. 60958 data output from iceLynx-Micro is bi-phase encoded using this clock. Audio Error Signal. iceLynx-Micro asserts this signal whenever an Audio Error condition occurs. (Receive from 1394 only.) Audio Mute Status. iceLynx-Micro asserts this signal whenever an Audio Mute condition has occurred, and hardware has muted the HSDI1 audio interface. (Receive from 1394 only.) 60958 Data Input. 60958 Data Output This signal is also used as FLWCTRL_DVALID in Flow Control Data Valid mode.
HSDI1_AMCLK_OUT HSDI1_AUDIO_ERR HSDI1_AUDIO_MUTE
C5 A4 B4
170 171 172
O O O
HSDI1_60958_IN HSDI1_60958_OUT
C4 A3
173 174
I O
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
25
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O Description
HSDI1_AVz
C9
155
O
HSDI Port 1 Available. Programmable. Default active low. For receive from 1394, this signal indicates if a 1394 packet is available in the receive buffer for reading. The HSDI_AV signal for MPEG2 data also depends on time stamp based release. For transmit onto 1394, this signal is used to indicate buffer level in HSDI TX mode 8 and 9 by programming a CFR. This pin is used to indicate buffer level in transmit mode by programming a CFR. If the buffer level is above a programmed level, HSDI_AV is asserted. HSDI Port 1 Clock. Programmable. Default rising edge sample. This clock is used to operate the HSDI port 1 logic. In parallel mode, the maximum clock is 27MHz. In serial mode, the maximum clock is 70MHz. This signal is used as HSDI1_SACD_BCLK for SACD Transmit and Receive. MLPCM Interface, HSDI1 Audio Port, and HSDI1 video port share IsoPathBuffer 1. Only one interface can access the buffer at a time. HSDI Port 1 Data 0 Pin. Data 0 is the least significant bit on the HSDI data bus. In serial mode, only HSDI0_D0 is used. This signal is used as HSDI1_SACD_D0 for SACD Transmit and Receive. HSDI Port 1 Data 1 Pin This signal is used as HSDI1_SACD_D1 for SACD Transmit and Receive.
HSDI1_CLKz
A9
153
I/O
HSDI1_D0
B8
158
I/O
HSDI1_D1
D8
159
I/O
HSDI1_D2
C7
163
I/O
HSDI Port 1 Data 2 Pin This signal is used as HSDI1_SACD_D2 for SACD Transmit and Receive. HSDI Port 1 Data 3 Pin This signal is used as HSDI1_SACD_D3 for SACD Transmit and Receive. HSDI Port 1 Data 4 Pin This signal is used as HSDI1_SACD_D4 for SACD Transmit and Receive.
HSDI1_D3
D7
164
I/O
HSDI1_D4
A6
165
I/O
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name HSDI1_D5 B6 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O Description HSDI Port 1 Data 5 Pin This signal is used as HSDI1_SACD_D5 for SACD Transmit and Receive. HSDI Port 1 Data 6 Pin This signal is used as HSDI1_SACD_A for SACD Transmit and Receive. HSDI Port 1 Data 7 Pin. Data 0 is the most significant bit on the HSDI data bus. HSDI Port 1 Data Valid Pin. Programmable. Default active high. This pin indicates if data on the HSDI data bus valid for reading or writing. For transmit onto 1394, this signal is provided by the system with the data. For receive from 1394, iceLynx-Micro provides this signal with the data. For HSDI DV modes, this signal is used as HSDI0_FrameSync indicating DV frame boundary. If not used in transmit mode, this signal is pulled low. HSDI Port 1 Enable. Programmable. Default active low. Input by the system to enable the HSDI for both transmit and receive from 1394. If not used, this signal is pulled enabled (low or high depending on the polarity set). The application can use HSDI_DVALID or HSDI_SYNC to validate the HSDI data. HSDI Port 1 Sync Signal. Programmable. Default active high. This signal is used to indicate the start of packet For transmit onto 1394, this signal is provided by the system with the data. For receive from 1394, iceLynx-Micro provides this signal with the data. If not used in transmit mode, this signal is pulled low or high depending on the polarity. This signal is used as HSDI1_SACD_FRAME for SACD Transmit and Receive.
166
HSDI1_D6
C6
167
I/O
HSDI1_D7 HSDI1_DVALIDz
A5 A8
168 157
I/O I/O
HSDI1_ENz
D9
154
I
HSDI1_SYNCz
B9
156
I/O
DVD-Audio Interface Pins MLPCM_A G3
14
I/O
Audio MLPCM Interface Ancillary Data. Ancillary data is input/output using this pin. For DVD-Audio, MLPCM_LRCLK determines if Ancillary Left or Ancillary Right data is present. This signal also functions as FLWCTL_A in Flow Control mode
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name MLPCM_BCLK E1 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O Description Audio MLPCM Interface Bit Clock. Multiple functions: DVD Audio BCK (I) DVD Audio BCK (O) Flow Control BCK (I/O) MLPCM Interface, HSDI1 Audio Port, and HSDI1 video port share IsoPathBuffer 1. Only one interface can access the buffer at a time. Audio MLPCM Interface D0. Contains Channel 1 and Channel 2 information. MLPCM_LRCLK determines which channel is present. This signal also functions as FLWCTL_D0 in Flow Control mode. Audio MLPCM Interface D1. Contains Channel 3 and Channel 4 information. MLPCM_LRCLK determines which channel is present. This signal also functions as FLWCTL_D0 in Flow Control mode Audio MLPCM Interface D2. Contains Channel 5 and Channel 6 information. MLPCM_LRCLK determines which channel is present. This signal also functions as FLWCTL_D0 in Flow Control mode Audio MLPCM Interface Left-Right Clock. Multiple functions: DVD Audio LRCLK (I) DVD Audio LRCLK (O) Flow Control LRCLK (I/O) Output for External Phase Detector. This signal is the divided VCO_CLK. It used by the external phase detector to compare with the REF_SYT signal. The divide ratios are setup in CFR. PLL Test. This signal is used for Internal TI testing and should be unconnected for normal operation. Output for External Phase Detector. This signal represents the SYT match for received audio or DV packets. The phase detector uses it as input to detect differences between the SYT match and the VCO clock. Input from VCO. This is used to generate internal audio and DV clocks for receive clock recovery. Audio Frequency: 33.868MHz or 36.864MHz. DV Frequency: 30.72MHz, 27 MHz Test Mode. Used for Internal TI testing. Should be pulled low for normal operation.
9
MLPCM_D0
F2
11
I/O
MLPCM_D1
F1
12
I/O
MLPCM_D2
G4
13
I/O
MLPCM_LRCLK
F3
10
I/O
Audio Phase Lock Loops Pins DIV_VCO E3 7
O
PLL_TEST REF_SYT
E2 D1
8 6
O O
VCO_CLK
D2
5
I
Test Mode Pins TEST_MODE0
C2
2
I/O
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Pin Name TEST_MODE1 TEST_MODE2 TEST_MODE3 TEST4 TEST5 Pin No
BGA QFP
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 I/O I/O I/O I/O I/O I/O Description Test Mode. Used for Internal TI testing. Should be pulled low for normal operation. Test Mode. Used for Internal TI testing. Should be pulled low for normal operation. Test Mode. Used for Internal TI testing. Should be pulled low for normal operation. Factory Test Pin. Should tie to low for normal operation. Recommend connection to ground through a 1 k resistor. Factory Test Pin. Should tie to low for normal operation. Recommend connection to ground through a 1 k resistor.
C1 P7 R7 R9 T9
3 57 58 67 68
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.6 Memory Map
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
0000 0000 0000 001C
Exception Vectors
256 x 1024 Byte Program Memory
Programmable Write Base Address (Comm Memory)
0004 0000
2 x 1024 byte RAM Memory Access
Programmable Read Base Address (Comm Memory)
0004 0800
Reserved
0010 0000
Configuration Registers
0010 0800
Reserved
FFFF FFFF
Figure 8: TSB43Cx43 Memory Map
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
The diagram above shows the memory map for iceLynx-Micro. The program memory (256K bytes) includes the communication memory for transactions between the internal and external CPU. The boundaries of the communication memory are programmable. (Refer to the register address) Two 1024 byte RAMs are included for Ex-CPU Memory Access functions. The Configuration Registers start at offset 0x 0010 0000. Note: The program memory is divided into physical blocks. (For example, 4 blocks of 64K each.) Each memory block is accessed by the ARM or ex-CPU independently. The ARM could access program memory in block 1 at the same time as the ex-CPU accesses Comm memory in block 4. Because of this, software should program the comm memory pointers into the highest memory block (the last 64K of block 4.) Non-critical program code can also be loaded into this block. 1.7 DTCP Encryption - Hardware Implementation (TSB43CA43A & TSB43CA42 Only)
The TSB43CA43A & TSB43CA42 version of iceLynx-Micro is fully compliant with the DTCP method of digital content protection. iceLynx-Micro supports the baseline M6 cipher, content key creation and key updates in iceLynx-Micro hardware. iceLynx-Micro has the capability to encrypt or decrypt MPEG2-DVB, DSS, DV, or audio. The Authentication and Key Exchange (AKE) is also implemented in hardware. Customers requiring the DTCP version of iceLynx-Micro MUST have signed an NDA with TI and be a current DTLA licensee. Information on the DTCP implementation within the TSB43CA43A & TSB43CA42 devices are found in the following document provided by TI: Note: **Recipients MUST have signed TI NDA and be a current DTLA licensee to receive this document. ** 1.8 1.8.1 Program Memory Overview/Description
iceLynx-Micro provides 256K bytes of internal program RAM. The program memory is loaded by the external CPU interface. The external CPU cannot read the program memory. Anytime the RESET_ARMn pin is asserted (transitions from high to low), the Cipher and AKE registers are cleared. 1.8.2 External CPU ( Parallel Mode) Steps for loading Program Memory 1) ARM is placed in reset (using RESET_ARMn pin) and ex-CPU initiates write to the program memory CFR. (Sys.IntMemLoad at 0x5C) If the ARM is only put into reset, there is no change in the program memory. 2) The program must contain a 2-quadlet header. The 2-quadlet header specifies if the program is DES encrypted. See 1.9.5 for more information on DES. 3) The program is loaded into program memory through the Sys.IntMemLoad CFR. The program is placed in memory starting at address 0x 0000 0000. The ex-CPU indicates the end of program load by deasserting the RESET_ARMn signal. When the RESET_ARMn signal is deasserted, the iceLynx-Micro hardware pads the rest of program memory with zeros. 4) The ARM is executing code as soon as RESET_ARMn signal is deasserted AND all 256K bytes of program memory are loaded.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 1.9 1.9.1 External CPU Interface Overview/Description
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
The ex-CPU accesses iceLynx-Micro configuration registers and FIFOs using 32-bit addressing. The quadlet-aligned address is provided for the first 16-bit access. iceLynx-Micro internally increments the address for the second 16-bit access. All 32-bits of a register or FIFO must be read using back-to-back transactions. (An access to address N should be followed by address N+2.) A 16-bit processor can be used with iceLynx-Micro. However, the processor must access the entire quadlet address (all 32-bits) in order. For example, for a register address N, the ex-CPU must first access register address N and then address N+2. It cannot access address N+2 first. If the ex-CPU accesses the 32-bit address incorrectly, the ExCPUInt.ExCPUErr interrupt occurs. The Ex-CPU can access to iceLynx-Micro by I/O- or Memory-type methods. iceLynx-Micro supports four memory types of processor interfaces: Type-1, Type-2, I/O TYPE-1 SH3, I/O TYPE2 M16C. The Ex-CPU I/F's and access types are categorized as follows: 1. Asynchronous I/O-type Bus clock is not provided. I/O Type-0 68K + Wait I/O TYPE-1 SH3 SRAM-like + Wait I/O TYPE-2 M16C SRAM-like + Wait 2. Synchronous I/O-type Bus clock is provided. I/O TYPE-3 MPC850 3. Memory-type Access to single port RAM. Timing matches I/O type except Bus clock is provided and special Memory Chip Select signal is used. Type-1 Memory access Type-2 Memory access SH3-type Memory access M16C/62 Memory access Users can select the ex-CPU by setting the external pin MCIF_MODE[2:0]. The following table shows the pin assignments.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 External MCU Interface Method I/O Type Memory Type
Table 1. External CPU MCIF Pin Assignment Modes
MCIF_MODE[2:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
I/O Type-0: 68K+ Wait I/O Type-1: SH3 + Wait I/O Type-2: M16C + Wait I/O Type-3: MPC850 Memory Access Available
I/O Types Reserved
Memory Access Invalid
0x7 1 1 1 Note: External MCU acess type (I/O or Memory) is dependent on the chip select signal used, MCIF_CS_IOz or MCIF_CS_MEMz, respectively. With regard to the above four types of processors, , shows the relation between the signals of iceLynx-Micro and those of the ex-CPU.
Note: ARM must be in reset to load program memory.
Table 2: Ex-CPU I/F Signals
Signal Name I/O Type MCIF_CS_IOz MCIF_RW MCIF_STRBz MCIF_ACKz MCIF_WAITz MCIF_OEz MCIF_WEz MCIF_BUSCLKz Memory Type MCIF_CS_MEMz MCIF_OEz MCIF_WEz MCIF_BUSCLKz
Port Type I I I O (3S) O (3S) I I I I I I I
Type-0 (68K) CSn R_nW STRBz NA WAITz ----------
External Interface Method Type-1 Type-2 (SH3) (M16C) CSn ---------WAITz RDn WRn ---CSn ---------WAITz RDn WRn ----
Type-3 (MPC850) CSn R_nW TSn TAn ---------BUSCLKz
CSn RDn WRn BUSCLKz
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TEXAS INSTRUMENTS 1.9.2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Endian Setting (Parallel and Memory Accesses)
iceLynx-Micro registers in the CFR map are structured as (Byte 0, Byte 1, Byte 2, and Byte 3). iceLynx-Micro has an Endian pin (MCIF_ENDIAN) that controls the byte order between the exCPU interface and internal iceLynx-Micro memory (including CFRs, FIFOs, and RAM for Memory Access.) The status of the MCIF_ENDIAN pin is shown at ExCPUCfg.Endian CFR. Note: In I/O mode, the MCIF_ENDIAN pin is asserted or deasserted for individual 32-bit accesses. MCIF_A[1] MCIF_A[1] = = 0, 1, Data = ABCD Data = EF01
If MCIF_ENDIAN is set to 0, the data written to the FIFO is ABCD EF01. If MCIF_ENDIAN is set to 1, the data written to the FIFO is EF01 ABCD. 1.9.2.1 Parallel Mode and Memory Access In I/O mode, the ex-CPU has access to program memory, comm memory, and CFRs through registers. The ex-CPU only has write access to the program memory. It can only perform writes while the ARM is in reset. In memory mode, the ex-CPU directly accesses the 2 1024-byte single port RAMs. The 2 RAMS is used individually (1024 bytes each) and is randomly accessed by the ARM (32-bit) and ex-CPU (16-bit). The MCIF_ADDR signals are used to indicate where the ex-CPU is accessing. The MCIF_ADDR range to address the single port RAMs is 0x000 through 0x7FF. The ex-CPU has priority access to the RAM. The software should guarantee there are no collisions. (Use GPInts)
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TEXAS INSTRUMENTS 1.9.3 Ex-CPU Access
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Async Tx 0,1 ASYNC TX FIFO 2048 byte
CFR
Program Mem ory 256K bytes Async Rx 0,1 ASYNC RX FIFO 2048 byte CFR
Com m W rite Base Addr Ex-CPU W rite Area ARM Ex-CPU Read Area Comm Read Base Addr
1024 byte RAM 1024 byte RAM CFR I/O Type Access
Ex-CPU
Memory Access
Figure 9: Ex-CPU Access
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
The communication area is part of the 256K-byte memory. This area is used for data communication between Ex-CPU and ARM. CFR CommWrBase and CommRdBase define the top address of the area. The communication area consists of an Ex-CPU write area and Ex-CPU read area.
W rite
Ex-CPU W rite Area
Read
Host
ARM
Read
Ex-CPU Read Area
W rite
On the chip reset, "CommWrBase" and "CommRdBase" is 0x 0000 FFFF. When set to this default value, the ex-CPU is not allowed to access the communication memory. The ARM manages the communication area between the ex-CPU and ARM. General interrupts share the access time for the areas. The ARM has full random access of the communication memory area. The parallel ex-CPU can access the communication memory through the "CommData" CFR . The ARM can know how much data was read or written into the communication area by reading the Sys.CommStat.RdCnt and Sys.CommStat.WrCnt bits in CFR. The ARM can also reset the internal address counters using Sys.CommStat.RdCnt and Sys.CommStat.WrCnt bits in CFR. Note: Only the ARM can set the Comm (Read/Write) Base Addresses. 1.9.3.1 Ex-CPU and ARM Communication Sequence in Parallel Ex-CPU I/F Mode Note: The Ex-CPU and ARM use GPInts (General Purpose Interrupts) for communication. Any reference to "interrupt" in the following sections refers to the GPInts. GPInts are available in the Sys.InCPUCommInt and Sys.ExCPUCommInt CFRs. 1.9.3.1.1 Ex-CPU Read ARM sends an interrupt to Ex-CPU as "READ ENABLE". Ex-CPU sends an interrupt to ARM as "READ REQUEST". ARM invokes a timer to watch access timeout and can't access read Communication Area memory Ex-CPU access end. Ex-CPU reads data from Communication Area. Ex-CPU sends an interrupt to ARM as "READ ACCESS END". ARM stops the timer. ARM sends an interrupt to Ex-CPU as "READ DISABLE" Sys.* CPUInt.GPInt bits and the associated Sys.*CPUCommInt CFRs are used for this communication.
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Rev. 1.7
1.9.3.1.2 Ex-CPU Write ARM sends an interrupt to Ex-CPU as "WRITE ENABLE". Ex-CPU sends an interrupt to ARM as "WRITE REQUEST". ARM invokes a timer to watch access timeout and can't access write Communication memory until Ex-CPU access end. Ex-CPU writes data into Communication Area. Ex-CPU sends an interrupt to ARM as "WRITE ACCESS END". ARM stops the timer. ARM sends an interrupt to Ex-CPU as "WRITE DISABLE". Sys.*CPUInt.GPInt bits and the associated Sys.*CPUCommInt CFRs are used for this communication. 1.9.3.1.3 Ex-CPU Access Limitation Table 3 EX-CPU access limitation
Addr 018h 018h 018h 048h 04Ch 05Ch Bit 16 8 N/A 15:0 15:0 31:0 Bit Name InCPUCfg.DbgRegUnlock InCPUCfg.DebugEn RSVD CommWrBase.Addr CommRdBase.Addr IntMemLoad.IntMemLoad Read Access Yes Yes N/A No No Conditional Write Access Yes No N/A No No Conditional Condition
Write access only while ARM_RESET= LOW in normal operation mode: IntMemDiag.ProtectDis=0. Read and write access in diagnostic mode: IntMemDiag.ProtectDis = 1
060h 060h 03Ch 024h 028h, 02Ch 1FA -1FCh, 324 - 32Ch 200 - 204h, 330 - 334h 208 - 20Ch, 338 - 33Ch 630 - 774h
25 24 31:0 31:0 31:0 N/A N/A N/A N/A
IntMemDiag.EncryptDis IntMemDiag.ProtectDis InCPUComIntEn.* InCPUInt.* InCPUIntEn.* RSVD RSVD RSVD RSVD
Yes Yes Yes Yes Yes N/A N/A N/A N/A
No No No No No N/A N/A N/A N/A
Note: The BLUE coded CFRs are reserved (RSVD).
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TEXAS INSTRUMENTS 1.9.4 Ex-CPU Timing
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.9.4.1 I/O Type-0 68K + Wait WAIT signal should be added. The Ex-CPU should freeze the bus transaction while WAIT is active. (Asynchronous).
I MCIF_MODE Tsu4 I MCIF_ENDIAN Tsu3 I MCIF_CS_MEMz Tw1 I MCIF_CS_IOz Tw2 Th5 I MCIF_STRBz Tsu2 I MCIF_R_nWz Tsu1 I MCIF_ADDR[10:1] ADDR N or N+2
#
0x0 Th4 Th3
Th5
Th2 Th1 Tsu1 ADDR N or N+2 Tv2 Tdis2 Ten2 Th1
#
Tsu2
Th2
Tdis2 Tv1 Ten2 DATA n+2 Tdis1 Td2|| Tv2
IO
MCIF_DATA[15:0] Ten1 Td1||
Tv1 DATA n
O
MCIF_ACKz Td3 Ten1 Td3 Tdis1
O
MCIF_WAITz
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The MCIF_WAITz defaults to the active high polarity in the MCIF I/O Type-0 68K mode. B. MCIF_OEz, MCIF_WEz and MCIF_BUSCLKz are "Don't Care" for the MCIF I/O Type-0 68K mode. C. Single 16-bit read accesses will not result in an error or an interrupt. D. For a read access to occur both MCIF_CS_IOz and MCIF_STRBz must be asserted. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. The MCIF_STRBz is not required to deassert between accesses. MCIF_R_nWz may change between accesses. # CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. || The MCIF_ACKz / MCIF_WAITz assert delays Td1 and Td2 are measured from the MCIF_CS_IOz or MCIF_STRBz assert, whichever occurs last in the access.
Figure 10: I/O Type-0 68K + Wait Read
The MCIF_WAITz signal timing is relative to MCIF_CSn.
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Th1 Th2 Th3 Th4 Th5 Td1 Td2 Td3 Tv1 Tv2 Ten1 Ten2 Tdis1 Tdis2 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 0 0 0 0 0 0 0 0 260 260 15 0 0 15 15 15 15 25 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 4: I/O Type-0 68K + Wait Read MCIF AC Timing Parameters Description Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, MCIF_R_nWz before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after MCIF_ACKz asserted Hold time, MCIF_R_nWz after MCIF_ACKz asserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Hold time, MCIF_CS_IOz or MCIF_STRBz after MCIF_ACKz asserted / MCIF_WAITz deasserted Delay time, Read Access, MCIF_ACKz asserted / MCIF_WAITz deasserted after MCIF_STRBz asserted Delay time, Read Access, MCIF_ACKz asserted / MCIF_WAITz deasserted after MCIF_CS_IOz asserted Delay time, MCIF_WAITz asserted after MCIF_CS_IOz asserted Valid time, MCIF_DATA before MCIF_ACKz asserted / MCIF_WAITz deasserted Valid time, MCIF_DATA after MCIF_CS_IOz or MCIF_STRBz deasserted Enable time, MCIF_CS_IOz asserted to MCIF_ACKz / MCIF_WAITz driven Enable time, MCIF_CS_IOz and MCIF_STRBz asserted to MCIF_DATA driven Disable time, MCIF_ACKz / MCIF_WAITz high impedance from MCIF_CS_IOz deasserted Disable time, MCIF_DATA high impedance from MCIF_CS_IOz or MCIF_STRBz deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, MCIF_STRBz deasserted to MCIF_STRBz asserted
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I MCIF_MODE Tsu5 I MCIF_ENDIAN Tsu4 I MCIF_CS_MEMz
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
0x0 Th4
Th5
Tw1 I MCIF_CS_IOz Tw2 Th6 I MCIF_STRBz Tsu2 I MCIF_R_nWz Tsu1 I MCIF_ADDR[10:1] ADDR N or N+2 Tsu3 IO MCIF_DATA[15:0] Ten1 O MCIF_ACKz Td3 O MCIF_WAITz Tdis1 Td3 Ten1 DATA n Td1
|| #
Th6
Th2 Th1 Tsu1 ADDR N or N+2 Th3
#
Tsu2
Th2
Th1
Tsu3 DATA n+2 Tdis1 Td2
||
Th3
Tdis1
Tdis1
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The MCIF_WAITz defaults to the active high polarity in the MCIF I/O Type-0 68K mode. B. MCIF_OEz, MCIF_WEz and MCIF_BUSCLK are "Don't Care" for the MCIF I/O Type-0 68K mode. C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set. D. For a write access to occur both MCIF_CS_IOz and MCIF_STRBz must be asserted. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet write cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. MCIF_STRBz is not required to deassert between accesses. MCIF_R_nWz may change between accesses. # CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. || The MCIF_ACKz / MCIF_WAITz assert delays Td1 and Td2 are measured from the MCIF_CS_IOz or MCIF_STRBz assert, whichever occurs last in the access.
Figure 11: I/O Type-0 68K + Wait Write
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Th1 Th2 Th3 Th4 Th5 Th6 Td1 Td2 Td3 Ten1 Tdis1 Tw1 Tw2 Tsu1
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 0 -40 0 0 0 0 0 0 0 0 140 100 15 15 15 25 0 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 5: I/O Type-0 68K + Wait Write MCIF AC Timing Parameters Description Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, MCIF_R_nWz before MCIF_CS_IOz asserted Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after MCIF_CS_IOz asserted Hold time, MCIF_R_nWz after MCIF_CS_IOz asserted Hold time, MCIF_DATA valid after MCIF_ACKz asserted / MCIF_WAITz deasserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Hold time, MCIF_CS_IOz or MCIF_STRBz after MCIF_ACKz asserted / MCIF_WAITz deasserted Delay time, 1st Write Access, MCIF_ACKz asserted / MCIF_WAITz deasserted after MCIF_CS_IOz / MCIF_STRBz asserted Delay time, 2nd Write Access, MCIF_ACKz asserted / MCIF_WAITz deasserted after MCIF_CS_IOz / MCIF_STRBz asserted Delay time, MCIF_WAITz asserted after MCIF_CS_IOz asserted Enable time, MCIF_CS_IOz asserted to MCIF_ACKz / MCIF_WAITz driven Disable time, MCIF_ACKz / MCIF_WAITz high impedance from MCIF_CS_IOz deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, MCIF_STRBz deasserted to MCIF_STRBz asserted Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted
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TEXAS INSTRUMENTS 1.9.4.2
I
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
I/O TYPE-1 SH3 SRAM-like + WAIT
0x1 Tsu5 Th5 Tsu4 Th4
MCIF_MODE
I
MCIF_ENDIAN
I
MCIF_CS_MEMz Tw1 Th2
I
MCIF_CS_IOz Tw2 Tsu2 Th2 Tsu3 Th3 Tsu2
I
RDn (MCIF_OEz)
I
WRn (MCIF_WEz) Tsu1 Th1 ADDR N or N+2 Ten2
I
MCIF_ADDR[10:1]
Tsu1 ADDR N or N+2 Tv2 # Tdis2
Th1
Tdis2 Ten2 DATA n+2 Tdis1 Td1 Ten1 Tdis1 Tv2 #
IO
MCIF_DATA[15:0] Td1 Ten1
Tv1 DATA n
O (RDY) MCIF_WAITz
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz) defaults to the active low polarity in the MCIF I/O Type-1 SH3 mode. B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz output is not used in the MCIF I/O Type-1 SH3 mode. C. Single 16-bit read accesses will not result in an error or an interrupt. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. For a read access to occur, both MCIF_CS_IOz and RDn (MCIF_OEz) must be asserted. The RDn (MCIF_OEz) is not required to deassert between accesses. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. # Valid time Tv2 is from RDn (MCIF_OEz) or MCIF_CS_IOz, whichever deasserts first in the access.
Figure 12: I/O TYPE-1 SH3 Read
This type supports SH3(HD6417709A) Bus State controller specification. The below figure shows the signal on MCIF_WAITz and critical timing.
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Th1 Th2 Th3 Th4 Th5 Td1 Tv1 Tv2 Ten1 Ten2 Tdis1 Tdis2 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 -40 0 0 0 0 0 0 0 0 260 0 0 15 15 15 15 25 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 6: I/O TYPE-1 SH3 Critical Timing (Read) Description Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, RDn (MCIF_OEz) asserted before MCIF_CS_IOz asserted Setup time, WRn (MCIF_WEz) deasserted before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted Hold time, RDn (MCIF_OEz) or MCIF_CS_IOz asserted after RDY (MCIF_WAITz) asserted Hold time, WRn (MCIF_WEz) deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Delay time, Read Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Valid time, MCIF_DATA before RDY (MCIF_WAITz) asserted Valid time, MCIF_DATA after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven Enable time, MCIF_CS_IOz and RDn (MCIF_OEz) asserted to MCIF_DATA driven Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz deasserted Disable time, MCIF_DATA high impedance after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted
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TEXAS INSTRUMENTS
I MCIF_MODE Tsu6 I MCIF_ENDIAN Tsu5 I MCIF_CS_MEMz
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
0x1 Th5
Th6
Tw1 I MCIF_CS_IOz Tsu4 I RDn (MCIF_OEz) Th2 Tsu2 I WRn (MCIF_WEz) Tsu1 I MCIF_ADDR[10:1] ADDR N or N+2 Tsu3 IO MCIF_DATA[15:0] Ten1 O RDY (MCIF_WAITz) DATA n Td1 Tdis1
Th2
Th4
Tsu2 Tw2
Th1
Tsu1 ADDR N or N+2
Th1
Th3
Tsu3 DATA n+2 Td2 Ten1
Th3
Tdis1
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz) defaults to the active low polarity in the MCIF I/O Type-1 SH3 mode. B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz output is not used in the MCIF I/O Type-1 SH3 mode. C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. For a write access to occur, both MCIF_CS_IOz and MCIF_WEz must be asserted. The WRn (MCIF_WEz) is not required to deassert between accesses. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
Figure 13: I/O TYPE-1 SH3 Write
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Th1 Th2 Th3 Th4 Th5 Th6 Td1 Td2 Ten1 Tdis1 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 -40 -40 0 0 0 0 0 0 0 0 0 120 120 15 15 25 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 7: I/O TYPE-1 SH3 AC Timing (Write) Description Setup Time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, WRn (MCIF_WEz) asserted before MCIF_CS_IOz asserted Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted Setup time, RDn (MCIF_OEz) deasserted before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted Hold time, WRn (MCIF_WEz) or MCIF_CS_IOz asserted after RDY (MCIF_WAITz) asserted Hold time, MCIF_DATA valid after RDY (MCIF_WAITz) asserted Hold time, RDn (MCIF_OEz) deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Delay time, 1st Write Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Delay time, 2nd Write Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.9.4.3 I/O TYPE-2 M16C SRAM-like + WAIT This type supports the M16C/62 interface timing. The following figure shows the signal timing.
I MCIF_MODE Tsu5 I MCIF_ENDIAN Tsu4 I MCIF_CS_MEMz Tw1 I MCIF_CS_IOz Tw2 Tsu2 I RDn (MCIF_OEz) Tsu3 I WRn (MCIF_WEz) Tsu1 I MCIF_ADDR[10:1] ADDR N or N+2 Ten2 IO MCIF_DATA[15:0] Td1 Ten1 O (RDY) MCIF_WAITz
0x2 Th5 Th4
Th2
Th2
Tsu2
Th3
Th1
Tsu1 ADDR N or N+2
Th1
Tv1 DATA n
Tdis2 Tv2 #
Ten2 Tv1 DATA n+2 Td1 Tdis1 Ten1
Tdis2 Tv2 #
Tdis1
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz) defaults to the active low polarity in the MCIF I/O Type-2 M16C mode. B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLKz inputs are "Don't Care" and the MCIF_ACKz output is not used in the MCIF I/O Type-2 M16C mode. C. Single 16-bit read accesses will not result in an error or an interrupt. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. For a read access to occur, both MCIF_CS_IOz and RDz (MCIF_OEz) must be asserted. The RDn (MCIF_OEz) is not required to deassert between accesses. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. # Valid time Tv2 is from RDn (MCIF_OEz) or MCIF_CS_IOz, whichever deasserts first in the access.
Figure 14: I/O TYPE-2 M16C SRAM-like + WAIT Read
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Th1 Th2 Th3 Th4 Th5 Td1 Tv1 Tv2 Ten1 Ten2 Tdis1 Tdis2 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 -40 0 0 0 0 0 0 0 0 210 30 0 15 15 15 15 25 0 340 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 8: I/O TYPE-2 M16C SRAM-like + WAIT AC Timing Parameters (Read) Description Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, RDn (MCIF_OEz) asserted before MCIF_CS_IOz asserted Setup time, WRn (MCIF_WEz) deasserted before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted Hold time, RDn (MCIF_OEz) or MCIF_CS_IOz asserted after RDY (MCIF_WAITz) asserted Hold time, WRn (MCIF_WEz) deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Delay time, Read Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Valid time, MCIF_DATA before RDY (MCIF_WAITz) asserted Valid time, MCIF_DATA after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven Enable time, MCIF_CS_IOz and RDn (MCIF_OEz) asserted to MCIF_DATA driven Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz deasserted Disable time, MCIF_DATA high impedance after MCIF_CS_IOz or RDn (MCIF_OEz) deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted
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I MCIF_MODE Tsu6 I MCIF_ENDIAN Tsu5 I MCIF_CS_MEMz
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
0x2 Th5
Th6
Tw1 I MCIF_CS_IOz Tsu4 I RDn (MCIF_OEz) Th2 Tsu2 I WRn (MCIF_WEz) Tsu1 I MCIF_ADDR[10:1] ADDR N or N+2 Tsu3 IO MCIF_DATA[15:0] DATA n Td1 Ten1 O RDY (MCIF_WAITz) Tdis1 Ten1
Th2
Th4
Tw2 Th1
Tsu2
Tsu1 ADDR N or N+2
Th1
Th3
Tsu3 DATA n+2 Td2
Th3
Tdis1
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. The RDY (MCIF_WAITz) defaults to the active low polarity in the MCIF I/O Type-2 M16C mode. B. The MCIF_STRBz, MCIF_R_nWz and MCIF_BUSCLK inputs are "Don't Care" and the MCIF_ACKz output is not used in the MCIF I/O Type-2 M16C mode. C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. For a write access to occur, both MCIF_CS_IOz and WRn (MCIF_WEz) must be asserted. The WRn (MCIF_WEz) is not required to deassert between accesses. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode.
Figure 15: I/O TYPE-2 M16C SRAM-like + WAIT Write
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Th1 Th2 Th3 Th4 Th5 Th6 Td1 Td2 Ten1 Tdis1 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 0 -40 -40 0 0 0 0 0 0 0 0 0 80 80 340 340 15 15 25 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 9: I/O TYPE-2 M16C SRAM-like + WAIT AC Timing Parameters (Write) Description Setup time, MCIF_ADDR valid before MCIF_CS_IOz asserted Setup time, WRn (MCIF_WEz) asserted before MCIF_CS_IOz asserted Setup time, MCIF_DATA valid before MCIF_CS_IOz asserted Setup time, RDn (MCIF_OEz) deasserted before MCIF_CS_IOz asserted Setup time, MCIF_CS_MEMz deasserted before MCIF_CS_IOz asserted Setup time, MCIF_ENDIAN before MCIF_CS_IOz asserted Hold time, MCIF_ADDR valid after RDY (MCIF_WAITz) asserted Hold time, WRn (MCIF_WEz) or MCIF_CS_IOz asserted after RDY (MCIF_WAITz) asserted Hold time, MCIF_DATA valid after RDY (MCIF_WAITz) asserted Hold time, RDn (MCIF_OEz) deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_CS_MEMz deasserted after MCIF_CS_IOz deasserted Hold time, MCIF_ENDIAN after MCIF_CS_IOz deasserted Delay time, 1st Write Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Delay time, 2nd Write Access, RDY (MCIF_WAITz) asserted after MCIF_CS_IOz asserted Enable time, MCIF_CS_IOz asserted to RDY (MCIF_WAITz) driven Disable time, RDY (MCIF_WAITz) high impedance after MCIF_CS_IOz deasserted Access width, MCIF_CS_IOz deasserted to MCIF_CS_IOz asserted Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
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1.9.4.4 I/O TYPE-3 MPC850 Supports Motorola MPC850 external bus
Td1 R_nW = Read TSn Detect N CSn Detect Tc I I MCIF_BUSCLK MCIF_MODE Tsu6 I MCIF_ENDIAN Tsu5 I MCIF_CS_MEMz Th4 Tsu4 I MCIF_CS_IOz Th1 Tsu1 ADDR N or N+2 Th2 Tsu2 I MCIF_R_nWz Th3 Tsu3 I TSn (MCIF_STRBz) # Tv1 Ten2 IO MCIF_DATA[15:0] DATA n Tv4 Tv3 Tv2 DATA n+2 Tdis1 Ten1 O TAn (MCIF_ACKz) Tv4 Tv3 Tv1 Tdis2 Tsu3 Tv2 # Th3 Tsu2 Th1 Tsu1 ADDR N or N+2 Th2
Td1 Read Data n TAn N Asserted TSn Detect N+2 Tc Tc Read Data n+2 TAn Assert N+2 CSn_Detect Tc Tc
Tc
Tc
Tc
0x3 Th6 Th5
Tsu4
I
MCIF_ADDR[10:1]
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. B. MCIF_OEz, MCIF_WEz and MCIF_WAITz are "Don't Care" for the MCIF I/O Type-3 MPC850 mode. C. Single 16-bit read accesses will not result in an error or an interrupt. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. MCIF_CS_IOz may deassert after TAn (MCIF_ACKz) is detected as long as Th5 is met. In synchronous designs it may be better to allow at least one clock period delay between TAn (MCIF_ACKz) detect and the next MCIF_CS_IOz access cycle. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. # MCIF_R_nWz and TSn (MCIF_STRBz) may remain valid / asserted or become invalid /deasserted during the access.
Figure 16: I/O TYPE-3 MPC850 Read
The following figures and tables show AC timing and access timing.
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TEXAS INSTRUMENTS Symbol Tc Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Th1 Th2 Th3 Th4 Th5 Th6 Td1 Tv1 Tv2 Tv3 Tv4 Ten1 Ten2 Tdis1 Tdis2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 24 2 16 15 4 4 4 14 2 2 14 0 0 150 10 2 11 0 15 15 15 15 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 10: I/O TYPE-3 MPC850 Read AC Timing Parameters Description Cycle time, MCIF_BUSCLKz Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge [TSn (MCIF_STRBz) assert cycle] Setup time, MCIF_R_nWz before MCIF_BUSCLKz rising edge [TSn (MCIF_STRBz) assert cycle] Setup time, TSn (MCIF_STRBz) asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_CS_IOz asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_CS_MEMz deasserted before MCIF_BUSCLKz rising edge (MCIF_CS_IOz assert cycle) Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (MCIF_CS_IOz assert cycle) Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz) assert cycle] Hold time, MCIF_R_nWz after MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz) assert cycle] Hold time, TSn (MCIF_STRBz) asserted after MCIF_BUSCLKz rising edge Hold time, MCIF_CS_IOz asserted after MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz) assert cycle] Hold time, MCIF_CS_MEMz deasserted after MCIF_BUSCLKz rising edge [MCIF_CS_IOz deassert cycle] Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge [MCIF_CS_IOz deassert cycle] Delay time, Read Access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz) assert cycle Valid time, MCIF_DATA before MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz) asserted cycle] Valid time, MCIF_DATA after MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz) asserted cycle] Valid time, TAn (MCIF_ACKz) asserted before MCIF_BUSCLKz rising edge Valid time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge Enable time, MCIF_CS_IOz asserted to TAn (MCIF_ACKz) driven Enable time, MCIF_BUSCLKz rising edge to MCIF_DATA driven [TSn (MCIF_ACKz) assert cycle] Disable time, TAn (MCIF_ACKz) high impedance after MCIF_CS_IOz deasserted Disable time, MCIF_DATA high impedance after MCIF_CS_IOz deasserted
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Td1 R_nW = Write Write Data n TSn Detect N CSn Detect Tc I I MCIF_BUSCLK MCIF_MODE Tsu7 I MCIF_ENDIAN Tsu6 I MCIF_CS_MEMz Tc
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Td1 R_nW_=_Write Write Data n + 2 TSn Detect N+2 Tc TAn Assert N Tc Tc Tc
TAn Assert N+2 CSn_Detect Tc Tc
0x3 Th7 Th6
Th4 Tsu4 I MCIF_CS_IOz Th1 Tsu1 I MCIF_ADDR[10:1] Tsu2 I MCIF_R_nWz Th3 Tsu3 I TSn (MCIF_STRBz) Th5 IO MCIF_DATA[15:0] Tsu5 DATA n Tsu5 DATA n+2 # Th5 Tsu3 # Th3 ADDR N or N+2 Th2 Tsu2
Tsu4
Th1 Tsu1 ADDR N or N+2 Th2
Tdis1 Ten1 O TAn (MCIF_ACKz) Tv2 Tv1 Tv2 Tv1
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. B. MCIF_OEz, MCIF_WEz and MCIF_WAITz are "Don't Care" for the MCIF I/O Type-3 MPC850 mode. C. Single 16-bit write accesses are not allowed, resulting in the ExCPUErr interrupt bit being set. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during a quadlet access cycle. MCIF_ENDIAN may change during device operation. It should not change during a quadlet access or data corruption may result. MCIF_CS_IOz may deassert after TAn (MCIF_ACKz) is detected as long as Th5 is met. In synchronous designs it may be better to allow at least one clock period delay between TAn (MCIF_ACKz) detect and the next MCIF_CS_IOz access cycle. CFR accesses must be quadlet aligned. The MCIF_ADDR[1] bit is immaterial and the MCIF_ADDR may be of value "N" or "N+2" when considered as a byte address ( ADDR[10:0] ). MCIF_ADDR[0] is internally grounded. MCIF_ADDR[1] is used in the Memory MCIF mode. # MCIF_R_nWz and TSn (MCIF_STRBz) may remain valid / asserted or become invalid /deasserted during the access.
Figure 17: I/O TYPE-3 MPC850 Write
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Table 11: I/O TYPE-3 MPC850 Write AC Timing Parameters Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Tsu7 Th1 Th2 Th3 Th4 Th5 Th6 Th7 Td1 Tv1 Tv2 Ten1 Tdis1 Description Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge [TSn (MCIF_STRBz) assert cycle] Setup time, MCIF_R_nWz before MCIF_BUSCLKz rising edge [TSn (MCIF_STRBz) assert cycle] Setup time, TSn (MCIF_STRBz) asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_CS_IOz asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_DATA valid before MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz) assert cycle] Setup time, MCIF_CS_MEMz deasserted before MCIF_BUSCLKz rising edge (MCIF_CS_IOz assert cycle) Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (MCIF_CS_IOz assert cycle) Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz) assert cycle] Hold time, TSn (MCIF_STRBz) asserted after MCIF_BUSCLKz rising edge Hold time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge Hold time, MCIF_CS_IOz asserted after MCIF_BUSCLKz rising edge [TAn (MCIF_ACKz) assert cycle] Hold time, MCIF_DATA valid after MCIF_BUSCLKz rising edge [TSn (MCIF_ACKz) assert cycle] Hold time, MCIF_CS_MEMz deasserted after MCIF_BUSCLKz rising edge [MCIF_CS_IOz deassert cycle] Delay time, Read Access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz) assert cycle Delay time, Read Access, TSn (MCIF_STRBz) assert cycle to TAn (MCIF_ACKz) assert cycle Valid time, TAn (MCIF_ACKz) asserted before MCIF_BUSCLKz rising edge Valid time, TAn (MCIF_ACKz) asserted after MCIF_BUSCLKz rising edge Enable time, MCIF_BUSCLKz risign edge to TAn (MCIF_ACKz) driven (MCIF_CS_IOz assert cycle) Disable time, TAn (MCIF_ACKz) high impedance after MCIF_BUSCLKz rising edge (MCIF_CS_IOz deassert cycle) Min 2 16 15 4 16 4 4 14 2 0 14 2 0 0 130 11 2 15 15 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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1.9.4.5 Memory Type All ex-CPU modes (Type-0 (68K) and Type-2 (M16C/62)) use the same timing for memory type access. The ex-CPU provides the bus clock, MCIF_BUSCLKz, in all modes.
I
MCIF_MODE Tc Tc
0x0 - 0x3 Tc Tc Tc
I
MCIF_BUSCLK Tsu6 Th6 Tsu5 Th5
I
MCIF_ENDIAN
I
MCIF_CS_IOz Tw1 Tsu3 Th3 Tw2 Tsu2 Th2 Tsu4 Th4 Tsu2 Th2 Tsu3 Th3
I
MCIF_CS_MEMz
I
RDn (MCIF_OEz)
I
WRn (MCIF_WEz) Th1 Tsu1 ADDR N Tv1 Ten1 Tdis1 Tv2 # Th1 Tsu1 ADDR M+1
I
MCIF_ADDR[10:1]
ADDR M
Tv1 Tv3 Ten1 DATA m
Tdis1 Tv3 Tv1 DATA m+1 Tv2
IO MCIF_DATA[15:0]
DATA n
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. B. The MCIF_STRBz and MCIF_R_nWz inputs are "Don't Care". The MCIF_ACKz and MCIF_WAITz outputs are not used in the MCIF Memory Access mode. C. Single 16-bit read accesses will not result in an error or an interrupt. D. MCIF Memory Mode read access latency is two clock cycles. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during an MCIF Memory Access cycle. Memory accesses may only occur if MCIF_MODE is valid (0x0 through 0x3). MCIF_ENDIAN may change during device operation. It should not change during an access or data corruption may result. For a read access to occur, both MCIF_CS_MEMz and RDn (MCIF_OEz) must be asserted. The MCIF_CS_MEMz and RDn (MCIF_OEz) are not required to deassert between accesses. Memory accesses are not required to be quadlet aligned. The MCIF_ADDR[1] bit is used along with the MCIF_ENDIAN to determine which 16-bit word is read. Addressing should be considered as byte addressing ( ADDR[10:0] ) with MCIF_ADDR[0] internally grounded. # Valid time Tv2 is from MCIF_CS_MEMz or RDn (MCIF_OEz), whichever deasserts first in the access.
Figure 18: Memory Type
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TEXAS INSTRUMENTS Symbol Tc Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Th1 Th2 Th3 Th4 Th5 Th6 Tv1 Tv2 Tv3 Ten1 Tdis1 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 8.33 8 8 8 8 8 8 0 0 0 0 0 0 8 8 2 15 15 0 0 Max Units 142.86 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 12: Memory Type Read AC Timing Parameters Description Cycle time, MCIF_BUSCLKz [Assume 20pF loading] Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Setup time, RDn (MCIF_OEz) asserted before MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Setup time, MCIF_CS_MEMz asserted before MCIF_BUSCLKz rising edge Setup time, WRn (MCIF_WEz) deasserted before MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Setup time, MCIF_CS_IOz deasserted before MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge (MCIF_CS_MEMz assert cycle) Hold time, RDn (MCIF_OEz) asserted after MCIF_BUSCLKz rising edge (data read cycle) Hold time, MCIF_CS_MEMz asserted after MCIF_BUSCLKz rising edge (data read cycle) Hold time, WRn (MCIF_WEz) deasserted after MCIF_BUSCLKz rising edge (data read cycle) Hold time, MCIF_CS_IOz deasserted after MCIF_BUSCLKz rising edge (data read cycle) Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge (data read cycle) Valid time, MCIF_DATA before MCIF_BUSCLKz rising edge (data read cycle) Valid time, MCIF_DATA after MCIF_CS_MEMz or RDn (MCIF_OEz) deasserted Valid time, MCIF_DATA after MCIF_BUSCLKz rising edge (data read cycle) Enable time, MCIF_CS_MEMz and RDn (MCIF_OEz) asserted to MCIF_DATA driven Disable time, MCIF_DATA high impedance after MCIF_CS_MEMz deasserted Access width, MCIF_CS_MEMz deasserted to MCIF_CS_MEMz asserted Access width, RDn (MCIF_OEz) deasserted to RDn (MCIF_OEz) asserted ** Note: Measurements based on a 20 pF loading.
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I MCIF_MODE Tc I MCIF_BUSCLK Tsu7 I MCIF_ENDIAN Tsu6 I MCIF_CS_IOz Tw1 Tsu5 Th5 I MCIF_CS_MEMz Tsu4 I RDn (MCIF_OEz) Tsu2 Th2 I WRn (MCIF_WEz) Th1 Tsu1 I MCIF_ADDR[10:1] ADDR N Tsu3 DATA n
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
0x0 - 0x3 Tc Tc
Th7 Th6
Tsu5 Th4
Th5
Tsu2 Tw2 Th1 Tsu1 ADDR M Th3
Th2
Th1 Tsu1 ADDR M+1
ADDR P
Th3 Tsu3 DATA m
IO MCIF_DATA[15:0]
Th3 Tsu3 DATA m+1
DATA p
NOTES: A. The timing diagram assumes MCIF signals used their default polarities. B. The MCIF_STRBz and MCIF_R_nWz inputs are "Don't Care". The MCIF_ACKz and MCIF_WAITz outputs are not used in the MCIF Memory Access mode. C. Single 16-bit write accesses are allowed and will not result in an error or an interrupt. D. MCIF Memory Mode write access latency is zero clock cycles. MCIF_MODE may be changed during device operation but is not recommended. MCIF_MODE should not change during an MCIF Memory Access cycle. Memory accesses may only occur if MCIF_MODE is valid (0x0 through 0x3). MCIF_ENDIAN may change during device operation. It should not change during an access or data corruption may result. For a write access to occur, both MCIF_CS_MEMz and WRn (MCIF_WEz) must be asserted. The MCIF_CS_MEMz and WRn (MCIF_WEz) are not required to deassert between accesses. Memory accesses are not required to be quadlet aligned. The MCIF_ADDR[1] bit is used along with the MCIF_ENDIAN to determine which 16-bit word is written. Addressing should be considered as byte addressing ( ADDR[10:0] ) with MCIF_ADDR[0] internally grounded.
Figure 19: Memory Write
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TEXAS INSTRUMENTS Symbol Tsu1 Tsu2 Tsu3 Tsu4 Tsu5 Tsu6 Tsu7 Th1 Th2 Th3 Th4 Th5 Th6 Th7 Tw1 Tw2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Min 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 13: Memory Type Write AC Timing Parameters Description Setup time, MCIF_ADDR valid before MCIF_BUSCLKz rising edge Setup time, WRn (MCIF_WEz) asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_DATA valid before MCIF_BUSCLKz rising edge Setup time, RDn (MCIF_OEz) deasserted before MCIF_BUSCLKz rising edge (data write cycle) Setup time, MCIF_CS_MEMz asserted before MCIF_BUSCLKz rising edge Setup time, MCIF_CS_IOz deasserted before MCIF_BUSCLKz rising edge (data write cycle) Setup time, MCIF_ENDIAN before MCIF_BUSCLKz rising edge (data write cycle) Hold time, MCIF_ADDR valid after MCIF_BUSCLKz rising edge Hold time, WRn (MCIF_WEz) asserted after MCIF_BUSCLKz rising edge Hold time, MCIF_DATA valid after MCIF_BUSCLKz rising edge Hold time, RDn (MCIF_OEz) deasserted after MCIF_BUSCLKz rising edge (data write cycle) Hold time, MCIF_CS_MEMz asserted after MCIF_BUSCLKz rising edge (data write cycle) Hold time, MCIF_CS_IOz deasserted after MCIF_BUSCLKz rising edge (data write cycle) Hold time, MCIF_ENDIAN after MCIF_BUSCLKz rising edge (data write cycle) Access width, MCIF_CS_MEMz deasserted to MCIF_CS_MEMz asserted Access width, WRn (MCIF_WEz) deasserted to WRn (MCIF_WEz) asserted ** Note: Measurements based on a 20 pF loading.
1.9.5
DES Encryption
The external CPU interface contains an option for encryption. The purpose of the encryption is to protect DTLA key transfer over the external CPU interface. Parallel external CPU mode use this method. 1) The external CPU starts program load to iceLynx-Micro. The code is loaded starting at address 0 hex. The first two quadlets have encryption information. The other quadlets are the encrypted download program (up to 256K bytes). The program code must always contain these two header quadlets, even if the data is not encrypted. The "C" bits indicate if data should be decrypted. The first two quadlets have the following format:
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TEXAS INSTRUMENTS 31 29 28 24 C Key No Key Seed 23 Key Seed
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 0
Table 14: Ex-CPU Encryption First Quadlet
2) iceLynx-Micro uses the values in the first quadlet to determine how to decrypt the data. Table 15: Ex-CPU Encryption Reference Field Description Purpose Indicates encryption mode. Values from 000 to 111 are valid. If value is 111, the hardware stops DES decryption. The program is loaded to program memory without being decrypted. If value is any other than 111, the hardware performs DES decryption on the data loaded into program memory. Used to indicate which 56 bit key iceLynx-Micro uses for DES decryption. The keys are available in a Device Key ROM table. There are 32 separate 56-bit entries. Each key corresponds to a specific Key No. Key No Key Number** Key No Single DES
C
Three bit encryption indicator
0 AAAA AAAA AAAA AA 1 BBBB BBBB BBBB BB 2... CCCC CCCC CCCC CC 31 6666 6666 6666 66 This 56-bit number is used as an input to the Key Seed Seed value provided by ex CPU Single DES decryption hardware. Note**: Contact TI for actual key numbers and key data. 3) DES Decryption Hardware An XOR operation is performed on the Key Seed provided by the ex-CPU and the Device Key (selected from Device Key ROM table by Key No). If the C values are any value except "111," the hardware decrypts the program code. 1.10 The maximum throughput for the program load using DES is 20Mbytes per second. 1.10 Integrated CPU 1.10.1 Description/Overview iceLynx-Micro has an integrated ARM7TDMI processor. The operating frequency is 50MHz. The processor is intended to handle all 1394 transactions as well as DTCP related software. It operates in 16-bit mode in addition to 32-bit mode.
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Rev. 1.7
Access to CFRs requires three (3) clock cycles for reads and writes. All other internal memory locations are accessed in a single cycle. 1.10.2 Interaction with External CPU Only one CPU (internal or external) can access memory locations at one time. This includes configuration registers and FIFOs. The integrated CPU has access to program memory and communication memory in byte mode, 16-bit mode, or 32-bit mode. The external CPU has priority over the internal CPU. While the ex-CPU performs a memory access (2x1024 byte RAMs), the ARM can use the internal bus freely. 1.10.3 External Interrupts The GPIO pins is configured as IRQ and/or FIQ interrupts used to signal interrupts for the ARM. GPIO pins can also be configured as other types of interrupts as specified in GPIOIntCfg CFR. General Purpose interrupts can also be used for communication between the internal and external processors. These interrupts are available in InCPUComInt and ExCPUComInt CFRs. 1.10.4 Timer iceLynx-Micro has 3 general timers. One of these timers, Timer2, is configured as the Watch Dog Timer. WTCH_DG_TMRn (WatchDog Timer Output) port is used to detect any internal ARM software failure. If watchdog timer expires, HW sets WTCH_DG_TMRn = low, Low_Pwr_Rdy = low. Value for CFR and output are the following: Low_Pwr_Rdy = low (hardware sets) WTCH_DG_TMRn = low (hardware sets) HPS = hi (external application sets) LPS = high RESET_ARMn = low (external application sets) PHYNoticeEn = hi or low The following describes WTCH_DG_TMRn behavior whenever PinCfg.WtchDgTmrN is set to 0. The WTCH_DG_TMRn pin reflects the value of Timer2.Enable.
(b) W TCH_DG_TMRZ (a) (c) (d)
Figure 20: WatchDog Timer Waveform At phase (a), iceLynx-Micro is in the power-up stage. The ARM has not been programmed and is not operating. Sys.Timer2.Enable bit is 0, and the WTCH_DG_TMRn pin is asserted (low). At phase (b), iceLynx-Micro is in the active stage. The ARM is executing code and has set Sys.Timer2.Enable == 1. The ARM clears the Timer2 counter by periodically writing a "1" to Sys.Timer2.Enable bit to keep Sys.Timer2.Counter from equaling Sys.Timer2.Period. The WTCH_DG_TMRn pin reflects the status of Sys.Timer2.Enable and is deasserted (high). At phase (c), iceLynx-Micro is still in the active stage. However, the ARM has failed to clear the Timer2 counter in time. Sys.Timer2.Counter == Sys.Timer2.Period. At this point, iceLynx-Micro hardware clears Sys.Timer2.Enable. The WTCH_DG_TMRn pin is asserted (low). If
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Sys.Timer2.RstInCPU == 1, the ARM gets a reset. The Sys.*CPUInt.Timer2 interrupt indicates what happened to the ARM after it comes out of reset. The system decides to perform a device reset and reload program code according to system conditions. At phase (d), the ARM (or Ex-CPU) has set Sys.Timer2.Enable == 1. The WTCH_DG_TMRn signal is deasserted (goes high.). Note: WTCH_DG_TMRn function is independent of Sys.InCPUCfg.Reset function. If the ARM is placed in reset by setting Sys.InCPUCfg.Reset == 1, WTCH_DG_TMRn is still active as long as Sys.Timer2.Enable == 1. 1.11 High Speed Data Interface 1.11.1 Overview/Description The High Speed Data Interface (HSDI) is used for transmitting and receiving high-speed video data. The HSDI is connected to the isochronous buffers. HSDI0 is connected to ISO FIFO 0 and HSDI1 is connected to ISO FIFO 1. The HSDI ports can be configured as transmit or receive. A single port cannot transmit and receive at the same time. The buffer direction, HSDI mode, and stream type are all set by CFR. Refer toTable 16: HSDI Signals for a description of the HSDI signals. Table 16: HSDI Signals Signal HSDI*_CLK Polarity Programmable Defaults to rising edge Tx Direction Input Rx Direction Input Description All activity on HSDI uses this clock. The clock must be always provided by an external codec in read and write mode except for TX mode 3. In TX mode 3, the clock is only available during data transmit. Enables the HSDI interface. This signal should be enabled all the time by tying it low or high for modes that do not provide an enable signal.
HSDI*_EN
Programmable Defaults to active low
Input
Input
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TEXAS INSTRUMENTS HSDI*_SYNC
note1
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Input Output HSDI*_SYNC is used to indicate the start of the packet The rising edge (or falling edge, depending on polarity setting) of this signal indicates first byte of data. An internal packet counternote2 keeps track of the packet end. For TX operations of all data types, the packet counter should be programmed by software in HSDI*Cfg.TxDatBlkSz. On TX operation, the width of the HSDI*_SYNC pulse can vary. On RX operation, HSDI*_SYNC is an output from iceLynx-Micro. It is the width of one HSDI*_CLK cycle. For DVB TX, if the application chooses to use the modes that do not provide the HSDI*_Sync signal, the frame sync detection circuitry should be enabled by setting HSDI*Cfg.FrmSyncDetEn = 1. Indicates data is available in FIFO for reading. For MPEG2 RX, data is available once SPH=cycle timer (Timestamp). For DV, data is available once the entire 480-byte cell has been received into the FIFO. For HSDI TX modes 8 and 9, it indicates the number of quadlets in the TX ISO buffer is over the programmed limit. The limit is programmed at CFR Byte wide data bus. HSDI*_D7 is MSB. For serial mode, only HSDI*_D0 is used.
Programmable Defaults to active high
HSDI*_AV
Programmable Defaults to active low
Output for HSDI TX modes 8 and 9(DV)
Output
HSDI*_Data
Input
Output
HSDI*_DVALID HSDI*_FrameS ync
Programmable Defaults to active high
Input
Output For transmit, this signal is input and indicates data is valid and is written to TX ISO buffer. For receive, this signal is output and indicates data is valid on HSDI. On RX operation, this signal is not deasserted for back to back packets. In DV I/F mode (HSDI TX mode 9, RX mode 4), HSDI*_DVALID is used as HSDI*_FrameSync.
Notes: 1) HSDI*SYNC Data on HSDI is ignored until the HSDI*_SYNC signal is detected. Detection mode, data is ignored until the SyncLock event occurs.
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In Frame Sync
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
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The SyncLock event is signaled by an interrupt in CFR-Iso*CPUInt.SyncLock when the HSDI*_Sync signal is activated as programmed in CFR-or- in Frame Sync Detection mode when the MPEG2-DVB synchronization byte 0x47 are detected 188-bytes apart. The Iso*TxCfg.SyncLock status bit is also asserted. The Iso*TxCfg.SyncLock status bit stays asserted until a Sync violation event occurs. If a Sync violation occurs (such as a synchronization byte occurs too soon or too late) the Iso*InCPUInt.SyncUnlock interrupt occurs, and the current packet is flushed. 2) Packet Counter Once the HSDI*_SYNC edge or SyncLock event is detected, the counter starts. The packet is written into the FIFO once the counter value is reached. Data on the HSDI is ignored until the next HSDI*_SYNC or SyncLock event when the frame sync detection circuitry is enabled. If another HSDI*_SYNC occurs before the end of the counter, the packet is aborted. More details on the frame sync detection circuit provided in section 1.12.2 Frame Sync Detection Circuit. The following table shows the counter values to be programmed for the applications shown below: Table 17: Application Counter Values Application MPEG2-DVB MPEG2-DSS-130 MPEG2-DSS-140 DV-SD 1.11.2 Frame Sync Detection Circuit iceLynx-micro supports the frame sync detection feature for MPEG2-DVB applications that do not provide a Sync signal(=byte start) to the HSDI. It is enabled in CFR using HSDI*Cfg.FrmSyncDetEn. The frame detection circuit looks for the MPEG2-DVB transport stream synchronization byte, (0x47). iceLynx-Micro detects synchronization bytes that are 188 bytes apart and signal a SyncLock event. The number of sync bytes detected for a lock condition is programmable in HSDICfg.SyncLockDetNum (the range is 2-7). For example, if HSDICfg.SyncLockDetNum is set to 2, iceLynx-Micro searches for two synchronization bytes 188 bytes apart. The second synchronization byte should be marked as "start of packet" and assert the Iso*CPUInt.SyncLock Interrupt. The first packet is confirmed into the TX FIFO when the second synchronization byte is detected. Otherwise, the first packet is flushed from the FIFO. After the last byte is input to HSDI (188th byte), iceLynx-Micro does not capture any packet data until the next MPEG2 transport stream synchronization byte. Note: The Frame Sync Detection circuit can only be used for MPEG2-DVB (188 byte) data. 1.11.3 HSDI Pass Through Function This function is enable/disabled by a CFR setting. (HSDI*Cfg.PassThru). Both the HSDI0 and HSDI1 ports will support the "data pass-through" function in accordance with the following conditions: The MPEG2-TS data for HSDI TX modes 1-7. The pass through direction is input to HSDI0 and output HSDI1. Counter Value 188 bytes 130 bytes 140 bytes 480 bytes
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1. In this case, HSDI*Cfg.PassThru and Iso*Cfg.Enable must both be set. The DVD MPEG2-TS data is transmitted onto 1394 as well as passed through to HSDI1. Audio Interface, which uses ISO PATH1 (data buffer 1), can also be used at the same time. 2. The direction is only HSDI0->HSDI1 available. 3. When the data pass through function is enabled, the signals shown in below table will be handled. Table 18: HSDI Pass Through Function HSDI0 -> HSDI1 Signal name of HSDI0 Data CLK SYNC Data Valid Data I/O I I I I Direction -> -> -> -> Signal name of HSDI1 Data CLK SYNC Data Valid Data I/O O O O O
Example For Data Pass Through Function
IEEE 1394 Serial Bus
Internal Circuit
MUX
CFR
HSDI_0
HSDI_1
TransPort FrontEnd LSI
Decrypt
Demux
BackEnd LSI
Figure 21: Data Pass-Through Function
1.11.4 HSDI Maximum Clock Rates and Through-Put Refer to Table 19: HSDI Maximum Clock Rates and Through-Put for the maximum clock rates and throughput on the HSDI interface.
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Rev. 1.7
Table 19: HSDI Maximum Clock Rates and Through-Put HSDI Format Serial Parallel 1.11.5 HSDI Mode Settings HSDI Modes, for both transmit and receive, are set by CFR bits (HSDI*Cfg.Mode) as below. See Error! Reference source not found. for general mode settings. Maximum Clock Rate 70MHz 27MHz Maximum Through-put 8.75 Mbytes/sec 27 Mbytes/sec
Table 20: General HSDI Mode Settings Mode Setting At HSDI*Cfg.Mode VideoModes 0000b 0001b 0010b Description
0011b 0100b AudioModes 0101b 60958 Interface
Serial Video Burst I/F (MPEG2, DSS) Serial Video Burst I/F (MPEG2, DSS) Clock Active only when Data is Valid Parallel Video Burst I/F (MPEG2, DSS) MPEG2 I/F Mode DV I/F Mode
0110b
0111b
For HSDI0, uses HSDI0_AMCLK_IN and HSDI0_60958_IN signals. For transmit only. For HSDI1, uses HSDI1_AMCLK_IN and HSDI1_60958_IN for transmit. Uses HSDI1_AMCLK_OUT and HSDI1_60958_OUT for receive. 60958 Data with MLPCM Interface For HSDI0, uses DVD-Audio-In pins muxed on HSDI0 interface. (D0 only.) For transmit only. For HSDI1, uses DVD-Audio I/F for receive only, defined as: MLPCM_BCLK MLPCM_LRCLK MLPCM_D0 MLPCM I/F For HSDI0, uses DVD-Audio-In pins muxed on HSDI0 interface. For transmit only. For HSDI1, uses DVD-Audio I/F for transmit and receive defined as: MLPCM_BCLK MLPCM_LRCLK MLPCM_D0-D2 MLPCM_A SACD I/F For HSDI0, there is no SACD I/F.
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TEXAS INSTRUMENTS Mode Setting At HSDI*Cfg.Mode
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Description
For HSDI1, uses SACD-IN and SACD-OUT signal multiplexed on HSDI1 signals. For flow control mode, uses DVD-Audio I/F signals. Other bits also determine the HSDI operations below summarizes all HSDI video modes available in iceLynx-micro. (See Table 21: HSDI Video Modes) Table 21: HSDI Video Modes HSDI*Cfg. Mode Setting HSDI*.FrmSync DetEn Setting HSDI*.V alidEn Setting Correspondin g Transmit Modes (see Timing Diagrams in section 1.12.6) TX Mode 1 TX Mode 2 Corresponding Receive Modes (see Timing Diagrams in section 1.12.7) None None Description
0000 0000
0 1
0 0
0000 0001
0 1
1 0
TX Mode 4 TX Mode 3
RX Mode 1 --none**--
0010 0010
0 1
0 1
TX Mode 5 TX Mode 6
None None
0010 0011 0100
0 0 0
1 0 NA**
TX Mode 7 TX Mode 8 TX Mode 9
RX Mode 2 RX Mode 3 RX Mode 4
Serial Video Burst I/F (MPEG2, DSS) Serial Video Burst I/F (MPEG2, DSS) with Frame Sync Detect circuit Serial Video Burst I/F (MPEG2, DSS) with Data Valid Signal Serial Video Burst I/F (MPEG2-DVB) Clock active only when Data is Valid Parallel Video Burst I/F (MPEG2, DSS) Parallel Video Burst I/F (MPEG2-DVB) with Frame Sync Detect Circuit Parallel Video Burst I/F (MPEG2, DSS) with Data Valid Signal MPEG2 I/F Mode DV I/F Mode
**Note: DV I/F mode (TX mode 9, RX mode 4). 1.11.6 HSDI Transmit Modes The following MPEG2-TS and DV Write Function Timing diagrams are with the polarity of Data CLK, Sync, Data Valid, HSDI*_FrameSync, Enable and Available signals at their default setting.
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1.11.6.1 TX Mode 1: Serial Burst I/F (MPEG2)
HSDI*_CLK(i) HSDI*_SYNC(i) HSDI*_D0(i) Packet N Packet N+1
Figure 22: MPEG2 Serial Burst I/F (TX Mode 1) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). HSDI*_DVALID is a Don't Care for this mode. It is pulled low.. 1.11.6.2 TX Mode 2: Serial Video Burst I/F (MPEG2) with Frame Sync Detect Circuit
HSDI*_CLK(i) HSDI*_D0(i) Packet N Packet N+1 Packet N+2
Figure 23: MPEG2 Serial Video Burst I/F with Frame Sync Detect Circuit (TX Mode 2) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). HSDI*_DVALID is a Don't Care for this mode. It is pulled low.
1.11.6.3 TX Mode 3: Serial Video Burst I/F (MPEG2) Clock Active Only When Data Is Valid
HSDI*_CLK(i) Min 240ns between pkts Packet N+1
HSDI*_D0(i)
Packet N
Figure 24: MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low) and stay active at all times. HSDI*_EN should not be toggled. HSDI*_DVAILD is a Don't Care for this mode. It is pulled low. Frame Sync Detect Circuit is used.
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1.11.6.4 TX Mode 4: Serial Video Burst I/F (MPEG2) with Data Valid
HSDI*_CLK(i) HSDI*_SYNC(i) HSDI*_DVALID(i) HSDI*_D0(i) Pkt N Pkt N Pkt N+1
Figure 25: MPEG2 Serial Video Burst I/F with Data Valid (TX Mode 4) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). 1.11.6.5 TX Mode 5: Parallel Burst Video I/F (MPEG2)
HSDI*_CLK(i) HSDI*_SYNC(i) HSDI*_D[7:0](i) Packet N Packet N+1
Figure 26: MPEG2 Parallel Burst Video I/F (TX Mode 5) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). HSDI*_DVALID is a Don't Care for this mode. It is pulled low. 1.11.6.6 TX Mode 6: Parallel Video Burst I/F (MPEG2) with Frame Sync Detect Circuit
HSDI*_CLK(i) HSDI*_DVALID(i) HSDI*_D[7:0](i) Pkt N Pkt N Pkt N+1
Figure 27: MEPG2 Parallel Video Burst I/F with Frame Sync Detect Circuit (TXMode 6) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low).
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.11.6.7 TX Mode 7: Parallel Video Burst I/F (MPEG2) with Data Valid
HSDI*_CLK(i) HSDI*_SYNC(i) HSDI*_DVALID(i) HSDI*_D[7:0](i) Pkt N Pkt N Pkt N+1
Figure 28: MPEG2 Parallel Video Burst I/F with Data Valid (TX Mode 7) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). 1.11.6.8 TX Mode 8: MPEG2 I/F Mode
HSDI*_CLK(i) HSDI*_EN(i) HSDI*_SYNC(i) HSDI*_D[7:0](i) HSDI*_AV(o) Pkt N Hold Pkt N Pkt N+1
Figure 29: MPEG2 I/F (TX Mode 8) Note: HSDI*_DVALID is a Don't Care for this mode. It is pulled low. HSDI*_AV is an output in this mode. It is used to indicate if the number of quadlets in the ISO transmit buffer is over a programmed limit. The watermark control must be programmed for the Watermark High. If Iso*WtrMrk.HSDIAvailEn is set to 1, the limit is programmed in Iso*WtrMrk.Level0. The watermark must be programmed less than BUFFER SIZE - (packet length + packet header.).
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TEXAS INSTRUMENTS 1.11.6.9 TX Mode 9: DV I/F Mode
HSDI*_CLK(i) HSDI*_EN(i) HSDI*_SYNC(i) HSDI*_D[7:0](i) HSDI*_AV(o) HSDI*_Fram eSync(i)
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Pkt N
Hold
Pkt N
Pkt N+1
Figure 30: DV I/F (TX Mode 9) Note: The HSDI*_FrameSync signal and SYT circuit are independent of the HSDI*Data [7:0]. HSDI*_FrameSync is multiplexed with HSDI*_DVALID. HSDI*_AV is an output in this mode. It is used to indicate if the number of quadlets in the transmit buffer is over a programmed limit. The watermark control must be programmed for the Watermark High. If Iso*WtrMrk.HSDIAvailEn is set to 1, the limit is programmed in Iso*WtrMrk.Level0. The watermark must be programmed less than BUFFER SIZE - (packet length + packet header.)
1.11.7 HSDI Receive Modes The following MPEG2-TS and DV Read Function Timing diagrams are with the polarity of Data CLK, Sync, Data Valid, HSDI*_FrameSync, Enable and Available signals are default setting. 1.11.7.1 RX Mode 1: Serial Burst Video I/F (MPEG2)
HSDI*_CLK(i) HSDI*_SYNC(o) HSDI*_DVALID(o) HSDI*_D0(o) Packet N Packet N+1
Figure 31: MPEG2 Serial Burst Video I/F (RX Mode 1) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low).
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.11.7.2 RX Mode 2: Parallel Burst Video I/F (MPEG2)
HSDI*_CLK(i) HSDI*_SYNC(o) HSDI*_DVALID(o) HSDI*_D[7:0](o) Packet N Packet N+1
Figure 32: MPEG2 Parallel Burst Video I/F (RX Mode 2) Notes: HSDI*_EN should be pulled low for this mode (HSDI*_EN defaults to active low). 1.11.7.3 RX Mode 3: Parallel Burst Video I/F (MPEG2) Mode
HSDI*_CLK(i) HSDI*_EN(i) HSDI*_AV(o) HSDI*_SYNC(o) HSDI*_D[7:0](o) Hold Pkt N Pkt N+1 Hold Pkt N+1
Figure 33: MPEG2 Parallel Burst Video I/F (RX Mode 3) 1.11.7.4 RX Mode 4: Parallel Burst Video I/F (DV) Mode
HSDI*_CLK(i) HSDI*_EN(i) HSDI*_AV(o) HSDI*_SYNC(o) HSDI*_D[7:0](o) HSDI*_FrameSync(o) Hold Pkt N Pkt N+1 Hold Pkt N+
Figure 34: DV Parallel Burst Video I/F (RX Mode 4) Notes: The HSDI*_FrameSync signal and the SYT circuit are independent of the HSDI*_D [7:0]. HSDI*_FrameSync is multiplexed with HSDI*_DVALID.
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TEXAS INSTRUMENTS 1.11.7.5 HSDI A/C Timing
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.11.7.5.1 Transmit HSDI AC Timing
T1 HSDI*_CLK T3 T2 Input Signals* T4 HSDI*_AV
Figure 35: Transmit HSDI AC Timing
Input Signals include the following: HSDI*_EN, and HSDI*_FrameSync.
HSDI*_SYNC, HSDI*_DVALID, HSDI*_D [7:0],
Table 22: AC Timing Parameters for Serial I/F (Modes 1 and 4)
Symbol T1 T2 T3 Description Data CLK period Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Min 14.3 2.2 0 Max Units ns ns ns
Table 23: AC Timing Parameters for Serial I/F (Modes 2 and 3)
Symbol T1 T2 T3 Description Data CLK period Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Min 12.5 2.2 0 Max Units ns ns ns
Table 24: AC Timing Parameters for Parallel I/F (Modes 5, 6, and 7)
Symbol T1 T2 T3 Description Data CLK period Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Min 37 11 0 Max Units ns ns ns
Table 25: AC Timing Parameters for Parallel I/F (Modes 8 and 9)
Symbol T1 T2 T3 T4 Description Data CLK period Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Signals Delay from rising edge of Data CLK Min 37 15 0 7 Max Units ns ns ns ns
** Note: Measurements based on a 20 pF loading.
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
T3 T1 T2
1.11.7.5.2 Receive HSDI AC Timing
HSDI*_CLK T6 Output Signals* T4 HSDI*_EN T5
Figure 36: Receive HSDI AC Timing Output Signals include the following: HSDI*_SYNC, HSDI*_DVALID, HSDI*_D[7:0], HSDI*_AV, and HSDI*_FrameSync. Table 26: AC timing parameters for Serial I/F (Mode1)
Symbol T1 T2 T3 T4 T5 T6 Description Data CLK period CLK low width CLK high width Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Signals Delay from rising edge of Data CLK Min 14.3 4 4 2.2 0 7 Max Units ns ns ns ns ns ns
Table 27: AC timing parameters for Parallel I/F (Mode2)
Symbol T1 T2 T3 T4 T5 T6 Description Data CLK period CLK low width CLK high width Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Signals Delay from rising edge of Data CLK Min 37 14 14 2.4 0 7 Max Units ns ns ns ns ns ns
Table 28: AC timing parameters for Parallel I/F (Mode3 and 4)
Symbol T1 T2 T3 T4 T5 T6 Description Data CLK period CLK low width CLK high width Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Signals Delay from rising edge of Data CLK Min 37 15 0 2.4 0 2.4 25 Max Units ns ns ns ns ns ns
** Note: Measurements based on a 20 pF loading.
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TEXAS INSTRUMENTS 1.11.8 Audio Interface on HSDI
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.11.8.1 HSDI0 On HSDI0, only DVD-Audio (MBLA) transmit and 60958 transmit are supported. DVD-Audio (MBLA) and 60958 data cannot be transmitted at the same time. Both interfaces share the same data buffer. The hardware selects the interface based on Iso*Cfg.DataType. For DVD-Audio transmit, the DVD-Audio signals are muxed onto the HSDI pins as follows: Table 29: HSDI0 DVD Audio Signals DVD-Audio Signal BCLK LRCLK D0 D1 D2 Ancillary Muxed HSDI Pin HSDI0_CLKz HSDI0_ENz HSDI0_D0 HSDI0_D1 HSDI0_D2 HSDI0_D3
For 60958 data, the HSDI0_AMCLK_IN and HSDI0_60958_IN pins are used. 1.11.8.2 HSDI1 On HSDI1, 60958, SACD, and DVD-Audio (MBLA) are all supported for transmit or receive. The DVD-Audio (MBLA) has dedicated pins, which are not muxed with HSDI pins. However, the DVD-Audio (MBLA) pins and HSDI pins cannot be used at the same time. They access the same data buffer. The hardware selects the interface based on Iso*Cfg.DataType. DVD-Audio (MBLA) dedicated pins are also used for DVD-Audio (MBLA) flow control mode. HSDI1 signal descriptions are as follows: Table 30: HSDI1 DVD-Audio Signals Audio Signal SACD MCLK FRAME D0 D1 D2 D3 D4 D5 D6 60958 CLK DATA CLK DATA DVD-AUDIO (MBLA) BCLK
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Direction Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx Tx Rx Rx Tx/Rx
Hardware Pin HSDI1_CLKz HSDI1_SYNCz HSDI1_D0 HSDI1_D1 HSDI1_D2 HSDI1_D3 HSDI1_D4 HSDI1_D5 HSDI1_D6 HSDI1_AMCLK_IN HSDI1_60958_IN HSDI1_AMCLK_OU T HSDI1_60958_OUT MLPCM_BCLK
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Direction Tx/Rx Tx/Rx Tx/Rx Tx/Rx Tx/Rx Hardware Pin MLPCM_LRCLK MLPCM_D0 MLPCM_D1 MLPCM_D2 MLPCM_A
Audio Signal LRCLK D0 D1 D2 Ancillary
1.11.8.3 IEC60958 I/F AC Timing Characteristic AC timing characteristic on receiving CeLynx_Micro should follow the section 5.3.4.2 and 5.3.4.3 of EIAJ (Electronic Industries Association of Japan) CP-1201 "Digital Audio Interface" standard. Extracts from EIAJ CP-1201 [5.3.4.2 rise and fall time rates] Rise and fall time rates are specified by following equations.
rise _ time _ rate =
100 x T (r ) T (l ) + T (h ) 100 x T ( f ) fall _ time _ rate = T (l ) + T (h )
(%) (%)
rise and fall time rates should be less than following ranges. When the data bit is logically "1" : 0% ~ 20%
When the data bit is logically "0" continuously for 2 times : 0% ~ 10%
T(h)
T(l)
90% 50% 10%
T(r)
T(f)
[5.3.4.3 duty cycle rate] Duty cycle rate are specified by following equation.
duty _ cycle _ rate =
100 x T (h ) T (l ) + T (h )
(%)
Duty cycle rate should be less than following ranges.
When the data bit is logically "1": 40% ~ 60% When the data bit is logically "0" continuously for 2 times: 45% ~ 55% AC timing characteristic on transmitting
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TEXAS INSTRUMENTS
HSDI*_AMCLK_IN
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
T1
T2 HSDI*_60958_IN
T3
Figure 37: Example 1 Sampling frequency (fs): 192kHz, Master clock frequency: 256fs
T1 HSDI*_AMCLK_IN T2 HSDI*_60958_IN T3
Figure 38: Example 2 Sample frequency (fs): 48kHz, Master clock frequency: 768fs Table 31: AC Timing Parameters
Symbol T1 T2 T3 Description Data CLK period Signals setup to rising edge of Data CLK Signals Hold to rising edge of Data CLK. Min 27 5 5 Max Units ns ns ns
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
MLPCM I/F AC Timing Characteristic
T2 T1 BCLK* T4 Data** T5 LRCLK*** T3
Figure 39: AC timing characteristic on receiving
* ** ***
BCLK includes the following: MLPCM_BCLK and FLWCTL_BCLK. Data includes the following: MLPCM_D[2:0], MLPCM_A, FLWCTL_D[2:0], and FLWCTL_A. LRCLK includes the following: MLPCM_LRCLK and FLWCTL_LRCLK. Table 32: AC Timing Parameters
Symbol T1 T2 T3 T4 T5
Description Data CLK period CLK Low Width CLK High Width Signals Delay to Data CLK Signals Delay to Data CLK.
Min 50 20 20
Max
Units ns ns ns
10 10
ns ns
T2 T1 BCLK* T4 Data** T6 LRCLK***
T3
T5
t7
Figure 40: AC timing characteristic on transmitting
* ** ***
BCLK includes the following: HSDI0_MLPCM_BCLK and MLPCM_BCLK. Data includes the following: HSDI0_MLPCM_D[2:0], HSDI0_MLPCM_A, MLPCM_D[2:0], and MLPCM_A. LRCLK includes the following: HSDI0_MLPCM_LRCLK and MLPCM_LRCLK.
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Symbol T1 T2 T3 T4 T5 T6r T7 Description
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Table 33: AC Timing Parameters
Min 75 35 35 8 8 8 8 Max Units ns ns ns ns ns ns ns
Data CLK period CLK Low Width CLK High Width Signals Setup to Data CLK Signals Hold to Data CLK Signals Setup to Data CLK Signals Hold to Data CLK.
1.12 UART Interface iceLynx-Micro includes one UART port that is memory mapped and fully accessible from the internal CPU. The output of the UART requires level shifting for RS-232 compliance. This UART transmits/receives one start bit, 7 or 8 data bits, optional parity, and 1 or 2 stop bits. UART errors are indicated in iceLynx-Micro interrupts in table below. 1.12.1 UART Registers Software uses the iceLynx-Micro UART CFR (0x070) to access UART registers. The UART CFR contains address offset, data, and read/write control bits. The UART address offsets are described in Table 34: UART CFR Address Offsets. Table 34: UART CFR Address Offsets DLAB 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 1 0 0 1 1 0 0 A0 0 1 0 0 1 0 1 0 1 0 1 Name RBR/THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLH Register Receiver buffer register (read) or transmitter holding register (write) Interrupt Enable Register Interrupt Id Register (read only) FIFO Control Register (write) Link Control Register Modem Control Register Link Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Divisor Latch (MSB)
Note: Only A2-A0 address bits are implemented in the UART register. The DLAB bit is set in the LCR register. If DLAB is set to 0, reads/writes to address 000b and 001b accesses the RBR/THR and IER registers. If DLAB is set to 1, reads/writes to address 000b and 001b accesses the DLL and DLH registers.
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TEXAS INSTRUMENTS Register RBR (RX only) THR (TX only) IER Address 000 DLAB=0 000 DLAB=0 001 DLAB=0 Bit 0 Data Bit 0 Data Bit 0 Enable Receiver Data Available Int 0 if Int Pending FIFO Enable Word Length Select Bit 0 Data Terminal Ready Data Ready Data Clear to Send Bit 0 Bit 0 Bit 8
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Table 35: UART Registers Bit 1 Data Bit 1 Data Bit 1 Enable Transmi tter Holding Register Empty Int Int ID bit 1 RX FIFO Reset Word Length Select Bit 1 Request to Send Overrun Error Delta Set Ready Bit 1 Bit 1 Bit 9 Bit 2 Data Bit 2 Data Bit 2 Enable Receive r Line Status Int Int ID bit 2 TX FIFO Reset Number of Stop Bits OUT1 Parity Error Trailing Edge Ring Indicator Bit 2 Bit 2 Bit 10 Bit 3 Data Bit 3 Data Bit 3 Enable Modem Status Int Bit 4 Data Bit 4 Data Bit 4 0 Bit 5 Data Bit 5 Data Bit 5 0 Bit 6 Data Bit 6 Data Bit 6 0 Bit 7 Data Bit 7 Data Bit 7 0
IIR (read only) FCR (write only) LCR
010 010 011
Int ID bit 3 DMA Mode Select Parity Enable
0 RSVD Even Parity Select Loop Break INT Clear to Send Bit 4 Bit 4 Bit 12
0 RSVD Stick Parity
FIFOs enabled Receive r Trigger (LSB) Break Control
FIFOs enabled Receiver Trigger (MSB) Divisor latch Access Bit (DLAB) RSVD Error in RCVR FIFO Carrier Detect Bit 7 Bit 7 Bit 15
MCR LSR
100 101
OUT2 Framing Error Delta Carrier Detect Bit 3 Bit 3 Bit 11
MSR
110
Autoflow Control Enable Transmi tter Holding Register Data Set Ready Bit 5 Bit 5 Bit 13
RSVD Transmi tter Empty Ring Indicator Bit 6 Bit 6 Bit 14
SCR DLL DLH
111 000 DLAB=1 001 DLAB=1
1.12.2 UART Baud Rate Example: To set the UART baud speed, Equation 1 must be used to determine the Divisor Value. The Divisor Value is written into the UART registers to set the baud rate.
Baud rate = 50MHz/ (16 x Divisor Value)
Equation 1
Write 0x0000 43X1 to UART0 register. This tells iceLynx-Micro to write a value of X1 to the UART address offset 3 (LCR register). The value X1 sets the DLAB bit to 1.
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TEXAS INSTRUMENTS Write 0x0000 40XX UART DLL register. Write 0x0000 41XX UART DLH register. 1.13
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
to UART0 register. This tells iceLynx-Micro to write a value of XX to the This is the Divisor Latch LSB. to UART0 register. This tells iceLynx-Micro to write a value of XX to the This is the Divisor Latch MSB.
JTAG - Boundary Scan and ARM
iceLynx-Micro implements IEEE 1149.1 JTAG for boundary scan (iceLynx-micro and ARM core) and ARM debug. Control signals include: JTAG_TMS - Test Mode Select for JTAG boundary scan JTAG_TDI - Test Data Input for JTAG boundary scan JTAG_TDO - Test Data Output for JTAG boundary scan ARM_JTAG_TMS - Test Mode Select for ARM ARM_JTAG_TDI - Test Data Input for ARM ARM_JTAG_TDO - Test Data Output for ARM JTAG_TCK - Test Clock - Common pin for boundary scan and ARM JTAG_TRSTn - Test Reset (active low) Common pin for boundary scan and ARM. JTAG boundary scan is always available. To disable JTAG, the JTAG_TRSTn signal should be held high. The JTAG_TCK can operate up to 10.358MHz, the frequency used by the TI-ARM JTAG emulation tools. The ARM JTAG can only be enabled by the ARM. A small program must be loaded into program memory that enables the ARM JTAG. (InCPUCfg.DebugEn). 1.14 Integrated 3-Port PHY 1.14.1 3 Port PHY iceLynx-Micro contains an integrated 3-port PHY. The PHY operates at 100Mbps, 200Mbps, or 400Mbps and meets the requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards. For applications that only need 2 PHY ports, the TPB+/- signals is terminated to ground on the board, or the PHY port is disabled through a CFR. When this occurs, the PHY still reports itself as a 3-port node in self-ID packets. The PHY core contains a CFR bit that controls the BIAS function. This bias function can either operate using the 1394-1995 method of bias or the IEEE 1394a-2000 method of bias. The 13941995 method always asserts a continuous bias. The IEEE 1394a-2000 method asserts bias for 980 ms. The PHY can be set to operation at S100 and S200 node only. If the MSPCTL hardware pin is asserted to a high state, the maximum transaction speed is S200. Also PHY maximum node speed is recognized as S200. If MSPCTL is zero (i.e. pulled to ground), the PHY supports S100, S200, and S400. The PHY registers is accessed through the PhyAccess configuration register as described in Table 36: PHY Access Register Table 36: PHY Access Register 31 RdReg 30 WrReg 29 28 RSVD 27 24 PhyRegA ddr 23 16 PhyRegWr Data 15 12 RSV D 11 8 PhyRegA ddrRcvd 7 0 PhyRegDat Rcvd
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TEXAS INSTRUMENTS 1.14.2 PHY Registers
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
In the iceLynx-Micro are 16 accessible internal PHY registers. They are accessed using the PHY Access Register. The address offset is used to specify the location. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8 through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The selected page is set in base register 7. The configuration of the base registers is shown in Table 37: Base Register Configuration, and corresponding field descriptions given in Table 38: Base Register Field Descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as "Reserved" or "Rsvd" in the register configuration tables below) is read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved. Table 37: Base Register Configuration Bit Position Address 0000 0001 0010 0011 0100 0101 0110 0111 0 1 2 3 4 5 6 R Gap_Count Rsvd Rsvd Jitter (`b000) CTOI CPSI STOI Num_Ports (`b0011) Delay (`b0000) Pwr_Class PEI EAA EMC 7 CPS
Physical ID RHB IBR
Extended (`b111) PHY_Speed (`b010) LCtrl WDIE Reserved Page_Select C ISBR
Rsvd
Port_Select
Table 38: Base Register Field Descriptions FIELD Physical ID SIZE 6 TYPE Rd DESCRIPTION This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus-reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus-reset, and is set to 1 during tree-ID if this node becomes root. Cable-power-status. This bit indicates the state of the CPS input pin. The CPS pin is normally pulled to serial bus cable power through a 400 k resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for guaranteed reliable operation. Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus-reset. The RHB bit is reset to 0 by hardware reset and is unaffected by bus-reset.
R CPS
1 1
Rd Rd
RHB
1
Rd/Wr
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TEXAS INSTRUMENTS FIELD IBR SIZE 1 TYPE Rd/Wr
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 DESCRIPTION Initiate bus-reset. This bit instructs the PHY to initiate a long (166 s) bus-reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus-reset is initiated. The IBR bit is reset to 0 by hardware reset or bus-reset. Arbitration gap count. This value is used to set the sub action (fair) gap, arb-reset gap, and arb-delay times. The gap count is set either by a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus-resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended register definition. For iceLynx-Micro this field is `b111, indicating that the extended register set is implemented. Number of ports. This field indicates the number of ports implemented in the PHY. For iceLynx-Micro this field is 3. PHY speed capability. For iceLynx-Micro PHY this field is `b010, indicating S400 speed capability. The setting of this field also depends on the MSPCTL setting. PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed as 144+(delay*20) ns. This field is 0 (default.) Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the "L" field (bit 9) of the self-ID packet. The LLC is considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides software controllable means to indicate the LLC active status in lieu of using the LPS input. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continues to be presented on the interface, and any requests indicated on the LREQ input is processed, even if the LCtrl bit is cleared to 0.
Gap_Count
6
Rd/Wr
Extended Num_Ports PHY_Speed
3 4 3
Rd Rd Rd
Delay
4
Rd
LCtrl
1
Rd/Wr
C
1
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the "c" field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON input pin upon hardware reset and is unaffected by busreset. PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater data delay, expressed as (JITTER+1)*20 ns. For iceLynx-Micro this field is 0.
Jitter
3
Rd
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TEXAS INSTRUMENTS FIELD Pwr_Class SIZE 3 TYPE Rd/Wr
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 DESCRIPTION Node power class. This field indicates this node's power consumption and source characteristics, and is replicated in the "pwr" field (bits 21-23) of the self-ID packet. This field is set to 000 default value at hardware reset and is unaffected by bus-reset. Software can program this field to change the power class. Software should perform a bus reset after setting this field. Watch dog interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits is set. This bit is reset to 0 by hardware reset and is unaffected by bus-reset. Initiate short arbitrated bus-reset. This bit, if set to 1, instructs the PHY to initiate a short (1.30 s) arbitrated bus-reset at the next opportunity. This bit is reset to 0 by bus-reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus-resets. Therefore, initiation of a short bus-reset in a network that contains such a legacy device results in a long busreset being performed.
WDIE
1
Rd/Wr
ISBR
1
Rd/Wr
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during tree-ID start, and indicates that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. NOTE: If the network is configured in a loop, only those nodes that are part of the loop generate a configuration time-out interrupt. All other nodes instead, time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset.
CPSI
1
Rd/Wr
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power is too low for reliable operation. This bit is reset to 1 by hardware reset. It is cleared by writing a 1 to this register bit. If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt.
STOI
1
Rd/Wr
State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus-reset to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt.
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TEXAS INSTRUMENTS FIELD PEI SIZE 1 TYPE Rd/Wr
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 DESCRIPTION Port event interrupt. This bit is set to 1 upon a change in the bias (unless disabled), connected, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt.
EAA
1
Rd/Wr
Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus-reset. NOTE: The EAA bit should be set only if the attached LLC is 1394a-2000 compliant. If the LLC is not 1394a-2000 compliant, use of the arbitration acceleration enhancements interferes with isochronous traffic by excessively delaying the transmission of cycle-start packets.
EMC
1
Rd/Wr
Enable multi-speed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware reset and is unaffected by bus-reset. NOTE: The use of multi-speed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multi-speed concatenation requires that the attached LLC be 1394a-2000 compliant.
Page_Select
3
Rd/Wr
Page-select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by hardware reset and is unaffected by bus-reset. Port-select. This field selects the port when accessing per-port status or control (e.g., when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware reset and is unaffected by bus-reset.
Port_Select
4
Rd/Wr
Port Status Page Register The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the Port Status page registers is shown in
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 If the selected port is
Table 39: Page 0 (Port Status) Register Configuration, and corresponding field descriptions given in Table 40: Page 0 (Port Status) Register Field Descriptions. unimplemented, all registers in the Port Status page are read as 0. Bit Position Address 1000 1001 1010 1011 1100 1101 1110 1111 0 Astat Peer_Speed Reserved Reserved Reserved Reserved Reserved Reserved Table 40: Page 0 (Port Status) Register Field Descriptions FIELD AStat SIZE 2 TYPE Rd DESCRIPTION TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: Code 11 01 10 00 Bstat Ch 2 1 Rd Rd Line State Z 1 0 invalid 1 2 Bstat PIE 3 4 Ch Fault 5 Con Reserved 6 Bias 7 Dis
Table 39: Page 0 (Port Status) Register Configuration
TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the ASTAT field. Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus-reset until tree-ID has completed. Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus-reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but the port is not necessarily active.
Con
1
Rd
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TEXAS INSTRUMENTS FIELD Bias SIZE 1 TYPE Rd
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 DESCRIPTION Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 s for the Bias bit to be set to 1. Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus-reset. Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: Code 000 001 010 011-111 Peer Speed S100 S200 S400 invalid
Dis
1
Rd/Wr
Peer_Speed
3
Rd
The Peer_Speed field is invalid after a bus-reset until self-ID has completed. NOTE: Peer speed codes higher than `b010 (S400) are defined in 1394a2000. However, iceLynx-Micro is only capable of detecting peer speeds up to S400. PIE 1 Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port sets the port event interrupt (PEI) bit and notify the link. This bit is reset to 0 by hardware reset and is unaffected by bus-reset. Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the Fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus-reset.
Fault
1
Rd/Wr
Vendor Identification Page Register The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the Vendor Identification page is shown in Table 41: Page 1 (Vendor ID) Register Configuration, and corresponding field descriptions given in Table 42: Page 1 (Vendor ID) Register Field Descriptions. Table 41: Page 1 (Vendor ID) Register Configuration Bit Position Address 1000 1001 1010
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0
1
2
3
4 Compliance Reserved Vendor_ID[0]
5
6
7
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TEXAS INSTRUMENTS Address 1011 1100 1101 1110 1111 0 1 2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Bit Position 3 4 Vendor_ID[1] Vendor_ID[2] Product_ID[0] Product_ID[1] Product_ID[2] 5 6 7
Table 42: Page 1 (Vendor ID) Register Field Descriptions FIELD Compliance Vendor_ID SIZE 8 24 TYPE Rd Rd DESCRIPTION Compliance level. For iceLynx-Micro this field is controlled by a link register bit Manufacturer's organizationally unique identifier (OUI). For iceLynx-Micro this field is 08_00_28h (Texas Instruments) (the MSB is at register address `b1010). Product identifier. For iceLynx-Micro this field is 41_44_99h (the MSB is at register address `b1101).
Product_ID
24
Rd
1.14.3 PHY Application Information The PHY pins should be connected as shown in the following figures. XI and XO pins should be connected to a crystal as described by TI application note SLLA051.
TPBP 1394 Connector TPBN 56 O hm 220 pF 56 Ohm 5K Ohm
Figure 41: TPBP and TPBN Connection
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1 uF TPBIAS TPAP TPAN 56 Ohm 56 Ohm 1394 Connector
Figure 42: TPAP, TPAN, and TPBIAS Connection
R0 6.34k Ohm +/- 1%
R1
Figure 43: R0 and R1 Connection
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
FILTER0 0.1uF +/- 10% FILTER1
Figure 44: FILTER0 and FILTER1 Connection
TPBIAS TPAP TPAN TPBP TPBN
Figure 45: TPB, TPA, TPBIAS Connection for Terminated Port (Port is not used)
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.14.3.1 PHY Reference Documents Visit Texas Instruments website to obtain the following reference documents: Literature Number Title SLLA117 IEEE 1394 EMI Board Design and Layout Guidelines SLLA051 Selection and Specification of Crystals for TI's IEEE 1394 Physical Layers 1.15 Power Management iceLynx-Micro operates from a single 3.3V power supply. When REG_ENn is asserted, three internal regulators are used to operate the 1.8V core. When the internal regulator is not supplied, the application must externally supply the core voltage. The PHY also automatically conforms to IEEE1394a-2000 power states according to bus activity. Table 43: Power State Summary summarizes all the power modes that iceLynx-Mirco supports. Table 43: Power State Summary Power State InCPUCfg.Reset PhyCfg.LPS PHY Ports Max Power w/Internal Regulator Enabled (mW) 695 Max Power w/External Regulator Enabled (mW) 531
Active - Full 0 1 Active Power Link, ARM, and PHY are active Low Power 1 0 0 Disabled or ARM Active Suspended by software Link and PHY are low power Low Power 2 1 1 Active Link and PHY Only ARM in low power Low Power 3 1 0 Disabled or PHY Only - PHY Suspended by Low Power software Link and ARM are low power Note: All other configurations are not valid for normal operation.
473
223
125
102
31
4
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TEXAS INSTRUMENTS
Power-Up(PU) State
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Active(A) State Low Power(LP) States
A to LP1 Low Power1 LP1 to A
ARM active PHY in low power Link off
A to LP2 Low Power2 Power-Up PU to A
PHY in Repeater Mode. All register values at default PHY Active ARM Active Link Active Link, PHY active ARM off
Active
LP2 to A
A to LP3 Low Power3 LP3 to A
PHY in low power ARM, Link off
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.15.1 PU to A (Power Up State to Active State) At the power-up state, all registers are at the default value. Following are the power-up status of registers and signals related to power control. Register/pin name InCPUCfg.Reset InCPUCfg.ClkEn InCPUCfg.PhyNoticeEn PhyCfg.LPS WTCH_DG_TMRn HPS Power-up status 0 (ARM is held in reset using RESET_ARMn pin) 1 0 0 (PHY is in repeater mode) Low High
1. The external system holds the ARM in reset using RESET_ARMn pin. 2. The external CPU loads the ARM program code. Once it has completed loading the code, it deasserts RESET_ARMn. 3. The ARM sets PhyCfg.LPS to 1. Now the PHY, link, and ARM are fully functional. 1.15.2 A to LP1 (Active State to Low Power 1 State) In the active state, the Link, ARM, and PHY are fully operational. In the Low Power State 1, the Link is off. The PHY ports are suspended or disabled. The ARM may choose to put iceLynxMicro into a low power state based on the the HPS pin. A falling edge of the HPS pin indicates the external system is ready for iceLynx-Micro to go into low power mode. The ARM will set the following bits to move to LP1 State: 1. Suspend or disable PHY ports. S/W can disable a PHY port by setting the Dis bit in PHY register b1000. S/W can suspend a PHY port by sending a 1394a-2000 remote command packet to its own node. 2. PhyCfg.LPS = 0 (PHY can go into low power mode according to IEEE 1394a-2000) 1.15.3 LP1 to A (Low Power 1 State to Active State) 1. On the detection of the following events, ARM should enable the link and PHY to the active state. * Rising edge of HPS input pin. * InCPUCfg.PhyNoticeEn=1 and LinkOn or PHY_INT occurs. 2. ARM must set PhyCfg.LPS = 1. If any of the ports were disabled, software must reenable the PHY ports by setting the Dis bit in PHY register b1000 to make the PHY active. The software must issue a bus reset once PhyCfg.LPS is set to 1. 1.15.4 A to LP2 (Active State to Low Power 2 State) In the active state, the Link, ARM, and PHY are fully operational. In the Low Power State 2, the ARM is off, link and PHY are fully operational. The system may choose to put iceLynx-Micro into the Low Power State 2 when the internal ARM is not used. The ex-CPU will set the following bits to move to LP2 State: 1. Set InCPUCfg.Reset =1 and InCPUCfg.ClkEn=0 at the SAME TIME.
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.15.5 LP2 to A (Low Power 2 State to Active State) 1. The iceLynx-Micro hardware will set InCPUCfg.Reset = 0 and InCPUClkEn = 1 for either of the following conditions: Rising edge of HPS input pin. InCPUCfg.PhyNoticeEn=1 and LinkOn or PHY_INT occurs.
* *
1.15.6 A to LP4 (Low Power 3 State to Active State) In the active state, the Link, ARM, and PHY are fully operational. In the Low Power State 4, the ARM and Link are off. The PHY ports are suspended or disabled. The ARM may choose to put iceLynx-Micro into a low power state based on the the HPS pin. A falling edge indicates the external system is ready for iceLynx-Micro to go into low power mode. The ARM will set the following bits to move to LP4 State: 1. Suspend or disable PHY ports. S/W can disable a PHY port by setting the Dis bit in PHY register 0b1000. S/W can suspend a PHY port by sending a 1394a-2000 remote command packet to its own node. 2. PhyCfg.LPS = 0 {PHY can go into low power mode according to IEEE 1394a-2000} 3. Set InCPUCfg.Reset =1 and InCPUClkEn=0 at the at the SAME TIME. 1.15.7 LP4 to A (Low Power 3 State to Active State) 1. The iceLynx-Micro hardware will set InCPUCfg.Reset = 0 and InCPUClkEn = 1 for either of the following conditions: * Rising edge of HPS input pin * InCPUCfg.PhyNoticeEn=1 and LinkOn or PHY_INT occurs Once the ARM and Link are active, the ARM must set PhyCfg.LPS = 1. If any of the ports were disabled, software must reenable the PHY ports by setting the Dis bit in PHY register b1000 to make the PHY active. The software must issue a bus reset once PhyCfg.LPS is set to 1. The input/output pins and CFRs that control each power management state are defined in Table 44: I/O Pin and CFR Descriptions for Controlling Power Management States. Table 44: I/O Pin and CFR Descriptions for Controlling Power Management States Signal Name LOW_PWR_RDY InCPUCfg.LowPwr Rdy Location Pin and CFR Direction Output Description This signal is output to the system to indicate iceLynx-Micro can go into a low power state. The ARM controls this output signal using CFR. The signal also depends on the watchdog timer output signal. If the watchdog timer is asserted, this signal is asserted. Indicates watchdog timer status. Hardware asserts this when the ARM software is not functioning correctly. Host Power Status. (Ex-CPU Power Status). This signal indicates the ex-CPU's power status. A rising edge indicates the ex-CPU has been turned ON. The internal ARM should wake up. The internal ARM decides if it should
Copyright 2003, Texas Instruments Incorporated
WTCH_DG_TMRn HPS ExCPUCfg.HPS InCPUInt.HPSHi InCPUInt.HPSLo
Pin Pin and CFR
Output Input
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TEXAS INSTRUMENTS Signal Name Location
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Direction Description wake up the rest of iceLynx-Micro. A falling edge indicates the ex-CPU has shut down. ARM can decide how to react. Interrupts are available for both the rising and falling edge of this signal. This bit is set in CFR to indicate low power status to the PHY. The ARM should set this when it wants to put the link into lower power mode. The ARM should clear this to bring the link out of low power mode. Note: Software should wait at least 2mS before setting PhyCtrl.LPS after iceLynx-Micro power up. This insures the internal clocks are stable. This bit enables PHY events. These PHY events is used to signal Wake Up event to the ARM while the ARM is powered down. The PHY events include LinkOn and PHY_INT. This pin and CFR bit put ARM into reset.
PhyCfgLPS
CFR
InCPUCfg.PhyNotic eEn RESET_ARMn InCPUCfg.Reset
CFR
Pin and CFR
Input
ARM cannot be put into reset by setting InCPUCfg.Reset = 1 if InCPUCfg.ResetDis is set to 1. See the description for InCPUCfg.ResetDis. InCPUCfg.ResetDis bit must be cleared before the ARM is put into reset. The RESET_ARMn pin does not have these qualifying conditions. When RESET_ARMn = Low, the ARM is put inot reset regardless of InCPUCfg.ResetDis bit status. LINKON Pin and Output This signal is asserted whenever LPS is low PhyCfg.LinkOn CFR and a LinkOn packet is received. It is cleared whenever LPS is detected or the PHY register LCtrl bit is set to zero. PhyCfg.LinkOn gives the current status of the LINKON signal. DISABLE_IFn Pin Input Interface Disable. When this pin is asserted by the system, all interfaces on iceLynx-Micro are in high-Z state. This includes Ex-CPU I/F, HSDI I/F, GPIO, and WTCH_DG_TMRn. This function does not include LOW_PWR_RDY. This function is active low. The interface is disabled if DISABLE_IFn=0. InCPUCfg.ResetDis CFR This bit is set by hardware any time one of the following bits transitions from 0 to 1. PhyCfg.LinkOn LinkInt.PhyInt InCPUInt.HPSHi Note: The WTCH_DG_TMRn is configured for output on the Timer2 interrupt.
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TEXAS INSTRUMENTS 1.16 16.5K Byte Memory - FIFO 1.16.1 Overview/Description
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
iceLynx-Micro has 16.5Kbyte FIFO. The FIFO sizes are set and not programmable. 1.16.2 Isochronous FIFOs 0 and 1: These FIFOs are connected to the HSDI0 and HSDI1 ports, respectively. They are both 4K bytes in size. These FIFOs are designed to handle MPEG2, DSS, DV, or audio data. These data types cannot be interleaved. The buffer must be dedicated to one data type and a single direction. It can be reprogrammed to handle different data types. Both of these buffers can be configured for either transmit or receive. The buffer is only accessible using the HSDI. Refer to Figure 46: Isochronous FIFOs for a block diagram of the isochronous FIFO architecture.
ISO FIFO 0 4K
HSDI0
Packetizer
HSDI1
ISO FIFO 1 4K
Packetizer
Figure 46: Isochronous FIFOs
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.16.3 Asynchronous/Asynchronous Stream FIFOs: These FIFOs are connected to the external and internal CPU interfaces. The transmit FIFOs are 2048 bytes each, and the receive FIFOs are 2048 bytes each. Either FIFO can be configured for asynchronous stream or asynchronous packets. Refer to Figure 47: Asynchronous/ Asynchronous Stream FIFOs for a block diagram of the asynchronous FIFO architecture.
External or Internal Host
Asynchronous or Asynchrnous Stream Transmit FIFO 0 2K
Packetizer/ Transmitter
External or Internal Host
Asynchronous or Asynchronous Stream Transmit FIFO 1 2K
Packetizer/ Transmitter
External or Internal Host
Asynchronous or Asynchrnous Stream Receive FIFO 0 2K
Packetizer/ Receiver
External or Internal Host
Asynchronous or Asynchronous Stream Receive FIFO 1 2K
Packetizer/ Receiver
Figure 47: Asynchronous/ Asynchronous Stream FIFOs Note: iceLynx-Micro has the ability to insert headers for asynchronous stream transmit. This feature should be used for Asynchronous Stream TX only. For any type of packet other than Asynchronous Stream, do not enable this feature. 1.16.4 Broadcast Receive FIFO: This FIFO is designed to receive all broadcast packets, such as self-Ids, broadcast asynchronous packets, and PHY packets. The broadcast receive FIFO is 512 bytes in size to accommodate self-Ids for a 63-node network. This FIFO is accessed separately for software convenience. It is only accessible by the external or internal CPU. This FIFO is only for receive operations. All transmit operations must take place using an asynchronous transmit FIFO. Refer to Figure 48: Broadcast Receive FIFO for a block diagram of the broadcast FIFO architecture.
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Broadcast Receive FIFO 512 bytes
External or Internal Host
Packetizer/ Receiver
Figure 48: Broadcast Receive FIFO
1.16.5 FIFO Priority For two FIFOs that are the same data type, the lower number FIFO always has priority. For example, if the iceLynx-Micro were configured for two Asynchronous Transmit FIFOs, FIFO 0 and 1, FIFO 0 would have priority over FIFO 1. 1.16.6 FIFO Monitoring The FIFO size is monitored by several interrupts and status bits. An example of these monitoring bits is included in Table 45: FIFO Monitoring Bits. Table 45: FIFO Monitoring Bits Name Watermark High (Iso*CPUInt.Wtr Mrk*, Iso*BufStat.Wtr Mrk*) Watermark Low (Iso*CPUInt.Wtr Mrk*, Iso*BufStat.Wtr Mrk*) Cell Available (Iso*CPUInt.Cell Avail, Iso*BufStat.Cell Avail) Quadlets Available (Iso*BufStat.Qua dAvail) Notes: Description The watermark control (Iso*WtrMrk.Control*) needs to be set to 1. The watermark level is programmed at Iso*WtrMrk.Level*. When the level in the FIFO is above the programmed value at Iso*WtrMrk.Level*, the Watermark High is activated. The watermark control (Iso*WtrMrk.Control*) needs to be set to 0. The watermark level is programmed at Iso*WtrMrk.Level*. When the level in the FIFO is below the programmed value at Iso*WtrMrk.Level*, the Watermark Low is activated. A full 1394 packet (or individual cell: 188-bytes for DVB, 480-bytes for DV, 130 or 140 bytes for DSS) is available in the FIFO. This is valid for transmit or receive. This value reflects the Number of quadlets currently in FIFO. This is valid for transmit or receive.
The FIFO Watermark levels are only checked on packet boundaries. If the buffer is not a multiple of (packet _length+ header length) and the watermark level is programmed between BUFFER SIZE and (BUFFER SIZE - 1 Packet Length - Header Length), Watermark Level indicators (Iso*CPUInt.WtrMrk*, Iso*BufStat.WtrMrk*) are not activated.
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TEXAS INSTRUMENTS 1.17 GPIO Configurations
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
GPIOs can be configured to achieve the following: DSS TX - DSS SCC (System Clock Count) Input and DSS Error Flag Watermark Level indicatoor in FIFOs Flow Control GPIO Interrupts. There are four possible GPIO interrupts. These are configured as ARM FIQ or IRQs. Note: GPIO interrupts are synchronously detected. The interrupt must be held at the level for at least one 50MHz clock cycle. (for both level sensitive and edge sensitive interrupts) Example: The FIQ and IRQ GPIOs are programmed in CFR. For example, the FIQ interrupt is input using GPIO9. 1. The GPIOCfg.GPIO9Sel is set to "general purpose input." 2. The GPIOIntCfg.GPIOInt*Sel bits (or GPIOIntCfg.GPIOIntYSel bits) are set to reference GPIO 9. 3. The edge detection is set in GPIOIntCfg.GPIOInt*Det bit. 4. After this setup is complete, the InCPUInt.GPIO* (or InCPUInt.GPIOY) bit indicates when the programmed edge occurs on FIQ GPIO. This must be enabled in IntCPUHiIntEn.GPIO*. The GPIOData.GPIO9 indicates the GPIO9 status. Table 46: Summary of GPIO use GPIO function DSS SCC Input DSS Error Flag Wather Marks for Iso FIFOs Programmable GPIOs GPIO 2, GPIO 3 for HSDI 0 GPIO 6, GPIO 7 for HSDI 1 GPIO 0, 1 for Iso Data Path 0 GPIO 4, 5 for Iso Data Path 1 Note: All GPIOs (i.e. GPIO 0 through GPIO 10) can be configured as General Purpose Input/Output.
1.17.1 GPIO Setup The Flow Control writes to GPIOs through the software functions. The GPIO is set up as a general-purpose input or output. The values are read/written using the GPIOStat CFR for the appropriate GPIO. The Watermark GPIOs are linked to the watermark status bits.
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TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
1.18 IEEE 1394a-2000 Requirements 1.18.1 Features iceLynx-Micro is compliant to the IEEE 1394a-2000 standard. features: Arbitrated (short) bus reset Ack-accelerated arbitration Fly-by concatentation Multi-speed packet concatentation PHY ping packets Priority arbitration Port disable, suspend, and resume 1.18.2 Cycle Master The hardware automatically makes the node cycle master. This depends on the root status of the node. If LinkCfg.CycMasAuto =1 and the node is root, the node becomes the cycle master after the next bus reset. The software should set LinkCfg.CycMasAuto = 1 at initialization phase immediately after device reset or power-up. This requires the following
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
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JUNE 10, 2003
98
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
2
2.1 2.2
Appendix A: Configuration Registers
Configuration Registers Description Notes R - Bit location is read by software R0- Bit location is read by software and always returns 0 when read R1 - Bit location is read by software and always returns 1 when read R0W - Bit location is read by software and always returns 0 when read. Bit location can also be written by software. RCS - Bit location is read. Writing a "1" to the bit clears the field. The bit is synchronously updated. RS - Bit location is read by software and is synchronously updated RW - Bit location is read and written by software RWS - Bit location is read and written by software. Bit is synchronously updated. RM - Read, write to 1 modify. The result of the write depends on which CPU (internal or external) performed the write. This function is used for CPU communication interrupts. For the External CPU interrupts, a write from the internal CPU sets the bit. A write from the external CPU clears the bit. For the Internal CPU interrupts, a write from the internal CPU clears the bit. A write from the external CPU sets the bit.
The configuration registers are maintained in a separate document.(TBD)
2.3
CFR Address Ranges (Offset from CFR Base Address)
CFR Base Address is offset 10 0000 hex. Table 47: CFR Address Ranges Name SYS LLC IsoDP0 IsoDP1 Aud0 Aud1 AsyTx0 AsyTx1 AsyRx0 AsyRx1 BrdCstRx PLL Starting Address Offset (hex) 000 0A0 100 230 360 3E0 460 4B0 500 550 5A0 5E0 Ending Address Offset ( hex) 09F 0FF 22F 35F 3DF 45F 4AF 4FF 54F 59F 5DF 62F
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
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TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 2.4 Register Access
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
The IntCPUCfg.CFRLock bit is included to lock the ex-CPU from all DTCP related registers. When this bit is set to 1, the ex-CPU cannot access these registers. All register access by the external CPU are 32-bits. During reads, a "snap shot" value is used for both the lower and upper 16-bit accesses. This "snap shot" value is created during the first access to the register. It expires after a short amount of time. For the internal ARM, some registers have restricted accesses. 32-bit Access only. These registers can only be accessed 32-bits at a time. CycTmr AsyTx*AckBuffer Anc*Data 32-bit write access while the associated function is being used. 32/16/8 bit access during read accesses and when the associated function is not being used. Iso*TmStmp Iso*CIP1 Iso*FltrCIP1 Iso*MskCIP1 PLL*Cfg2 PLL*Cfg3 PLL*Cfg4 PLL*Cfg5 Aud*NoData 16-bit write access while the associated function is being used. 32/16/8 bit access during all read accesses and while the associated function is not being used Timer0 Timer1 Timer2 BusRstDat (read only register) Iso0BufStat HSDI0Cfg Iso*WtrMrk Iso*Hdr Iso*FltrIsoHdr Iso*MskIsoHdr Iso*DVTmgCtl Iso*DVTmgCfg Anc*Data Anc*Def Anc*Data1 Anc*Data2 Anc*NoData AsyRx*WtrMrk AsyTx*WtrMrk AsyTx*StrmHdr
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
100
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
3
3.1
General Information
Package Size
iceLynx-Micro includes two package options: 176 pin microstar BGA and 176 pin QFP. 3.2 Operating Voltage Nominal Voltage 3.3 V Max Voltage 3.6 V
Min Voltage 3.0 V Note: I/Os are not 5V tolerant.
3.3
Operating Temperature MIN -20 NOM MAX 70 Unit
O
Operating ambient temperature
C
4
Absolute Maximum Ratings Over Operating Temperature Ranges
AVdd Vdd PLL_Vdd - 0.3 V to 4.0 V - 0.3 V to 4.0 V - 0.3 V to 4.0 V 20 mA 20 mA HBM: 2 kV See Dissipation Rating Table -20 OC to 70 OC - 65 OC to 150 OC 260 OC
Supply voltage range:
Input clamp current, IIK (VI < 0 or VI > VDD) (see Note 1) Output clamp current, IOK (VO < 0 or VO > VDD) (see Note 2) Electrostatic discharge (see Note 3) Continuous total power dissipation Operating free-air temperature, TA Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds
Stresses beyond those listed under absolute maximum ratings causes permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability. NOTES: 1. Applies to external input and bi-directional buffers 2. Applies to external output and bi-directional buffers. 3. HBM is human body model, MM is machine model. DISSIPATION RATING TABLE PACKAGE
O O
= 25 C TA POWER RATING 1.1 W *BGA 176 # 0.8 W *BGA 176 * TQFP 176 # 1.8 W TQFP 176 * 1.3 W Notes: 1) *: Standard JEDEC Low-K board 2) #: Standard JEDEC High-K board
DERATING FACTOR O ABOVE TA = 25 C O 13.8 W/ C O 10.4 W/ C O 22.6 W/ C O 16.5 W/ C
TA = 70 POWER RATING 0.5 W 0.4 W 0.8 W 0.6 W
C
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
101
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 4.1
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Recommended Operating Conditions (Analog IEEE 1394 I/F)
TEST CONDITION MIN 3 3 2.7 LVCMOS terminals LVCMOS terminals LVCMOS terminals TPBIAS outputs Cable inputs, during data reception Cable inputs, during arbitration 0 2 0 - 5.6 118 168 0.9706 0.4706 96.6 107 113 128 2 TBD 1.08 0.5 0.315 0.8 0.55 0.5 ms ms ns ns ns ns ns ns NOM 3.3 3.3 3 MAX 3.6 3.6 3.6 Vdd Vdd 0.8 1.3 260 265 2.515 2.015
UNIT V V V V V V mA mV
Analog voltage, AVdd Supply voltage, Vdd PLL Supply voltage, PLL_Vdd Output voltage, VO High-level input voltage, VIH Low-level input voltage, V Output current, IO Differential input voltage, VID Common-mode input voltage, VIC Maximum junction temperature, TJ
IL
TPB cable inputs, source power node TPB cable inputs, nonsource power node 176-PQFP high-K JEDEC board O O RJA =44.3 C /W, TA = 70 C, Pd = 0.6 W 176-PQFP low-K JEDEC board O O RJA = 60.8 C /W, TA = 70 C, Pd = 0.6 W 176-u*BGA high-K JEDEC board O O RJA = 72.5 C /W, TA = 70 C, Pd = 0.6 W 176-u*BGA low-K JEDEC board O O RJA = 96.7 C /W, TA = 70 C, Pd = 0.6 W
V
O
C
Power-up reset time, tpu Power-up reset time, tpu Receive input jitter
RESETn input RESET_ARMn input TPA, TPB cable inputs, S100 operation TPA, TPB cable inputs, S200 operation TPA, TPB cable inputs, S400 operation
Receive input skew
Between TPA and TPB cable inputs, S100 operation Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation

Applies to external inputs and bi-directional buffers without hysteresis. Applies to external output buffers. For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a-2000.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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102
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Electrical Characteristics (unless otherwise noted)
PARAMETER VOH VOL IOZ IIL IIH High-level output voltage Low-level output voltage 3-state output high-impedance Low-level input current High-level input current
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7 Over Recommended
OPERATION TEST CONDITIONS IOH = - 2 mA IOL = 6 mA Output pins Input pins I/O pins
Operating
MIN 2.4
Conditions
MAX UNIT V 0.5 20 20 V A A A
3.6 V 3.6 V 3.6 V 3.6 V
VO = Vdd or GND VI = GND VI = GND VI = Vdd 20 20
For I/O terminals, input leakage (IIL and IIH) includes IOZ of the disabled output.
4.2
Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted)
TEST CONDITIONS MIN TYP 180 MAX UNIT mA 7.5 2.015 - 20 - 20 V V A
Device
PARAMETER Idd VTH VO IIRST Supply current (internal voltage regulator enabled, See Note 4 REG_ENn = L) Power status threshold, CPS input TPBIAS output voltage Pullup current (RESETn input)
400-k resistor VI = 1.5 V VI = 0 V
4.7 1.665 - 90 - 90
At rated IO current
Measured at cable power side of resistor. NOTES: 4. Conditions: VDD = 3.3V HSDI0: MPEG TS Tx (mode-7) HSDI1: Audio Rx (IEC60958, 44.1kHz) 3 Ports Connected Cipher not enabled ARM: Application PGM running
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
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JUNE 10, 2003
104
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS Driver
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
TEST CONDITIONS 56 , see Figure 1-1 Drivers enabled, speed signaling off S200 speed signaling enabled S400 speed signaling enabled Drivers disabled, see Figure 1-1 MIN 172 - 1.05 - 4.84 - 12.4 MAX 265 1.05 - 2.53 - 8.10 20 UNIT mV mA mA mA mV
PARAMETER VOD Differential output voltage IDIFF Driver difference current, TPA+, TPA-, TPB+, TPB ISP200 Common-mode speed signaling current, TPB+, TPB ISP400 Common-mode speed signaling current, TPB+, TPB VOFF Off state differential voltage
Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB - algebraic sum of driver currents. Limits defined as absolute limit of each of TPB+ and TPB - driver currents.
TPAx+ TPBx+
56
TPAxTPBx-
Figure 49: Test Load Diagram Receiver
PARAMETER ZID Differential impedance ZIC VTH-R VTH-CB VTH+ VTHVTH-SP200 VTH-SP400 Common-mode impedance Receiver input threshold voltage Cable bias detect threshold, TPBx cable inputs Positive arbitration comparator threshold voltage Negative arbitration comparator threshold voltage Speed signal threshold Speed signal threshold TEST CONDITIONS Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled TPBIAS-TPA common mode voltage, drivers disabled TPBIAS-TPA common mode voltage, drivers disabled MIN 4 20 - 30 0.6 89 -168 49 314 24 30 1.0 168 - 89 131 396 TYP 7 MAX 10 4 UNIT k pF k pF mV V mV mV mV mV
4.3
PARAMETER
Thermal Characteristics
TEST CONDITIONS Board mounted, no air flow, JEDEC test board Board mounted, no air flow, JEDEC test board Board mounted, no air flow, JEDEC test board Board mounted, no air flow, JEDEC test board MIN TYP MAX 63.93 82.1 44.3 60.8 UNIT
O O O O
176-uBGA RJA, high-K board 176-uBGA RJA, low-K board 176-PQFP RJA, high-K board 176-PQFP RJA, low-K board
C /W C /W C /W C /W
4.4
PARAMETER
Switching Characteristics for PHY Port Interface
TEST CONDITIONS Between TPA and TPB Between TPA and TPB 10% to 90%, at 1394 connector 90% to 10%, at 1394 connector 0.5 0.5 MIN TYP MAX 0.15 0.10 1.2 1.2 UNIT ns ns ns ns
Jitter, transmit Skew, transmit tr tf TP differential rise time, transmit TP differential fall time, transmit
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
105
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 4.5
PARAMETER Vdd VIH VIL PLL_Vdd High-level input voltage Low-level input voltage Input clock frequency Input clock frequency tolerance Input slew rate Input clock duty cycle
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
Operating, Timing, and Switching Characteristics of XI
MIN 3.0 TYP 3.3 0.63 Vdd 0.33 Vdd 24.576 <100 0.2 40% 4 60% MAX 3.6 UNIT V\ V V MHz PPM V/ns
Note - When using an external clock, input is supplied to XI, the XO terminal must be left unconnected and the XI clock must be stable before the 2 ms device reset begins.
5
Reset Power States
Table 48: Pin state during power on reset , just after power on reset and DISABLE_IFn=L
Pin name WTCH_DG_TMRn LOW_PWR_RDY MCIF_INTz MCIF_CS_IOz= MCIF_CS_MEMz MCIF_ACKz MCIF_WAITz MCIF_DATA[15:0] HSDI*_D[0] HSDI*_D[7:1] HSDI*_EN HSDI*_SYNC HSDI*_DVALID HSDI*_AV HSDI*_AMCLK_OUT HSDI1_AUDIO_ERR HSDI1_AUDIO_MUTE MLPCM_LRCLK MLPCM_BCLK MLPCM_D{2:0] MLPCM_A HSDI*_60958_OUT RESETn==L&&DISABLE_IFn=L During power on Hiz 0 Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz RESETn=H && DISABLE_IFn=H Just after power on 0 0 1 Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz 0 Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz RESETn=H&&DISABLE_IFn=L DISABLE_IFn=L Hiz 0 Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz Hiz
Note: All CFR values are the default value.
6
Configuration Register Map
Refer to "Appendix A: TSB43CA43A & TSB43CA42 CFR Map Version 1.5" for the configuration Register map and descriptions.
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
106
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
7
7.1
Mechanical Data
PQFP Package Information
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
107
TSB43Cx43A/ TSB43CA42
TEXAS INSTRUMENTS 7.2
TI iceLynx-MicroTM IEEE 1394a-2000 Consumer Electronics Solution
Rev. 1.7
* BGA Package Dimensions
PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TEXAS INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
JUNE 10, 2003
108

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