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TSC2300
SLAS372 -- NOVEMBER 2002
PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH AUDIO CODEC
FEATURES APPLICATIONS
* *
* * * * * *
SPITM Serial Interface Touch screen Controller - 4-Wire Touch Screen Interface - Internal Detection of Screen Touch and Keypad Press - Touch Pressure Measurement - Ratiometric Conversion - Programmable 8, 10 or 12 Bit Resolution - Programmable Sampling Rates Up to 125 kHz - Direct Battery Measurement (0 to 6 V) - On-Chip Temperature Measurement - 4-by-4 Keypad Interface With Programmable De-bounce - Integrated Touch Screen Processor Reduces Host CPU Interrupts and Overhead - Internal Timing Control With Programmable Delays Audio Codec - 20-Bit Delta-Sigma ADC/DAC - Dynamic Range: 98 dB - Sampling Rate Up To 48 kHz - I2S Serial Interface Full Power Down Control On-Chip Crystal Oscillator 6 GPIO Pins Single 2.7-V to 3.6-V Supply 64-pin TQFP Package
* * * * *
Personal Digital Assistants Cellular Phones MP3 Players Internet Appliances Smartphones
DESCRIPTION
The TSC2300 is a highly integrated PDA analog interface circuit. It contains a complete 12-bit A/D resistive touch screen converter including drivers, touch pressure measurement capability, keypad controller and 8-bit D/A converter output for LCD contrast control. The TSC2300 offers programmable resolution of 8, 10, and 12 bits and sampling rates up to 125 kHz to accommodate different screen sizes. The TSC2300 interfaces to the host controller through a standard SPI serial interface. The TSC2300 features a high-performance 20-bit, 48-ksps audio codec with highly integrated analog functionality. The audio portion of the TSC2300 contains microphone input with built-in pre-amp and microphone bias circuit, an auxiliary stereo analog input, a stereo line-level output, a differential mono line-level output, and a stereo headphone amplifier output. The digital audio data is transferred through a standard I2S interface. The TSC2300 also offers two battery measurement inputs capable of battery voltages up to 6 V, while operating at a supply voltage of only 2.7 V. It also has an on-chip temperature sensor capable of reading 0.3C resolution. The TSC2300 is available in a 64-lead TQFP. US Patent No. 6246394 SPI is a trademark of Motorola.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002, Texas Instruments Incorporated
TSC2300
SLAS372 -- NOVEMBER 2002 MICBIAS AFILT
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AVDD 20 k VCM 20 k AGND MICIN RLINEIN +12dB to -35dB 0.5dB steps LLINEIN
AVDD-1V I2S INTERFACE
I2SDIN I2SDOUT LRCLK BCLK
Mute, 0db, 6dB, 12dB
+20 to -40dB, 0.5dB Steps
317
-
ADC
Digital Audio Processing MCLK DVDD (2)
MONO+ MONO- VREF+ VREF- HPVDD HPGND HPR VOUTR VOUTL HPL Headphone Driver DAC Headphone Driver
DGND (2)
RESET

-
DAC
Digital Gain 0 to -63.5dB 0.5dB Steps
POL SCLK SS
DAC
-
Digital Gain 0 to -63.5dB 0.5dB Steps
CONTROL Control LOGIC and Interface SPI INTERFACE
MOSI MISO DAV PENIRQ
DACSET DACOUT VREFIN X+
X-
Y+ Y-
Touch Panel Drivers
KBIRQ Internal 2.5V/ 1.25V Reference
Temp Sensor VBAT1 VBAT2 AUX1 AUX2 Battery Monitor Battery Monitor
SAR ADC GPIO_0 GPIO_1
GPIO
GPIO_2 GPIO_3 GPIO_4
INTERFACE
Keypad Scanner and State Control
COI COO
OSC
GPIO_5/CLKO
C1 C2
C3 C4
R1 R2
R3
R4
2
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TSC2300
SLAS372 -- NOVEMBER 2002
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFICATION TEMPERATURE RANGE -40C to +85C ORDERING NUMBER TSC2300IPAG TSC2300IPAGR TRANSPORT MEDIA
TSC2300I
TQFP-64
PAG
Trays Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TSC2300 Supply voltage: Ground voltage differences: Digital input voltage Analog input voltage Ambient temperature under bias, TA Storage temperature, Tstg Junction temperature, TJ Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds AVDD, HPVDD, DVDD AGND, DGND 4V 0.1 V -0.3 V to (DVDD + 0.3 V) -0.3 V to (AVDD + 0.3 V) -40C to 125C -55C to 150C 150C 260C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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TSC2300
SLAS372 -- NOVEMBER 2002
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ELECTRICAL CHARACTERISTICS
At 25C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted.
PARAMETER AUXILARY ANALOG INPUTS Input voltage range Input capacitance Input leakage current BATTERY MONITOR INPUT Input voltage range Input capacitance Input leakage current TEMPERATURE MEASUREMENT Temperature range Temperature resolution Accuracy TOUCH SCREEN A/D CONVERTER Resolution No missing codes Integral linearity Offset error Gain error Noise AUDIO CODEC Sampling frequency AUDIO I/O Audio in Audio out AUDIO ADC Signal-to-noise ratio, A-weighted Total harmonic distortion Full-scale input voltage Transition band Stop band Stop band rejection AUDIO DAC Full-scale output voltage Signal-to-noise ratio, A-weighted Total harmonic distortion Frequency response Transition band Stop band Stop band rejection 4 1 kHz input 1 kHz, 0 dB input 20 0.45Fs 0.55Fs 65 DAC performance measured at Line Outputs using Fs=48 KHz 0.18* AVDD 98 -100 0.45Fs 0.55Fs 3.5Fs Vrms dB dB Hz Hz Hz dB 0.45Fs 0.55Fs 70dB Line, Mic inputs Line outputs ADC performance measured using Fs=48 KHz 1 kHz input 1 kHz, -0.5 dB input 80 88 -70 0.18* AVDD 0.55Fs 127Fs -60 dB dB Vrms Hz Hz 0.15* AVDD 0.15* AVDD 0.65* AVDD 0.65* AVDD V V 48 kHz <300 Programmable: 8-, 10-,12-Bits 12-bit resolution 10 6 6 6 12 Bits Bits LSB LSB LSB V RMS -40 0.3 2 +85 C C C 0.5 25 1 6.0 V F A 0 25 1 +VREFIN V F A CONDITIONS TSC2300 MIN TYP MAX UNITS
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TSC2300
SLAS372 -- NOVEMBER 2002
ELECTRICAL CHARACTERISTICS (continued)
At 25C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted.
PARAMETER HEADPHONE DRIVER Output power per channel CONDITIONS DAC playback through headphone driver R=32 R=16 R=16 VDD=3.6V Signal-to-noise ratio, A-weighted Total harmonic distortion D/A CONVERTER Output current range Resolution VOLTAGE REFERENCE Voltage range Reference drift Current drain DIGITAL INPUT / OUTPUT Internal clock frequency Logic family Logic level: VIH VIL VOH VOL POWER SUPPLY REQUIREMENTS Power supply voltage DVDD, AVDD, HPVDD Quiescent current (1) Touch screen only Touch screen only Playback only Voice Record only Power down (1) 1 kHz SAR sample rate, external Vref 20 kHz SAR sample rate, internal Vref 44.1 kHz Playback, VDD=2.7V Mono 8 kHz record, VDD=2.7V Audio fully powered down 14 1.7 10 5.8 .05 A mA mA mA A 2.7 3.6 V IIH=5A IIL=5A IOH=2 TTL loads IOL=2 TTL loads 0.7VDD -0.3 0.8* DVDD 0.2* DVDD 0.3VDD 8.8 CMOS V V V V MHz Internal 2.5 V 2.34 2.49 50 20 2.54 V ppm/ C A Measured with ARNG floating 0.75 1.10 8.8 mA Bits R=32 1 kHz, 0 dB input R=16 1 kHz, -3 dB input 85 14 27 32 96 -83 -77 -70 mW mW mW dB dB dB TSC2300 MIN TYP MAX UNITS
For more details on power consumption, see the Audio Codec section of the description overview.
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TSC2300
SLAS372 -- NOVEMBER 2002
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PIN ASSIGNMENT (TOP VIEW)
NC VCM MICBIAS MICIN
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MONO+ 49 MONO- 50 VOUTR 51 VOUTL 52 AGND 53 AVDD 54 HPL 55 HPR 56 HPGND 57 X- 58 Y- 59 X+ 60 Y+ 61 HPVDD 62 AUX1 63 AUX2 64
RLINEIN LLINEIN C4 C3 C2 C1 R4 R3 R2
VREF- VREF+ AFILT
32 31 30 29 28 27
TSC2300
26 25 24 23 22 21 20 19 18 17
R1 RESET KBIRQ DGND DVDD I2SDOUT I2SDIN LRCLK BCLK MCLK COO COI DAV MISO MOSI SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VREFIN DACSET DACOUT
PENIRQ POL GPIO_0
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 O O I I/O I/O I/O I/O I/O I/O I I/O I I I/O NAME VBAT1 VBAT2 VREFIN ARNG AOUT PENIRQ POL GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 DVDD DESCRIPTION Battery monitor input 1 Battery monitor input 2 SAR reference voltage DAC analog output range set Analog output current from DAC Pen interrupt SPI clock polarity General-purpose input/output pin General-purpose input/output pin General-purpose input/output pin General-purpose input/output pin General-purpose input/output pin Digital voltage supply
GPIO_5/CLKO General-purpose input/output pin/buffered oscillator clock out
6
GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5/CLKO DVDD DGND SS
VBAT1 VBAT2
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TSC2300
SLAS372 -- NOVEMBER 2002
PIN DESCRIPTION (continued)
PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 I/O I I I I O O I O I I I I O I I O I O O O O I I I I I I I O O O O I I O O O O I I O O I I I NAME DGND SS SCLK MOSI MISO DAV COI COO MCLK BCLK LRCLK I2SDIN I2SDOUT DVDD DGND KBIRQ RESET R1 R2 R3 R4 C1 C2 C3 C4 LLINEIN RLINEIN MICIN MICBIAS VCM NC AFILT VREF+ VREFMONO+ MONOVOUTR VOUTL AGND AVDD HPL HPR HPGND XYDESCRIPTION Digital ground Slave select input (active low). Data is not clocked into DIN unless SS is low. When SS is high, MOIS is high impedance. SPI clock input SPI data input. Data is clocked in at SCLK rising edge SPI data output. Data is clocked out at SCLK falling edge. High impedance when SS is high. Data available (active low). Crystal input Crystal output Master clock input for audio codec I2S bit clock I2S left/right clock I2S serial data in I2S serial data out Digital voltage supply Digital ground Keypad interrupt (active low). Indicates a key has been depressed Device reset (active high) Keypad row 1 Keypad row 2 Keypad row 3 Keypad row 4 Keypad column 1 Keypad column 2 Keypad column 3 Keypad column 4 Left-channel analog input to audio codec Right-channel analog input to audio codec Analog input from microphone Bias voltage output Common-mode voltage bypass capacitor No connection Audio ADC antialiasing filter capacitor Audio codec positive reference voltage Audio codec negative reference voltage Mono differential output Mono differential output Audio right line output Audio left line output Analog ground Analog supply Headphone amplifier left output Headphone amplifier right output Analog ground for headphone amplifier and touch screen circuitry X- position input Y- position input
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TSC2300
SLAS372 -- NOVEMBER 2002
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PIN DESCRIPTION (continued)
PIN 60 61 62 63 64 I/O I I I I I NAME X+ Y+ HPVDD AUX1 AUX2 DESCRIPTION X+ position input Y+ position input Analog supply for headphone amplifier and touch screen circuitry SAR auxiliary analog input 1 SAR auxiliary analog input 2
TIMING DIAGRAM
SS tLead SCLK t sck tw sck tw sck tv MISO ta tsu MOSI MSB IN thi BIT . . . 1 LSB IN MSB OUT tho BIT . . . 1 LSB OUT tdis tf tr tL ag t td
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TSC2300
SLAS372 -- NOVEMBER 2002
TIMING CHARACTERISTICS (1)
(2)
All specifications typical at -40C to +85C, +VDD = +2.7 V.
PARAMETER SCLK period Enable lead time Enable lag time Sequential transfer delay Data setup time Data hold time (inputs) Data hold time (outputs) Slave access time Slave DOUT disable time Data valid Rise time Fall time tsck tLead tLag ttd tsu thi tho ta tdis tv tr tf SYMBOL MIN 30 15 15 30 10 10 0 15 15 10 30 30 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
(1) (2)
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram, above.
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TSC2300
SLAS372 -- NOVEMBER 2002
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TYPICAL CHARACTERISTICS
At TA = +25C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
CHANGE IN GAIN ERROR vs TEMPERATURE
1 0.5 0.5 Change in Error (LSB) 0.4 0.3 Change in Error (LSB) 0 0.2 0.1 Idd (mA) 50 0 Temperature (5C) 100 0 -0.1 -0.2 1.7 -0.3 -0.4 -2 -50 0 50 100 -0.5 -50 1.65 1.6 -50 1.85 1.8 1.75
CHANGE IN OFFSET ERROR vs TEMPERATURE
CONVERSION SUPPLY CURRENT vs TEMPERATURE
2 1.95 1.9
-0.5 -1
-1.5
Temperature (5C)
50 0 Temperature (5C)
100
Figure 1 TOUCH SCREEN DRIVER ON-RESISTANCE vs TEMPERATURE
6.5 1.202 1.201
Figure 2
Figure 3 INTERNAL OSCILLATOR FREQUENCY vs TEMPERATURE
9.1 9 Internal Oscillator Frequency 8.9 8.8 osc 8.7 8.6 8.5 8.4
INTERNAL 1.25-V REFERENCE vs TEMPERATURE
6 On-Resistance (Ohms)
1.2 1.199
5.5 Vref (V) 1.198 1.197 1.196 4.5 1.195 1.194 4 -50 0 50 100 Temperature (5C) 1.193 -50
5
0
50
100
-50
0
50
100
Temperature (5C)
Temperature (5C)
Figure 4 INTERNAL 2.5-V REFERENCE vs TEMPERATURE
2.5 2.495 2.49 2.485 Vref (V) 2.48 2.475 2.47 1.235 2.465 2.46 -50 1.23 1.225 100 0.9 -50 1.275 1.27 1.15 1.265 DAC Output Current (mA) 1.26 1.255 1.25 1.245 1.24 1.2
Figure 5 DAC OUTPUT CURRENT vs TEMPERATURE
900
Figure 6 TEMP2 DIODE VOLTAGE vs TEMPERATURE
800 Temp2 Voltage (mV) 0 50 100 1.1
1.05
700
1
600
0.95
0
50
500 -60 -40 -20 0 20 40 60 Temperature (5C) 80 100
Temperature (C)
Temperature (C)
Figure 7 10
Figure 8
Figure 9
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TSC2300
SLAS372 -- NOVEMBER 2002
TEMP1 DIODE VOLTAGE vs TEMPERATURE
750 700 650 Vmicbias (V) 600 550 500 2.095 450 400 -50 50 0 Temperature (5C) 100 2.09 2.085 -50 2.13 2.125 2.12 Temp1 Voltage (mV) 2.115
MICBIAS vs TEMPERATURE
TOTAL HARMONIC DISTORTION OF DAC (LINEOUT) vs TEMPERATURE
-97.00 -98.00 -99.00 THD (dBm) -100.00 -101.00 -102.00 -103.00 -104.00 -60 -40 -20
2.11 2.105 2.1
0
50
100
Temperature (C)
0 20 40 60 Temperature (5C)
80 100
Figure 10 SIGNAL-TO-NOISE RATIO OF DAC (LINEOUT) vs TEMPERATURE
99 98.875 98.75 -65.000 THD (dB) 98.625 SNR (dB) 98.5 98.375 98.25 -70.000 98.125 98 -60 -40 -20 0 20 40 60 80 100 Temperature (5C)
-71.000
Figure 11 TOTAL HARMONIC DISTORTION OF ADC (LINEIN) vs TEMPERATURE
-62.000 -63.000 -64.000 89 88 87 86 85 84 -72.000 -60 -40 -20 0 20 40 60 80 100 Temperature (5C) 83 -60 -40 -20 90
Figure 12 SIGNAL-TO-NOISE RATIO OF ADC (LINEIN) vs TEMPERATURE
-66.000 -67.000 -68.000 -69.000 SNR (dB)
0
20
40
60
80
100
Temperature (5C)
Figure 13 TOTAL HARMONIC DISTORTION OF DAC (HP DRIVER), 32LOAD vs TEMPERATURE
-70.000 -72.000 97 -74.000
Figure 14 SIGNAL-TO-NOISE RATIO OF DAC (HP DRIVER) vs TEMPERATURE
98
Figure 15 TOTAL HARMONIC DISTORTION OF BYPASS PATH vs TEMPERATURE
-98.0
-99.0
THD (dB)
-78.000
THD (dB)
THD (dB) -60 -40 -20 0 20 40 60 80 100
-76.000
96
-100.0
-80.000 -82.000 -84.000 -86.000 -60 -40 -20
95
-101.0
94
-102.0
93 0 20 40 60 80 100 Temperature (5C) Temperature (5C)
-103.0 -60 -40 -20
0 20 40 60 Temperature (5C)
80
100
Figure 16
Figure 17
Figure 18
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TSC2300
SLAS372 -- NOVEMBER 2002
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SIGNAL-TO-NOISE RATIO OF BYPASS PATH vs TEMPERATURE
102
TOTAL HARMONIC DISTORTION OF MONO PATH vs TEMPERATURE
-95 -96 -97 99 100
SIGNAL-TO-NOISE RATIO OF MONO PATH vs TEMPERATURE
101
100 SNR (dB) SNR (dB) SNR (dB) -98 -99 -100 97 97 -101 -102 -60 -40 -20 96 0 20 40 60 Temperature (5C) 80 100 -60 -40 -20 0 20 40 60 Temperature (5C) 80 100 98
99
98
96 -60 -40 -20 0 20 40 60 Temperature (5C) 80 100
Figure 19 1.25-V REFERENCE vs SUPPLY VOLTAGE
1.2005
Figure 20
Figure 21 SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE
5.35 5.3 5.25 On-Resistance (Ohms) 5.2 5.15 5.1 5.05 5 4.95 4.9
2.5-V INTERNAL REFERENCE vs SUPPLY VOLTAGE
2.4875
1.2004 2.48675 1.2003 2.486 Vref (V) Vref (V) 1.2002
2.48525
1.2001 1.2
2.4845
2.48375 1.1999 2.5
3 Vdd (V)
3.5
2.483 2.5 3 Vdd (V) 3.5
2.5
3 Vdd (V)
3.5
Figure 22
Figure 23
Figure 24 INTERNAL OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE
9
TEMP2 DIODE VOLTAGE vs SUPPLY VOLTAGE
730 611 610.8 728 Temp2 Voltage (mV) Temp1 Voltage (mV) 610.6 610.4 610.2 610 609.8 609.6 609.4 609.2 720 2.5 3 Vdd (V) 3.5 609 2.5
TEMP1 DIODE VOLTAGE vs SUPPLY VOLTAGE
Internal Oscillator Frequency (MHz)
8.9
726
8.8
724
8.7
722
8.6
8.5 3 Vdd (V) 3.5 2.5 3 Vdd (V) 3.5
Figure 25
Figure 26
Figure 27
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TSC2300
SLAS372 -- NOVEMBER 2002
DAC MAXIMUM CURRENT vs SUPPLY VOLTAGE
1.0899 0.45
POWER-DOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
INTEGRAL NONLINEARITY MAXIMUM vs SUPPLY VOLTAGE
4.5
0.375 DAC Output Current (mA) 1.0878
4.25
Supply Current (uA)
INL_Max (LSB)
0.3
4
0.225
3.75
1.0857
0.15
3.5
0.075 1.0836 2.5 3 Vdd (V) 3.5
3.25
0 2.5 3 Vdd (V) 3.5
3 2.5 3 Vdd (V) 3.5
Figure 28 INTEGRAL NONLINEARITY MINIMUM vs SUPPLY VOLTAGE
-1.5
Figure 29
Figure 30
CONVERSION SUPPLY CURRENT vs SUPPLY VOLTAGE
2 2.5
MICBIAS vs SUPPLY VOLTAGE
2.4
-1.75 1.75 INL_Min (LSB) -2 Idd_Total (mA)
2.3 2.2 Vmicbias (V) 2.5 3 Vdd (V) 3.5 2.1 2 1.9 1.8 1.7 1.6
-2.25
1.5
-2.5
1.25 -2.75
-3 2.5 3 Vdd (V) 3.5
1
1.5 2.5 3 Vdd (V) 3.5
Figure 31 TOTAL HARMONIC DISTORTION OF DAC (LINEOUT) vs SUPPLY VOLTAGE
-95 100
Figure 32 SIGNAL-TO-NOISE RATIO OF DAC (LINEOUT) vs SUPPLY VOLTAGE
Figure 33 TOTAL HARMONIC DISTORTION OF ADC (LINEIN) vs SUPPLY VOLTAGE
-67 -68
-96
99
-97
-69 -70
THD (dB)
THD (dB) 2.5 3 Vdd (V) 3.5
-98
98
-71 -72 -73 -74
-99
97
SNR (dB)
-100
96
-75 -76
-101
-102 2.5
95 3 Vdd (V)
3.5
-77 2.5 3 Vdd (V) 3.5
Figure 34
Figure 35
Figure 36 13
TSC2300
SLAS372 -- NOVEMBER 2002
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SIGNAL-TO-NOISE RATIO OF ADC (LINEIN) vs SUPPLY VOLTAGE
90 89 88 SNR (dB) THD (dB) 87 86 85 84 83 2.5 3 Vdd (V) 3.5
TOTAL HARMONIC DISTORTION OF DAC (HP DRIVER) vs SUPPLY VOLTAGE
-78 -79 -80 -81 -82 -83 -84 -85 2.5 SNR (dB) 99 98 97 96 95 94 93 92 3 Vdd (V) 3.5
SIGNAL-TO-NOISE RATIO OF DAC (HP DRIVER) vs SUPPLY VOLTAGE
2.5
3 Vdd (V)
3.5
Figure 37 TOTAL HARMONIC DISTORTION OF BYPASS PATH vs SUPPLY VOLTAGE
-98 102
Figure 38 SIGNAL-TO-NOISE RATIO OF BYPASS PATH vs SUPPLY VOLTAGE
Figure 39 TOTAL HARMONIC DISTORTION OF MONO PATH vs SUPPLY VOLTAGE
-95
-99
101
-96
THD (dB)
SNR (dB)
99
-101
THD (dB)
-100
100 -97
-98
98 -102 97 -103 2.5 -100 2.5 3 Vdd (V) 3.5 2.5 3 Vdd (V) 3.5 -99
3 Vdd (V)
3.5
96
Figure 40
Figure 41 SIGNAL-TO-NOISE RATIO OF MONO PATH vs SUPPLY VOLTAGE
102
Figure 42
101
100 SNR (dB)
99
98
97
96 2.5 3 Vdd (V) 3.5
Figure 43
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TSC2300
SLAS372 -- NOVEMBER 2002
OVERVIEW
The TSC2300 is an analog interface circuit for human interface devices. A register-based architecture eases integration with microprocessor-based systems through a standard SPI bus. All peripheral functions are controlled through the registers and onboard state machines. The TSC2300 consists of the following blocks (refer to the block diagram on p. 2): Touch Screen Interface Keypad Interface Battery Monitors Auxiliary Inputs Temperature Monitor Current Output Digital-to-Analog Converter Audio Codec and Signal Processing
* * * * * * *
Communication to the TSC2300 is via a standard SPI serial interface. This interface requires that the slave select signal be driven low to communicate with the TSC2300. Data is then shifted into or out of the TSC2300 under control of the host microprocessor, which also provides the serial data clock. Control of the TSC2300 and its functions is accomplished by writing to different registers in the TSC2300. A simple command protocol is used to address the 16-bit registers. Registers control the operation of the touch screen A/D converter, keypad scanner, and audio codec. The result of measurements made will be placed in the TSC2300's memory map and may be read by the host at any time. Three signals are available from the TSC2300 to indicate that data is available for the host to read. The DAV output indicates that an analog-to-digital conversion has completed and that data is available. The KBIRQ output indicates that an unmasked key on the keypad has been pressed and de-bounced. The PENIRQ output indicates that a touch has been detected on the touch screen. A typical application of the TSC2300 is shown in Figure 44.
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TSC2300
SLAS372 -- NOVEMBER 2002 MICROPHONE JACK HEADPHONE JACK 10 to 100
220F 220F A A 1 to 10 F A
VREF-
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Rbias
A 1nF A A 1F
Line Inputs KEYPAD
1F 0.1F A 1F
MICBIAS RLINEIN LLINEIN VREF+ MICIN VCM AFILT
15 14 13 12 11 10 9 8 7654 3210
1F
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C4 C3 C2 C1 R4 R3 NC R2 R1 32 RESET 31 KBIRQ 30 DGND 29 2 DVDD 8 I2SDOUT 27 I2SDIN 26
MONO AMP Line Outputs
49 MONO+
1F 1F A
50 MONO- 51 VOUTR 52 VOUTL 53 AGND 54 AVDD
D 0.1 F D 1 to 10 F
1 to 10 F
A
0.1F A A
55 HPL 56 HPR 57 HPGND 58 X-
D
TSC2300
LRCLK 25 BCLK 24 MCLK 23 COO 22 COI 21 DAV 20 GPIO_5/CLK0 MISO 19 MOSI 18 DVDD DGND SCLK 17 SS
1 M
15pF D
TOUCH SCREEN
1 to 10 F
59 Y- 60 X+ 61 Y+ 62 HPVDD PENIRQ VREFIN
15pF
D
GPIO_0
GPIO_1
GPIO_2
GPIO_3
VBAT1
VBAT2
ARNG
AOUT
64 AUX2
Auxilliary Inputs Voltage Regulator
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15 16
GPIO_4
A
0.1F A
63 AUX1 POL
D
1 to 10 F 1 to 10 F A 0.1F A D
0.1F D
Main Battery
A A
Secondary Battery Voltage Regulator
Rrng
A
LCD Contrast Control
Figure 44. Typical Circuit Configuration.
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TSC2300
SLAS372 -- NOVEMBER 2002
DETAILED DESCRIPTION OPERATION - TOUCH SCREEN
A resistive touch screen works by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where a screen is touched by an input stylus, pen, or finger. The change in the resistance ratio marks the location on the touch screen. The TSC2300 supports the resistive 4-wire configuration (see Figure 44). The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.
The 4-Wire Touch Screen Coordinate Pair Measurement
A 4-wire touch screen is constructed as shown in Figure 45. It consists of two transparent resistive layers separated by insulating spacers.
Conductive Bar Transparent Conductor (ITO) Bottom Side X+
Y+
Transparent Conductor (ITO) Top Side
X- Silver Ink Y-
Insulating Material (Glass) ITO= Indium Tin Oxide
Figure 45. 4-wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network. The A/D converts the voltage measured at the point where the panel is touched. A measurement of the Y position of the pointing device is made by connecting the X+ input to A/D converter input, driving Y+ to +VDD and Y- to GND using switches internal to the TSC2300, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion, due to the high input impedance of the A/D converter. Voltage is then applied to the other axis, and the A/D converts the voltage representing the X position on the screen. This provides the X and Y coordinates to the associated processor. Measuring touch pressure (Z) can also be done with the TSC2300. To determine pen or finger touch, the pressure of the touch needs to be determined. Generally, it is not necessary to have very high performance for this test, therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2300 supports two methods. The first method requires knowing the X-plate resistance, measurement of the X-Position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 46). Using equation 1 calculates the touch resistance:
R
TOUCH
+R
X-plate
X-position Z 2 *1 4096 Z1
(1)
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position and Y-position, and Z1. Using equation 2 will also calculate the touch resistance:
R R TOUCH +
X-position X-plate 4096
4096 * 1 Z 1
*R
Y-plate
1*
Y-position 4096
(2)
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TSC2300
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Measure X-Position X+ Touch X-Position X- Y- Y+
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Measure Z1-Position X+ Touch Z-Position X-
Y+
Y-
X+
Touch
Y+
Z 2 -Position
X-
Y-
Measure Z2-Position
Figure 46. Pressure Measurement
When the touch panel is pressed or touched, and the drivers to the panel are turned on, the voltage across the touch panel often overshoots and then slowly settles (decay) down to a stable dc value. This is due to mechanical bouncing, which is caused by vibration of the top layer sheet of the touch panel when the panel is pressed. This settling time must be accounted for, or else the converted value is in error. Therefore, a delay must be introduced between the time the driver for a particular measurement is turned on, and the time measurement is made. In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen, i.e. noise generated by the LCD panel or back-light circuitry. The value of these capacitors provides a low-pass filter to reduce the noise, but causes an additional settling time requirement when the panel is touched. Several solutions to this problem are available in the TSC2300. A programmable delay time is available which sets the delay between turning the drivers on and making a conversion. This is referred to as the panel voltage stabilization time, and is used in some of the modes available in the TSC2300. In other modes, the TSC2300 can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the command is issued to perform a conversion. The TSC2300 touch screen interface can measure position (X,Y) and pressure (Z). Determination of these coordinates is possible under three different modes of the A/D converter: conversion controlled by the TSC2300, initiated by detection of a touch; conversion controlled by the TSC2300, initiated by the host responding to the PENIRQ signal; or conversion completely controlled by the host processor.
A/D CONVERTER
The analog inputs of the TSC2300 are shown in Figure 47. The analog inputs (X, Y, and Z touch panel coordinates, battery voltage monitors, chip temperature and auxiliary inputs) are provided via a multiplexer to the successive approximation register (SAR) analog-to-digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture which inherently includes a sample/hold function. A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch on-resistances. The A/D is controlled by an A/D converter control register. Several modes of operation are possible, depending upon the bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate may all be programmed through this register. These modes are outlined in the sections below for each type of analog input. The results of conversions made are stored in the appropriate result register.
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TSC2300
SLAS372 -- NOVEMBER 2002
PENIRQ TEMP1 TEMP0 +VCC VREF
X+ X-
Ref ON/OFF
Y+ Y-
+IN -IN 1.25/2.5 V Reference
+REF Converter -REF
7.5 k VBAT1 VBAT2 5.0 k 5.0 k 2.5 k Battery on
Battery on IN1 IN2 GND
Figure 47. Simplified Diagram of the Touch Screen Analog Input Section Data Format
The TSC2300 output data is in straight binary format as shown in Figure 48. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.
FS = Full- Scale Voltage = VREF(1) 1 LSB = VREF(1)/4096 1 LSB 11...111 11...110 Output Code 11...101
00...010 00...001 00...000 0V Input Voltage(2) (A) NOTES: (1) Reference voltage at converter: +REF-(-REF). See Figure 4. (2) Input voltage at converter, after multiplexer: +IN-(-IN). See Figure 4 FS - 1 LSB
Figure 48. Ideal Input Voltages and Output Codes. Reference
The TSC2300 has an internal voltage reference that can be set to 1.2 V or 2.5 V, through the reference control register. This reference can also be set to automatically power down between conversions to save power, or remain on to reduce settling time. The internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs. Optimal touch screen performance is achieved when using a ratiometric conversion, thus all touch screen measurements are done automatically in the differential mode. An external reference can also be applied to the VREFIN pin, and the internal reference can be turned off.
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TSC2300
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Variable Resolution
The TSC2300 provides three different resolutions for the A/D converter: 8, 10 or 12 bits. Lower resolutions are often practical for measurements such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which lowers power consumption.
Conversion Clock and Conversion Time
The TSC2300 contains an internal 8-MHz clock, which is used to drive the state machines inside the device that perform the many functions of the part. This clock is divided down to generate the actual A/D conversion clock. The division ratio for this clock is set in the A/D converter control register. The ability to change the conversion clock rate allows the user to choose the optimal value for resolution, speed, and power. If the 8-MHz clock is used directly, the A/D converter is limited to 8-bit resolution; using higher resolutions at this speed will not result in accurate conversions. Using a 4-MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution requires that the conversion clock run at 1 or 2 MHz. Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion time of the TSC2300 is dependent upon several functions. While the conversion clock speed plays an important role in the time it takes for a conversion to complete, a certain number of internal clock cycles is needed for proper sampling of the signal. Moreover, additional times, such as the panel voltage stabilization time, can add significantly to the time it takes to perform a conversion. Conversion time can vary depending upon the mode in which the TSC2300 is used. Throughout this data sheet, internal and conversion clock cycles are used to describe the times that many functions take. In considering the total system design, these times must be taken into account by the user.
Touch Detect
The pen interrupt (PENIRQ) output function is detailed in Figure 49. While in the touch screen monitoring mode, the Ydriver is ON and connected to GND, the X+ input is connected through a pullup resistor to VDD, and the PENIRQ output reflects the state of the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen and PENIRQ output goes LOW due to the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycles for X- and Y-position, the X+ input is disconnected from PENIRQ to eliminate any leakage current from the pullup resistor that might flow through the touch screen, thus causing no errors.
PENIRQ
VDD VDD TEMP1 Internal 50 kW TEMP2
Y+
High Except When TEMP1, TEMP2 Activated
TEMP DIODE
X+
Y-
ON
Y+ or X+ Drivers on, or TEMP1, TEMP2 Measurements Activated
Figure 49. PENIRQ Functional Block Diagram.
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TSC2300
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In modes where the TSC2300 needs to detect if the screen is still touched (for example, when doing a PENIRQ-initiated X, Y, and Z conversion), the TSC2300 must reconnect the drivers so that the 50-k resistor is connected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs cause a long delay time, and may prevent the detection from occurring correctly. To prevent this, the TSC2300 has a circuit which allows any screen capacitance to be precharged through a low-resistance connection to VDD, so that the pullup resistor doesn't have to be the only source for the charging current. The time allowed for this precharge, as well as the time needed to sense if the screen is still touched, can be set in the configuration control register. All other drivers (X-,Y+, Y-) are off during precharging. This does point out, however, the need to use the minimum capacitor values possible on the touch screen inputs. These capacitors may be needed to reduce noise, but too large a value increases the needed precharge and sense times, as well as panel voltage stabilization time. In self-controlled modes where the TSC2300 automatically performs conversions when it detects a pen touch, it is generally not necessary for the host processor to monitor PENIRQ. Instead, the host should monitor DAV, which goes low when data is available in the appropriate data register, and returns high when all new data has been read back by the host.
DIGITAL INTERFACE
The TSC2300 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by a SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. The idle state of the serial clock for the TSC2300 is LOW, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The TSC2300 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the TSC2300 only interprets the first 16 bits transmitted after the falling edge of SS as a command word, and the next 16 bits as a data word only if writing to a register. Reserved register bits should be written to their default values (see Table 5).
TSC2300 Communication Protocol
The TSC2300 is entirely controlled by registers. Reading and writing these registers is accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in Table 3. The command word begins with an R/W bit, which specifies the direction of data flow on the serial bus. The following 4 bits specify the page of memory this command is directed to, as shown in Table 2. The next six bits specify the register address on that page of memory to which the data is directed. The last five bits are reserved for future use.
Table 2. Page Addressing
PG3 0 0 0 0 0 0 0 0 1 1 1 1 PG2 0 0 0 0 1 1 1 1 0 0 0 0 PG1 0 0 1 1 0 0 1 1 0 0 1 1 PG0 0 1 0 1 0 1 0 1 0 1 0 1 PAGE ADDRESSED 0 1 2 reserved reserved reserved reserved reserved reserved reserved reserved reserved 21
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Page Addressing (continued)
PG3 1 1 1 1 PG2 1 1 1 1 PG1 0 0 1 1 PG0 0 1 0 1 PAGE ADDRESSED reserved reserved reserved reserved
To read all the first page of memory, for example, the host processor must send the TSC2300 the command 0x8000 this specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the TSC2300. The TSC2300 automatically increments its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the TSC2300 simply sends back the value 0xFFFF. Continuous writing is generally not recommended for the control registers, but for the coefficients of BBCF registers, continuous writing works. Writing to these registers consists of the processor writing the command 0x10E0, which specifies a write operation, with PG1 set to 1, and the ADDR bits set to 07h. This results in the address pointer pointing at the location of the first bass-boost coefficient in memory see Table 4(Page 2). See the section on the TSC2300 memory map for details of register locations
Table 3. TSC2300 Command Word
BIT 15 MSB R/W* BIT 14 PG3 BIT 13 PG2 BIT 12 PG1 BIT 11 PG0 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB X
ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
X
X
X
X
Figure 50 shows an example of a complete data transaction between the host processor and the TSC2300.
Figure 50. Write and Read Operation of TSC2300 Interface.
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TSC2300
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TSC2300 MEMORY MAP
The TSC2300 has several 16-bit registers which allow control of the device as well as providing a location for results from the TSC2300 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the TSC2300: a data page (Page 0), a control page (Page 1), and an audio control page (Page 2). The memory map is shown in Table 4.
Table 4. TSC2300 Memory Map
PAGE 0: DATA REGISTERS ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F REGISTER X Y Z1 Z2 KPData BAT1 BAT2 AUX1 AUX2 TEMP1 Temp2T1 DAC reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved PAGE 1: CONTROL REGISTERS ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F REGISTER ADC KEY DACCTL REF RESET CONFIG CONFIG2 reserved reserved reserved reserved reserved reserved reserved reserved reserved1 KPMask1 reserved1 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved PAGE 2: AUDIOCONTROL REGISTERS ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F REGISTER Audio control ADC volume control DAC volume control Analog audio bypass volume control Keyclick control Audio power/ crystal oscillator control GPIO control DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients DAC bass-boost filter coefficients reserved reserved reserved reserved reserved
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TSC2300 REGISTER OVERVIEW
Table 5. Register Summary for TSC2300
PAGE ADDR (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 REGISTER NAME X Y Z1 Z2 KPDATA BAT1 BAT2 AUX1 AUX2 TEMP1 Temp2T1 DAC reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved ADC KEY DACCTL REF RESET CONFIG CONFIG2 reserved reserved reserved reserved reserved reserved reserved reserved reserved KPMASK reserved reserved reserved D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET VALUE (HEX) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0080 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4000 4000 8000 0002 FFFF FFC0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0000 FFFF FFFF FFFF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 K15 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PSM STC DPD 0 1 1 SDAV 1 1 1 1 1 1 1 1 1 M15 1 1 1
0 0 0 0 K14 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 STS SCS 0 0 0 1 1 1 1 1 1 1 1 1 1 1 M14 1 1 1
0 0 0 0 K13 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AD3 DB2 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M13 1 1 1
0 0 0 0 K12 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AD2 DB1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M12 1 1 1
R11 R11 R11 R11 K11 R11 R11 R11 R11 R11 R11 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AD1 DB0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M11 1 1 1
R10 R10 R10 R10 K10 R10 R10 R10 R10 R10 R10 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AD0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 M10 1 1 1
R9 R9 R9 R9 K9 R9 R9 R9 R9 R9 R9 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RS1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M9 1 1 1
R8 R8 R8 R8 K8 R8 R8 R8 R8 R8 R8 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RS0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M8 1 1 1
R7 R7 R7 R7 K7 R7 R7 R7 R7 R7 R7 D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AV1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M7 1 1 1
R6 R6 R6 R6 K6 R6 R6 R6 R6 R6 R6 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AV0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 M6 1 1 1
R5 R5 R5 R5 K5 R5 R5 R5 R5 R5 R5 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CL1 0 0 0 1 PR2 1 1 1 1 1 1 1 1 1 1 M5 1 1 1
R4 R4 R4 R4 K4 R4 R4 R4 R4 R4 R4 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CL0 0 0 INT 1 PR1 1 1 1 1 1 1 1 1 1 1 M4 1 1 1
R3 R3 R3 R3 K3 R3 R3 R3 R3 R3 R3 D3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PV2 0 0 DL1 1 PR0 1 1 1 1 1 1 1 1 1 1 M3 1 1 1
R2 R2 R2 R2 K2 R2 R2 R2 R2 R2 R2 D2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PV1 0 0 DL0 1 SN2 1 1 1 1 1 1 1 1 1 1 M2 1 1 1
R1 R1 R1 R1 K1 R1 R1 R1 R1 R1 R1 D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PV0 0 0 PDN 1 SN1 1 1 1 1 1 1 1 1 1 1 M1 1 1 1
R0 R0 R0 R0 K0 R0 R0 R0 R0 R0 R0 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 RFV 1 SN0 1 1 1 1 1 1 1 1 1 1 M0 1 1 1
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TSC2300
SLAS372 -- NOVEMBER 2002
REGISTER NAME reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET VALUE (HEX) FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF C003 D7D7 FFFF E7E7 4411 FFA4 0000 6BE2 9667 675D 6BE2 9667 675D 7D82 84EF 7D82 84EF 6BE2 9667 675D 6BE2 9667 675D 7D82 84EF 7D82 84EF 0400 FFFF 0000 0000 4000
Register Summary for TSC2300 (continued)
PAGE ADDR (HEX) 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1 HPF1 ADMU
1 1 1 1 1 1 1 1 1 1 1 1 HPF0 ADV6
1 1 1 1 1 1 1 1 1 1 1 1 INM1 ADV5
1 1 1 1 1 1 1 1 1 1 1 1 INM0 ADV4
1 1 1 1 1 1 1 1 1 1 1 1 0 ADV3
1 1 1 1 1 1 1 1 1 1 1 1 0 ADV2
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 I2SF0 1
AUDCNTL ADCVOL DACVOL BPVOL KEYCLICK PD/MISC GPIO BBCFN0L BBCFN1L BBCFN2L BBCFN3L BBCFN4L BBCFN5L BBCFD1L BBCFD2L BBCFD4L BBCFD5L BBCFN0R BBCFN1R BBCFN2R BBCFN3R BBCFN4R BBCFN5R BBCFD1R BBCFD2R BBCFD4R BBCFD5R reserved reserved reserved reserved reserved
MICG1 MICG0 MCLK1 MCLK0 I2SFS3 I2SFS2 I2SFS1 I2SFS0 I2SF1 ADV1 ADV0 1 1 0 1 0 1 1
DAMUL DAVL6 DAVL5 DAVL4 DAVL3 DAVL2 DAVL1 DAVL0 DAMUR DAVR6 DAVR5 DAVR4 DAVR3 DAVR2 DAVR1 DAVR0 BPMUL BPVL6 BPVL5 BPVL4 BPVL3 BPVL2 BPVL1 BPVL0 BPMUR BPVR6 BPVR5 BPVR4 BPVR3 BPVR2 BPVR1 BPVR0 KEYST KCAM2 KCAM1 KCAM0 APD 0 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 CF15 0 1 0 0 0 AVPD 0 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 CF14 0 1 0 0 1 ABPD IO5 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 CF13 0 1 0 0 0 0 KCFR2 KCFR1 KCFR0 KCLN3 KCLN2 KCLN1 KCLN0 DAPD IO2 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 CF10 1 1 0 0 0 ADPD IO1 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 CF9 0 1 0 0 0 1 IO0 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 CF8 0 1 0 0 0 PDSTS MIBPD OSCC 0 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 CF7 0 1 0 0 0 0 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 CF6 0 1 0 0 0 BCKC 0 MONS SSRTE SSTEP
HAPD MOPD IO4 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 CF12 0 1 0 0 0 IO3 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 CF11 0 1 0 0 0
SMPD OTSYN BASS DEEMP
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 CF5 0 1 0 0 0 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 CF4 0 1 0 0 0 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 CF3 0 1 0 0 0 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 CF2 0 1 0 0 0 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 CF1 0 1 0 0 0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 CF0 0 1 0 0 0
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TSC2300
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TSC2300 TOUCH SCREEN CONTROL REGISTERS
This section describes each of the registers shown in the memory map of Figure 54. The registers are grouped according to the function they control. Note that in the TSC2300, bits in control registers may refer to slightly different functions depending upon if you are reading the register or writing to it. A summary of all registers and bit locations is shown in Table 5.
TSC2300 A/D Converter Control Register (Page 1, Address 00H)
The A/D converter in the TSC2300 is shared between all the different functions. A control register determines which input is selected, as well as other options. The result of the conversion is placed in one of the result registers in Page 0 of memory, depending upon the function selected. The A/D Converter Control Register controls several aspects of the A/D converter. The register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 MSB PSM STS AD3 AD2 AD1 AD0 BIT 9 RS1 BIT 8 RS0 BIT 7 AV1 BIT 6 AV0 BIT 5 CL1 BIT 4 CL0 BIT 3 PV2 BIT 2 PV1 BIT 1 PV0 BIT 0 LSB X
Bit 15 -- PSM
Pen Status/Control Mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit determines the mode used to read coordinates: host controlled or under control of the TSC2300 responding to a screen touch. When reading, the PENSTS bit indicates if the pen is down or not. When writing to this register, this bit determines if the TSC2300 controls the reading of coordinates, or if the coordinate conversions are host-controlled. The default state is host-controlled conversions (0).
Table 6. PSM Bit Operation
PSM READ/WRITE Read Read Write Write VALUE 0 1 0 1 DESCRIPTION No screen touch detected (default) Screen touch detected Conversions controlled by host Conversions controlled by TSC2300
Bit 14 -- STS
A/D Status. Reading this bit indicates if the converter is busy. Writing a 0 to this bit causes the touch screen scans to continue until either the pen is lifted or the process is stopped. Continuous scans or conversions can be stopped by writing a 1 to this bit. This immediately halts a conversion (even if the pen is still down) and causes the A/D to power down. The default state is continuous conversions, but if this bit is read after a reset or power-up, it reads 1.
Table 7. STS Bit Operation
STS READ/WRITE Read Read Write Write VALUE 0 1 0 1 DESCRIPTION Converter is busy Converter is not busy (default) Normal operation Stop conversion and power down
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TSC2300
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Bits [13:10] -- AD3 - AD0
A/D Function Select bits. These bits control which input is to be converted, and what mode the converter is placed in. These bits are the same whether reading or writing. See Table 8 for a complete listing of how these bits are used.
Table 8. A/D Function Select
A/D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A/D2 A/D1 A/D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Invalid. No registers are updated. This is the default state after a reset. Touch screen scan function: X and Y coordinates converted and the results returned to X and Y data registers. Scan continues until either the pen is lifted or a stop bit is sent. Touch screen scan function: X, Y, Z1 and Z2 coordinates converted and the results returned to X, Y, Z1 and Z2 data registers. Scan continues until either the pen is lifted or a stop bit is sent. Touch screen scan function: X coordinate converted and the results returned to X data register. Touch screen scan function: Y coordinate converted and the results returned to Y data register. Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 data registers. Battery Input 1 converted and the results returned to the BAT1 data register. Battery Input 2 converted and the results returned to the BAT2 data register. Auxiliary Input 1 converted and the results returned to the AUX1 data register. Auxiliary Input 2 converted and the results returned to the AUX2 data register. A temperature measurement is made and the results returned to the temperature measurement 1 data register. Port scan function: Battery Input 1, Battery Input 2, Auxiliary Input 1, and Auxiliary Input 2 measurements are made and the results returned to the appropriate data registers A differential temperature measurement is made and the results returned to the temperature measurement 2 data register. Turn on X+, X- drivers Turn on Y+, Y- drivers Turn on Y+, X- drivers
Bits[9:8] -- RS1, RS0
Resolution Control. The A/D converter resolution is specified with these bits. SeeTable 9 for a description of these bits. These bits are the same whether reading or writing.
Table 9. A/D Converter Resolution Control
RS1 0 0 1 1 RS0 0 1 0 1 12-bit resolution. Power up and reset default. 8-bit resolution 10-bit resolution 12-bit resolution FUNCTION
Bits[7:6] -- AV1, AV0
Converter Averaging Control. These two bits (see Table 10) allow you to specify the number of averages the converter performs. Note that when averaging is used, the STS/STP bit and the DAV output indicates that the converter is busy until all conversions necessary for the averaging are complete. The default state for these bits is 00, selecting no averaging. These bits are the same whether reading or writing.
Table 10. A/D Conversion Averaging Control
AV1 0 AV0 0 None (one conversion) (default) FUNCTION
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A/D Conversion Averaging Control (continued)
AV1 0 1 1 AV0 1 0 1 4 data averages 8 data averages 16 data averages FUNCTION
Bits[5:4] -- CL1, CL0
Conversion Clock Control. These two bits specify the internal clock rate which the A/D converter uses when performing a conversion. See Table 11. These bits are the same whether reading or writing.
Table 11. A/D Converter Conversion Clock Control
CL1 0 0 1 1 CL0 0 1 0 1 FUNCTION 8-MHz internal clock rate - 8-bit resolution only (default) 4-MHz internal clock rate - 8- or 10-bit resolution only 2-MHz internal clock rate 1-MHz internal clock rate
Bits [3:1] -- PV2 - PV0
Panel Voltage Stabilization Time control. These bits allow the user to specify a delay time from when a driver is turned on to the time sampling begins and a conversion is started. In self-controlled mode, when a pen touch is detected, the part first turns on a driver, waits a programmed delay time set by PV2-PV0, and then begins sampling and A/D conversion. See Table 12 for settings of these bits. The default state is 000, indicating a 0s stabilization time. These bits are the same whether reading or writing.
Table 12. Panel Voltage Stabilization Time Control
PV2 0 0 0 0 1 1 1 1 PV1 0 0 1 1 0 0 1 1 PV0 0 1 0 1 0 1 0 1 0 sec. (default) 100 sec. 500 sec. 1 msec. 5 msec. 10 msec. 50 msec. 100 msec. STABILIZATION TIME
Bit 0
This bit is reserved. When read, it always reads as a zero.
DAC Control Register (Page 1, Address 02H)
The single bit in this register controls the power down control of the onboard digital-to-analog converter (DAC). This register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 MSB DPD X X X X X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 LSB X
Bit 15 -- DPD
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DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If the DAC is powered down, the AOUT pin neither sinks nor sources current.
Table 13. DPD Bit Operation
DPD VALUE 0 1 DESCRIPTION DAC is powered and operational DAC is powered down. (default)
Reference Register (Page 1, Address 03H)
This register controls whether the TSC2300 uses an internal or external reference, and if the internal reference is used, the value of the reference voltage, whether it powers down between conversions and the programmable settling time after reference power-up. This register is formatted as follows:
BIT 15 MSB X BIT 14 X BIT 13 X BIT 12 X BIT 11 X BIT 10 X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 INT BIT 3 DL1 BIT 2 DL0 BIT 1 PDN BIT 0 LSB RFV
Bit 4 --INT
Internal Reference Mode. If this bit is written to a 1, the TSC2300 uses its internal reference; if this bit is a 0, the part assumes an external reference is being supplied. The default state for this bit is to select an external reference (0). This bit is the same whether reading or writing.
Table 14. INT Bit Operation
INT VALUE 0 1 DESCRIPTION External reference selected (default) Internal reference selected
Bits [3:2] -- DL1, DL0
Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required for the reference to settle. If measurements are made before the reference has settled, these measurements are in error. These bits allow for a delay time for measurements to be made after the reference powers up, thereby assuring that the reference has settled. Longer delays are necessary depending upon the capacitance present at the VREFIN pin (see Typical Curves). The delays are shown in Table 15. The default state for these bits is 00, selecting a 0 microsecond delay. These bits are the same whether reading or writing.
Table 15. Reference Power-Up Delay Settings.
DL1 0 0 1 1 DL0 0 1 0 1 0us (default) 100 s 500 s 1000 s DELAY TIME
Bit 1 --PDN
Reference Power Down. If a 1 is written to this bit, the internal reference are powered down between conversions. If this bit is a zero, the internal reference is powered at all times. The default state is to power down the internal reference, so this bit will be a 1. This bit is the same whether reading or writing.
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Table 16. PDN Bit Operation
PDN VALUE 0 1 DESCRIPTION Internal reference is powered at all times Internal reference is powered down between conversions. (default)
Note that the PDN bit, in concert with the INT bit, creates a few possibilities for reference behavior. These are detailed in Table 17.
Table 17. Reference Behavior Possibilities
INT 0 0 1 1 PDN 0 1 0 1 REFERENCE BEHAVIOR External reference used, internal reference powered down. External reference used, internal reference powered down. Internal reference used, always powered up Internal reference used, powers up during conversions and then powers down.
Bit 0 -- RFV
Reference Voltage control. This bit selects the internal reference voltage, either 1.2 V or 2.5 V. The default value is 1.2 V. This bit is the same whether reading or writing.
Table 18. RFV Bit Operation
RFV Value 0 1 Description 1.2-V reference voltage (default) 2.5-V reference voltage
TSC2300 Configuration Control Register (Page 1, Address 05H)
This control register controls the configuration of the precharge and sense times for the touch detect circuit. The register is formatted as follows:
Bit 15 MSB RES Bit 14 RES Bit 13 RES Bit 12 RES Bit 11 RES Bit 10 RES Bit 9 RES Bit 8 RES Bit 7 RES Bit 6 RES Bit 5 PRE2 Bit 4 PRE1 Bit 3 PRE0 Bit 2 SNS2 Bit 1 SNS1 Bit 0 LSB SNS0
Bits [5:3] -- PRE[2:0]
Precharge time selection bits. These bits set the amount of time allowed for precharging any pin capacitance on the touch screen prior to sensing if the screen is being touched.
Table 19. Precharge Times
PRE[2:0] PRE2 0 0 0 0 1 PRE1 0 0 1 1 0 PRE0 0 1 0 1 0 TIME 20 s (default) 84 s 276 s 340 s 1.044 ms
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Precharge Times (continued)
PRE[2:0] PRE2 1 1 1 PRE1 0 1 1 PRE0 1 0 1 TIME 1.108 ms 1.300 ms 1.364 ms
Bits [2:0] -- SNS[2:0]
Sense time selection bits. These bits set the amount of time the TSC2300 will wait to sense a screen touch between coordinate axis conversions in self-controlled mode.
Table 20. Sense Times
SNS[2:0] SNS2 0 0 0 0 1 1 1 1 SNS1 0 0 1 1 0 0 1 1 SNS0 0 1 0 1 0 1 0 1 TIME 32 s (default) 96 s 544 s 608 s 2.080 ms 2.144 ms 2.592 ms 2.656 ms
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TSC2300 KEYPAD REGISTERS
The keypad scanner hardware in the TSC2300 is controlled by two registers: the keypad control register and the keypad mask register. The keypad control register controls general keypad functions such as scanning and de-bouncing, while the keypad mask register allows you to mask certain keys from being detected at all.
Keypad Control Register (Page 1, Address 01H)
The Keypad Control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 MSB STC SCS DB2 DB1 DB0 X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 LSB X
Bit 15 -- STC
Keypad Status. This bit reflects the operation of the KBIRQ pin, with inverted logic. This bit goes high when a key is pressed and debounced. The default value for this bit is 0.
Table 21. STC Bit Operation
STC VALUE 0 1 DESCRIPTION No keys are pressed (default) Key pressed and debounced
Bit 14 -- SCS
Keypad Scan Status. When reading, this bit indicates if the scanner or de-bouncer is busy. Writing a 0 to this bit causes keypad scans to continue until either the key is lifted or the process is stopped. Continuous scans can be stopped by writing a 1 to this bit. This immediately halts a conversion (even if a key is still down). The default value for this bit when read is 1.
Table 22. SCS Bit Operation
SCS READ/WRITE Read Read Write Write VALUE 0 1 0 1 DESCRIPTION Scanner or de-bouncer busy Scanner not busy (default) Normal operation Stop scans
Bits [13:11] -- KBDB2-KBDB0
Keypad De-bounce Control. These bits set the length of the de-bounce time for the keypad, as shown in Table 23. The default setting is a 2-mS de-bounce time (000).
Table 23. Keypad De-bounce Control
KBDB2 0 0 0 0 1 1 KBDB1 0 0 1 1 0 0 KBDB0 0 1 0 1 0 1 De-bounce: 2 ms (default) De-bounce: 10 ms De-bounce: 20 ms De-bounce: 50 ms De-bounce: 60 ms De-bounce: 80 ms Function
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Keypad De-bounce Control (continued)
KBDB2 1 1 KBDB1 1 1 KBDB0 0 1 De-bounce: 100 ms De-bounce: 120 ms Function
Keypad Mask Register (Page 1, Address 10H)
The Keypad Mask register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 MSB M15 M14 M13 M12 M11 M10 BIT 9 M9 BIT 8 M8 BIT 7 M7 BIT 6 M6 BIT 5 M5 BIT 4 M4 BIT 3 M3 BIT 2 M2 BIT 1 M1 BIT 0 LSB M0
This is the same format as used in the keypad data register (Page 0, Address 04H). Each bit in these registers represents one key on the keypad. In the mask register, if a bit is set (1), then that key is not detected in keypad scans. Pressing that key on the keypad also does not cause a KBIRQ, if the bit is set. If the bit is cleared (0), the corresponding key is detected when pressed. A 16-key keypad is mapped into the keypad mask (and keypad data) register as shown in Table 24. The default value for this register is 0000H, detecting all key presses.
Table 24. Keypad to Key Bit Mapping.
C1 R1 R2 R3 R4 K0 K4 K8 K12 C2 K1 K5 K9 K13 C3 K2 K6 K10 K14 C4 K3 K7 K11 K15
The result of a keypad scan appears in the keypad data register. Each bit is set in this register, corresponding to the key(s) actually pressed. For example, if only key 1 was pressed on a particular scan, the data in the register would read as 0x0002; however, if keys 6, 8, and 13 were all pressed simultaneously on that scan, the data would read as 0x2140. Multiple keys may be pressed simultaneously, and are generally decoded correctly by the keypad scan circuitry. However, keys that land on three corners of a rectangle may cause a false reading of a key on the fourth corner of the rectangle. For example, if keys 0, 3, and 11 were pressed simultaneously, the KEY0, KEY3, and KEY11 bits are set, but the KEY8 bit is also set. Thus, when considering using multiple-key combinations in an application, try to avoid combinations that put three keys on the corners of a rectangle.
Secondary Configuration Register (Page 1, Address 06H):
This register allows the user to read the status of the DAV pin through the SPI interface.
BIT 15 MSB SDAV BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 X X X X X BIT 9 X BIT 8 X BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 LSB X
Bit 15 -- SDAV
SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host processor to the TSC2300 DAV pin. This bit is normally high, goes low when touch screen or ADC data is available, and is reset high when all the new data has been read.
Table 25. SPI Data Available
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SPI Data Available (continued)
SDAV 0 1 DESCRIPTION Touch screen or SAR ADC data is available. No new data available. (default)
Bits [14:0] -- Reserved
These bits are reserved, and should be written to 0. If read, they will read back as 0.
Reset Register (Page 1, Address 04H):
The TSC2300 has a special register, the RESET register, which allows a software reset of the device. Writing the code 0xBB00, as shown below, to this register causes the TSC2300 to reset all its registers to their default, power-up values.
BIT 15 MSB 1 BIT 14 0 BIT 13 1 BIT 12 1 BIT 11 BIT 10 1 0 BIT 9 1 BIT 8 1 BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 LSB 0
Other values should not be written to this register. Reading this register or any reserved register results in reading back all 1's, or 0xFFFF.
TSC2300 DATA REGISTERS
The data registers of the TSC2300 hold data results from conversions or keypad scans, or the value of the DAC output current. All of these registers default to 0000H upon reset, except the DAC register, which is set to 0080H, representing the midscale output of the DAC.
X, Y, Z1, Z2, BAT1, BAT2, AUX1, AUX2, TEMP1, AND TEMP2T1 REGISTERS
The results of all A/D conversions are placed in the appropriate data register, as described in Table 6 and Table 4. The data format of the result word, R, of these registers is right-justified, as follows (assuming a 12-bit conversion):
BIT 15 MSB 0 BIT 14 0 BIT 13 0 BIT 12 0 BIT 11 R11 MSB BIT 10 R10 BIT 9 R9 BIT 8 R8 BIT 7 R7 BIT 6 R6 BIT 5 R5 BIT 4 R4 BIT 3 R3 BIT 2 R2 BIT 1 R1 BIT 0 LSB R0 LSB
Keypad Data Register (Page 0, Address 04H)
The keypad data register (Page 0, Address 04H) is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 MSB K15 K14 K13 K12 K11 K10 BIT 9 K9 BIT 8 K8 BIT 7 K7 BIT 6 K6 BIT 5 K5 BIT 4 K4 BIT 3 K3 BIT 2 K2 BIT 1 K1 BIT 0 LSB K0
This is the same format as used in the keypad mask register (Page 1, Address 10H). Each bit in these registers represents one key on the keypad. A 16-key keypad is mapped into the keypad data register as shown in Table 24.
D/A Converter Data Register (Page 0, Address 0BH)
The data to be written to the D/A converter is written into the D/A converter data register, which is formatted as follows:
BIT 15 MSB RES 34 BIT 14 RES BIT 13 RES BIT 12 RES BIT 11 RES BIT 10 RES BIT 9 RES BIT 8 RES BIT 7 D7 BIT 6 D6 BIT 5 D5 BIT 4 D4 BIT 3 D3 BIT 2 D2 BIT 1 D1 BIT 0 LSB D0
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There are three different touch screen conversion modes available in the TSC2300: self-controlled or PENIRQ-Initiated, host-initiated, and host-controlled. These three modes are described below.
OPERATION - TOUCH SCREEN MEASUREMENTS
Conversion Controlled by TSC2300 Initiated at Touch Detect
In this mode, the TSC2300 detects when the touch panel is touched and causes the PENIRQ line to go low. At the same time, the TSC2300 powers up its internal clock. It then turns on the Y-drivers, and after a programmed panel voltage stabilization time, powers up the A/D converter and convert the Y coordinate. If averaging is selected, several conversions may take place; when data averaging is complete, the Y coordinate result is stored in the Y register. This mode is recommended to fully utilize the integrated touch screen processing of the TSC2300 and reduce the processing overhead and number of interrupts to the host processor. In this mode, the host processor does not need to monitor PENIRQ, instead the host needs only to configure the TSC2300 once at power-up, and then monitor DAV and read back data after a falling edge on DAV. If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measures instead the X coordinate, storing the result in the X register. If only X and Y coordinates are to be measured, then the conversion process is complete. Figure 51 shows a flowchart for this process. The time it takes to go through this process depends upon the selected resolution, internal conversion clock rate, averaging selected, panel voltage stabilization time, and precharge and sense times. The time needed to get a complete X/Y coordinate reading can be calculated by:
t
coordinate
+ 2.5 ms ) 2 t
PVS
)t
PRE
)t
SNS
) 2N
AVG
N
1 ) 4.4 ms BITS f conv
(3)
where tcoordinate = time to complete X/Y coordinate reading; tPVS = panel voltage stabilization time, as given in Table 12; tPRE = precharge time, as given in Table 19; tSNS = sense time, as given in Table 20; NAVG = number of averages, as given in Table 10; for no averaging, NAVG = 1; NBITS = number of bits of resolution, as given in Table 9; fconv = A/D converter clock frequency, as given in Table 11.
* * * * * * *
If the pressure of the touch is also to be measured, the process continues after the X-conversion is complete, measuring the Z1 and Z2 values, and placing them in the Z1 and Z2 registers. This process is illustrated in Figure 55. As before, this process time depends upon the settings described above. The time for a complete X/Y/Z1/Z2 coordinate reading is given by:
t
coordinate
+ 4.75 ms ) 3 t
PVS
)t
PRE
)t
SNS
) 4N
AVG
N
1 ) 4.4 ms BITS f conv
(4)
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Screen Touch
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Touch Screen Scan X and Y PENIRQ Initiated
Issue Interrupt PENIRQ
N Is PENSTS =1 Y Go To Host Controlled Conversion Turn On Drivers: X+, X-
Start Clock N Is Panel Voltage Stabilization Done Turn On Drivers: Y+, Y- Y Power up ADC
N
Is Panel Voltage Stabilization Done
Convert X coordinates
Y N Power up ADC
Is Data Avereraging Done
Y Convert Y coordinates Store X Coordinates in X Register
Power Down ADC N Is Data Avereraging Done Set /DAV = 0
Y Store Y Coordinates in Y Register
Y Is Screen Touched
Power Down ADC
N Turn off clock Turn off clock N Reset PENIRQ and Scan Trigger Reset PENIRQ and Scan Trigger Done
Is Screen Touched
Y
Done
Figure 51. X & Y coordinate touch screen scan, initiated by touch.
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Touch Screen Scan X, Y and Z PENIRQ Initiated
Turn On Drivers: Y+, X-
Screen Touch
N
Is Panel Voltage Stabilization Done Y
Issue Interrupt PENIRQ
Turn On Drivers: X+, X-
Power up ADC N Is PENSTS =1
Go To Host Controlled Conversion
N
Is Panel Voltage Stabilization Done Y
Convert Z1 coordinates
Y Power up ADC Start Clock Convert X coordinates N Is Data Avereraging Done Y
Turn On Drivers: Y+, Y- N Is Data Avereraging Done Y
Store Z1 Coordinates in Z1 Register
Convert Z2 coordinates
N
Is Panel Voltage Stabilization Done Y
Store X Coordinates in X Register N Is Data Avereraging Done Y
Power up ADC Power Down ADC
Convert Y coordinates Is Screen Touched
Turn off clock
Store Z2 Coordinates in Z2 Register
Reset PENIRQ and Scan Trigger N Is Data Avereraging Done Y Done
Power Down ADC
Set /DAV = 0
Store Y Coordinates in Y Register
Y Is Screen Touched Turn off clock
Power Down ADC
N Turn off clock
N Is Screen Touched
Reset PENIRQ and Scan Trigger Reset PENIRQ and Scan Trigger
Y
Done Done
Figure 52. X,Y and Z Coordinate Touch Screen Scan, Initiated by Touch. Conversion Controlled by TSC2300 Initiated By Host Responding to PENIRQ
This mode is provided for users who want more control over the A/D conversion process. This mode requires more overhead from the host processor, so it is generally not recommended.
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In this mode, the TSC2300 detects when the touch panel is touched and causes the PENIRQ line to go low. The host recognizes the interrupt request, and then writes to the A/D Converter Control register to select one of the touch screen scan functions (single X-, Y-, or Z-conversions, continuous X/Y or X/Y/Z1/Z2 Conversions). The conversion process then proceeds as described above, and as outlined in Figure 53 through Figure 57. The main difference between this mode and the previous mode is that the host, not the TSC2300, decides when the touch screen scan begins after responding to a PENIRQ. In this mode, the host must either monitor both PENIRQ and DAV, or wait a minimum time after writing to the A/D converter control register. This wait time can be calculated from Equations (5) in the case of single conversions, or from Equations (3) or (4) in the case of multiple conversions. The nominal conversion times calculated by these equations should be extended by approximately 12% to account for variation in the internal oscillator frequency.
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TSC2300
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Touch Screen Scan X and Y Host Initiated
Screen Touch
Issue Interrupt PENIRQ
N Is PENSTS =1
Go To Host Controlled Conversion
Turn On Drivers: X+, X- Host Writes A/D Converter Control Register Done
Reset PENIRQ
N
Is Panel Voltage Stabilization Done
Y Start Clock Power up ADC
Turn On Drivers: Y+, Y- Convert X coordinates
N
Is Panel Voltage Stabilization Done
N Is Data Avereraging Done
Y Y Power up ADC Store X Coordinates in X Register Convert Y coordinates
Power Down ADC N Is Data Avereraging Done Y Set /DAV = 0
Store Y Coordinates in Y Register Turn off clock
Y Is Screen Touched
N Power Down ADC Reset PENIRQ and Scan Trigger N Is Screen Touched Done Done Turn off clock
Y
Figure 53. X and Y Coordinate Touch Screen Scan, Initiated by Host.
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Touch Screen Scan X, Y and Z Host Initiated
Screen Touch
Issue Interrupt PENIRQ
Turn On Drivers: Y+, X-
Turn On Drivers: X+, X- N Is PENSTS =1 Go To Host Controlled Conversion N Is Panel Voltage Stabilization Done Y
Host Writes A/D Converter Control Register
Done
N
Is Panel Voltage Stabilization Done Y
Power up ADC
Reset PENIRQ
Power up ADC
Convert Z1 coordinates
Start Clock
Convert X coordinates N Is Data Avereraging Done Y Store Z1 Coordinates in Z1 Register
Turn On Drivers: Y+, Y- N Is Data Avereraging Done Y N Is Panel Voltage Stabilization Done Y Power Down ADC Power up ADC Turn off clock Is Screen Touched Reset PENIRQ and Scan Trigger N
Store X Coordinates in X Register
Convert Z2 coordinates
Is Data Avereraging Done Y
Convert Y coordinates
Store Z2 Coordinates in Z2 Register Done N Is Data Avereraging Done Y Set /DAV = 0 Store Y Coordinates in Y Register Y Power Down ADC Turn off clock
Power Down ADC
Is Screen Touched N
Is Screen Touched
N
Reset PENIRQ and Scan Trigger
Turn off clock
Done Y
Done
Figure 54. X,Y and Z Coordinate Touch Screen Scan, Initiated by Host.
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Touch Screen Scan X Coordinate Host Initiated
Screen Touch
Issue Interrupt PENIRQ Convert X coordinates
N Is PENSTS =1
Go To Host Controlled Conversion N Done Y Is Data Avereraging Done
Host Writes A/D Converter Control Register
Store X Coordinates in X Register
Reset PENIRQ Power Down ADC
N Are Drivers On
Start Clock Set /DAV = 0
Y Turn On Drivers: X+, X- Start Clock Turn off clock
N
Is Panel Voltage Stabilization Done
Done
Y Power up ADC
Figure 55. X Coordinate Reading Initiated by Host.
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Touch Screen Scan Y Coordinate Host Initiated
Screen Touch
Issue Interrupt PENIRQ
Is PENSTS =1
N
Go To Host Controlled Conversion Store Y Coordinates in Y Register Done
Host Writes A/D Converter Control Register
Power Down ADC
Set /DAV = 0 Reset PENIRQ Turn off clock Are Drivers On Y Turn On Drivers: Y+, Y- Start Clock N Start Clock Done
N
Is Panel Voltage Stabilization Done
Power up ADC
Convert Y coordinates
N Is Data Avereraging Done
Figure 56. Y Coordinate Reading Initiated by Host.
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TSC2300
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Screen Touch
Touch Screen Scan Z Coordinate Host Initiated
Issue Interrupt PENIRQ
Is PENSTS =1
N
Go To Host Controlled Conversion
DONE
Host Writes A/D Converter Control Register
Convert Z2 coordinates
Reset PENIRQ
N
Is Data Avereraging Done Y
Are Drivers On
N Start Clock
Store Z2 Coordinates in Z2 Register Turn On Drivers: Y+, X- Start Clock Power Down ADC N Is Panel Voltage Stabilization Done Y
Set /DAV = 0
Power up ADC
Turn off clock Convert Z1 coordinates DONE
N
Is Data Avereraging Done Y Store Z1 Coordinates in Z1 Register
Figure 57. Z Coordinate Reading Initiated by Host. Conversion Controlled by the Host
In this mode, the TSC2300 detects when the touch panel is touched and causes the PENIRQ line to go low. The host recognizes the interrupt request. Instead of starting a sequence in the TSC2300 which then reads each coordinate in turn, the host now must control all aspects of the conversion. An example sequence would be: (a) PENIRQ goes low when screen is touched. (b) Host writes to TSC2300 to turn on X-drivers. (c) Host waits a desired delay for panel voltage stabilization. (d) Host writes to TSC2300 to begin X-conversion. After waiting for the settling time, the host then addresses the TSC2300 again, this time requesting an X coordinate conversion.
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The process is then repeated for Y and Z coordinates. The processes are outlined in Figure 58 through Figure 60. The time needed to convert any single coordinate under host control (not including the time needed to send the command over the SPI bus) is given by:
t
coordinate
+ 2.125 ms ) t
PVS
)N
AVG
N
1 ) 4.4 ms BITS conv Host Controlled X Coordinate
(5)
Screen Touch
Host Writes A/D Converter Control Register
Issue Interrupt PENIRQ
Start Clock
N
Are Drivers On
Y Is PENSTS =1 N Go To Host Controlled Conversion Turn On Drivers: X+, X- Start Clock
Done Is Panel Voltage Stabilization Done Host Writes A/D Converter Control Register Y
Power up ADC
N Convert X coordinates
Reset PENIRQ
N Turn On Drivers: X+, X-
Is Data Avereraging Done
Y
Done
Store X Coordinates in X Register
Power Down ADC
Issue Data Available
Turn off clock
Done
Figure 58. X Coordinate Reading Controlled by Host.
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TSC2300
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Host Controlled Y Coordinate
Screen Touch Host Writes A/D Converter Control Register
Issue Interrupt PENIRQ
Start Clock
N
Are Drivers On
Y Is PENSTS =1 N Go To Host Controlled Conversion
Turn On Drivers: Y+, Y-
Start Clock
Done Is Panel Voltage Stabilization Done Host Writes A/D Converter Control Register Y
Power up ADC
N Conver Y coordinates
Reset PENIRQ
N Turn On Drivers: Y+, Y-
Is Data Avereraging Done
Y
Done
Store Y Coordinates in Y Register
Power Down ADC
Set /DAV = 0
Turn off clock
Done
Figure 59. Y Coordinate Reading Controlled by Host.
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Screen Touch
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Host Controlled Z Coordinate
Issue Interupt PENIRQ
N Is PENSTS =1
Go To Host Controlled Conversion
DONE
Host Writes A/D Converter Control Register
Reset PENIRQ
Turn On Drivers: X+, X-
Done
Host Writes A/D Converter Control Register
Convert Z2 coordinates
Reset PENIRQ
N
Is Data Avereraging Done
Are Drivers On
N
Start Clock
Y
Y Store Z2 Coordinates in Z2 Register Start Clock Turn On Drivers: Y+,X-
Power Down ADC N
Is Panel Voltage Stabilization Done Y
Set /DAV = 0 N
Power up ADC
Turn off clock Convert Z1 coordinates DONE
N
Is Data Avereraging Done Y
Store Z1 Coordinates in Z1 Register
Figure 60. Z Coordinate Reading Controlled by Host.
OPERATION - TEMPERATURE MEASUREMENT
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TSC2300
SLAS372 -- NOVEMBER 2002
In some applications, such as estimating remaining battery life or setting RAM refresh rate, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2300 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the 25C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2300 offers two modes of temperature measurement. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. A diode, as shown in Figure 61, is used during this measurement cycle. The voltage across this diode is typically 600 mV at +25C while conducting a 20-A current. The absolute value of this diode voltage can vary several millivolts, but the temperature coefficient (TC) of this voltage is very consistent at -2.1 mV/C. During the final test of the end product, the diode voltage would be measured by the TSC2300's ADC at a known room temperature, and the corresponding digital code stored in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3C/LSB. This measurement of what is referred to as Temperature 1 is illustrated in Figure 62.
X+ MUX A/D Converter
Temperature Select TEMP1 TEMP2
Figure 61. Functional Block Diagram of Temperature Measurement Mode. K + q DV k n(N)
(6)
The second mode does not require a test temperature calibration, but uses a two-measurement (differential) method to eliminate the need for absolute temperature calibration, and achieves a 2C/LSB accuracy. This mode requires a second conversion with a current 82 times larger than the first 20uA current. The voltage difference between the first (TEMP1) and second (Temp2) conversion, using 82 times the bias current, is represented by kT/q ln (N), where N is the current ratio = 82, k = Boltzmann's constant (1.38054 x 10-23 electron volts/degree Kelvin), q = the electron charge (1.602189 x 10-19 C), and T = the temperature in degrees Kelvin. This method can provide much improved absolute temperature measurement without calibration, with resolution of 2C/LSB. The resultant equation for solving for K is: where
DV + V I
82
-V I
1 (inmV)
(7)
NK + 2.573DVK mV C + 2.573 DV(mV) * 273K
Temperature 2 measurement is illustrated in Figure 63. (8)
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TSC2300
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Temperature Input 1
Host Writes A/D Converter Control Register
Start Clock
Power Up Reference (Including Programmed Delay) Power Down ADC
Power up ADC
Power Down Reference Convert Temperature Input 1 Set /DAV = 0
N
Is Data Avereraging Done
Turn off clock
Y DONE Store Temperature Input 1 in TEMP1 Register
Figure 62. Single Temperature Measurement Mode
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TSC2300
SLAS372 -- NOVEMBER 2002
Temperature Input 2
Host Writes A/D Converter Control Register
Start Clock
Power Up Reference (Including Delay)
Power Down ADC
Power up ADC
Power Down Reference
Convert Temperature Input 2 Set /DAV = 0
N
Is Data Avereraging Done Y
Turn off clock
Store Temperature Input 2 in TEMP2 Register
DONE
Figure 63. Additional Temperature Measurement for Differential Temperature Reading
OPERATION - BATTERY MEASUREMENT
An added feature of the TSC2300 is the ability to monitor the battery voltage which may be much larger than the supply voltage of the TSC2300. An example of this is shown in Figure 64, where a battery voltage ranging up to 6V may be regulated by a dc/dc converter or low-dropout regulator to provide a lower supply voltage to the TSC2300. The battery voltage can vary from 0.5 V to 6 V while maintaining the voltage to the TSC2300 at a level of 2.7 V-3.6 V. The input voltage on VBAT1 is divided down by 4 so that a 6.0V battery voltage is represented as 1.5 V to the A/D, while the input voltage on VBAT2 is divided by 2 so that 3.0-V battery voltage is represented as 1.5 V to the A/D. If the battery voltage is low enough, the 1.2 V internal reference can be used to decrease LSB size, potentially improving accuracy. The battery voltage on VBAT1 must be below 4* VREF, and the voltage on VBAT2 must be below 2* VREF. Due to constraints of the internal switches, the input to the A/D after the voltage divider cannot be above 1.5 V or VREF, whichever is lower. In order to minimize the power consumption, the divider is only ON during the sampling of the battery input.
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TSC2300
SLAS372 -- NOVEMBER 2002 DC/DC Converter
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2.7 V
Battery 0.5 V+ to 6.0 V
+
VCC
0.125 V to 1.5 V VBAT1 7.5 kW 2.5 kW ADC
DC/DC Converter
2.7 V
Battery 0.25 V+ to 3.0 V
+
VCC
0.125 V to 1.5 V VBAT2 5.0 kW 5.0 kW ADC
Figure 64. VBAT Example Battery Measurement Functional Block Diagrams, VDD = 2.7 V, VREF = 2.5 V.
Flowcharts which detail the process of making a battery input reading are shown in Figure 65 and Figure 66. The time needed to make temperature, auxiliary, or battery measurements is given by:
t
coordinate
+ 2.625 ms ) t
REF
)N
AVG
N
1 ) 4.4 ms BITS conv
(9)
where tREF is the reference delay time as given in Table 15.
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TSC2300
SLAS372 -- NOVEMBER 2002
Battery Input 1
Host Writes A/D Converter Control Register
Start Clock
Power Down ADC Power Up Reference (Including Delay)
Power Down Reference Power up ADC
Convert Battery Input 1
Set /DAV = 0
N
Is Data Avereraging Done
Turn off clock
Y
DONE Store Battery Input 1 in BAT1 Register
Figure 65. VBAT1 Measurement Process.
This assumes the reference control register is configured to power up the internal reference when needed.
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TSC2300
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Battery Input 2
Host Writes A/D Converter Control Register
Start Clock
Power Down ADC Power Up Reference (Including Delay)
Power Down Reference Power up ADC
Convert Battery Input 2
Set /DAV = 0
N
Is Data Avereraging Done
Turn off clock
Y
DONE Store Battery Input 2 in BAT2 Register
Figure 66. VBAT2 Measurement process.
OPERATION - AUXILIARY MEASUREMENT
The two auxiliary voltage inputs can be measured in similar fashion to the battery inputs, with no voltage dividers. The input range of the auxiliary inputs is 0 V to VREF. Figure 67 and Figure 68 illustrate the process. Applications for this feature may include external temperature sensing, ambient light monitoring for controlling an LCD back-light, or sensing the current drawn from the battery.
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TSC2300
SLAS372 -- NOVEMBER 2002
Auxiliary Input 1
Host Writes A/D Converter Control Register
Start Clock
Power Up Reference (Including Delay) Power Down ADC
Power up ADC Power Down Reference
Convert Auxiliary Input 1 Set /DAV = 0
N
Is Data Avereraging Done
Turn off clock
Y DONE Store Auxiliary Input 1 in AUX1 Register
Figure 67. AUX1 Measurement Process
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TSC2300
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Auxiliary Input 2
Host Writes A/D Converter Control Register
Start Clock
Power Up Reference (Including Delay)
Power Down ADC
Power up ADC
Power Down Reference
Convert Auxiliary Input 2
Set /DAV = 0
N
Is Data Avereraging Done
Turn off clock
Y
DONE
Store Auxiliary Input 2 in AUX2 Register
Figure 68. AUX2 Measurement Process
OPERATION - PORT SCAN
If measurements of all the battery and auxiliary inputs are required, the port scan mode can be used. This mode causes the TSC2300 to sample and convert both battery inputs and both auxiliary inputs. At the end of this cycle, the battery and auxiliary data registers contain the updated values, and the DAV pin is asserted low, signaling the host to read the data. Thus, with one write to the TSC2300, the host can cause four different measurements to be made. Because the battery and auxiliary data registers are consecutive in memory, all four registers can be read in one SPI transaction, as described in Figure 50. The flowchart for this process is shown in Figure 69. The time needed to make a complete port scan is given by:
t
coordinate
+ 7.5 ms ) t
REF
) 4N
AVG
N
1 ) 4.4 ms BITS conv
(10)
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TSC2300
SLAS372 -- NOVEMBER 2002
Port Scan
Host Writes A/D Converter Control Register
Convert Auxiliary Input 1
Start Clock
N
Is Data Avereraging Done
Y
Power Up Reference (Including Delay)
Store Auxiliary Input in AUX1 Register
Power up ADC
Convert Auxiliary Input 2
Convert Battery Input 1
N
Is Data Avereraging Done
Y
N
Is Data Avereraging Done
Y
Store Auxiliary Input 2 in AUX2 Register
Store Battery Input 1 in BAT1 Register
Power Down ADC
Convert Battery Input 2
Power Down Reference
Set /DAV = 0
N
Is Data Avereraging Done
Y
Turn off clock
Store Battery Input 2 in BAT2 Register
DONE
Figure 69. Port Scan Mode.
OPERATION-D/ACONVERTER
The TSC2300 has an onboard 8-bit D/A converter, configured as shown in Figure 70. This configuration yields a current sink (AOUT) controlled by the value of a resistor connected between the ARNG pin and ground. The D/A converter has a control register, which controls whether or not the converter is powered up. The eight-bit data is written to the D/A converter through the D/A converter data register.
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TSC2300
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V+
R1 VBIAS R2 AOUT TSC2301 1M 10 M
8-Bits
DAC
ARNG
RRNG
Figure 70. D/A Converter Configuration
This circuit is designed for flexibility in the output voltage at the VBIAS point shown in Figure 70 to accommodate the widely varying requirements for LCD contrast control bias. V+ can be a higher voltage than the supply voltage for the TSC2300. The only restriction is that the voltage on the AOUT pin can never go above the absolute maximum ratings for the device, and should stay above 1.5 V for linear operation. The D/A converter has an output sink range which is limited to approximately 1 mA. This range can be adjusted by changing the value of RRNG shown in Figure 70. As this DAC is not designed to be a precision device, the actual value of the output current range can vary as much as 20%. Furthermore, the current output changes due to variations in temperature; the DAC has a temperature coefficient of approximately 0.9 uA/C. To set the full-scale current, RRNG can be determined from the graph shown in Figure 71.
DAC FULLSCALE OUTPUT CURRENT vs RRNG RESISTOR VALUE
1100 1000 DAC Fullscale Output Current - A 900 800 700 600 500 400 300 200 100 0 10 k 100 k 100 M
RRNG Resistor Value
Figure 71. DAC Output Current Range vs RRNG Resistor Value.
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TSC2300
SLAS372 -- NOVEMBER 2002
For example, consider an LCD that has a contrast control voltage VBIAS that can range from 2 V to 4 V, that draws 400 A when used, and has an available 5-V supply. Note that this is higher than the TSC2300 supply voltage, but it is within the absolute maximum ratings. The maximum VBIAS voltage is 4 V, and this occurs when the D/A converter current is 0, so only the 400-A load current ILOAD is flowing from 5 V to VBIAS. This means 1 V is dropped across R1, so R1 = 1 V/400 A = 2.5 k. The minimum VBIAS is 2 V, which occurs when the D/A converter current is at its full scale value, IMAX. In this case, 5 V - 2 V = 3 V is dropped across R1, so the current through R1 is 3 V/2.5 k = 1.2 mA. This current is IMAX + ILOAD = IMAX + 400 uA, so IMAX must be set to 800 A. Looking at Figure 73, this means that RRNG should be around 1 M. Since the voltage at the AOUT pin should not go below 1.5 V, this limits the voltage at the bottom of R2 to be 1.5-V minimum; this occurs when the D/A converter is providing its maximum current, IMAX. In this case, IMAX +ILOAD flows through R1, and IMAX flows through R2. Thus, R2 x IMAX + R1(IMAX + ILOAD) = 5 V - 1.5 V = 3.5 V (11) W R1 = 2.5 k IMAX = 800A, ILOAD = 400A, thus allowing R2 to be solved as 625 . In the previous example, when the DAC current is zero, the voltage on the AOUT pin rises above the TSC2300 supply voltage. This is not a problem, however, since V+ was within the absolute maximum ratings of the TSC2300, so no special precautions are necessary. Many LCD displays require voltages much higher than the absolute maximum ratings of the TSC2300. In this case, the addition of an NPN transistor, as shown in Figure 72, protects the AOUT pin from damage.
V+ R1 VBIAS R2
2N3904
AOUT VDD TSC2301
8-Bits
DAC
ARNG
RRNG
Figure 72. DAC Circuit When Using V+ Higher Than Vsupply.
OPERATION - KEYPAD INTERFACE
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TSC2300
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The TSC2300 contains a keypad interface which is suitable for use with matrix keypads up to 4 x 4 keys. A control register, the keypad control register, is used to set the scan rate for the keypad and de-bounce times. There is also a keypad mask register which allows certain keys to be masked from being read, or from causing the TSC2300 to detect a key-press on selected keys. The results of keypad scans are placed in the keypad data register. When a key-press is detected by the TSC2300, it automatically scans the keypad and de-bounces the key-press. It then drives KBIRQ low. All keys pressed at the time of the scan are then reflected in the keypad data register. This mode is shown in Figure 73.
Keypad Scan KBIRQ Initiated
Keypad Touch
Start Clock
Scan and debounce keys
Issue Interrupt KBIRQ
Store Keypad scan results in KPData Register
Turn off clock
Reset KBIRQ and Scan Trigger
Done
Figure 73. Keypad Scan Initiated by Keypress.
AUDIO CODEC
Audio Analog I/O
The TSC2300 has one pair of stereo inputs, LLINEIN and RLINEIN, and one mono audio input, MICIN. The part also has one pair of stereo line outputs capable of driving a 10-k load, VOUTL and VOUTR, as well as a stereo headphone output amplifier capable of driving a 16- load at up 30 mW/channel, HPL HPR. Finally, the part includes a differential mono output capable of driving a 10-k load per side, MONO+ and MONO-. A special circuit has also been included for inserting a keyclick sound into the analog output signal path based on register control. This functionality is intended for generating keyclick sounds for user feedback. This function is controlled by Reg 04h, Pg 2, and is available when either of the DAC or analog bypass paths are enabled.
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TSC2300
SLAS372 -- NOVEMBER 2002
The common-mode voltage, VCM, used by the audio section can be powered up independently by the AVPD bit (Bit 14, Reg 05h, Pg 2). Because the audio outputs are biased to this voltage, this voltage is slowly ramped up when powered on, and there is an internally programmed delay of approximately 500 msec between powering up this voltage and unmuting the analog audio signals of the TSC2300, in order to avoid pops and clicks on the outputs. It is recommended to keep VCM powered up if the 500-msec delay is not tolerable.
Audio Digital I/O
Digital audio data samples can be transmitted between the TSC2300 and the CPU via the I2S bus (BCLK, LRCLK, I2SDIN, I2SDOUT). However, all registers, including those pertaining to audio functionality, are only accessible via the SPI bus. The I2S bus operates only in slave mode, meaning the BCLK and LRCLK must be provided as inputs to the part. Four programmable modes for this serial bus are supported and can be set through the I2SFM bits (Bits[1:0], Reg 00h, Pg 2) .
PCM Audio Interface
The 4-wire digital audio interface for TSC2300 is comprised of BCLK (pin 24), LRCLK (pin 25), I2SDIN (pin 26), and I2SDOUT (pin 27). For the TSC2300, these formats are selected through the I2SFM bits in Reg 00h, Pg 2. The following figures illustrate audio data input/output formats and timing. The TSC2300 can accept 32-, 48- or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can be selected when 32-bit clocks/LRCIN are applied.
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FORMAT 0
DAC: 16-Bit, MSB-First, Right-Justified L-ch R-ch
LRCIN BCKIN I2SDIN 16 1 2
3
14
15
16
1
2
3
14
15 16
MSB ADC: 16-Bit, MSB-First, Left-Justified
LSB
MSB
LSB
LRCIN BCKIN I2SDOUT 1 2 3
L-ch
14
15 16
1
MSB
LSB
FORMAT 1
DAC: 20-Bit, MSB-First, Right-Justified L-ch R-ch
LRCIN BCKIN I2SDIN 20 1 2 3
18
19
20
1
2
3
18
19 20
MSB ADC: 20-Bit, MSB-First, Left-Justified
LSB
MSB
LSB
LRCIN BCKIN I2SDOUT 1 2 3
L-ch
18
19
20
1
MSB
LSB
FORMAT 2
DAC: 20-Bit, MSB-First, Left-Justified L-ch R-ch
LRCIN BCIN I2SDIN 1 2 3
18
19 20
1
2
3
18
19
20
1
MSB ADC: 20-Bit, MSB-First, Left-Justified
LSB
MSB
LSB
LRCIN BCIN I2SDOUT 1 2 3
L-ch
18
19 20
1
MSB
LSB
Figure 74. Audio Data Input/Output Format
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TSC2300
SLAS372 -- NOVEMBER 2002
FO RM AT 3
D A C : 2 0 -B i t , M S B -F i r s t , I 2 S L -c h
LRCIN BCKIN I2SDIN 1 2 3
R -c h
18 19 20
1
2
3
18 19 20
MSB A D C : 2 0 -B it , M S B -F i r s t , I 2 S L -c h
LSB
MSB
LSB
LRCIN BCKIN I2SDOUT 1 2 3
18 19 20
MSB
LS B
Figure 75. Audio Data Input/Output Format
t LRP
LRCIN t BL t BCH t BCL t LB
0.5V DD
BCKIN
0.5V DD t BCY
t DIS
t DIH
I2SDIN
0.5V DD
t BDO I2SDOUT
t LDO 0.5V DD
Figure 76. Audio Data Input/Output Timing
Table 26. Audio Data Input/Output Timing
Parameter BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width Low BCKIN Rising Edge to LRCIN Edge LRCIN Edge to BCKIN Rising Edge LRCIN Pulse Width I2SDIN Setup Time I2SDIN Hold Time I2SDOUT Delay Time to BCKIN Falling Edge I2SDOUT Delay Time to LRCIN Edge Rising Time to All Signals Falling Time to All Signals Symbol tBCY tBCH tBCL tBL tLB tLRP tDIS tDIH tBDO tLDO tRISE tFALL Min 300 nsmin 120 ns 120 ns 40 ns 40 ns tBCY ns 40 ns 40 ns 40 ns 40 ns 20 ns 20 ns 61 Max
TSC2300
SLAS372 -- NOVEMBER 2002
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Audio Data Converters
The TSC2300 includes a stereo 20-bit audio DAC and a mono 20-bit audio ADC. The DAC and ADC are both capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz. The DAC and ADC must operate at the same sampling rate. When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the I2S bus clock. The MCLK can be 256/384/512 times the I2S LRCLK rate. An internal PLL takes any of these possible input clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 = 22.5792 MHz (when 44.1 kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48 kHz submultiple sample-rates are selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2) to tell the part the ratio between MCLK and the I2S LRCLK rate (there is no specific phase alignment requirement between MCLK and BCLK). The user is also required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell the part what sample rate is in use. When the user is using either 44.1 kHz or 48-kHz sampling rates, and providing a 512 x Fs MCLK, the internal PLL is powered down, as MCLK can be used directly to clock the internal circuitry. This reduces power consumption. If the user wishes to change sampling rates, the data converters (both DAC's and ADC) should be muted, then powered down. The LRCLK and BCLK rates should then be changed. Next the user should write the appropriate settings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converters can be un-muted. Due to the wide supply range over which this part must operate, the audio does not operate on an internal reference voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by a divider between the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audio codec must be provided as inputs to the part at the Vref+/Vref- pins and are intended to be connected to the same voltage levels as AVDD and AGND, respectively. Because of this arrangement, the voltages applied to AVDD, AGND, Vref+, and Vref- should be kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPI registers. The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel. The user can mute each channel independently by setting the mute bits in the DAC volume control register (Reg 02h, Pg 2). There is a soft-stepping algorithm included in this block, which only changes the actual volume every 20 s, either up or down, until the desired volume is reached. This speed of soft-stepping can be slowed to once every 40 s through the SSRTE bit (Bit 1, Reg 04h, Pg 2). Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the part provides a flag back to the host via a read-only SPI register bit (Bit 0, Reg 04h, Pg 2) that alerts the host when the part has completed the soft-stepping, and the actual volume has reached the desired volume level. The part also includes functionality to detect when the user switches on or off the de-emphasis or bass-boost functions, and to first soft-mute the DAC volume control, then change the operation of the digital effects processing, then soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC/ADC. The circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired volume level slowly. At power-down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.
Stereo DAC Overview
The stereo DAC consists of a digital block to implement digital interpolation filter, volume control, de-emphasis filter and programmable digital effects/bass-boost filter for each channel. These are followed by a 5th-order single-bit digital delta-sigma modulator, and switched capacitor analog reconstruction filter. The DAC has been designed to provide enhanced performance at low sample rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed in the full audio band of 20 Hz-20 kHz, even at low sample rates such as 8 kHz. This is realized by keeping the upsampled rate approximately constant and changing the oversampling ratio as the input sample rate is reduced. For rates of 8/12/16/24/32/48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz, giving oversampling ratios of 768/512/384/256/192/128, respectively. This ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for rates of 11.025/22.05/44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz, yielding oversampling ratios of 512/256/128, respectively.
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TSC2300
SLAS372 -- NOVEMBER 2002
Conventional audio DAC designs utilize high-order analog filtering to remove quantization noise that falls within the audio band when operating at low sample rates. Here, however, the increased oversampling at low sample rates keeps the noise above 20 kHz, yielding a similar noise floor out to 20 kHz whether the sample rate is 8 kHz or 48 kHz. If the audio bypass path is not in use when the stereo DAC is in use, the user should power down the bypass path, as this improves DAC SNR and reduces power consumption. In addition, the digital interpolation filter provides enhanced image filtering to reduce signal images caused by the upsampling process that land below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples of 8 kHz, i.e., 8 kHz, 16 kHz, 24 kHz, etc. The images at 8 kHz and 16 kHz are below 20 kHz and thus are still audible to the listener, therefore they must be filtered heavily to maintain a good quality output. The interpolation filter is designed to maintain at least 65-dB rejection of signal images landing between 0.55 Fs and 3.5 Fs, for all sample rates, including any images that land within the audio band (20 Hz-20 kHz). Passband ripple for all sample-rate cases (from 20 Hz to 0.4535 Fs) is +/-0.1-dB maximum. The analog reconstruction filter design consists of a switched-capacitor filter with one pole and three zeros. The single-bit data operates at 128 x 48 kHz = 6.144 MHz (for selected sample-rates that are submultiples of 48 kHz) or at 128 x 44.1 kHz = 5.6448 MHz (for selected sample-rates that are submultiples of 44.1 kHz). The interpolation filter takes data at the selected sample-rate from the effects processing block, then performs upsampling and image filtering, yielding a 6.144-MHz or 5.6448-MHz data stream, which is provided to the digital delta-sigma modulator. Audio DAC SNR performance is 98-dB-A typical over 20 Hz - 20 kHz bandwidth in 44.1/48-kHz mode at the line-outputs with a 3.3-V supply level.
DAC Digital De-emphasis
The DAC digital effects processing block can perform several operations on the audio data before it is passed to the interpolation filter. One such operation is a digital de-emphasis, which can be enabled or disabled by the user via the DEEMP bit (Bit 0, Reg 05h, Pg 2). This is only available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The transfer function consists of a pole with time constant of 50 sec and a zero with time constant of 15 sec.
DAC Programmable Digital Effects Filter
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable coefficients (independently programmable per channel). The filter transfer function is given by:
N0 ) 2 N1 Z -1 ) N2 Z -2 32768-2 D1 Z -1-D2 Z -2
N3 ) 2 N4 Z -1 ) N5 Z -2 32768-2 D4 Z -1-D5 Z -2
(12)
The N and D coefficients are set via SPI registers, and this filter can be enabled or disabled via the BASS bit (Bit 1, Reg 05h, Pg u2). This functionality can implement a number of different functions, such as bass-boost (default), treble-boost, mid-boost, or other equalization. This transfer function(s) can be determined by the user and loaded to the TSC2300 at power-up, and the feature can then be switched on or off by the user during normal operation. The default coefficients at reset are given by:
N0=N3=27618 N1=N4=-27033 N2=N5=26461 D1=D4=32130 D2=D5=-31505
which implements the bass-boost transfer function shown in Figure 77, having a 3-dB attenuation for signals above approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bit twos complement integers with values ranging from -32768 to +32767.
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Default Bass-Boost Transfer Function 48 kHz Mode 0
-0.5
-1
-1.5 Gain (dB)
-2
-2.5
-3
-3.5 1 10 100 1000 10000 100000 Frequency (Hz)
Figure 77. Transfer Function of Default Bass-Boost Filter Coefficients at 48-kHz Sampling Rate. Audio ADC
The audio ADC consists of a 4th order multi-bit analog delta-sigma modulator, followed by a digital decimation filter. The digital output data is then passed to the bus interface for transmission back to the CPU. The analog modulator is a fully differential switched-capacitor design with multi-bit quantizer and dynamic element matching to avoid mismatch errors. The modulator operates at an oversampling ratio of 128 for all sample rates. The input to the ADC is filtered by a single-pole analog filter with -3-dB point at approximately 500 kHz for antialiasing. This analog filter uses a single off-chip 1 nF cap per ADC (at the AFILT pins) and on-chip resistor. The digital decimation filter block includes a high-pass IIR filter for the purpose of removing any dc or sub-audio-frequency component from the signal. Since such a low frequency filter can have significant settling time, the filter has an adjustable cutoff frequency, in order to allow the host to set a faster settling time initially, then later switch it back to a level that does not affect the audio band. The settings for this high-pass filter are:
HPF -3-dB frequency: 0.000019 Fs (0.912 Hz at Fs=48 kHz) 0.000078 Fs (3.744 Hz at Fs=48 kHz) 0.1 Fs (4.8 kHz at Fs=48 kHz)
The filter block provides an audio passband ripple of +/-0.03 dB over a passband from 0 Hz to 0.454 Fs, and 70-dB minimum stopband attenuation from 0.548 Fs to 64 Fs. The ADC modulator and digital filter operate on a clock that changes directly with sampling frequency (Fs). This is in contrast to the DAC, which keeps the modulator running at a high rate of 128 x 44.1 kHz or 128 x 48 kHz even if the incoming data rate is much lower, such as 8 kHz. Group delay of the ADC path varies with sampling frequency and is given by 28.7/Fs. Audio ADC SNR performance is 88-dB-A typical over 20-Hz - 20-kHz bandwidth in 44.1/48-kHz mode with a 3.3-V supply level. The audio ADC is preceded by an analog volume control with gain programmable from 20 dB to -40 dB or mute in 0.5-dB steps using Reg 01h, Pg 2. The input to the volume control is selected as LLINEIN, RLINEIN, MICIN, or a mono mix of LLINEIN and RLINEIN through the INM bits (Bits [13:12], Reg 00h, Pg 2). An additional preamp gain is selectable on the MICIN input as 0 dB, 6 dB, or 12 dB using the MICG bits (Bits [9:8], Reg 00h, Pg 2).
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Audio Bypass Mode
In audio bypass mode, the L/RLINEIN analog inputs can be routed to mix with the DAC output and play to the line-outputs (VOUTL/R) as well as the headphone outputs (HPL/R) and mono output (MONO+/-). This path has a stereo analog volume control associated with it, with range settings from +12.0 dB to -35.5 dB in 0.5-dB steps. If the audio ADC's and DAC's are not used while the bypass path is in use, the ADC's and DAC should be powered down to improve noise performance and reduce power consumption. This analog volume control has soft-stepping logic associated with it, so that when a volume change is made via the SPI bus, the logic changes the actual volume incrementally, single-stepping the actual volume up or down once every 20 sec until it reaches the desired volume level. This volume control also has similar algorithms as the ADC/DAC volume controls, in that the volume starts at mute upon power-up, then is slowly single-stepped up to the desired level. At a power-down request, the volume is slowly single-stepped down to mute before the circuit is actually powered down.
Differential Monophonic Output (MONO+/-)
The differential mono output of the TSC2300 can be used to drive a power amplifier which drives a low-impedance speaker. This block can output either a mono mix of the stereo line outputs, or the analog input to the audio ADC. This is selected through the MONS bit (Bit 2, Reg 04h, Pg 2). The mono mix of the line outputs is represented by the equation VOUTL/2 + VOUTR/2. Similarly, the mono mix of the analog line inputs is represented by LLINEIN/2 + RLINEIN/2.
Microphone Bias Voltage (MICBIAS)
The TSC2300 provides an output voltage suitable for biasing an electret microphone capsule. This voltage is always 1 V below the supply voltage of the part. This output can be disabled through the MIBPD bit (Bit 6, Reg 05h, Pg 2) to reduce power consumption if not used.
Power Consumption
The TSC2300 provides maximum flexibility to the user for control of power consumption. Towards that end, every section of the TSC2300 audio codec can be independently powered down. The power down status of the different sections is controlled by Reg 05h in Pg 2. The analog bypass path, headphone amplifier, mono output, stereo DAC, audio ADC, microphone bias, crystal oscillator, and oscillator clock buffer sections can all be powered down independently. It is recommended that the end-user power down all unused sections whenever possible in order to minimize power consumption. Below is a table showing power consumption in different modes of operation.
OPERATING MODE DESCRIPTION REGISTER 05H BIT VALUES 15 STEREO RECORD AND PLAYBACK Mono record, line playback, 48 kHz Mono record, line playback, 8 kHz Mono record, headphone playback, 48 kHz Mono record, headphone playback, 8 kHz STEREO PLAYBACK ONLY Line playback only, 48 kHz Headphone playback only, 48 kHz RECORD ONLY Mono record, 48 kHz Mono record only, 8 kHz ANALOG BYPASS Line in to line out Line in to headphone out POWER DOWN Power down all Power down, VCM enabled 1 1 1 0 X X X X X X X X X X X X X X 0 0 0 0 TBD 0.8 mA A 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 TBD TBD mA mA 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 TBD TBD mA mA 0 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 TBD TBD mA mA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TBD TBD TBD TBD mA mA mA mA 14 13 12 11 10 9 8 6 5 4 POWER CONSUMPTION TYP UNITS
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TSC2300 AUDIO CONTROL REGISTERS
TSC2300 Audio Control Register (Page 2, Address 00H)
The audio control register of the TSC2300 controls the digital audio interface, the microphone preamp gain, the record multiplexer settings, and the ADC highpass filter pole. This register determines which ADC high pass filter response is selected, as well as which audio inputs are connected to the stereo ADC's. The gain of the MIC input (0 to +12 dB) is also selected. This register is also used to tell the data converters the frequency of MCLK, along with the frequency of LRCLK (ADC and DAC sample rates). The format of the audio data is also selected. The audio control register is formatted as follows:
BIT 15 MSB HPF1 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 HPF0 INM1 INM0 RESV RESV BIT 9 MICG 1 BIT 8 MICG 0 BIT 7 MCLK 1 BIT 6 MCLK 0 BIT 5 I2SFS 3 BIT 4 I2SFS 2 BIT 3 I2SFS 1 BIT 2 I2SFS 0 BIT 1 I2SF1 BIT 0 LSB I2SF0
Bits [15:14] HPF1-HPF0
ADC High Pass Filter. These two bits select the pass-band for the high-pass filter or disable the filter. The default state of the filter is enabled, with -3-dB frequency at 0.000019xFs.
Table 27. High-Pass Filter Operation
HPF[1:0] HPF1 0 0 1 1 HPF0 0 1 0 1 DESCRIPTION HPF Disabled, signal passes through unaltered HPF -3-dB frequency=0.1xFs HPF -3-dB frequency=0.000078xFs HPF -3-dB frequency=0.000019xFs (default)
Bits [13:12] INM1-INM0
Audio ADC Input Multiplexer. These two bits select the analog input for the audio ADC. The input to the ADC can come from the microphone input, right line input, left line input, or from a mono mix of the left and right line inputs. The default input to the audio ADC is the microphone input.
Table 28. Audio ADC Input Selection
INM[1:0] INM1 0 0 1 1 INM0 0 1 0 1 DESCRIPTION ADC input=MIC (default) ADC input=LLINEIN ADC input=RLINEIN ADC input=(RLINEIN+LLINEIN)/2
Bits [11:10] Reserved Bits [9:8] MICG1-MICG0
Microphone Preamp Gain. These two bits select the gain of the microphone input channel. The gain of the microphone input channel can be 0 dB, +6 dB, or +12 dB. The default gain of the microphone input channel is 0 dB.
Table 29. Microphone Input Gain Selection
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Microphone Input Gain Selection (continued)
MICG[1:0] MICG1 0 0 1 1 MICG0 0 1 0 1 DESCRIPTION MIC gain=0 dB (default) MIC gain=0 dB MIC gain=6 dB MIC gain=12 dB
Bits [7:6] MCLK1-MCLK0
Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio sampling frequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs.
Table 30. Master Clock Ratio Selection
MCLK[1:0] MCLK1 0 0 1 1 MCLK0 0 1 0 1 DESCRIPTION Master clock (MCLK)=256 x Fs (default) Master clock (MCLK)=384 x Fs Master clock (MCLK)=512 x Fs Master clock (MCLK)=256 x Fs
Bits [5:2] I2SFS3-I2SFS0
I2S Sample Rate. These bits tell the internal PLL what the audio sampling rate is so that it provides the proper clock rate to the data converters and the digital filters. The default sample rate is 48 kHz. See Table 31 for a complete listing of available sampling rates. All combinations of I2SFS[3:0] not in Table 31 are not valid.
Table 31. I2S Sample Rate Select
I2SFS3 0 0 0 0 0 0 0 0 1 I2SFS2 0 0 0 0 1 1 1 1 0 I2SFS1 0 0 1 1 0 0 1 1 0 I2SFS0 0 1 0 1 0 1 0 1 0 FUNCTION Fs=48 kHz (default) Fs=44.1 kHz Fs=32 kHz Fs=24 kHz Fs=22.05 kHz Fs=16 kHz Fs=12 kHz Fs=11.05 kHz Fs=8 kHz
Bits [1:0] I2SFM1-I2SFM0
I2S Format. These two bits select the I2S interface format. Both 16-bit and 20-bit data formats are supported. The default format is 20-bit I2S.
Table 32. I2S Format Selection
I2SFM [1:0] I2SFM1 0 0 1 I2SFM0 0 1 0 DESCRIPTION DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified
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I2S Format Selection (continued)
I2SFM [1:0] I2SFM1 1 I2SFM0 1 DESCRIPTION DAC: 20-bit, MSB-first, I2S (default) ADC: 20-bit, MSB-first, I2S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the programmable gain amplifier (PGA) on the input to the audio ADC of the TSC2300. The gain of this PGA can be adjusted from -40 dB to +20 dB in 0.5-dB steps. The ADC input can also be hard-muted, or internally shorted to VCM so that no input signal is seen. The ADC volume control register is formatted as follows:
BIT 15 MSB ADMU BIT 14 ADV6 BIT 13 ADV5 BIT 12 ADV4 BIT 11 ADV3 BIT 10 ADV2 BIT 9 ADV1 BIT 8 ADV0 BIT 7 RESV BIT 6 RESV BIT 5 RESV BIT 4 RESV BIT 3 RESV BIT 2 RESV BIT 1 RESV BIT 0 LSB RESV
Bit 15 ADMU
ADC Mute. This bit is used to mute the input to the ADC volume control. The user can set this bit to mute the ADC while retaining the previous gain setting in ADV[6:0], so that the PGA returns to the previous gain setting when ADMU is cleared. When the ADMU bit is set, theADC PGA soft-steps down to its lowest level, then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation. This soft-stepping process is reversed when the ADMUL bit is cleared (unmute).
Table 33. ADC Mute
ADMU 0 1 DESCRIPTION ADC is active. Audio ADC is mute. (default)
Bits [14:8] ADV6- ADV0
Audio ADC Volume Control. These 7 bits control the gain setting of the audio ADC volume control. This volume control can be programmed from -40 dB to +20 dB in 0.5-dB steps. Full volume (+20 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any value lower than 07h engages the mute function described above. Volume control changes are always soft-stepped, as described above. The default volume setting is 0 dB. ADV[6:0] = 1010111 (087d) = 0 dB (default) ADV[6:0] = 1111111 (127d) = +20 dB (Max) ADV[6:0] = 0000111 (007d) = -40 dB (Min) ADV[6:0] = 0d-6d = mute
Bits [7:0] Reserved DAC VOLUME CONTROL REGISTER (Page 02, Address 02h)
The DAC volume control register controls the independent digital gain controls on the left and right channel audio DAC's of the TSC2300. The gain of the DAC's can be adjusted from -63.5 dB to 0 dB in 0.5-dB steps. The DAC inputs can also be muted, so that all zeroes are sent to the DAC interpolation filters. The DAC volume control register is formatted as follows:
BIT 15 MSB DAMUL BIT 14 DAVL6 BIT 13 DAVL5 BIT 12 DAVL4 BIT 11 DAVL3 BIT 10 DAVL2 BIT 9 DAVL1 BIT 8 DAVL0 BIT 7 DAMUR BIT 6 DAVR6 BIT 5 DAVR5 BIT 4 DAVR4 BIT 3 DAVR3 BIT 2 DAVR2 BIT 1 DAVR1 BIT 0 LSB DAVR0
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Bit 15 DAMUL
Left DAC Mute. This bit is used to mute the input to the Left Channel DAC. The user can set this bit to mute the DAC while retaining the previous gain setting in DAVL[6:0], so that the gain control returns to the previous gain setting when DAMUL is cleared. When the DAMUL bit is set, the left DAC digital gain control soft-steps down to its lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduce any audible artifacts (pops or clicks) of the mute procedure. This soft-stepping process is reversed when the DAMUL bit is cleared (unmute).
Table 34. Left DAC Mute
DAMUL 0 1 DESCRIPTION Left channel DAC is active. Left channel DAC is mute. (default)
Bits [14:8] DAVL6- DAVL0
Left DAC Volume Control. These 7 bits control the gain setting of the left channel DAC volume control PGA. This volume control can be programmed from -63.5 dB to 0dB in 0.5-dB steps. Full volume (0dB) corresponds to a setting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB. DAVL[6:0] = 1111111 (127d) = 0 dB (default) DAVL[6:0] = 0000000 (000d) = -63.5 dB (Min) 1LSB = 0.5 dB
Bit 7 DAMUR
Right DAC Mute. This bit is used to mute the input to the right channel DAC. The user can set this bit to mute the DAC while retaining the previous gain setting in DAVR[6:0], so that the gain control returns to the previous gain setting when DAMUR is cleared. When the DAMUR bit is set, the left DAC digital gain control soft-steps down to its lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduce any audible artifacts (pops or clicks) of the mute procedure. This soft-stepping process is reversed when the DAMUR bit is cleared (unmute).
Table 35. Right DAC Mute
DAMUR 0 1 DESCRIPTION Right channel DAC is active. Right channel DAC is mute. (default)
Bits [6:0] DAVR6- DAVR0
Right DAC Volume Control. These 7 bits control the gain setting of the right channel DAC volume control. This volume control can be programmed from -63.5 dB to 0 dB in 0.5-dB steps. Full volume (0dB) corresponds to a setting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB. DAVR[6:0] = 1111111 (127d) = 0 dB (default) DAVR[6:0] = 0000000 (000d) = -63.5 dB (Min) 1LSB = 0.5 dB
ANALOG AUDIO BYPASS PATH VOLUME CONTROL REGISTER (Page 02, Address 03h)
The bypass path volume control register controls the independent programmable gain amplifiers (PGA's) on the left and right channel analog audio bypass paths of the TSC2300. These bypass paths direct the line inputs directly to the line and headphone outputs entirely in the analog domain, with no A/D or D/A conversion. This feature can be used for playback of an external analog source, such as an FM stereo tuner through the TSC2300's headphone amplifier. The gain of these PGA's can be adjusted from -35.5 dB to +12 dB in 0.5 dB steps. The bypass paths can also be muted, so that no signal is transmitted. The bypass path volume control register is formatted as follows:
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BIT 15 MSB BPMUL BIT 14 BPVL6 BIT 13 BPVL5 BIT 12 BPVL4 BIT 11 BPVL3 BIT 10 BPVL2 BIT 9 BPVL1 BIT 8 BPVL0 BIT 7 BPMUR BIT 6 BPVR6 BIT 5 BPVR5 BIT 4 BPVR4 BIT 3 BPVR3 BIT 2 BPVR2
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BIT 1 BPVR1
BIT 0 LSB BPVR0
Bit 15 BPMUL
Left Channel Audio Bypass Mute. This bit is used to mute the bypass path from the left channel line input (LLINEIN) to the left channel line and headphone outputs (VOUTL and HPL). The user can set this bit to mute the bypass path while retaining the previous gain setting in BPVL[6:0], so that the PGA returns to the previous gain setting when BPMUL is cleared. When the BPMUL bit is set, the PGA soft-steps down to its lowest level, then the bypass path is muted. This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation. This soft-stepping process is reversed when the BPMUL bit is cleared (unmute).
Table 36. Left Channel Audio Bypass Mute
BPMUL 0 1 DESCRIPTION Left channel audio bypass path is active. Left channel audio bypass path is mute. (default)
Bits [14:8] BPVL6- BPVL0
Left Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the left channel bypass path volume control PGA. This volume control can be programmed from -35.5 dB to +12 dB in 0.5 dB steps. Full volume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5 dB) corresponds to 20h. Any value lower than 20h engages the mute function described above. The default volume setting is 0 dB. BPVL[6:0] = 1100111 (103d) = 0 dB (default) BPVL[6:0] = 1111111 (127d) = +12 dB (Max) BPVL[6:0] = 0100000 (032d) = -35.5 dB (Min) BPVL[6:0] = 0d-31d = mute
Bit 7 BPMUR
Right Channel Audio Bypass Mute. This bit is used to mute the bypass path from the right channel line input (RLINEIN) to the right channel line and headphone outputs (VOUTR and HPR). The user can set this bit to mute the bypass path while retaining the previous gain setting in BPVR[6:0], so that the PGA returns to the previous gain setting when BPMUR is cleared. When the BPMUR bit is set, the PGA soft-steps down to its lowest level, then the bypass path is muted. This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation. This soft-stepping process is reversed when the BPMUR bit is cleared (unmute).
Table 37. Right Channel Audio Bypass Mute
BPMUR 0 1 DESCRIPTION Right channel audio bypass path is active. Right channel audio bypass path is mute. (default)
Bits [6:0] BPVR6- BPVR0
Right Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the right channel bypass path volume control PGA. This volume control can be programmed from -35.5 dB to +12 dB in 0.5-dB steps. Full volume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5 dB) corresponds to 20h. Any value lower than 20h engages the mute function described above. The default volume setting is 0 dB. BPVR[6:0] = 1100111 (103d) = 0 dB (default) BPVR[6:0] = 1111111 (127d) = +12 dB (Max) BPVR[6:0] = 0100000 (032d) = -35.5 dB (Min)
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BPVR[6:0] = 0d-31d = mute
KEYCLICK CONTROL REGISTER (Page 2, Address 04H)
The Keyclick Control Register of the TSC2300 controls the setup of the internal keyclick sound generator. This register is used to initiate and set the frequency, amplitude, and duration of the internally generated keyclick sound. This register also controls the input to the differential mono output, and the soft-stepping function of the TSC2300 volume controls. The keyclick control register is formatted as follows:
Bit 15 MSB KEYST Bit 14 KCAM2 Bit 13 KCAM1 Bit 12 KCAM0 Bit 11 RESV Bit 10 KCFR2 Bit 9 KCFR1 Bit 8 KCFR0 Bit 7 KCLN3 Bit 6 KCLN2 Bit 5 KCLN1 Bit 4 KCLN0 Bit 3 RESV Bit 2 MONS Bit 1 SSRTE Bit 0 LSB SSTEP
Bit 15 KEYST
Keyclick Start. This bit initiates a keyclick sound.
Table 38. Keyclick Start
KEYST 0 1 Description No keyclick sound (default) Initiate a keyclick sound
Bits [14:12] KCAM2-KCAM0
Keyclick Amplitude. These bits set the amplitude of the keyclick sound with eight amplitude levels provided. KCAM[2:0] = 100 = Medium amplitude (default) KCAM[2:0] = 111 = Maximum amplitude KCAM[2:0] = 000 = Minimum amplitude
Bit 11 RESERVED
This bit is reserved, and should be written to 0. If read, it will read back as 0.
Bits [10:8] KCFR2-KCFR0
Keyclick Frequency. These bits set the frequency of the keyclick sound (frequencies are approximate).
Table 39. Keyclick Frequency
KCFR2 0 0 0 0 1 1 1 1 KCFR1 0 0 1 1 0 0 1 1 KCFR0 0 1 0 1 0 1 0 1 KEYCLICK TONE FREQUENCY 62.5 Hz 125 Hz 250 Hz 500 Hz 1 k Hz (default) 2 k Hz 4 k Hz 8 k Hz
Bits [7:4] KCLN3-KCLN0
Keyclick Length. These bits set the approximate duration of the keyclick sound, 16 settings for duration are provided. The formula for the number of periods heard is:
N
periods
+ (KCLN ) 1)
2
(13)
KCLN[3:0] = 0000 = 2 periods of the keyclick sound (min)
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KCLN[3:0] = 0001 = 4 periods of the keyclick sound (default) KCLN[3:0] = 0010 = 6 periods of the keyclick sound KCLN[3:0] = 0011 = 8 periods of the keyclick sound KCLN[3:0] = 1111 = 32 periods of the keyclick sound (max)
Bit 3 RESERVED
This bit is reserved, and should be written as 0. If read, it is read back as 0.
Bit 2 MONS
Mono Select. This bit determines the position of the Mono multiplexer. This multiplexer allows either the audio ADC Input or the mono mix of the stereo line outputs to be played out the differential mono output (MONO+/-).
Table 40. Mono Select
MONS 0 1 DESCRIPTION Mono output comes from ADC input (default) Mono output comes from mono mix of line outputs
Bit 1 SSRTE
Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2300 volume controls. At normal speed, the actual volume is updated approximately once every 20 s. At half speed, the actual volume is updated approximately once every 40 s.
Table 41. Volume Soft-Stepping Rate Select
SSRTE 0 1 DESCRIPTION Normal step rate used (default) Half step rate used
Bit 0 SSTEP
Soft-step Flag. This read-only bit indicates that the TSC2300 volume control soft-stepping is completed.
Table 42. Soft-Step Flag
SSTEP 0 1 DESCRIPTION Soft-stepping is not complete Soft-stepping is complete (default)
AUDIO POWER CONTROL REGISTER (Page 2, Address 05H)
The audio power / miscellaneous control register of the TSC2300 controls the powering down of various audio blocks of the TSC2300. The default state of the TSC2300 has all audio blocks powered down. Before using any of the audio blocks, they must be powered up by writing to this register. This register also controls the crystal oscillator clock and buffer, the bass-boost filter, and the de-emphasis filter. The audio power / miscellaneous control register is formatted as follows:
BIT 15 MSB APD BIT 14 AVPD BIT 13 ABPD BIT 12 HAPD BIT 11 MOPD BIT 10 DAPD BIT 9 ADPDL BIT 8 RESV BIT 7 PDSTS BIT 6 MIBPD BIT 5 OSCC BIT 4 BCKC BIT 3 SMPD BIT 2 OTSYN BIT 1 BASS BIT 0 LSB DEEMP
For bits 15 through 8 of this register, writing a 1 to a selected bit powers down the affected section, writing a 0 powers up the section.
Bit 15 APD
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Audio Power Down. This bit powers down the entire audio section if set, regardless of the settings of the other bits in this register. When this bit is cleared, the individual sections of the audio codec still need to be powered up individually. The settings of the other bits in the register are retained when this bit is set and cleared. The default is 1 (powered down).
Bit 14 AVPD
Audio VCM Power Down. If this is set to 1, the VCM will power up whenever it is needed (such as when the audio ADC, DAC, or bypass path is enabled) and powers down when no longer needed. If this bit is set to 0, after an audio component is powered up and causes VCM to power up, it no longer powers down, even if all audio components are powered down. This is intended to avoid the 500 msec delay needed for VCM to power up slowly. The default is 1 (powered down).
Bit 13 ABPD
Audio Bypass Path Power Down. This is used to power up (set to 0) or power down (set to 1) the audio bypass path. The default is 1 (powered down).
Bits 12 HAPD
Headphone Amplifier Power Down. This is used to power up (set to 0) or power down (set to 1) the headphone amplifier. The default is 1 (powered down).
Bit 11 MOPD
Mono Driver Power Down. This is used to power up (set to 0) or power down (set to 1) the mono output driver. If only playback of the line or Mic inputs through the mono output is needed, the user need only power up the mono section, and not the DAC or ADC. The line inputs, Mic preamp, ADC multiplexer and volume control all power up if the mono output is powered up. The default is 1 (powered down).
Bit 10 DAPD
DAC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire stereo DAC. The default is 1 (powered down).
Bit 9 ADPDL
ADC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire ADC. The line inputs, Mic preamp, ADC multiplexer and volume control all automatically power up when the ADC is powered up. The default is 1 (powered down).
Bit 8 Reserved
The default is 1 (powered down).
Bit 7 PDSTS
Power Up/Down Done. This read-only bit indicates that all power-up or power-down processes requested are completed.
Table 43. Power Up/Down Flag
PDSTS 0 1 DESCRIPTION Power up/down is not complete Power up/down is complete (default)
Bit 6 MIBPD
Microphone Bias Power Down. This is used to power up (set to 0) or power down (set to 1) the Microphone Bias Output.
Table 44. Microphone Bias Power Down
OSCC 0 1 DESCRIPTION Microphone bias is on (default). Microphone bias is off.
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Bit 5 OSCC
Crystal Oscillator Control. The TSC2300 includes a crystal oscillator that can be used to generate the signal needed for the MCLK input, or any other purpose. However, it is not necessary to use the crystal oscillator. No function of the TSC2300 requires use of the crystal oscillator The OSCC bit in this register controls the crystal oscillator as described in Table 44.
Table 45. Crystal Oscillator Control
OSCC 0 1 DESCRIPTION Crystal oscillator is off. Crystal oscillator is on (default).
Bit 4 BCKC
Oscillator Clock Buffer Control. If the crystal oscillator is used to provide a clock for another part, a buffered version of the oscillator clock can be obtained from pin 13 (GPIO_5/CLKO). The BCKC bit in this register determines whether or not the buffered oscillator clock is driven. Note that GPIO_5 must be configured as an output for this option to fully function.
Table 46. Oscillator Clock Buffer Control
BCKC 0 1 DESCRIPTION The output clock buffer is off (default). The output clock buffer is on.
Bit 3 SMPD
Synchronization Monitor Power Down. The TSC2300 contains circuitry to monitor the I2S bus LRCLK and BCLK clocks and provide a flag to the system if they appear unsychronized. When this synchronization monitor detects a possible out-of-sync condition, it flags the data converter, which causes them to stop and wait for the bus to resynchronize. The SMPD bit is used to enable or disable the operation of this circuitry.
Table 47. Synchronization Monitor Power Down
SMPD 0 1 DESCRIPTION The I2S bus sync monitor is on (default). The I2S bus sync monitor is off.
Bit 2 OTSYN
I2S Out Of Sync. This read-only sticky bit reflects the sync status of the I2S bus. It will always reset to zero after being read.
Table 48. I2S Out of Sync
OTSYN 0 1 DESCRIPTION The I2S bus is in sync. The I2S bus is out of sync (default).
Bit 1 BASS
Digital-effects filter control. This bit turns ON/OFF the digital-effects filter. If the digital-effects filter is off, the signal passes through with no filtering performed.
Table 49. Digital-Effects Filter Control
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Digital-Effects Filter Control (continued)
BASS 0 1 DESCRIPTION The digital-effects filter is off (default). The digital-effects filter is on.
Bit 0 DEEMP
De-emphasis control. This bit turns ON/OFF the de-emphasis function.
Table 50. De-emphasis Control
DEEMP 0 1 DESCRIPTION De-emphasis is off (default). De-emphasis is on.
GPIO CONTROL REGISTER (Page 02, Address 06h)
The GPIO control register controls the GPIO pins of the TSC2300. The direction of each GPIO pin can be set independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO's configured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB which mirrors the state of the DAVB output line. The GPIO Control Register is formatted as follows:
BIT 15 MSB RESV BIT 14 RESV BIT 13 IO5 BIT 12 IO 4 BIT 11 IO 3 BIT 10 IO 2 BIT 9 IO 1 BIT 8 IO 0 BIT 7 RESV BIT 6 RESV BIT 5 GPIO5 BIT 4 GPIO4 BIT 3 GPIO3 BIT 2 GPIO2 BIT 1 GPIO 1 BIT 0 LSB GPIO 0
Bits 15,14 RESERVED
These bits are reserved and should be written to 0. If read, they will read back as 0.
Bits [13:8] IO5- IO0
GPIO Directional Control. These 6 bits control the direction of the TSC2300's six GPIO pins. When one of these bits is set to one, the corresponding GPIO pin is configured as an output. When one of these bits is set to zero, the corresponding GPIO pin is configured as an input. The default setting of these bits is zero (all inputs).
Bits 7,6 RESERVED
These bits are reserved, and should be written to 0. If read, they read back as 0.
Bits [5:0] GPIO5- GPIO0
GPIO Data. These bits control the data on the GPIO pins. When a GPIO pin is configured as an output, the data written to one of these bits is driven on the corresponding GPIO pin. When a GPIO pin is configured as an input, the data input on the GPIO pin is returned to the corresponding register bit, and can be read by the host processor.
DAC BASS-BOOST FILTER COEFFICIENT REGISTERS (Page 02, Addresses 07h-1Ah)
The DAC bass-boost coefficient registers implement the transfer function described . The coefficients are represented by 16-bit 2s complement integers with values ranging from -32768 to +32767. The DAC bass-boost coefficient registers are formatted as follows:
BIT 15 MSB D15 BIT 14 D14 BIT 13 D13 BIT 12 D12 BIT 11 D11 BIT 10 D10 BIT 9 D9 BIT 8 D8 BIT 7 D7 BIT 6 D6 BIT 5 D5 BIT 4 D4 BIT 3 D3 BIT 2 D2 BIT 1 D1 BIT 0 LSB D0
Table 51. DAC Bass-Boost Coefficient Registers
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TSC2300
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DAC Bass-Boost Coefficient Registers (continued)
ADDRESS 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah DAC CHANNEL Left Left Left Left Left Left Left Left Left Left Right Right Right Right Right Right Right Right Right Right COEFFICIENT N0 N1 N2 N3 N4 N5 D1 D2 D4 D5 N0 N1 N2 N3 N4 N5 D1 D2 D4 D5 DEFAULT 6BE2 9667 675D 6BE2 9667 675D 7D82 84EF 7D82 84EF 6BE2 9667 675D 6BE2 9667 675D 7D82 84EF 7D82 84EF
LAYOUT
The following layout suggestions should provide optimum performance from the TSC2300. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter's power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2300 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the internal conversion clock. The touch screen circuitry, as well as the audio headphone amplifiers, uses the HPVDD/HPGND supplies for its power, and any noise on this supply may adversely affect performance in these blocks. As described earlier, the audio common-mode voltage VCM is derived directly through an internal resistor divider between AVDD and AGND. Therefore, noise that couples onto AVDD/AGND will be translated onto VCM and can adversely impact audio performance. The reference pins for the audio data converters, VREF+/VREF-, should also be kept as clean and noise-free as possible, since noise here will affect audio DAC/ADC quality. De-coupling capacitors are recommended between VREF+ and VREF-, in addition to a series resistance between VREF+ and the source of the voltage (such as connecting to the source providing AVDD). With this in mind, power to the TSC2300 should be clean and well bypassed. A 0.1-F ceramic bypass capacitor should be placed as close to the device as possible on each supply pin to its respective ground pin. A 1-F to 10-F capacitor may also be needed if the impedance of the connection between a supply and the power supply is high. A bypass capacitor on the SAR Vref pin may not be absolutely necessary because this reference is buffered by an internal op amp, but a 0.1uF bypass capacitor may reduce noise on this reference. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation.
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TSC2300
SLAS372 -- NOVEMBER 2002
The TSC2300 SAR converter architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove. The HPGND pin should be connected to a clean ground point. In many cases, this is the analog ground for the SAR converter. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that require a back-lit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted data. Several things can be done to reduce this error, such as utilizing a touch screen with a bottom-side metal layer connected to ground. This couples the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y-, X+, and X- to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and requires longer panel voltage stabilization times, as well as increased precharge and sense times for the touch screen control circuitry of the TSC2300.
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MECHANICAL DATA
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,50 48 33
0,27 0,17
0,08 M
49
32
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane 16 Gage Plane 0,25 0,05 MIN 0 -7 0,75 0,45
1,20 MAX
0,08 4040282/C 11/96
(A) All linear dimensions are in millimeters. (B) This drawing is subject to change without notice. (C) Falls within JEDEC MS-026
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