View U2783B_1006550.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

U2783B
1250-MHz / 400-MHz Twin PLL
Description
The IC U2783B is a low-power twin PLL manufactured with TEMIC Semiconductors' advanced UHF process. The maximum operating frequency is 1250 MHz and 400 MHz respectively. It features a wide supply-voltage range from 2.7 V to 5.5 V. Prescaler and power-down function for both PLLs is integrated. Applications are CT1, CT2, IS54 etc. Electrostatic sensitive device. Observe precautions for handling.
Features
D Very low current consumption (typical 3 V/10 mA) D Supply-voltage range 2.7 V to 5.5 V D Maximum input frequency PLL1: 1250 MHz,
PLL2: 400 MHz
Benefits
D Low current consumption leads to extended talk time D Twin PLL saves costs and space D One foot print for all TEMIC Semiconductors twin
PLLs saves design-in time
D D D D D
2 pins for separate power-down functions Output for PLL lock status Prescaler 64/65 for PLL1 and 32/33 for PLL2 SSO20 package ESD protected according to MIL-STD 833 method 3015 cl.2
Block Diagram
1 VS analog VS digital DGND 4 2 6 Power down Test Ports 9 14 20 5I/Port 0 HPD1/Port 1 HPD2/Port 4 Port3
AGND 15 7 OSCi 8 OSCo
Oscillator
Control functions 16-bit latch
Lock select
10
Lock Port2
On / off divide by 2
12-bit latch 1 12-bit reference divider 1 17-bit latch 1 Phase detector 1 Charge pump 1 3 17 CP1 VScp
RFi1
5
64/65 Prescaler 1
17-bit main divider 1
Clock
11 3-bit 13 Load control
17-bit Shift register
Pump bias
19
Iset
Data 12 Enable 12-bit latch 2 12-bit reference divider 2 15-bit latch 2 RFi2 16 32/33 Prescaler 2 15-bit main divider 2
94 8918
Phase detector 2
Charge pump 2
18 CP2
Figure 1. Block diagram
Rev. A4, 19-May-99
1 (10)
U2783B
Ordering Information
Extended Type Number U2783B-AFS U2783B-AFSG3 Package SSO20 SSO20 Remarks Tube, MOQ 830 pcs Taped and reeled, MOQ 4000 pcs
Pin Description
5I/Port 0 VS digital CP 1 VS analog RFi 1 GNDD OSCi OSCo HPD1/Port 1 1 2 3 4 5 6 7 8 9 20 Port 3 19 Iset 18 CP 2 17 VScp 16 RFi 2 15 GNDA 14 HPD2/Port 4 13 Enable 12 Data 11 Clock
95 9622
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Lock/Port 2 10
Figure 2. Pinning
Symbol Function 5I/Port 0 5I - Control input / o.c.output VS digital Power supply digital section CP 1 Charge-pump output of synthesizer 1 VS analog Power supply analog section RFi 1 RF divider input synthesizer GNDD Ground for digital section OSCi Reference oscillator input OSCo Reference oscillator output HPD 1/ Hardware power-down input of Port 1 synthesizer 1 / o.c.output Lock/ Lock output / o.c.output / Port 2 testmode output Clock 3-wire-bus: serial clock input Data 3-wire-bus: serial data input Enable 3-wire-bus: serial enable input HPD 2/ Hardware power-down input of Port 4 synthesizer 2 / o.c.output GNDA Ground for analog section RFi 2 RF divider input synthesizer 2 VScp Charge-pump supply voltage CP 2 Charge-pump output of synthesizer 2 Iset Reference pin for charge-pump currents Port 3 o.c.output
Absolute Maximum Ratings
Supply voltage Input voltage Parameters Pins 2, 4 and 17 Pins 1, 3, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18 and 20 Symbol VS, VScp Vi Tj Tstg Value 6 0 to VS 125 - 40 to + 125 Unit V V C C
Junction temperature Storage-temperature range
Operating Range
Parameters Supply voltage Pins 2, 4 and 17 Ambient-temperature range Symbol VS, VScp Tamb Value 2.7 to 5.5 - 40 to + 85 Unit V C
2 (10)
Rev. A4, 19-May-99
U2783B
Thermal Resistance
Junction ambient Parameters SSO20 Symbol Rthja Value 140 Unit K/W
Electrical Characteristics
Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified
AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAA AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VS = 3 V VCP = 5 V, PLL in lock condition IS ICP 10 1 mA A PLL 1 Input voltage Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter Reference counter PLL 2 Input voltage fRFi1 = 200 - 1250 MHz VRFi1 SPSC SM SS SR fRFi2 = 50 MHz fRFi2 = 100 - 400 MHz VRFi2 SPSC SM SS SR RS AC coupled sinewave RF/2 = 0 RF/2 = 1 AC coupled sinewave OSCi 1 1 100 20 40 MHz mVRMS 20 5 0 5 40 20 32/33 5 0 5 10 1023 31 4096 200 200 mVRMS 64/65 2047 63 4096 200 200 mVRMS Scaling factor prescaler Scaling factor main counter Scaling factor swallow Reference counter Reference oscillator Recommended crystal series resistance External reference input frequency
Parameters DC Supply Supply current Supply current CP
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
W
2) External reference input OSCi amplitude Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I) High input level ViH Low input level ViL High input current IiH Low input current IiL Logic output levels (Ports 0, 1, 2, 3, 4, Lock) Leakage current VOH = 5.5 V IL Saturation voltage IOL = 0.5 mA VSL Charge-pump output (Rset = 10 kW, see figure 3) Source current VCP VScp/2 PLL2 5I = L PLL1 Isource 5I = H PLL1 Sink current VCP VScp/2 PLL2 Isink 5I = L PLL1 5I = H PLL1 Leakage current VCP VScp/2 IL
1.5 0 -5 -5
0.4 5 5 10 0.4 -1 -0.2 -1 1 0.2 1
mA mA mA
V mA
V V
x x x
mA nA
1)
RMS voltage at 50 W;
2)
OSCo is open if an external reference frequency is applied
"5
Rev. A4, 19-May-99
3 (10)
U2783B
Serial Bus Programming
Reference and programmable counters can be programmed by 3-wire bus (Clock, Data and Enable). After setting enable signal to high condition, the data status is transfered bit by bit on the rising edge of the clock signal into the shift register, starting with the MSB bit. After the Enable signal returns the addressed latch. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable high condition. In power-down mode the 3-wire-bus remains active and the IC can be programmed. Data is entered with the most significant bit first. The leading bits deliver the divider or control information. The trailing three bits are the address field. There are six different addresses used. The trailing address bits are decoded upon the falling edge of the Enable signal. The internal loadpulse is beginning with the falling edge of the Enable signal and ending with the falling edge of the Clock signal. Therefore a minimum holdtime clock-enable tHCE is required.
Bit Allocation
MSB
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 D9 M3 R9 M4 Bit Bit 9 10 Data bits D8 M2 R8 M3 D7 M1 R7 M2 Bit 11 D6 M0 R6 M1 R6 LP B Bit 12 D5 S5 R5 M0 R5 LPA Bit 13 D4 S4 R4 S4 R4 P4 Bit 14 D3 S3 R3 S3 R3 P3 Bit 15 D2 S2 R2 S2 R2 P2 Bit 16 D1 S1 R1 S1 R1 P1 Bit 17 D0
PLL1 S0 PLL1 R0 PLL2 S0 PLL2 R0
LSB
Bit Bit Bit 18 19 20 Address bits A2 0 0 0 1 1 A1 0 1 1 0 0 A0 1 0 1 0 1
D16 D15 D14 D13 D12 D11 D10
PLL1 M10
M9
M8
M7
M6
M5
PLL1 R11
M4 R10 M5
PLL 2 M9
M8
M7
M6
PLL2 R11
RF/ 2
Test
5IP
TRI 2
TRI 1
R10 R9 R8 R7 PS2 PS1 H2P H1P
P0 SP D1
SP SP D 5I D 2
1
1
0
Scaling Factors PGD of PLL1:
These bits are setting the swallow counter SS. TS = S0*20 + S1*21 + ... + S4*24 + S5*25 allowed scaling factors for SS: 0 ... 63, TS < TM M0 ... M10: These bits are setting the main counter SM. TM = M0*20 + M1*21 + ... + M9*29 + M10*210 allowed scaling factors for SM: 5 ... 2047 SPGD: Total scaling factor of the programmable counter: Condition: SS < SM SPGD = (64*SM) + SS S0 ... S5:
RFD of PLL1 and PLL2:
R0 ... R11: These bits are setting the reference counter SR. SR = R0*20 + ... + R10*210 + R11*211 allowed scaling factors for SR: 5 ... 4096 SRFD = 2 * SR SRFD = SR
RF/2 = 1: RF/2 = 0:
PGD of PLL2:
S0 ... S4: These bits are setting the swallow counter SS. TS = S0*20 + S1*21 + ... + S3*23 + S4*24 allowed scaling factors for SS: 0 ... 31, TS < TM These bits are setting the main counter SM. TM = M0*20 + M1*21 + ... + M8*28 + M9*29 allowed scaling factors for SM: 5 ... 1023 Total scaling factor of the programmable counter: Condition: SS < SM SPGD = (32*SM) + SS
M0 ... M9:
SPGD:
4 (10)
Rev. A4, 19-May-99
U2783B
Serial Programming Bus
Control Bits:
P0 ... P4: LPA, LPB: o.c. output ports (1 = high impedance) selection of P2 output or locksignal function of Pin 10 TEST 0 0 0 0 H1P, H2P: 5IP: LPA 0 0 1 1 LPB 0 o.c. output P2 1 locksignal of synthesizer 2 0 locksignal of synthesizer 1 1 wiredor locksignal of both synthesizer
selection of P1/4 output or hardware power-down input of synthesizer 1/2 (0 = Port / 1 = HPD)
selection of P0 output or high current switching input for the charge-pump current of synthesizer 1 (0 = Port / 1 = charge-pump 1 current switch input) phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers) PS-PLL1/2 = 1 CP1/2 Isink Isource 0 PS-PLL1/2 = 0 CP1/2 Isource Isink 0
PS1, PS2:
fR > fP fR < fP fR = fP
RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on) SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = power down / 1 = power up) 5I: software switch for the charge-pump current of synthesizer 1 (0 = low current / 1 = high current)
TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate) TEST: enables counter testmode (0 = disabled / 1 = enabled) TEST 1 1 1 1 LPA 1 1 0 0 LPB 0 0 1 1 PS1 1 0 x x PS2 x x 1 0 Testsignal at pin 10 RFD1 PGD1 RFD2 PGD2
To operate the software power-down mode the following condition must be set: HXP = 0; power up and power down will be set by SPDX = 1 (on) and SPDX = 0 (off). To operate the hardware power-down mode the following condition must be set: HXP = 1; SPDX = 1; power up and power down will be set by high and low state at the hardware power down Pins 9/14. High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge-pump current control input Pin 1 is in high state.
Rev. A4, 19-May-99
5 (10)
Application Circuit
U2783B
6 (10)
VS VCO 5I / P0 47u VS 12 R1 VCO1 47u 10n C1 C2 10n 10n 12 18 51 10n RF1 Crystal-oscillator input 51 10n 18 18 18 51 HPD2 / PORT4 HPD1 / PORT1 ENABLE 10n DATA CLOCK LOCK / PORT2 / TEST
94 9621
10n Rset
P3 C2
R1 C1 47u 10n 12 VScp
12
Figure 3. Application circuit
18 18 10n
VCO2
10n
47u
10n
RF2
Rev. A4, 19-May-99
U2783B
Timing Diagram Serial Bus
Data Clock
Enable tEL tSEC tCH tCL Internal Loadpulse
Figure 4.
tSDC
tHDC
tHCE tHEC
96 11828
Table 1. Timing
Parameters Clock-High Time Clock-Low Time Clock Period Set-up Time Data to Clock Hold Time Data to Clock Hold Time Clock to Enable Hold Time Enable to Clock Enable Low Time Set-up Time Enable to Clock
Symbol tCH tCL tPER tSDC tHDC tHCE tHEC tEL tSEC
Value > 750 > 350 > 1100 > 100 > 400 > 400 > 400 > 200 > 4000
Unit ns ns ns ns ns ns ns ns ns
Rev. A4, 19-May-99
7 (10)
U2783B
4.0 3.5 1m Veff on 50W 3.0 Icp / mA 2.5 5I=1 2.0 1.5 1.0 0.5 0 3000
96 11679
1000
100 Guaranteed Area
10
1 30000 R19/ W 300000
96 11682
0
100
200
300
400
500
600
Frequency/ MHz
Figure 5. Charge pump characteristics
1000
Figure 7. Input sensitivity of PLL2
1m Veff on 50W
100 Guaranteed Area
10
1 0
96 11681
200
400
600
800 1000 1200 1400
Frequency/ MHz
Figure 6. Input sensitivity of PLL1
8 (10)
Rev. A4, 19-May-99
U2783B
Input Impedance of PLL1 and PLL2
j 0.5j 2j
0.2j
5j
0
0.2
0.5
1
2
5 100 MHz
1
-5j
-0.2j
-0.5j
96 11687
Figure 8. Output impedance of PLL1 and PLL2
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
0.25 0.65 5.85 20 11
1
Rev. A4, 19-May-99
A AA A AAAA A AA A AAAA
500 MHz PLL2 1 GHz 1.5 GHz PLL1 -j 1.30 0.15 0.05 6.6 6.3
technical drawings according to DIN specifications
-2j Z0 = 50 W
0.15
13007
10
9 (10)
U2783B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
10 (10)
Rev. A4, 19-May-99

▲Up To Search▲

Price & Availability of U2783B

	To Download U2783B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .