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| Features * * * * * * * * * * * * * * * * * * * High performance ULC family suitable for large-sized CPLDs and FPGAs Conversions to over 2,000,000 FPGA gates Pin counts to over 976 pins Any pin-out matched due to limited number of dedicated pads Full range of packages: LCC/PLCC, PQFP/TQFP, fine pitch BGA, PGA/PPGA 2.5V I/O and 3.3V tolerant/compliant Low quiescent current: <0.3 nA/gate Available in commercial and industrial grades 0.25 mm Drawn CMOS, 5 Metal Layers Library Optimised for Synthesis, Static Timing Analysis & Automatic Test Pattern Generation (ATPG) High Speed Performance: - 100 ps Typical Gate Delay @2.5V - Typical 280 MHz Flip-Flop Toggle Frequency @2.5V High System Frequency Skew Control: - Clock Tree Synthesis Software 2.5Volts & 3.3Volts Operation; Single or Dual Supply Modes Low Power Consumption: - <0.18 W/Gate/MHz @2.5V Power on Reset Standard 2, 4, 6, 8,10, 12 and 18 mA I/Os CMOS/TTL/PCI Interface, LVCMOS, LVTTL, PECL, PCI (33/66 MHz) levels, GTL/GTL+, HSTL, SSTL2, SSTL3, CCT, AGP, LVDS ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core 0.25 m ULC Series UA2 Preliminary Description The UA2 series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.25- m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 280 MHz at 2.5V, and input to output delay cells as fast as 100ps at 2.5V. The architecture of the UA2 series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing. Conversion to the UA2 series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA2 series has a very low standby consumption of less than 0.3 nA/gate typically commercial temp, which would yield a standby current of 0.3 nA/gate, 0.42A on a 144,000 gates design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. The UA2 series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required. Rev. A - 29-Oct-01 1 UA2 The UA2 series is designed to allow conversion of high performance 2.5V devices. Support of mixed supply conversions (2.5V core, 3.3V periphery) is also possible, allowing optimal trade-offs between speed and power consumption. Array Organization Device Number UA2044 UA2/68 UA2084 UA2100 UA2120 UA2132 UA2144 UA2160 UA2184 UA2208 UA2228 UA2256 UA2304 UA2352 UA2388 UA2432 UA2484 UA2540 UA2600 UA2700 UA2800 UA2900 UA2976 4LM Routable Gates 9,535 30,096 50,410 75,472 106,278 131,670 159,778 200,998 270,663 329,281 401,010 512,398 733,635 925,815 1,133,594 1,417,125 1,651,406 2,069,052 2,567,790 3,520,954 4,231,979 5,378,257 5,765,320 5LM Routable Gates 10,727 33,858 56,712 84,906 120,449 149,226 181,081 227,797 306,751 376,321 458,298 585,598 838,440 1,068,248 1,307,994 1,635,145 1,926,640 2,413,894 2,995,755 4,107,780 5,001,430 6,356,122 6,918,384 Full Programmable usable pads 36 60 76 92 112 124 136 152 176 200 220 248 296 344 380 424 476 532 592 692 792 892 968 Architecture The basic element of the UA2 family is called a cell. One cell can typically implement between one to four FPGA gates. Cells are located contiguously through out the core of the device, with routing resources provided in three to four metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. 2 Rev. A - 29-Oct-01 In order to improve noise immunity within the device, separate VDD and VSS busses are provided for the internal cells and the I/O cells. I/O buffer interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator could be located close to each buffer. Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen option. 36mA achievable, using 2 pads. Slew Rate Controlled Output Buffer In this mode, the p- and n-output transistors commands are delayed, so that they are never set "ON" simultaneously, resulting in a low switching current and low noise. These buffers are dedicated to very high load drive. I/O Options 2.5V Compatibility The UA2 series of ULC's is fully capable of supporting high-performance operation at 2.5V for core or 3.3V for periphery. The performance specifications of any given ULC design however, must be explicitly specified as 2.5V, 3.3V or both. Power Supply and Noise Protection The speed and density of the UA2 technology cause large switching current spikes, for example, when: * * 16 high current output buffers switch simultaneously, or 10% of the 700 000 gates are switching within a window of 1ns. Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the setting time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the UA2 core matrix, several mechanisms have been implemented inside the UA2 arrays. Two types of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O buffers switching protection Three features are implemented to limit the noise generated by the switching current: * * * The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed. 3 UA2 Rev. A - 29-Oct-01 UA2 Matrix switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: * * Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. * 4 Rev. A - 29-Oct-01 Electrical Characteristics Absolute Maximum Ratings Max Supply Voltage (VDD) .................................................... 2.7V Max Supply Voltage (VDD5)................................................... 3.6V Input Voltage (VIN)VDD VDD ................................................... + 0.5V 3.3V Tolerant/CompliantVDD5 .............................................. + 0.5V Storage Temperature .......................................................... -65 to 150C Operating Ambient Temperature .......................................... -40 to 85C Recommended Operating Range VDD ................................................................................ 2.5V 5% or 3.3V 5% Operating Temperature: Commercial .......................................................................... 0 to 70C Industrial............................................................................... -40 to 85C 5 UA2 Rev. A - 29-Oct-01 UA2 DC Characteristics 2.5V Symbol TA VDD IIH Parameter Operating Temperature Supply Voltage High level input current PCI CMOS IIL Low Level input current PCI IOZ High-Impedance State Output Current Output short-circuit current PO11 CMOS VIH High-level Input Voltage PCI CMOS Schmitt CMOS VIL Low-Level Input Voltage PCI CMOS Schmitt Vhys Hysteresis CMOS Schmitt PO11 VOH High-Level output voltage PCI PO11 VOL Low-Level output voltage PCI 0.1VDD 0.9VDD 0.4 V IOL = 1.4 mA, VDD = VDD (min) IOL = 1.5 mA 0.7VDD 1.0 0.5 0.7VDD 0.475VDD 0.7VDD 1.5 0.3VDD 0.325VDD 0.3VDD V V IOH = 1.4mA, VDD = VDD (min) IOH = -500 A V 6 V All PO11 IOS -10 9 10 A mA VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD= VDD (max) -10 10 A VIN=VSS,VDD=VDD (max) Specified at VDD = +2.5V +/- 5% Buffer All All CMOS Min. -40 2.3 2.5 Typ Max +85 2.7 10 Unit C V A VIN=VDD,VDD=VDD(max) Conditions 6 Rev. A - 29-Oct-01 3.3V Symbol TA VDD IIH Parameter Operating Temperature Supply Voltage High level input current Specified at VDD = +3.3V +/- 5% Buffer All All CMOS PCI Min -40 3.0 3.3 Typ Max +85 3.6 10 10 -10 A VIN=VSS,VDD=VDD (max) Unit C V A VIN=VDD,VDD=VDD(max) Conditions IIL Low Level input current CMOS PCI IOZ IOS High-Impedance State Output Current Output short-circuit current All PO11 PO11 -10 14 -9 2.0 0.475VDD 2.0 1.7 10 A mA VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD= VDD (max) VIH High-level Input Voltage CMOS,LVTTL PCI CMOS Schmitt V VIL Low-Level Input Voltage CMOS PCI CMOS/TTL-level Schmitt 1.1 0.6 0.7VDD 0.8 0.325VDD 0.8 V Vhys VOH Hysteresis High-Level output voltage TTL-level Schmitt PO11 PCI V IOH = 2mA, VDD = VDD (min) V IOH = -500 A 0.9VDD 0.4 V 0.1VDD IOL = 2 mA, VDD = VDD (min) IOL = 1.5 mA VOL Low-Level output voltage PO11 PCI I/O Buffer Symbol C IN C OUT Parameter Capacitance, Input Buffer (Die) Capacitance, Output Buffer (Die) Capacitance, Bidirectional Typ 2.4 5.6 6.6 Unit pF pF pF Conditions 3.3V 3.3V 3.3V C I/O 7 UA2 Rev. A - 29-Oct-01 Atmel Wireless & Microcontrollers Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11 Sweden Kavallerivaegen 24, Rissne 17402 Sundbyberg Sweden Tel: 468587 48 800 Fax: 468587 48 850 Hong Kong 77 Mody Rd., Tsimshatsui East, Rm.1219 East Kowloon Hong Kong Tel: 85223789 789 Fax: 85223755 733 United Kingdom Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371 Germany Erfurter Strasse 31 85386 Eching Germany Tel: 49893 19 70 0 Fax: 49893 19 46 21 Kruppstrasse 6 45128 Essen Germany Tel: 492 012 47 30 0 Fax: 492 012 47 30 47 Theresienstrasse 2 74072 Heilbronn Germany Tel: 4971 3167 36 36 Fax: 4971 3167 31 63 Korea Ste.605,Singsong Bldg. Youngdeungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137 USA 2325 Orchard Parkway San Jose California 95131 USA-California Tel: 1408441 0311 Fax: 1408436 4200 1465 Route 31, 5th Floor Annandale New Jersey 08801 USA-New Jersey Tel: 1908848 5208 Fax: 1908848 5232 Singapore 25 Tampines Street 92 Singapore 528877 Rep. of Singapore Tel: 65260 8223 Fax: 65787 9819 Taiwan Wen Hwa 2 Road, Lin Kou Hsiang 244 Taipei Hsien 244 Taiwan, R.O.C. Tel: 88622609 5581 Fax: 88622600 2735 Italy Via Grosio, 10/8 20151 Milano Italy Tel: 390238037-1 Fax: 390238037-234 Japan 1-24-8 Shinkawa, Chuo-Ku 104-0033 Tokyo Japan Tel: 8133523 3551 Fax: 8133523 7581 Spain Principe de Vergara, 112 28002 Madrid Spain Tel: 3491564 51 81 Fax: 3491562 75 14 Web site http://www.atmel-wm.com (c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Printed on recycled paper. |
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